Semiconductor structure and manufacturing method therefor, and semiconductor device

Abstract

A semiconductor structure and a manufacturing method therefor, and a semiconductor device. The semiconductor structure comprises: an interposer, which is internally provided with slots and trenches extending from the top surface of the interposer towards the interior of the interposer; and a capacitor, which is located in the slots and the trenches, the capacitor comprising a first electrode layer, a capacitor dielectric layer and a second electrode layer which are stacked in sequence, the capacitor dielectric layer covering the surface of the first electrode layer, and the second electrode layer covering the surface of the capacitor dielectric layer, wherein the trenches further extend in a preset direction parallel to the top surface of the interposer and are in communication with the plurality of slots arranged at intervals in the preset direction, the width dimension of the slots is greater than the width dimension of the trenches, and the direction of the width dimension is parallel to the top surface of the interposer and is perpendicular to the preset direction. The semiconductor structure has the advantages of a large capacity, fast charging and discharging, and high integration, and the arrangement thereof can also better solve the problem of stress.

Description

Semiconductor structure, its fabrication method, and semiconductor devices

[0001] This application claims priority to Chinese Patent Application No. 202411640113.8, filed on November 15, 2024, entitled "Semiconductor Structure and Method of Fabrication Thereof and Semiconductor Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for fabricating the same, and a semiconductor device. Background Technology

[0003] To improve the integration of semiconductor structures, many chips can be stacked and soldered together, such as in 3-Dimensional Stack (3DS) memory. This allows the layout to be expanded from 2D to 2.5D (between 2D and 3D packaging) or 3D, significantly increasing chip density. In advanced packaging technology, especially in 2.5D and 3D packaging, interposer packaging is widely used. Multiple chips are mounted on a substrate through an interposer, allowing them to receive signals from or transmit signals to other chips. This increases the overall signal density of the package while simultaneously reducing its overall size.

[0004] In interposer devices, deep trench capacitors (DTCs) are typically used to prevent signal lines from interfering with each other in order to maintain signal stability. However, the structural design of existing deep trench capacitor structures has significant limitations, and their performance still needs further improvement. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: an interposer having vias and trenches extending from the top surface of the interposer toward the interior of the interposer; and a capacitor located in the vias and trenches, the capacitor comprising a first electrode layer, a capacitor dielectric layer, and a second electrode layer stacked sequentially, the capacitor dielectric layer covering the surface of the first electrode layer, and the second electrode layer covering the surface of the capacitor dielectric layer; wherein the trenches further extend along a predetermined direction parallel to the top surface of the interposer and connect a plurality of vias spaced apart along the predetermined direction, the width of the vias being greater than the width of the trenches, the direction of the width being parallel to the top surface of the interposer and perpendicular to the predetermined direction.

[0006] In some embodiments, the semiconductor structure further includes: an exposed contact layer located in the via, covering the surface of the second electrode layer located in the via and filling the via.

[0007] In some embodiments, the material of the lead-out contact layer includes copper.

[0008] In some embodiments, the semiconductor structure further includes: a first contact and a second contact located above the capacitor, the first contact being connected to the lead-out contact layer and the second contact being connected to the first electrode layer.

[0009] In some embodiments, the slot corresponds one-to-one with the lead-out contact layer, and the lead-out contact layer corresponds one-to-one with the first contact element.

[0010] In some embodiments, the intermediary layer includes a plurality of the grooves, and the plurality of holes connected by adjacent grooves are arranged alternately along a direction perpendicular to the preset direction.

[0011] In some embodiments, the intermediary layer further includes a first region and a second region disposed adjacent to each other, wherein the preset direction in the first region is a first direction, and the preset direction in the second region is a second direction, wherein the first direction and the second direction are perpendicular to each other.

[0012] In some embodiments, in the first region, a plurality of the grooves extend along the first direction and are spaced apart along the second direction, and in the second region, a plurality of the grooves extend along the second direction and are spaced apart along the first direction.

[0013] In some embodiments, the semiconductor structure further includes: a bottom dielectric layer covering at least the bottom and sidewalls of the vias and trenches, the bottom dielectric layer being located between the interposer layer and the first electrode layer, the first electrode layer covering the surface of the bottom dielectric layer.

[0014] According to a second aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising: providing an interposer layer; forming vias and trenches extending from the top surface of the interposer layer toward the interior of the interposer layer in the interposer layer; forming a capacitor in the vias and trenches, comprising a first electrode layer, a capacitor dielectric layer, and a second electrode layer stacked sequentially, wherein the capacitor dielectric layer covers the surface of the first electrode layer, and the second electrode layer covers the surface of the capacitor dielectric layer; wherein the trenches further extend along a predetermined direction parallel to the top surface of the interposer layer and connect a plurality of vias spaced apart along the predetermined direction, the width dimension of the vias being greater than the width dimension of the trenches, and the direction of the width dimension being parallel to the top surface of the interposer layer and perpendicular to the predetermined direction.

[0015] In some embodiments, the method of fabricating the semiconductor structure further includes: forming an lead-out contact layer in the via, covering the surface of the second electrode layer located in the via, and filling the via.

[0016] In some embodiments, the method of fabricating the semiconductor structure further includes: forming a first contact and a second contact above the capacitor, wherein the first contact is connected to the lead-out contact layer and the second contact is connected to the first electrode layer; wherein the hole and the lead-out contact layer, and the lead-out contact layer and the first contact are all in one-to-one correspondence.

[0017] In some embodiments, the intermediary layer further includes a first region and a second region disposed adjacent to each other. In the first region, the preset direction is a first direction, and in the second region, the preset direction is a second direction. The first direction and the second direction are perpendicular to each other. Forming holes and grooves extending from the top surface of the intermediary layer toward the interior of the intermediary layer includes: forming a plurality of grooves extending along the first direction and spaced apart along the second direction in the first region; forming a plurality of grooves extending along the second direction and spaced apart along the first direction in the second region; and in a direction perpendicular to the preset direction, a plurality of holes connected by adjacent grooves are staggered.

[0018] In some embodiments, before forming the capacitor in the via and the trench, the method of fabricating the semiconductor structure further includes: forming a bottom dielectric layer in the via and the trench, at least covering the bottom and sidewalls of the via and the trench; the bottom dielectric layer is located between the interposer layer and the subsequently formed first electrode layer, the first electrode layer covering the surface of the bottom dielectric layer.

[0019] According to a third aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor structure as described in any of the foregoing embodiments; a chip located on the semiconductor structure; wherein the chip and the semiconductor structure are electrically connected via solder balls, bumps and / or pads. Attached Figure Description

[0020] Figure 1 is a schematic diagram illustrating the provision of an intermediary layer according to an exemplary embodiment;

[0021] Figure 2 is a schematic diagram illustrating the formation of holes and trenches according to an exemplary embodiment;

[0022] Figure 3 is a schematic diagram illustrating the formation of holes and grooves according to another exemplary embodiment;

[0023] Figure 4 is a schematic diagram illustrating the formation of a substrate layer according to an exemplary embodiment;

[0024] Figure 5 is a schematic diagram illustrating the formation of a capacitor according to an exemplary embodiment;

[0025] Figure 6 is a schematic diagram illustrating the formation of an outgoing contact layer and first and second contacts according to an exemplary embodiment;

[0026] Figure 7 is a schematic diagram illustrating the formation of an outgoing contact layer and first and second contacts according to another exemplary embodiment;

[0027] Figure 8 is a schematic diagram of the arrangement of a semiconductor structure according to an exemplary embodiment;

[0028] Figure 9 is a schematic diagram of a semiconductor device according to an exemplary embodiment. Detailed Implementation

[0029] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0030] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0031] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0032] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0033] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0034] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0035] In related technologies, DTC structures are basically deep-hole structures, typically fabricated simultaneously using a through-silicon via (TSV) process within the interposer. The inventors of this application have discovered that with the development of 2.5D packaging technology and further miniaturization of device dimensions, the capacitor area of ​​DTC structures is shrinking, making it increasingly difficult to increase capacitor density. Simultaneously, this is accompanied by increasingly severe stress problems during the support process. Therefore, seeking a new DTC structure design solution has become increasingly important.

[0036] To address the aforementioned technical problems, this disclosure provides a semiconductor structure, a method for fabricating the same, and a semiconductor device. The following will describe, in conjunction with Figures 1 to 9, an exemplary semiconductor structure, a method for fabricating the semiconductor structure, and a semiconductor device provided by this disclosure. Figures 1 to 7 are schematic diagrams illustrating methods for fabricating semiconductor structures according to various exemplary embodiments of this disclosure; Figure 8 is a schematic diagram illustrating the arrangement of a semiconductor structure according to an exemplary embodiment of this disclosure; and Figure 9 is a schematic diagram illustrating a semiconductor device according to an exemplary embodiment of this disclosure.

[0037] In an exemplary embodiment of this disclosure, a semiconductor structure is provided. Referring to FIG6 or FIG7, FIG6(a) or FIG7(a) shows a top view of the reverse direction towards the top surface of the interposer 1 along the Z direction, FIG6(b) or FIG7(b) is a cross-sectional schematic diagram along the A-A' direction in FIG6(a) or FIG7(a), FIG6(c) or FIG7(c) is a cross-sectional schematic diagram along the B-B' direction in FIG6(a) or FIG7(a), FIG6(d) or FIG7(d) is a cross-sectional schematic diagram along the C-C' direction in FIG6(a) or FIG7(a), and FIG6(e) or FIG7(e) is a cross-sectional schematic diagram along the D-D' direction in FIG6(b) or FIG7(b). The semiconductor structure includes: an interposer 1 having vias 21 and trenches 22 extending from the top surface of the interposer 1 toward its interior; and a capacitor 4 located within the vias 21 and trenches 22. The capacitor 4 includes a first electrode layer 41, a capacitor dielectric layer 42, and a second electrode layer 43 stacked sequentially. The capacitor dielectric layer 42 covers the surface of the first electrode layer 41, and the second electrode layer 43 covers the surface of the capacitor dielectric layer 42. The trenches 22 extend along a predetermined direction parallel to the top surface of the interposer 1 and connect to a plurality of vias 21 spaced apart along the predetermined direction. The width of the vias 21 is greater than the width of the trenches 22, and the direction of the width dimension is parallel to the top surface of the interposer 1 and perpendicular to the predetermined direction. It should be noted that, in an exemplary embodiment of this disclosure, the predetermined direction is the same as or opposite to the X direction, and the direction of the width dimension is the same as or opposite to the Y direction. It should also be noted that the X, Y, and Z directions in all the accompanying drawings of this disclosure are mutually perpendicular.

[0038] In an exemplary embodiment of this disclosure, the interposer 1 is a silicon interposer. The material of the silicon interposer may be at least one of the following: silicon, germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or a combination of a group III-V material and an organic material.

[0039] The slots 21 and grooves 22 are located in the interposer layer 1, extending from the top surface of the interposer layer 1 and toward the interior of the interposer layer 1. That is, the openings of the slots 21 and grooves 22 are on the top surface of the interposer layer 1, and the depth direction of the slots 21 and grooves 22 is perpendicular to the plane containing the top surface of the interposer layer 1 and toward the interior of the interposer layer 1, opposite to the Z direction in the figure. On a plane parallel to the top surface of the interposer layer 1, the grooves 22 extend along a predetermined direction, and the slots 21 are spaced apart along this predetermined direction, as shown by the dashed lines in Figure 6(a) or 7(a). The grooves 22 extend along the X direction or its reverse direction and connect multiple slots 21 spaced apart along the X direction or its reverse direction. In some embodiments, as shown in Figures 6(b) to 6(d) or 7(b) to 7(d), the cross-sectional view of the slots 21 and / or grooves 22 along the depth direction is rectangular, meaning that the opening size of the slots 21 and / or grooves 22 is substantially the same as the bottom size. In other embodiments, the cross-sectional view of the slots 21 and / or trenches 22 is trapezoidal. For example, the opening size of the slots 21 and / or trenches 22 is larger than the bottom size, or the bottom size of the slots 21 and / or trenches 22 is larger than the opening size. In other embodiments, the bottom of the slots 21 and / or trenches 22 is an arc shape that is recessed towards the interior of the interposer layer 1. In some embodiments, the width of the slot 21 is larger than the width of the trench 22, wherein the direction of the width is parallel to the top surface of the interposer layer 1 and perpendicular to the preset direction in the foregoing embodiments, that is, the direction of the width is in the same direction as or opposite to the Y direction.

[0040] The capacitor 4 is located in the vias 21 and the trench 22, and includes a first electrode layer 41, a capacitor dielectric layer 42, and a second electrode layer 43 stacked sequentially. The capacitor dielectric layer 42 covers the surface of the first electrode layer 41, and the second electrode layer 43 covers the surface of the capacitor dielectric layer 42. In some embodiments, specifically as shown in FIG6(b) to 6(e) or 7(b) to 7(e), the capacitor 4 located in a plurality of vias 21 connected by the same trench 22 and arranged at intervals along the X direction or in the opposite direction is integrated with the vias 22. In other embodiments, the capacitor 4 also includes one or more other electrode layers (not shown) besides the first electrode layer 41 and the second electrode layer 43, and adjacent electrode layers are separated by the capacitor dielectric layer 42 or additional capacitor dielectric layers (not shown).

[0041] In some embodiments, the materials of the first electrode layer 41 and / or the second electrode layer 43 may be at least one or a combination of doped silicon, titanium nitride (TiN), silicon-doped titanium nitride (TiSiN), titanium (Ti), tungsten (W), tungsten nitride (WN), and silicon-doped tungsten nitride (WSiN), and the materials of the capacitor dielectric layer 42 may be at least one or a combination of silicon oxide (SiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT). In an exemplary embodiment of this disclosure, the materials of the first electrode layer 41 and / or the second electrode layer 43 are titanium nitride, and the materials of the capacitor dielectric layer 42 are high-k dielectric materials.

[0042] In some embodiments, the semiconductor structure further includes: a lead-out contact layer 5, located in a via 21, covering the surface of the second electrode layer 43 located in the via 21 and filling the via 21. Specifically, the lead-out contact layer 5 is cylindrically inserted into the via 21, filling the space remaining in the via 21 except for the capacitor 4. The lead-out contact layer 5 is located only in the via 21 and shares a central axis with the via 21, with each via 21 corresponding to a lead-out contact layer 5. In some embodiments, the material of the lead-out contact layer 5 may be one or more combinations of tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu), and / or their nitrides. In an exemplary embodiment of this disclosure, the material of the lead-out contact layer 5 is copper.

[0043] In some embodiments, the semiconductor structure further includes: a first contact 61 and a second contact 62 located above the capacitor 4. The first contact 61 is connected to the lead-out contact layer 5, and the second contact 62 is connected to the first electrode layer 41. The lead-out contact layer 5 and the first contact 61 are in one-to-one correspondence. Specifically, the bottom of the first contact 61 is in direct contact with the top surface of the lead-out contact layer 5. In some embodiments, the first contact 61 can also directly contact a portion of the second electrode layer 43 adjacent to the lead-out contact layer 5. A window is formed on the surface of the capacitor 4, which opens the second electrode layer 43 and the capacitor dielectric layer 42 to expose a portion of the top surface of the first electrode layer 41. The second contact 62 directly contacts the first electrode layer 41 through this window. In some embodiments, as shown in FIG7(a), the first contact 61 and the second contact 62 are arranged in a hexagonal close-packed manner to achieve a high integration density while avoiding short circuits or interference between them. In other embodiments, the second contact 62 may be located in other positions, and its number may be reduced accordingly. However, it is necessary to ensure that the first contact 61 and the second contact 62 have a certain distance between them to avoid short circuits or interference between them.

[0044] In some embodiments, the material of the first contact 61 and / or the second contact 62 may be one or more combinations of tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu), and / or their nitrides. In an exemplary embodiment of this disclosure, the material of the first contact 61 and the second contact 62 is tungsten.

[0045] In some embodiments, an interlayer dielectric layer 7 is further provided above the capacitor 4, covering the top surface of the capacitor 4. The first contact 61 and the second contact 62 penetrate the interlayer dielectric layer 7 and are respectively connected to the lead-out contact layer 5 and the first electrode layer 41. In some embodiments, the material of the interlayer dielectric layer 7 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the interlayer dielectric layer 7 is silicon oxide.

[0046] In some embodiments, the semiconductor structure further includes a bottom dielectric layer 3, located below the capacitor 4, covering at least the bottom and sidewalls of the vias 21 and trenches 22. The bottom dielectric layer 3 is located between the interposer layer 1 and the first electrode layer 41, and the first electrode layer 41 covers the surface of the bottom dielectric layer 3. The bottom dielectric layer 3 serves to prevent the interposer layer 1 from interfering with the potential of the first electrode layer 41 and to prevent impurities in the interposer layer 1 from contaminating the material of the first electrode layer 41, thereby affecting the operating performance of the capacitor 4. In some embodiments, the material of the bottom dielectric layer 3 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the interlayer dielectric layer 3 is silicon oxide. In other embodiments, when the silicon-based material in the interposer layer 1 has high purity, the semiconductor structure may not have a bottom dielectric layer 3, and the first electrode layer 41 can directly contact the inner surfaces of the vias 21 and trenches 22 in the interposer layer 1. Furthermore, the first electrode layer 41 can be formed directly by doping the inner surfaces of the vias 21 and trenches 22.

[0047] In some embodiments, the semiconductor structure includes multiple trenches 22. These trenches 22, extending along the same predetermined direction, are arranged parallel to each other and spaced apart, as shown in FIG7(a) or 7(e). The trenches 22 extending along the X direction or its reverse direction are also spaced apart in the Y direction. Furthermore, along the Y direction or its reverse direction, multiple vias 21 connected by adjacent trenches 22 are arranged in an alternating manner. In some embodiments, the spacing between adjacent trenches 22 is equal, and the spacing between adjacent vias 21 connected by the same trench 22 and the spacing between adjacent vias 21 connected by adjacent trenches 22 are also equal; that is, the vias 21 are also arranged in a hexagonal close-packed configuration.

[0048] In an exemplary embodiment of this disclosure, referring to FIG8, the intermediary layer 1 further includes a first region 11 and a second region 12 disposed adjacent to each other. In the first region 11, a preset direction is a first direction, i.e., the same as or opposite to the X direction. In the second region 12, a preset direction is a second direction, i.e., the same as or opposite to the Y direction. In some embodiments, the intermediary layer 1 further includes a third region 13 and a fourth region 14 disposed adjacent to each other. The third region 13 has the same preset direction as the second region 12, and the fourth region 14 has the same preset direction as the first region 11. The third region 13 is also adjacent to the first region 11 in the Y direction, and the fourth region 14 is also adjacent to the second region in the Y direction. In other embodiments, the intermediary layer 1 may include more regions, but the preset directions of the adjacent regions must be mutually perpendicular. Regions with mutually perpendicular preset directions can effectively solve problems such as stress in the intermediary layer 1.

[0049] The semiconductor structure disclosed herein features trenches connecting multiple vias in the interposer layer. Capacitors are located within these vias and trenches, effectively increasing the capacitor area and capacitance, thereby enhancing capacitor performance. High-conductivity contact layers are also disposed within the vias, each corresponding to a first contact, meeting the capacitor's rapid charging and discharging requirements. Adjacent trenches extending along a predetermined direction are staggered in a direction perpendicular to the predetermined direction, significantly improving area utilization and thus increasing the integration density of the capacitor. The predetermined directions of trench extension in adjacent regions of the interposer layer are perpendicular to each other, effectively addressing stress issues within the interposer layer. In summary, the semiconductor structure disclosed herein offers advantages such as large capacity, fast charging and discharging, and high integration density, significantly improving the device performance of the DTC structure. Its arrangement also effectively mitigates stress issues in the interposer layer.

[0050] Based on the above semiconductor structure, this disclosure also provides a method for fabricating a semiconductor structure, including: providing an interposer 1, as shown in FIG1, wherein FIG1(a) is a top view of the interposer 1 in the opposite direction along the Z direction, and FIG1(b) is a cross-sectional schematic diagram along the dashed line A-A' in FIG1(a), and the cross-section along the dashed line A-A' is perpendicular to the top surface of the interposer 1.

[0051] In an exemplary embodiment of this disclosure, the interposer 1 is a silicon interposer. The material of the silicon interposer may be at least one of the following: silicon, germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or a combination of a group III-V material and an organic material.

[0052] Next, vias 21 and trenches 22 extending from the top surface of the interposer 1 toward the interior of the interposer 1 are formed in the interposer 1, as shown in Figures 2 and 3. Figure 2(a) / 3(a) is a top view of the interposer 1 in the opposite direction of the Z-direction, and Figure 2(b) / 3(b) is a cross-sectional view along the dashed line A-A' in Figure 2(a) / 3(a). The cross-section along the dashed line A-A' is perpendicular to the top surface of the interposer 1. Specifically, vias 21 and trenches 22 of a certain depth are etched from the surface of the interposer 1 toward the interior of the interposer 1. That is, the openings of the vias 21 and trenches 22 are on the top surface of the interposer 1, and the depth direction of the vias 21 and trenches 22 is perpendicular to the plane containing the top surface of the interposer 1 and toward the interior of the interposer 1, opposite to the Z-direction in the figure. On a plane parallel to the top surface of the interposer layer 1, trenches 22 extend along a predetermined direction, and slots 21 are spaced apart along this predetermined direction. In Figure 2, the predetermined direction can be the X direction or its reverse direction. The trenches 22 extend along the X direction or its reverse direction and connect multiple slots 21 spaced apart along the X direction or its reverse direction. In some embodiments, as shown in Figure 2(a) or 3(a), the width of the slots 21 is greater than the width of the trenches 22, wherein the direction of the width is parallel to the top surface of the interposer layer 1 and perpendicular to the predetermined direction in the aforementioned embodiments, i.e., the direction of the width is in the same direction as or opposite to the Y direction. In some embodiments, the cross-sectional view of the slots 21 and / or trenches 22 along the depth direction is rectangular, i.e., the opening size of the slots 21 and / or trenches 22 is substantially the same as the bottom size. In other embodiments, the cross-sectional view of the slots 21 and / or trenches 22 is trapezoidal. For example, the opening size of the slots 21 and / or trenches 22 is greater than the bottom size, or the bottom size of the slots 21 and / or trenches 22 is greater than the opening size. In one exemplary embodiment of this disclosure, as shown in FIG2(b), the via 21 and the trench 22 have the same depth. In another exemplary embodiment of this disclosure, as shown in FIG3(b), the depth of the via 21 is greater than that of the trench 22 because the via 21 has a larger width. Therefore, in a synchronous adaptive etching process, a larger opening size often corresponds to a larger etching depth. In other embodiments, the depths of the via 21 and the trench 22 can also be controlled separately through step-by-step etching.

[0053] In some embodiments, photolithography can be used to etch the surface of the interposer layer 1 to form vias 21 and / or trenches 22. Specifically, a photoresist mask layer can be formed on the surface of the interposer layer 1. By exposure and development, the patterns of vias 21 and / or trenches 22 are formed in the photoresist mask layer. Then, dry etching is performed to etch the interposer layer 1 along the patterns to form vias 21 and / or trenches 22. In some embodiments, before coating the photoresist mask layer, an anti-reflective layer and a hard mask layer (not shown) are also formed on the surface of the interposer layer 1, and both are removed after the vias 21 and / or trenches 22 are formed. In some embodiments, vias 21 and trenches 22 are formed by simultaneous etching, that is, during exposure and development, the patterns of both vias 21 and trenches 22 are formed in the photoresist mask layer (the pattern of both vias 21 and trenches 22 can be exposed in one exposure or exposed separately in two exposures), and then etched to form them. In other embodiments, the hole 21 and the trench 22 are formed by step etching, that is, the hole 21 can be formed by the first photolithography and the trench 22 can be formed by the second photolithography. The order of formation of the hole 21 and the trench 22 can also be reversed.

[0054] Next, in an exemplary embodiment of this disclosure, a bottom medium layer 3 is formed in the hole 21 and the trench 22, at least covering the bottom and sidewalls of the hole 21 and the trench 22. Referring to FIG4, FIG4(a) is a top view of the intermediate layer 1 in the opposite direction of the Z direction, FIG4(b) is a cross-sectional schematic diagram along the dashed line A-A' in FIG4(a), and FIG4(c) is a cross-sectional schematic diagram along the dashed line B-B' in FIG4(a). The cross-sections along the dashed line A-A' and along the dashed line B-B' are perpendicular to each other and both are perpendicular to the top surface of the intermediate layer 1.

[0055] In some embodiments, the material of the bottom dielectric layer 3 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the bottom dielectric layer 3 is silicon oxide. In some embodiments, the deposition method of the bottom dielectric layer 3 may be at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), in-situ water vapor growth (ISSG), and thermal oxidation growth.

[0056] Then, a capacitor 4 is formed in the hole 21 and the trench 22, consisting of a first electrode layer 41, a capacitor dielectric layer 42, and a second electrode layer 43 stacked sequentially. The capacitor dielectric layer 42 covers the surface of the first electrode layer 41, and the second electrode layer 43 covers the surface of the capacitor dielectric layer 42. Referring to FIG5, FIG5(a) is a top view facing the intermediate layer 1 in the opposite direction along the Z direction, FIG5(b) is a cross-sectional schematic diagram along the dashed line A-A' in FIG5(a), and FIG5(c) is a cross-sectional schematic diagram along FIG5(a). Figure 5(d) shows a cross-section along the direction of dashed line B-B' in Figure 5(a), and Figure 5(e) shows a cross-section along the direction of dashed line D-D' in Figure 5(b). The cross-sections along the direction of dashed line A-A' and along the direction of dashed line B-B' are perpendicular to each other and both perpendicular to the top surface of intermediate layer 1. The cross-sections along the direction of dashed line C-C' are parallel to the cross-sections along the direction of dashed line B-B', and the cross-sections along the direction of dashed line D-D' are parallel to the top surface of intermediate layer 1.

[0057] In some embodiments, after the capacitor 4 is formed, the trench 22 is filled with the material of the capacitor 4, as shown in FIG5(d), while the hole 21 is not filled, forming gaps 50, as shown in FIG5(b) and FIG5(c). The gaps 50 correspond one-to-one with the hole 21 and are spaced apart along a predetermined direction. The gaps 50 are surrounded by a second electrode layer 43 located in the hole 21. In some embodiments, the capacitor 4 also extends to cover the top surface of the intermediate layer 1.

[0058] In some embodiments, the bottom dielectric layer 3 is located between the interposer layer 1 and the first electrode layer 41, with the first electrode layer 41 covering the surface of the bottom dielectric layer 3. The bottom dielectric layer 3 serves to prevent the interposer layer 1 from interfering with the potential of the first electrode layer 41 and to prevent impurities in the interposer layer 1 from contaminating the material of the first electrode layer 41, thereby affecting the working performance of the capacitor 4. In other embodiments, when the silicon-based material in the interposer layer 1 has high purity, the semiconductor structure may not have a bottom dielectric layer 3, and the first electrode layer 41 may directly contact the inner surfaces of the vias 21 and trenches 22 in the interposer layer 1. Furthermore, the first electrode layer 41 may be formed directly by doping the inner surfaces of the vias 21 and trenches 22.

[0059] In some embodiments, the materials of the first electrode layer 41 and / or the second electrode layer 43 may be at least one or a combination of doped silicon, titanium nitride (TiN), silicon-doped titanium nitride (TiSiN), titanium (Ti), tungsten (W), tungsten nitride (WN), and silicon-doped tungsten nitride (WSiN), and the materials of the capacitor dielectric layer 42 may be at least one or a combination of silicon oxide (SiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), and lead titanate (PZT). In an exemplary embodiment of this disclosure, the materials of the first electrode layer 41 and / or the second electrode layer 43 are titanium nitride, and the materials of the capacitor dielectric layer 42 are high-k dielectric materials.

[0060] In some embodiments, the formation of the first electrode layer 41, the capacitor dielectric layer 42, and the second electrode layer 43 may employ at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and sputtering.

[0061] Next, a lead-out contact layer 5 is formed in the hole groove 21, covering the surface of the second electrode layer 43 located in the hole groove 21 and filling the hole groove 21, as shown in Figure 6. Figure 6(a) is a top view facing the intermediate layer 1 in the opposite direction of the Z direction. Figure 6(b) is a cross-sectional schematic diagram along the dashed line A-A' in Figure 6(a). Figure 6(c) is a cross-sectional schematic diagram along the dashed line B-B' in Figure 6(a). Figure 6(d) is a cross-sectional schematic diagram along the dashed line C-C' in Figure 6(a). Figure 6(e) is a cross-sectional schematic diagram along the dashed line D-D' in Figure 6(b). The cross-sections along the dashed line A-A' and B-B' are perpendicular to each other and both perpendicular to the top surface of the intermediate layer 1. The cross-sections along the dashed line C-C' and B-B' are parallel to each other. The cross-section along the dashed line D-D' is parallel to the top surface of the intermediate layer 1.

[0062] Specifically, the lead-out contact layer 5 is cylindrically inserted into the slot 21 and fills the gap 50 left after the formation of the capacitor 4. The lead-out contact layer 5 is located only in the slot 21 and shares a central axis with the slot 21. The slot 21 and the lead-out contact layer 5 correspond one-to-one. In some embodiments, the material filling the lead-out contact layer 5 may escape from the gap 50. The excess material can be removed by subsequent etching or planarization to make the top surface of the lead-out contact layer 5 the same height as the top surface of the second electrode layer 43.

[0063] In some embodiments, the material of the lead-out contact layer 5 may be one or more combinations of tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu), and / or their nitrides. In an exemplary embodiment of this disclosure, the material of the lead-out contact layer 5 is copper. In some embodiments, the method for forming the lead-out contact layer 5 may employ at least one of the deposition methods mentioned below: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and sputtering.

[0064] Referring again to Figure 6, a first contact 61 and a second contact 62 are formed above the capacitor 4. The first contact 61 is connected to the lead-out contact layer 5, and the second contact 62 is connected to the first electrode layer 41. Each lead-out contact layer 5 corresponds one-to-one with the first contact 61. Specifically, the bottom of the first contact 61 is in direct contact with the top surface of the lead-out contact layer 5. In some embodiments, the first contact 61 can also directly contact a portion of the second electrode layer 43 adjacent to the lead-out contact layer 5. A window is formed on the surface of the capacitor 4, which opens the second electrode layer 43 and the capacitor dielectric layer 42, thereby exposing a portion of the top surface of the first electrode layer 41. The second contact 62 directly contacts the first electrode layer 41 through this window.

[0065] In some embodiments, the material of the first contact 61 and / or the second contact 62 may be one or more combinations of tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu), and / or their nitrides. In an exemplary embodiment of this disclosure, the material of the first contact 61 and the second contact 62 is tungsten. In some embodiments, the method of forming the first contact 61 and / or the second contact 62 may employ at least one of the deposition methods mentioned below: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and sputtering.

[0066] In some embodiments, before forming the first contact 61 and the second contact 62, the method further includes: forming an interlayer dielectric layer 7 covering the top surface of the capacitor 4, with the first contact 61 and the second contact 62 penetrating the interlayer dielectric layer 7 and respectively connecting to the lead-out contact layer 5 and the first electrode layer 41. Specifically, an interlayer dielectric layer 7 is formed on the capacitor 4 to cover the top surface of the second electrode layer 43 and the lead-out contact layer 5, and then the interlayer dielectric layer 7 is etched to form a first via and a second via. The first via penetrates the interlayer dielectric layer 7 and at least exposes the top surface of the lead-out contact layer 5, while the second via penetrates the interlayer dielectric layer 7 and simultaneously forms a window on the surface of the capacitor 4. This window opens the second electrode layer 43 and the capacitor dielectric layer 42, thereby exposing part of the top surface of the first electrode layer 41. The first contact 61 is filled in the first via and the second contact 62 is filled in the second via to form the first contact 61. In some embodiments, the bottom of the first contact 61 is in direct contact with the top surface of the lead-out contact layer 5, and may also directly contact a portion of the second electrode layer 43 adjacent to the lead-out contact layer 5, and the bottom of the second contact 62 is in direct contact with the top surface of the exposed portion of the first electrode layer 41.

[0067] In some embodiments, the material of the interlayer dielectric layer 7 may be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In an exemplary embodiment of this disclosure, the material of the interlayer dielectric layer 7 is silicon oxide. In some embodiments, the deposition method of the interlayer dielectric layer 7 may be at least one of the following deposition methods: chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), spin coating dielectric layer (SOD), in-situ water vapor growth (ISSG), and thermal oxidation growth.

[0068] In another exemplary embodiment of this disclosure, a plurality of grooves 22 extending along a preset direction are formed in the interposer layer 1. The plurality of grooves 22 are spaced apart in a direction perpendicular to the preset direction. Moreover, in a direction perpendicular to the preset direction, a plurality of holes 21 connected by adjacent grooves 22 are arranged alternately, as shown in FIG7. FIG7(a) is a top view of the interposer layer 1 in the opposite direction along the Z direction. FIG7(b) is a cross-sectional view along the dashed line A-A' in FIG7(a). FIG7(c) is a cross-sectional view along the dashed line A-A' in FIG7(a). Figure 7(d) shows a cross-sectional view along the dashed line B-B' direction in Figure 7(a), and Figure 7(e) shows a cross-sectional view along the dashed line D-D' direction in Figure 7(b). The cross-sections along the dashed line A-A' and B-B' are perpendicular to each other and both perpendicular to the top surface of the intermediate layer 1. The cross-sections along the dashed line C-C' and B-B' are parallel to each other, and the cross-sections along the dashed line D-D' are parallel to the top surface of the intermediate layer 1.

[0069] In this embodiment, apart from the method step of simultaneously forming multiple trenches 22 extending along a preset direction and arranging them at intervals in a direction perpendicular to the preset direction, the remaining method steps for forming the low dielectric layer 3, forming the capacitor 4, forming the lead-out contact layer 5, forming the interlayer dielectric layer 7, and the first contact 61 and the second contact 62 in the trenches 22 and the holes 21 are all the same as the method steps described in the previous embodiment, and will not be repeated here.

[0070] In some embodiments, as shown in Figures 7(a)-7(e), the slots 21 and the lead-out contact layers 5 are arranged in a hexagonal close-packed configuration. The first contact 61 and the second contact 62 can be arranged in a hexagonal close-packed configuration with even higher density to achieve a higher integration density while avoiding short circuits or interference between them. In other embodiments, the second contact 62 can be located in other positions, and its number can be reduced accordingly. However, it is necessary to ensure that the first contact 61 and the second contact 62 have a certain distance between them to avoid short circuits or interference between them.

[0071] In some embodiments, referring to FIG8, the intermediary layer 1 further includes a first region 11 and a second region 12 disposed adjacent to each other. In the first region 11, a preset direction is a first direction, i.e., the same as or opposite to the X direction. In the second region 12, a preset direction is a second direction, i.e., the same as or opposite to the Y direction. In some embodiments, the intermediary layer 1 further includes a third region 13 and a fourth region 14 disposed adjacent to each other. The third region 13 has the same preset direction as the second region 12, and the fourth region 14 has the same preset direction as the first region 11. The third region 13 is also adjacent to the first region 11 in the Y direction, and the fourth region 14 is also adjacent to the second region in the Y direction. In other embodiments, the intermediary layer 1 may include more regions, but the preset directions of the adjacent regions must be mutually perpendicular. Regions with mutually perpendicular preset directions can effectively solve problems such as stress in the intermediary layer 1.

[0072] In the above embodiments, multiple trenches 22 extending in different preset directions and through holes 21 are formed in different regions. The subsequent steps of forming a low dielectric layer 3, forming a capacitor 4, forming a lead-out contact layer 5, forming an interlayer dielectric layer 7, and forming a first contact 61 and a second contact 62 in the trenches 22 and holes 21 can be performed simultaneously and are the same as the steps described in the previous embodiments. Therefore, they will not be repeated here.

[0073] In an exemplary embodiment of this disclosure, a semiconductor device is also provided, as shown in FIG9, comprising at least the semiconductor structure 101 of any of the foregoing embodiments, and a chip 201 located on the semiconductor structure 101, wherein the chip 201 and the semiconductor structure 101 are electrically connected via solder ball bumps 401 and / or pads (not shown). In other embodiments, the chip 201 and the semiconductor structure may also be electrically connected via wire bonding. In some embodiments, the interposer 1 in the semiconductor structure 101 further includes interconnection structures such as a redistribution layer 1011 (RDL) and through-silicon vias 1012 (TSV). In some embodiments, the chip 201 may be multiple memory chips stacked on top of each other, such as DRAM chips or NAND FLASH chips, and the chips 201 may be interconnected via bumps or hybrid bonding and through-silicon vias 202 (TSV). In other embodiments, the chip 201 may also be a processor chip or an image sensor chip. In some embodiments, the semiconductor device further includes a substrate 301 on which the semiconductor structure 101 is located, and the substrate 301 and the semiconductor structure 101 can also be electrically connected via solder ball bumps 402. In some embodiments, the substrate 301 can be a glass substrate, an organic substrate, or an insulating substrate, and solder ball bumps 403 are further included below the substrate 301 for connecting to a motherboard or other PCB.

[0074] It should be noted that the semiconductor structure or semiconductor device in the embodiments of this disclosure can be used to fabricate the packaging structure of memory chips, or to fabricate other devices that require the fabrication of capacitor structures in the interposer layer, without further limitations.

[0075] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase-Change Memory (PCM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), Flash Memory, or some integrated storage products or systems-on-a-chip.

[0076] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, include: Intermediate layer (1), wherein the intermediate layer (1) has a hole (21) and a groove (22) extending from the top surface of the intermediate layer (1) toward the interior of the intermediate layer (1); A capacitor (4) is located in the hole (21) and the trench (22). The capacitor (4) includes a first electrode layer (41), a capacitor dielectric layer (42) and a second electrode layer (43) stacked in sequence. The capacitor dielectric layer (42) covers the surface of the first electrode layer (41), and the second electrode layer (43) covers the surface of the capacitor dielectric layer (42). The groove (22) extends along a predetermined direction parallel to the top surface of the intermediary layer (1) and connects to a plurality of holes (21) spaced apart along the predetermined direction. The width of the holes (21) is greater than the width of the groove (22), and the direction of the width is parallel to the top surface of the intermediary layer (1) and perpendicular to the predetermined direction.

2. The semiconductor structure of claim 1, wherein, Also includes: A contact layer (5) is brought out and located in the hole (21), covering the surface of the second electrode layer (43) located in the hole (21) and filling the hole (21).

3. The semiconductor structure according to claim 2, characterized in that, The material of the lead-out contact layer (5) includes copper.

4. The semiconductor structure according to claim 2, characterized in that, Also includes: A first contact (61) and a second contact (62) are located above the capacitor. The first contact (61) is connected to the lead-out contact layer (5), and the second contact (62) is connected to the first electrode layer (41).

5. The semiconductor structure according to claim 4, characterized in that, The slot (21) corresponds one-to-one with the lead-out contact layer (5), and the lead-out contact layer (5) corresponds one-to-one with the first contact element (61).

6. The semiconductor structure according to claim 1, characterized in that, The intermediate layer (1) includes multiple grooves (22), and multiple holes (21) connected by adjacent grooves (22) are arranged alternately along the preset direction.

7. The semiconductor structure according to claim 1, characterized in that, The intermediary layer (1) further includes a first region (11) and a second region (12) arranged adjacent to each other. In the first region (11), the preset direction is a first direction, and in the second region (12), the preset direction is a second direction. The first direction and the second direction are perpendicular to each other.

8. The semiconductor structure according to claim 7, characterized in that, In the first region (11), a plurality of the grooves (22) extend along the first direction and are spaced apart along the second direction. In the second region (12), a plurality of the grooves (22) extend along the second direction and are spaced apart along the first direction.

9. The semiconductor structure according to claim 1, characterized in that, Also includes: A bottom dielectric layer (3) covers at least the bottom and sidewalls of the hole (21) and the trench (22), the bottom dielectric layer (3) being located between the intermediate layer (1) and the first electrode layer (41), the first electrode layer (41) covering the surface of the bottom dielectric layer (3).

10. A method for fabricating a semiconductor structure, characterized in that, include: Provide an intermediary layer (1); Holes (21) and trenches (22) extending from the top surface of the intermediary layer (1) toward the interior of the intermediary layer (1) are formed in the intermediary layer (1); A capacitor (4) is formed in the hole (21) and the trench (22) by sequentially stacking a first electrode layer (41), a capacitor dielectric layer (42) and a second electrode layer (43), wherein the capacitor dielectric layer (42) covers the surface of the first electrode layer (41) and the second electrode layer (43) covers the surface of the capacitor dielectric layer (42). The groove (22) extends along a predetermined direction parallel to the top surface of the intermediary layer (1) and connects to a plurality of holes (21) spaced apart along the predetermined direction. The width of the holes (21) is greater than the width of the groove (22), and the direction of the width is parallel to the top surface of the intermediary layer (1) and perpendicular to the predetermined direction.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, Also includes: An outgoing contact layer (5) is formed in the hole (21) to cover the surface of the second electrode layer (43) located in the hole (21) and to fill the hole (21).

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Also includes: A first contact (61) and a second contact (62) are formed above the capacitor (4), the first contact (61) is connected to the lead-out contact layer (5), and the second contact (62) is connected to the first electrode layer (41); The hole (21) corresponds one-to-one with the lead-out contact layer (5), and the lead-out contact layer (5) corresponds one-to-one with the first contact element (61).

13. The method for fabricating a semiconductor structure according to claim 12, characterized in that, The intermediary layer (1) further includes a first region (11) and a second region (12) arranged adjacent to each other. In the first region (11), the preset direction is a first direction, and in the second region (12), the preset direction is a second direction. The first direction and the second direction are perpendicular to each other. Forming vias (21) and trenches (22) extending from the top surface of the interposer (1) toward the interior of the interposer (1) in the interposer (1) includes: Multiple grooves (22) extending along the first direction and spaced apart along the second direction are formed in the first region (11), and multiple grooves (22) extending along the second direction and spaced apart along the first direction are formed in the second region (12). Multiple holes (21) connected by adjacent grooves (22) are arranged alternately along the preset direction perpendicular to the first direction.

14. The method for fabricating a semiconductor structure according to claim 10, characterized in that, Before forming the capacitor (4) in the hole (21) and the trench (22), the method further includes: forming a bottom dielectric layer (3) in the hole (21) and the trench (22) to at least cover the bottom and sidewalls of the hole (21) and the trench (22); The bottom dielectric layer (3) is located between the intermediate layer (1) and the subsequently formed first electrode layer (41), and the first electrode layer (41) covers the surface of the bottom dielectric layer (3).

15. A semiconductor device, characterized in that, include: The semiconductor structure (101) as described in any one of claims 1-9; A chip (201) is located on the semiconductor structure (101); The chip (201) and the semiconductor structure (101) are electrically connected through solder ball bumps (401) and / or solder pads.

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