Amplifier-less potentiostat architecture for electrochemical sensing

Abstract

A potentiostat architecture includes one or more feedback loops configured to regulate and maintain electrode potentials while measuring a sensing current. At least one of the feedback loops include a comparator configured to sense a voltage difference and output a signal based on the voltage difference, a digital loop filter configured to receive the signal from the comparator and output feedback digital bits related to a control, and a digital to analog convertor configured to receive the signal from the comparator and output feedback digital bits related to a control.

Description

Atty. Dkt. No.: 046434-0936AMPLIFIER-LESS POTENTIOSTAT ARCHITECTURE FOR ELECTROCHEMICAL SENSING CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority to U.S. Provisional Patent App. No.63 / 720,626 filed on November 14, 2024, the disclosure of which is incorporated herein by reference in its entirety for all purposesTECHNICAL FIELD

[0002] The present disclosure relates generally to an amplifier-less potentiostat architecture for electrochemical sensing.BACKGROUND

[0003] Electrochemistry has been used to understand the relationship between electrical signals and chemical reactions. Electrochemical sensing plays a pivotal role in the advancement of a variety of fields, such as health-monitoring wearables and implantable diagnostics. In comparison to other sensing systems, such as optical, chromatographic, and magneto-elastic systems, electrochemical sensing typically takes up less space, has higher accuracy, and has a shorter response time. Potentiostats are critical components in this, as they facilitate high-precision current measurements for electrochemical biosensors. Potentiostats interface with a multiple-electrodes electrochemical cell to regulate the required voltages and measure the sensor currents. However, applications of potentiostats, including implantable diagnostics, require limited power budget in the sub-microwatts (pW) range and wide variations of the inputted sensing current, spanning the picoampere (pA) to microampere (pA) range. This poses challenges on potentiostats in terms of achieving high precision, while maintaining power efficiency. These requirements are increasingly crucial in applications, such as single-molecule biosensors, where the desired sensing currents exist within the nanoampere (nA) range. Achieving high precision in measurements, while also consuming ultra-low power is imperative with these conditions. Existing potentiostats attempt to achieve a wide dynamic range (DR) with a low power usage, but these are often noisy and utilize circuit components, such as amplifiers, which increase total power consumption; therefore, being unsuitable for use in electrochemical biosensing.Atty. Dkt. No.: 046434-0936SUMMARY

[0004] One aspect of the present disclosure is directed towards a system for electrochemical sensing. The system includes a working electrode, a reference electrode, and a counter electrode. The reference electrode and the working electrode have a potential difference that is maintained at a fixed value. The potential difference indues a reaction that causes a sensing current to change over time. The system for electrochemical sensing includes a potentiostat architecture that measures the sensing current.

[0005] One aspect of the present disclosure is directed towards a potentiostat architecture. The potentiostat architecture includes one or more feedback loops configured to regulate and maintain electrode potentials while measuring a sensing current. At least one of the feedback loops include a comparator, a digital loop filter, and a digital to analog convertor. In some embodiments, at least one of the feedback loops also includes a switch buffer configured to reduce loading effects from transistors in the digital to analog convertor. In some embodiments, the potentiostat architecture includes at least one background feedback loop. In such embodiments, the at least one background feedback loop is configured to regulate and maintain electrode potentials of a background working electrode.

[0006] In some embodiments, the potentiostat architecture includes two or more feedback loops. In some embodiments, at least one of the feedback loops is configured to regulate an electrode potential of a working electrode, at least one of the feedback loops is configured to regulate a reference voltage of a reference electrode, and a potential difference between the reference voltage and the electrode potential is maintained at a value while the sensing current is measured at a counter electrode.

[0007] One aspect of the present disclosure is directed towards a potentiostat architecture. The potentiostat architecture includes a first feedback loop configured to regulate a working electrode potential and a second feedback loop configured to regulate a reference electrode potential. The first feedback loop includes a first comparator configured to sense a voltage difference and output a signal based on the voltage difference, a first digital loop filter configured to receive the signal from the first comparator and output feedback digital bits related to a control, and a first digital to analog convertor configured to adjust an output of a sensing current to an electrochemical cell based on the control from the first digital loop filter.Atty. Dkt. No.: 046434-0936The voltage difference is between the working electrode potential and the reference electrode potential.

[0008] In some embodiments, the first feedback loop is configured to supply the sensing current into the electrochemical cell. In some embodiments, the second feedback loop includes a second comparator configured to sense a second voltage difference between the reference electrode potential and a second reference electrode potential and output a second signal based on the second voltage difference, a second digital loop filter configured to receive the second signal from the second comparator and output feedback digital bits related to a second control, and a second digital to analog convertor configured to adjust an output of a second sensing current to the electrochemical cell based on the second control. In some embodiments, the second feedback loop is configured to sink the second sensing current from the electrochemical cell into the second digital to analog convertor.

[0009] In some embodiments, the potentiostat architecture further includes a background feedback loop configured to regulate and maintain electrode potentials of a background working electrode. The background feedback loop includes a background digital to analog convertor configured to adjust an output of a background sensing current to the electrochemical cell. In some embodiments, the second feedback loop includes a second digital to analog convertor configured to sink a second sensing current from the electrochemical cell and the second sensing current is a sum of the background sensing current and the sensing current.

[0010] One aspect of the present disclosure is directed towards a potentiostat architecture. The potentiostat architecture includes a feedback loop configured to regulate a reference electrode potential. The feedback loop includes a comparator configured to sense a voltage difference between the reference electrode potential and a second reference electrode potential and output a signal based on the voltage difference, a digital loop filter configured to receive the signal from the comparator and output feedback digital bits related to a control, and a digital to analog convertor configured to sink a sensing current from an electrochemical cell based on the control from the digital loop filter. The potentiostat architecture is configured to maintain a given potential difference between a supply voltage and the reference electrode potential.Atty. Dkt. No.: 046434-0936

[0011] In some embodiments, the digital to analog convertor includes power transistors that are binary-weighted and the feedback loop further includes a switch buffer to reduce loading effects from the power transistors in the digital to analog convertor.

[0012] In some embodiments, a potentiostat of the potentiostat architecture is configured to operate at a frequency proportional to a power consumption of the potentiostat.

[0013] It should be appreciated that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as being part of the subject matter disclosed herein.BRIEF DESCRIPTION OF THE FIGURES

[0014] The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understanding that these drawings depict only several implementations in accordance with the disclosure and are therefore not to be considered limiting of its scope, the disclosure will be described with additional specificity and detail through use of the accompanying drawings.

[0015] FIG. 1 shows a system for electrochemical sensing, according to an exemplary embodiment.

[0016] FIG. 2 is a diagram of a potentiostat that can be integrated into the system of FIG.l, according to an exemplary embodiment.

[0017] FIG. 3 is a diagram of a potentiostat that can be integrated into the system of FIG.l, according to an exemplary embodiment.

[0018] FIG. 4 is a diagram of a potentiostat that can be integrated into the system of FIG.l, according to an exemplary embodiment.

[0019] FIG. 5 is a diagram of a potentiostat that can be integrated into the system of FIG.l, according to an exemplary embodiment.Atty. Dkt. No.: 046434-0936

[0020] FIG. 6A shows a schematic of a digital loop filter, according to an exemplary embodiment. FIG. 6B shows a schematic of an external clock for the digital loop filter of FIG. 6A

[0021] FIG. 7 shows example output waveforms of the potentiostat in FIG. 4.

[0022] FIGS. 8A-8B show a schematic of current-steering digital to analog convertors, according to an exemplary embodiment. FIG. 8A shows a current-souring digital to analog convertor and FIG. 8B shows a current-sinking digital to analog convertor.

[0023] FIG. 9 shows simulated outputs of the potentiostat in FIG. 5, according to exemplary embodiments.

[0024] FIG. 10 shows simulated outputs of the potentiostat in FIG. 4, according to exemplary embodiments.

[0025] FIG 11A-11B shows concentration measurement results of the potentiostat in FIG. 4, according to an exemplary embodiment. FIG 11A shows a relationship between concentration values and outputs of the potentiostat in FIG. 4. FIG 11B shows a relationship between periodic increases in concentrations and outputs of the potentiostat in FIG. 4.

[0026] Reference is made to the accompanying drawings throughout the following detailed description. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative implementations described in the detailed description, drawings, and claims are not meant to be limiting. Other implementations may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and made part of this disclosure.DETAILED DESCRIPTION

[0027] Electrochemical sensing is a sensing approach used for understanding the relationship between electrical signals and chemical reactions. Electrochemical sensors can be used to measure gases, ions, and biological elements by using the electrochemicalAtty. Dkt. No.: 046434-0936properties of the element and measuring the current generated through a multi-electrode system.

[0028] Amperometric sensing is a class of electrochemical sensing that provides quantitative information of an element by measuring the current resulting from the oxidation or reduction of the element. A common application of amperometric sensing is in glucose monitoring. In this application, glucose reacts with an element, usually oxygen, and undergoes oxidation. Glucose levels are estimated by measuring the current generated which is proportional to glucose concentration.

[0029] Potentiostats may be interfaced with an electrochemical cell to regulate the electrode potential between working electrodes and reference electrodes and measure the sensor currents. As the first step in measuring electrochemical sensor currents, it is critical the potentiostats facilitate high-precision current measurements for the biosensors, while ensuring low power consumption in wide variations of sensing currents.

[0030] Conventional potentiostats regulate the potential differences between the WE voltage and RE voltage using resistive or capacitive-transimpedance amplifiers and an analog-to-digital convertor (ADC). The use of amplifiers increases power consumption, and the use of an ADC increases area overhead. When measuring small and large currents, the amplifier consumes a large current for maintaining a low noise and matching the input current, respectively. This leads to a limited current operating range; therefore, also a limited dynamic range.

[0031] Embodiments described herein relate generally to a reconfigurable potentiostat, which may be interfaced with a multi-electrode electrochemical cell for electrochemical sensing. The present disclosure aims to address the problem of high power-consumption, limited dynamic range, and non-linearity in current potentiostat systems. The present disclosure could enhance the efficiency of biosensing in areas such as glucose monitoring. For example, the power consumption of the potentiostat may be reduced to less than 4 nanowatts (nW) across a current sensing range from 80 pA to 240 pW, corresponding to a dynamic range of approximately 129.5 decibels (dB).Atty. Dkt. No.: 046434-0936Electrochemical Sensor Model

[0032] FIG. 1 depicts a system 100 for electrochemical sensing, according to a particular embodiment. The system 100 includes an electrochemical cell 102, which includes a reference electrode RE, a working electrode WE, and a counter electrode CE. In some embodiments, there can be more than one working electrode. The reference electrode RE stabilizes the working electrode WE with negligible current, creating a fixed potential difference VCELL across the reference electrode RE and the working electrode WE. This potential difference VCELL induces a reaction which causes a change in the sensing current passed at the counter electrode CE.

[0033] The sensing current ISENSE generated at the counter electrode CE is supplied as an input to the current-readout circuitry 114 for measuring. The current-readout circuitry includes an analog frontend, such as a potentiostat, shown as potentiostat 116 and digitization 118.

[0034] At the potentiostat 116, the sensing current supplied is measured. The potentiostat 116 can use a variety of circuitry components to covert the sensing current into a voltage or frequency domain. At digitization 118, digitization is performed using analog-to-digital convertor.

[0035] In some embodiments, the potentiostat 116 is amplifier-less and digitally controlled. A potentiostat architecture of the potentiostat 116 is based on dual-side regulated (DSR) feedback loops, as is shown in FIG. 2. In this embodiment, the potentiostat 116 includes two working electrodes, labelled WEM (main working electrode) and WEBG (background working electrode), which provide for the capability of differential sensing. Both working electrodes and a control electrode, labelled CE, are connected to current sources which are digitally controlled by clocked comparators and counters within feedback loops of the potentiostat architecture of the potentiostat 116. Alternatively, the potentiostat 116 may be interfaced with the electrochemical cell, including the two working electrodes and the control electrode, such that the potentiostat 116 connects to the two working electrodes and the control electrode. The feedback loops function like low-dropout regulators, and regulate electrode potentials, labelled VWE (electrode potential of the WEM), VWEBG (electrode potential of the WEBG), and VRE (electrode potential of a reference electrode labelled RE),Atty. Dkt. No.: 046434-0936according to reference voltages, labeled VREF and VREF,RE. The feedback loops also supply currents, labelled ISENSE and ISENSEBG.

[0036] In some embodiments, the potentiostat 116 is amplifier-less and digitally controlled and the potentiostat architecture is based on single-side regulated (SSR) feedback loops, as is shown in FIG. 3. In this embodiment, a working electrode, labelled WE, is connected to a supply voltage, labelled VDD. Only a control electrode, labelled CE, is connected to a current source. The electrode potential of a reference electrode (RE), labelled VRE, is regulated according to a reference voltage labelled VREF, RE. The feedback loop sinks a current labelled ISENSE. The configuration of the DSR and SSR feedback loops eliminate the need for amplifiers, such as a transimpedance amplifier and a separate control amplifier for the control electrode.Example Potentiostat Models interfaced with Electrochemical Sensor Model

[0037] FIGS. 4-5 show the potentiostat 116 that can be used in system 100 according to various embodiments, shown as system 400 in FIG. 4 and system 500 in FIG. 5. FIG. 4 depicts an embodiment of the potentiostat 116 for regulating voltage and measuring a sensing current, in which at least two feedback loops are utilized in the potentiostat architecture. This embodiment utilizes a process similar to what is shown in FIG. 2. Labelling used in FIG. 4 (e.g., VRE, WEM, etc.) are representative of what was shown in FIG. 2.

[0038] The potentiostat 116 of the system 400 includes dynamic latch comparators (labelled in FIG. 4 as ‘Dynamic Latch Comp.’), digital loop filters, switch buffers, and current-steering DACs. This configuration eliminates the need for amplifiers. The feedback loops control the current-steering DACs based on comparative results and maintain VWE and VRE while measuring ISENSE and ISENSEBG. The potentiostat 116 includes feedback loops for WEM, and CE, herein called WEM loop and CE loop, respectively. All electrodes are connected to current sources, which represents the electrochemical cell 102.

[0039] A dynamic latch comparator in the WEM loop, herein called first comparator, senses a voltage difference between VREF and VWE, and outputs a signal based on the voltage difference, the output labelled UDi. Although a dynamic latch comparator is used in this embodiment, it can be appreciated by those skilled in the arts that other comparators (e.g., static, etc.) may be used. UDi is outputted as a Boolean of 1 or 0. The first comparator has zero static power and a small input-referred offset due to four transistor switches.Atty. Dkt. No.: 046434-0936

[0040] UDi is sent to a digital loop filter in the WEM IOOP, herein called first DLF, and generates feedback digital bites DOUT[9:0], FIG. 6 A shows a circuit schematic of a digitalloop filter according to an exemplary embodiment. This schematic applies to the first DLF. The digital loop filter operates as a low-pass filter and a loop controller. The digital loop filter includes a UD clock and a counter. The UD clock generates a counter clock CCLK by processing an external clock Fs, UD, which is the output of the dynamic latch comparator (e.g., UDi), and DOUT[9:0] through a chain of NOR and AND gates, as shown schematically in section 602 of FIG. 6B. The counter counts up or down on each rising edge of CCLK according to UD, as shown schematically in section 604. When UD is 0, the counter counts up and keeps generating DOUT[9:0] until UD changes. Once UD is 1, the counter starts counting down. When steady state is reached (e.g., VWE reaches the voltage of VREF), UD toggles between 0 and 1, resulting in the DOUT[9:0] toggling between up-count and downcount. The digital loop filter does not reset to 0 and keeps the previous counted value at the end of each pass through the feedback loop (e.g., WEM loop), allowing it to operate as a loop controller. The outputs of UDi and DOUT[9:0] as VWE reaches steady state is shown in FIG.7.

[0041] FIGS. 8 A and 8B show a circuit schematic of a DAC according to an exemplary embodiment. The DAC is configured to adjust an output of the sensing current (e.g., via current-sourcing or current-sinking). FIG. 8A includes a current-sourcing DAC 802 and FIG.8B includes a current-sinking DAC 804. In the potentiostat 116, the DAC in the WEM loop is current-sourcing and the DAC in the CE loop is current-sinking. The DACs include power transistors, and the gates of these power transistors are controlled with cascode-biasing currents that generate biasing-voltages. The power transistors are used with binary-weighted transistors sizing to achieve a fast switching speed and a wide current range. In this example 10-bit DACs are used, which results in the size of MSB reaching to 1024. This may lead to severe area overhead and routing issues, and the DAC may not be able to accurately match the small ISENSE for small currents. To achieve high resolution for accurate matching of ISENSE, on-resistance (TON) is used. LSB transistors of the DACs are sized to have TON / 8, which leads to the MSB size of 64*roN for a 10-bit DAC. This binary -weighted sizing can significantly reduce the silicon area and routing issues while achieving high resolution.

[0042] The DAC in the WEM loop includes p-channel metal-oxide-semiconductor (PMOS) power transistors that supply PMOS current, labelled IPM. IPM is equal to ISENSE. TheAtty. Dkt. No.: 046434-0936first DLF corresponds to the ISENSE value in digital and outputs DOUT[9:0] to control (e.g., turn on or off) the PMOS power transistors. In some embodiments, as is shown in FIG. 4, DOUT[9:0] is passed through a switch driving buffer before reaching the DAC to avoid any loading effects from the PMOS power transistors.

[0043] In some embodiments, as shown in FIG. 4, the system 400 includes a background working electrode WEBG. In such embodiments, the potentiostat is interfaced with the WEBG for a capability of differential sensing. The system 400 includes a background feedback loop for WEBG, herein called WEBG loop. The WEBG loop is configured the same as the WEM loop to supply a background sensing current ISENSEBG. In various embodiments, the system 400 does not include the background working electrode WEBG. In various embodiments, the system 400 includes more than one background working electrode WEBG.

[0044] To maintain a given potential difference VOELL between the WE and the RE, VREF,RE is applied to the dynamic latch comparator in the CE loop, herein called second comparator. The second comparator is configured similar to the first comparator, but senses a voltage difference between VREF,RE and VRE, and outputs a signal labelled UTh. The second comparator has zero static power and a small input-referred offset due to four transistor switches.

[0045] UTh is sent to the digital loop filter in the CE loop, herein called second DLF, and generates feedback digital bits. The second DLF is configured as shown in FIG. 6. When steady state is reached (e.g., VRE reached VREF,RE), UD2 toggles between 0 and 1, resulting in the feedback digital bits toggling between up-count and down count.

[0046] As shown in FIG. 8B, the DAC for the CE loop is the current-sinking DAC 804. The DAC in the CE loop includes n-channel metal-oxide-semiconductor (NMOS) power transistors that supply NMOS current, labelled INM. In some embodiments, as is shown in FIG. 4, the feedback digital bits are passed through a switch driving buffer before reaching the DAC to avoid any loading effects from the NMOS power transistors.

[0047] Because the feedback loops in the potentiostat 116, as is shown in FIG. 4, operates similar to a digital low-dropout regulator, the small dropout voltage (in some embodiments, < 50 mV) allows enough VCELL between the WE and the RE to meet sensing requirements.Atty. Dkt. No.: 046434-0936

[0048] In some embodiments, as is shown in FIG. 4, VRE is matched with ISENSE + ISENSEBG for differential sensing. The CE loop is configured to sink the sum of the currents, ISENSE + ISENSEBG, to maintain VRE. In embodiments where the potentiostat 116 uses a single working electrode, VRE is matched with ISENSE. The potentiostat 116 can be reconfigured to multi-sensing by increasing the number of background working electrodes, therefore increasing the number of background feedback loops and matching VRE to the sum of the sensing current from each background feedback loop of the background working electrodes.

[0049] FIG. 5 depicts an embodiment of the claimed potentiostat for regulating the voltage and measuring sensing current in which only one feedback loop is utilized in the potentiostat architecture. This embodiment utilizes a process similar to what is shown in FIG.3. Labelling used in FIG. 5 (e.g., VRE, WE, etc.) is representative of what is shown in FIG. 3.

[0050] The potentiostat 116 of the system 500 includes a dynamic latch comparator (labelled ‘dynamic latch comp.’ in FIG. 5), a digital loop filter (DLF), a switch buffer, and a current steering DAC. This configuration eliminates the need for amplifiers. The potentiostat 116 includes a feedback loop that controls the current-steering DAC based on comprative results and regulates and maintains VRE while sinking ISENSE. In this embodiment, CE is connected to a current source, while WE is supplied with a supply voltage VDD.

[0051] To maintain a given potential difference VOELL between VDD and VRE, VRE is regulated according to VREF, RE by sinking a NMOS current INM equal to ISENSE through the dynamic latch comparator, the DLF, and the current-steering DAC in a process similar to the CE loop in FIG. 4. VREF, RE is applied to the dynamic latch comparator. The dynamic latch comparator is configured similar to the first comparator in FIG. 4, but senses a voltage difference between VREF, RE and VRE, and outputs a signal labelled UD2. Although a dynamic latch comparator is used in this embodiment, it can be appreciated by those skilled in the arts that other comparators (e.g., static, etc.) may be used. The dynamic latch comparator has zero static power and a small input-referred offset due to four transistor switches.

[0052] UD2 is sent to the DLF and generates feedback digital bits DOUT[9:0], The DLF is configured as shown in FIG. 6A. When steady state is reached (e.g., VRE reached VREF, RE), UD2 toggles between 0 and 1, resulting in the DOUT[9:0] toggling between up-count and down count.Atty. Dkt. No.: 046434-0936

[0053] The DAC is current-sinking and includes n-channel metal-oxide-semiconductor (NMOS) power transistors that supply a current INM. In some embodiments, as is shown in FIG. 4, the DOUT[9:0] is passed through a switch driving buffer before reaching the DAC to avoid any loading effects from the NMOS power transistors.

[0054] The feedback loops may include more than one digital loop filters, comparators, and DACs. Additionally, various types of digital loop filters, comparators, and DACs may be used as previously discussed. The potentiostat 116 may operate over a wide frequency range from 0.001 megahertz (MHz) to 100 MHz, and a wide supply voltage range from 1 volt (V) to 1.8 V. The power consumption of the potentiostat 116 is proportional to the frequency and the settling time of the system is inversely proportional to the frequency. Therefore, by controlling the frequency, the potentiostat can be reconfigured to fit a power and time constraint. In addition, the potentiostat 116 as shown in FIG. 5 that utilizes only one feedback loop consumes less area than the potentiostat 116 as shown in FIG. 4 that utilizes two or more feedback loops.Examples

[0055] The system 500 was evalutated by performing simulations as shown in FIG. 9. The system 500 was set to a condition of VDD at 1.2 V, VREF,RE at 0.7 V, and the frequency at 1 kilohertz (kHz). Output digital code DOUT,NM linearity is measured at 3 IDAC biasing currents (IBIAS) of 1 nA, 100 nA, and 10 pA, which is shown in FIG. 9. The system 500 detects ISENSE from 100 pA to 490 pA and converts to output digital code DOUT,NM. This corresponds to an overall dynamic range of 133.8 dB. In this example, system 500 consumes less than 3.24 nW of power across the entire sensing range of 100 pA to 490 pA.

[0056] An oscilloscope capture of the system 400 was utilized to measure transient response. VREF, VREF,RE, and VDD were set to 1.1 V, 0.6 V, and 1.2 V, resepectively, with ISENSE and the frequency at 1 pA and 1 kHz, respectively. The oscilloscope capture showed that it takes 10.5 miliseconds for VWE and VRE to reach steady state, which is 1.1 V and 0.6 V, respectively. The feedback loops in the system 400 allow for the potential difference 0.5 V to be regulated an maintatined between the WE and the RE.

[0057] The system 400 was evalutated by performing simulations as shown in FIG. 10. The system 400 was set to a condition of VDD at 1.2 V, VREF at 1.1 V, VREF, RE at 0.6 V, and the frequency at 1 kHz. Output digital code Dour linearity is measured at 5 IDAC biasingAtty. Dkt. No.: 046434-0936currents (IBIAS) of 10 pA, 1 nA, 10 nA, 100 nA, and 5 A, which is shown in FIG. 10. The system 400 detects ISENSE from 80 pA to 240 pA and converts to output digital code Dour. This corresponds to an overall dynamic range of 129.5 dB. In this example, system 400 consumes less than 3.7 nW of power across the entire sensing range of 80 pA to 240 pA.

[0058] The system 400 was tested with a commercial three-electrode glucose-oxidase-based biosensor. In this biosensor, the WE is platinum and the RE is silver. Chronoamperometry measuremnts, shown in FIG. 11A-B are performed at the potential difference VCELL set to 0.5 V, which was regulated with the system 400 at a frequency of 1 kHz. FIG. 11A shows the output digital code Dour for glucose concentration from 1 millimolar (mM) to 5 mM. The output digital code Dour achieves a linearity of 0.9876 for the glucose concentration. FIG. 11B shows the output digital code Dour as the glucose concentration is increased by 1 mM at an interval of two minutes. With each increase in the glucose concentration, the output digital code Dour rises and the stabilizes at a new value within approximately one minute.Definitions.

[0059] Having now described some illustrative implementations, it is apparent that the foregoing is illustrative and not limiting, having been presented by way of example. In particular, although many of the examples presented herein involve specific combinations of method acts or system elements, those acts and those elements can be combined in other ways to accomplish the same objectives. Acts, elements, and features discussed in connection with one implementation are not intended to be excluded from a similar role in other implementations or implementations.

[0060] As used herein, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, the term “a member” is intended to mean a single member or a combination of members, “a material” is intended to mean one or more materials, or a combination thereof.

[0061] As used herein, the terms “about” and “approximately” generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, about 1000 would include 900 to 1100.Atty. Dkt. No.: 046434-0936

[0062] It should be noted that the term “exemplary” as used herein to describe various embodiments is intended to indicate that such embodiments are possible examples, representations, and / or illustrations of possible embodiments (and such term is not intended to connote that such embodiments are necessarily extraordinary or superlative examples).

[0063] As used herein, the terms “coupled,” “connected,” and the like mean the joining of two additional intermediate members being integrally formed as a single unitary body with one another or with the two members or the two members and any additional intermediate members being attached to one another.

[0064] Various embodiments are described in the general context of method steps, which may be implemented in one embodiment by a program product including computerexecutable instructions, such as program code, executed by computers in networked environments. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer-executable instructions, associated data structures, and program modules represent examples of program code for executing steps of the methods disclosed herein. The particular sequence of such executable instructions or associated data structures represents examples of corresponding acts for implementing the functions described in such steps.

[0065] Software and web implementations of the present invention could be accomplished with standard programming techniques with rule-based logic and other logic to accomplish the various database searching steps, correlation steps, comparison steps and decision steps. It should also be noted that the words “component” and “module,” as used herein and in the claims, are intended to encompass implementations using one or more lines of software code, and / or hardware implementations, and / or equipment for receiving manual inputs.

[0066] It is important to note that the construction and arrangement of the various exemplary embodiments are illustrative only. Although only a few embodiments have been described in detail in this disclosure, those skilled in the art who review this disclosure will readily appreciate that many modifications are possible (e.g., variations in sizes, dimensions, structures, shapes and proportions of the various elements, values of parameters, mounting arrangements, use of materials, colors, orientations, etc.) without materially departing from the novel teachings and advantages of the subject matter described herein. Other substitutions,Atty. Dkt. No.: 046434-0936modifications, changes, and omissions may also be made in the design, operating conditions, and arrangement of the various exemplary embodiments without departing from the scope of the present invention.

[0067] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any inventions or of what may be claimed, but rather as descriptions of features specific to particular implementations of particular inventions. Certain features described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Claims

Atty. Dkt. No.: 046434-0936WHAT IS CLAIMED IS:

1. A potentiostat architecture comprising:one or more feedback loops, at least one of the feedback loops comprising:a comparator,a digital loop filter, anda digital to analog convertor, the feedback loops configured to regulate and maintain electrode potentials while measuring a sensing current.

2. The potentiostat architecture of claim 1, wherein at least one of the feedback loops further comprise a switch buffer configured to reduce loading effects from transistors in the digital to analog convertor.

3. The potentiostat architecture of claim 1, wherein the potentiostat architecture comprises two or more feedback loops.

4. The potentiostat architecture of claim 3, wherein:at least one of the feedback loops is configured to regulate an electrode potential of a working electrode;at least one of the feedback loops is configured to regulate a reference voltage of a reference electrode; anda potential difference between the reference voltage and the electrode potential is maintained at a value while the sensing current is measured at a counter electrode.

5. The potentiostat architecture of claim 3, further comprising at least one background feedback loop, the background feedback loops each comprising:a background comparator,a background digital loop filter, anda background digital to analog convertor, each of the background feedback loops configured to regulate and maintain electrode potentials of a background working electrode.

6. A system for electrochemical sensing comprising:a working electrode;a reference electrode, the reference electrode and the working electrode having a potential difference maintained at a fixed value, the potential difference configured to induce a reaction to cause a sensing current to change over time;Atty. Dkt. No.: 046434-0936a counter electrode; andthe potentiostat architecture of claim 1, the potentiostat architecture to measure the sensing current.

7. The potentiostat architecture of claim 1, wherein the potentiostat architecture comprises one feedback loop, the feedback loop comprising:the comparator,the digital loop filter, andthe digital to analog convertor, the feedback loop configured to regulate an electrode potential while measuring the sensing current.

8. The potentiostat architecture of claim 7, wherein the feedback loop further comprises a switch buffer configured to reduce loading effects from transistors in the digital to analog convertor.

9. The potentiostat architecture of claim 7, wherein:the feedback loop regulates a reference voltage of a reference electrode; and a potential difference between the reference voltage and a supply voltage is maintained at a value while the sensing current is measured.

10. A system for electrochemical sensing comprising:a working electrode supplied with a supply voltage;a reference electrode, the reference electrode and the working electrode having a potential difference maintained at a fixed value, the potential difference to induce a reaction to cause a sensing current to change over time;a counter electrode; andthe potentiostat architecture of claim 7, the potentiostat architecture to measure the sensing current.

11. A potentiostat architecture comprising:a first feedback loop configured to regulate a working electrode potential, the first feedback loop comprising:a first comparator configured to sense a voltage difference and output a signal based on the voltage difference,a first digital loop filter configured to receive the signal from the first comparator and output feedback digital bits related to a control, andAtty. Dkt. No.: 046434-0936a first digital to analog convertor configured to adjust an output of a sensing current to an electrochemical cell based on the control from the first digital loop filter; and a second feedback loop configured to regulate a reference electrode potential; wherein the voltage difference is between the working electrode potential and the reference electrode potential.

12. The potentiostat architecture of claim 11, wherein the first feedback loop is configured to supply the sensing current into the electrochemical cell.

13. The potentiostat architecture of claim 11, wherein the second feedback loop, comprises:a second comparator configured to sense a second voltage difference between the reference electrode potential and a second reference electrode potential and output a second signal based on the second voltage difference;a second digital loop filter configured to receive the second signal from the second comparator and output feedback digital bits related to a second control; anda second digital to analog convertor configured to adjust an output of a second sensing current to the electrochemical cell based on the second control.

14. The potentiostat architecture of claim 13, wherein the second feedback loop is configured to sink the second sensing current from the electrochemical cell into the second digital to analog convertor.

15. The potentiostat architecture of claim 11, further comprising a background feedback loop configured to regulate and maintain electrode potentials of a background working electrode, the background feedback loop comprising a background digital to analog convertor configured to adjust an output of a background sensing current to the electrochemical cell.

16. The potentiostat architecture of claim 15, wherein:the second feedback loop comprises a second digital to analog convertor configured to sink a second sensing current from the electrochemical cell; andthe second sensing current is a sum of the background sensing current and the sensing current.Atty. Dkt. No.: 046434-093617. The potentiostat architecture of claim 11, wherein the first feedback loop further comprises a first switch buffer configured to reduce loading effects from transistors in the first digital to analog convertor.

18. A potentiostat architecture comprising:a feedback loop configured to regulate a reference electrode potential, the feedback loop comprising:a comparator configured to sense a voltage difference between the reference electrode potential and a second reference electrode potential and output a signal based on the voltage difference;a digital loop filter configured to receive the signal from the comparator and output feedback digital bits related to a control; anda digital to analog convertor configured to sink a sensing current from an electrochemical cell based on the control from the digital loop filter;wherein the potentiostat architecture is configured to maintain a given potential difference between a supply voltage and the reference electrode potential.

19. The potentiostat architecture of claim 18, wherein:the digital to analog convertor comprises power transistors that are binary-weighted; andthe feedback loop further comprises a switch buffer to reduce loading effects from the power transistors in the digital to analog convertor.

20. The potentiostat architecture of claim 18, wherein a potentiostat of the potentiostat architecture is configured to operate at a frequency proportional to a power consumption of the potentiostat.

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