Thin-film transistors with source / drain-channel interfaces and methods of manufacturing same

Abstract

An example thin-film transistor includes a source including a body of ruthenium metal, a drain, a body of semiconductor channel material extending between the source and the drain, and a source-channel interface positioned between the source and the body of semiconductor channel material. The source-channel interface is in contact with the body of ruthenium metal of the source and the body of semiconductor channel material. The source-channel interface is formed of ruthenium oxide and has a root mean square roughness of less than or equal to 0.3 nm. Such a source-channel interface may be made using reactive sputtering or ozone oxidation.

Description

P14521PC00Thin-Film Transistors with Source / Drain-Channel Interfaces and Methods of Manufacturing SameCross-Reference to Related Applications

[0001] This application claims priority to and the benefit of US 63 / 785,836, filed April 9, 2025, which is incorporated in its entirety herein by reference.Field

[0002] The present disclosure relates to thin-film semiconductor devices, such as thin-film transistors.Background

[0003] The manufacture and operation of thin-film semiconductor devices, such as thin-film transistors (TFTs), are heavily dependent on the structures, materials, and processes used.Summary

[0004] According to an aspect of this disclosure, a thin-film transistor includes a source including a body of ruthenium metal, a drain, a body of semiconductor channel material extending between the source and the drain, and a source-channel interface positioned between the source and the body of semiconductor channel material. The source-channel interface is in contact with the body of ruthenium metal of the source and the body of semiconductor channel material. The source-channel interface is formed of ruthenium oxide and has a root mean square roughness of less than or equal to 0.3 nm.

[0005] The source-channel interface may have a root mean square roughness of less than or equal to 0.2 nm.

[0006] The source-channel interface may be a deposited layer of ruthenium oxide.

[0007] The source-channel interface may be an oxidized portion of the body of ruthenium metal of the source.P14521PC00

[0008] The semiconductor channel material may be tin oxide.

[0009] The drain may include another body of ruthenium metal and the thin-film transistor may further include a drain-channel interface positioned between the drain and the body of semiconductor channel material. The drain-channel interface may be in contact with the body of ruthenium metal of the drain and the body of semiconductor channel material. The drain-channel interface may be formed of ruthenium oxide and may have a root mean square roughness of less than or equal to 0.3 nm.

[0010] According to another aspect of this disclosure, a method of manufacturing a thin-film transistor includes forming a source including a body of ruthenium metal, forming a drain, forming a source-channel interface of ruthenium oxide by exposing the body of ruthenium metal of the source to ozone at a temperature of 400 °C or lower, and forming a body of semiconductor channel material extending between the source and the drain. The source-channel interface is positioned between the source and the body of semiconductor channel material. The sourcechannel interface is in contact with the body of ruthenium metal of the source and the body of semiconductor channel material.

[0011] The method may include forming the source-channel interface of ruthenium oxide by exposing the body of ruthenium metal of the source to ozone at a temperature of between 190 and 235 °C.

[0012] The method may further include removing a native oxide from the body of ruthenium metal of the source prior to forming the source-channel interface.

[0013] The method may include forming a drain-channel interface of ruthenium oxide by exposing another body of ruthenium metal of the drain to ozone at a temperature of 400 °C or lower. The drain-channel interface may be positioned between the drain and the body of semiconductor channel material. The drain-channel interface may be in contact with the body of ruthenium metal of the drain and the body of semiconductor channel material.

[0014] According to another aspect of this disclosure, a method of manufacturing a thin-film transistor includes forming a source including a body of ruthenium metal, forming a drain, forming a source-channel interface of ruthenium oxide on the body of ruthenium metal of theP14521PC00source using reactive sputtering at a temperature of 400 °C or lower. The reactive sputtering includes using a ruthenium metal target and using oxygen as a reactant gas. The method further includes forming a body of semiconductor channel material extending between the source and the drain. The source-channel interface is positioned between the source and the body of semiconductor channel material. The source-channel interface is in contact with the body of ruthenium metal of the source and the body of semiconductor channel material.

[0015] The reactive sputtering may be performed at a temperature of 300 °C or lower.

[0016] The method may further include removing a native oxide from the body of ruthenium metal of the source prior to forming the source-channel interface.

[0017] The method may further include forming a drain-channel interface of ruthenium oxide on another body of ruthenium metal of the drain using the reactive sputtering at the temperature of 400 °C or lower. The drain-channel interface is positioned between the drain and the body of semiconductor channel material. The drain-channel interface is in contact with the body of ruthenium metal of the drain and the body of semiconductor channel material.Brief Description of the Figures

[0018] FIG. 1 is a cross-sectional view of an example thin-film transistor that includes a source / drain channel interface according to the present disclosure.

[0019] FIG. 2A is a cross-sectional view of the thin-film transistor of FIG. 1 under manufacture at the start of a process of treating source / drain metal to obtain a source / drain channel interface according to the present disclosure.

[0020] FIG. 2B is a cross-sectional view of the partially manufactured thin-film transistor after the process started at FIG. 2A is completed.

[0021] FIG. 3 is a flowchart of an example method of manufacturing a thin-film transistor according to the present disclosure.P14521PC00Detailed Description

[0022] During manufacture of a thin-film transistor or TFT, a source material and, optionally, a drain material, may be subjected to a process to form a source-channel interface and, optionally, a drain-channel interface. A source / drain channel interface serves to reduce the off current (leakage current) of the TFT, particularly when the TFT uses an oxide semiconductor that is susceptible to high off currents, such as tin oxide. Examples of such processes to form a source / drain channel interface are described below. Such processes may improve the operational properties of the source / drain channel interface by providing suitable physical characteristics to the source / drain channel interface, such as low roughness. Such processes may additionally or alternatively improve the stability of the source / drain channel interface to reduce the risk of degradation of the interface during subsequent manufacturing processes. In some examples, a process avoids the use plasma, which may reduce the risk of damage to the TFT under manufacture.

[0023] FIG. 1 shows an example TFT 10 according to the present disclosure. The TFT 10 includes a source 12, drain 14, and gate 16. In various examples, the TFT 10 may be manufactured using extended front-end-of-line (xFEOL), middle-of-line (MOL), back-end-of-line (BEOL), and / or back-side (BSide) processes. Such processes are normally performed at lower temperatures (e.g., 400 °C maximum) than front-end-of-line (FEOL) processes, which are commonly used to make complementary metal-oxide-semiconductor (CMOS) devices.

[0024] The TFT 10 is formed with a planar substrate 20. The substrate 20 may be disposed over other transistors or active devices, whether manufactured in accordance with the present disclosure or by another technique. For example, the substrate 20 may be disposed over CMOS devices or TFTs made using xFEOL, MOL, BEOL, and / or BSide processes, such as the TFTs discussed herein, to form three-dimensional (3D) stacks of devices.

[0025] Examples of materials for the substrate 20 include silicon dioxide; silicon nitride; glass; fluorosilicate glass (FSG); a silicon wafer whose surface is processed with wet thermal oxide (WTO) or similar treatment; carbon doped oxide (CDO); organic polymers such as perfluorocyclobutane or polytetrafluoroethylene; organosilicates such as silsesquioxane,P14521PC00siloxane, organosilicate glass; flexible polymer; plastic; etc. Suitable combinations of such materials may also be used.

[0026] An adhesion layer 22 may be formed over the substrate 20 to promote adhesion of material to the substrate 20. The adhesion layer 22 may be formed of titanium nitride, hafnium nitride, or similar material.

[0027] The source 12 is formed of a body of source material 30 disposed on the substrate 20. The source material is a metal, such as ruthenium, cobalt, molybdenum, or chromium; a suitable non-metal or metal-like material, such as polycrystalline silicon or titanium nitride; or an alloy / combination thereof. Alloys or combinations of the aforementioned metals with tin may also be used. The source material is presently preferred to be ruthenium or an alloy / combination where ruthenium is the majority constituent. In this example, the body of source material 30 is formed by sputtering to a thickness of about 25 nm. In other examples, other source thicknesses may be used, such as about 10 nm, 15 nm, 20 nm, 30 nm, etc.

[0028] In this example, the drain 14 is formed of a body of drain material 32 and has the same or similar material and / or structure as the source 12. Accordingly, such material and / or structure may be referred to as “source / drain” to individually or collectively refer to the source 12 and drain 14. In other examples, the drain 14 has a material and / or structure different to the source 12.

[0029] The adhesion layer 22 promotes the adhesion of the bodies of source and drain material 30, 32 to the substrate 20. In other examples, the adhesion layer 22 may be omitted if the source / drain material has suitable adhesion to the substrate 20 without it.

[0030] The body of source material 30 may be subject to a process to form a source-channel interface 40 at least between the body of source material 30 and the body of channel material 50. The process forms a layer or body of oxidized source material (e.g., ruthenium oxide). The source-channel interface 40 may be p-type or operate in a p-type manner, such as in the case of ruthenium oxide. The source-channel interface 40 may function to deplete the channel in at least the region of the body of channel material 50, which is n-type, adjacent the body of source material 30. In this manner, the source-channel interface 40 may serve as a voltage-controlledP14521PC00electron transport barrier, resulting in substantially less current flow through body of channel material 50 when the TFT 10 is off. The source-channel interface 40 may tune the threshold voltage at which TFT 10 turns on to reduce leakage current through TFT 10 in the off state.

[0031] Further, the source-channel interface 40 may also serve to reduce stress induced leakage currents (“SILC”) in TFT 10 by inhibiting the formation of interlayer stress-induced flaws between the body of channel material 50 and the body of source material 30.

[0032] A drain-channel interface 42 may be similarly formed and may have similar characteristics, but it is contemplated that the source-channel interface 40 provides significant benefit without the drain-channel interface 42. The source-channel interface 40 may provide most or all of the benefit.

[0033] In various examples, ruthenium metal bodies of source and drain material 30, 32 are treated to form a very thin layer of ruthenium-oxide channel interface material. For example, the source-channel interface 40 and / or drain-channel interface 42 may have a thickness of less than about 2 or 3 nm. A process may provide self-limiting growth of the channel interface 40, 42 or may provide controlled growth that allows the thickness of the interface to exceed what may be possible with self-limiting growth. Examples of suitable processes will be discussed in further detail below.

[0034] The TFT 10 further includes a body of n-type channel material 50 disposed between the source 12 and drain 14. In this example, the body of channel material 50 is disposed over at least the source / drain channel interfaces 40, 42 of the bodies of source and drain material 30, 32 and over the substrate 20 between the bodies of source and drain material 30, 32. The body of channel material 50 is a metal oxide. In this example, the body of channel material 50 is a layer of tin oxide, which is primarily or entirely tin (IV) oxide (SnCh), with a thickness of about 5 nm to about 10 nm. In this example, the layer of tin oxide is about 7 nm thick.

[0035] In various examples, the tin oxide forming the body of channel material 50 is generally polycrystalline with a preferred crystallite orientation of Miller index <110>, as determined using grazing-incidence x-ray diffraction (GI-XRD) with co = 0.5° on 20 nm and / or 40 nm thickP14521PC00samples. Polycrystalline tin oxide with this preferred crystal orientation provides good carrier mobility and good stability, which improves the performance and useful life of the TFT 10.

[0036] For sake of clarity, tin oxide with an orientation of <110> means that one of the directions in the family of directions <110>, such as direction

[0110] , is substantially normal to the plane of the substrate 20. In other words, a plane of the family {110}, such as the plane (110), is substantially parallel to the plane of the substrate 20.

[0037] The crystallinity of the thin film of tin oxide is preferably at least about 80%, more preferably at least about 85%, more preferably at least about 90%, and still more preferably at least about 95%. Regions outside the 20 angular range of 20 - 60° may be ignored when computing crystallinity.

[0038] It is important to note that GI-XRD measurements may be performed on thicker samples of tin oxide (e.g., 20 nm or 40 nm) to provide sufficient accuracy, as the GI-XRD technique is known to lose accuracy as film thickness decreases. While 20 nm and 40 nm are considerably thicker than the body of channel material 50 (about 5 - 10 nm, e.g., 1 nm) discussed above, GI-XRD may still be used to establish useful process parameters. Forming process parameters may be established by having a thicker film, such as 20 nm or 40 nm, take the preferred crystal orientation. A thinner film, such as 7 nm, may then be deposited using these established process parameters. If the thinner film performs sufficiently well, then the process parameters are useful. While it is contemplated that the thinner film will have the same or similar crystal orientation as the thicker film, this need not be confirmed with measurement.

[0039] The TFT 10 further includes a body of gate dielectric material 52 disposed over the body of channel material 50. Examples of gate dielectric materials include high-K dielectric materials, hafnium oxide, silicon dioxide, silicon nitride, zirconium oxide, and aluminum oxide. In this example, the body of gate dielectric material 52 is a layer of hafnium oxide about 5 - 15 nm thick, such as about 12.5 nm thick.

[0040] The TFT 10 further includes a body of gate material 54 (also termed “gate metal”) disposed over the gate dielectric material 52. The gate material is a conductor. Examples of gate materials include tungsten, titanium, titanium nitride, molybdenum, gold, platinum, aluminum,P14521PC00nickel, copper, chromium, hafnium, indium, manganese, iron, vanadium, zinc, tantalum, or alloys / combinations thereof. In this example, the body of gate material 54 is a layer of tungsten about 5 - 40 nm thick, such as about 30 nm thick.

[0041] The TFT 10 further includes a source electrode 60 as part of the source 12 and a drain electrode 62 as part of the drain 14. The source electrode 60 is electrically coupled to the body of source material 30 to conduct current to / from the body of source material 30. Likewise, the drain electrode 62 is electrically coupled to the body of drain material 32 to conduct current to / from the body of drain material 32. Examples of materials for electrodes 60, 62 include the gate materials listed above.

[0042] In operation, when a voltage is applied across the source electrode 60 and the drain electrode 62, and when a suitable voltage is applied to the body of gate material 54, a carrier channel forms in the body of channel material 50, which causes flow of current from source 12 to drain 14. When the voltage is removed, the flow of current is reduced to a very low amount, assisted by the source-channel interface 40 and, optionally, the drain-channel interface 42. On-off ratios of about 1010or greater have been measured.

[0043] FIG. 3 shows a method 100 of manufacturing a TFT, such as the TFT 10. The method 100 may include using xFEOE processes, MOE processes, BEOE processes, and / or BSide processes, or a combination of such. The method 100 may be used to form TFTs over other devices to create a 3D stack of devices.

[0044] The manufacture of materials, layers, and / or features of semiconductor devices is referred to herein as “forming.” As will be apparent to those of ordinary skill in the art, unless otherwise mentioned, “forming” is intended to include all semiconductor manufacturing techniques suitable and applicable therefor including, without limitation, deposition (e.g., chemical vapor deposition or CVD, atomic layer deposition or AED, physical vapor deposition or PVD, etc.), plasma-enhanced / assisted atomic layer deposition (PEALD / PAALD), thermal ALD (T-ALD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, lithography / photolithography, etching, implantation, annealing, oxidation, and similar processes. While examples of specific types of forming are given below, it should be understood that comparable methods of formingP14521PC00may be alternatively or additionally used, unless otherwise mentioned, without departing from the present disclosure.

[0045] The method 100 will now be described with reference to the TFT 10 as an example. This disclosure contemplates that steps of the method 100 may be modified or performed in another order, such as when the method 100 is used to make TFTs of other configurations (e.g., gate-on-bottom devices).

[0046] During manufacture, the TFT 10 in its partially or fully complete state may be subject to high temperatures and / or environments / materials that contain hydrogen, such as a forming gas (z.e., hydrogen and nitrogen mixture) anneal, as may be required for various reasons, such as to stabilize material or to support the forming of material of the TFT 10 or other materials, components, or devices that are formed before or after the TFT 10 is formed. For example, the forming of interlayer dielectric (ILD) may involve forming gas anneal, the use of silane (SiFU) may introduce hydrogen, etc.

[0047] Any suitable number and configuration of anneals may be performed. Annealing may be done at about 400 °C for a suitable time, such as 5 minutes, 10 minutes, 20 minutes, 30 minutes, 1 hour, 2 hours, etc. Higher temperatures and other times may also be suitable. Annealing may be done with forming gas, under vacuum, or other conditions.

[0048] A substrate 20 may be provided or formed as discussed above. An adhesion layer 22 may be formed over the substrate by PEALD, for example.

[0049] At block 102, a layer of source / drain material, e.g., ruthenium, is formed over the substrate 20 or the adhesion layer 22, if used. The source / drain material may be formed by sputtering to a desired thickness.

[0050] The layer of source / drain material is then patterned to form separate bodies of source and drain material 30, 32 and define a gap 68 therebetween. Lithography and etching, such as inductively coupled plasma reactive ion etching (ICP-RIE), may be used to form the bodies of source and drain material 30, 32. The adhesion layer 22, if used and if electrically conductive, should also be etched to avoid shorting the source 12 and drain 14.P14521PC00

[0051] Next, the source-channel interface 40, and optionally the drain-channel interface 42, is formed with the partially completed TFT 70 in the state shown in FIG. 2A to obtain the intermediate structure of the TFT 72 shown in FIG. 2B. This includes using one of the following processes. The examples below contemplate a body of source / drain material 30, 32 that includes ruthenium metal and a source / drain-channel interface 40, 42 that correspondingly includes ruthenium oxide and that further may be primarily or exclusively ruthenium oxide. However, it should be noted that each of the examples below may be applicable to other source / drain metals.

[0052] At block 104, if present, the native oxide is removed from the body of source / drain material 30, 32. This may include placing the partially made TFT 70 into a chamber and then introducing forming gas (e.g., 5% hydrogen and 95% nitrogen) to the partially made TFT 70 at a temperature of between about 20 to 400 °C, such as between about 190 to 280 °C. The forming gas is then evacuated from the chamber.

[0053] Next, at block 106, ozone is introduced to the TFT 70 under manufacture at a temperature of between about 190 and 280 °C for a duration of between 1 to 5 minutes. In some examples, the temperature is controlled to be between about 190 and 235 °C. No plasma is used in conjunction with this ozone treatment. Ozone breaks down and provides an unbonded oxygen to react with the body of source / drain material 30, 32 to form the oxidized source / drain-channel interface 40, 42. This is a self-limiting process, in that the source / drain-channel interface 40, 42 will reach a thickness of no more than about 2 to 3 nm and cease forming regardless of how long the treatment continues. In various tests, the source / drain-channel interface 40, 42 thickness was measured to be about 1.5 nm.

[0054] Ammonia may be introduced with the ozone and this may result in nitrogen being included in the source / drain-channel interface 40, 42, which can increase the stability of the source / drain-channel interface 40, 42 particularly its resistance to hydrogen.

[0055] The native oxide removal and ozone treatment may be performed in sequence in a closed environment whose atmosphere is controlled, such as by vacuum, to prevent inadvertent reformation of native oxide (z.e., an oxide formed in atmospheric air or uncontrolled environment) on the body of source / drain material 30, 32. The closed environment may be anP14521PC00ALD chamber or other tool previously used to form a film of the partially completed TFT 70. The native oxide removal and ozone treatment may be performed at about the same temperature.

[0056] Root mean square roughness (Rq) of the ozone-oxidized source / drain-channel interface 40, 42 has been measured to be 0.15 nm when formed at 190 °C, 0.16 nm when formed at 235 °C, and 0.68 nm when formed at 277 °C. Lower roughness improves operational characteristics of the source / drain-channel interface 40, 42.

[0057] Alternatively, at block 106, a film of ruthenium oxide for the source / drain-channel interface 40, 42 is formed using reactive sputtering. A ruthenium metal target may be used with oxygen as a reactant gas. The temperature of the process may be controlled to be between about 20 to 400 °C and, more specifically, between about 20 to 300 °C. In some examples, oxygen and argon are provided to the sputtering chamber at flow rates of 3 - 9 seem and 20 seem, respectively. In such examples, sputtering power is 60 W and chamber pressure is 2.5 mTorr. In various examples, the duration of reactive sputtering is between about 200 to 400 seconds, such as about 300 seconds. Reactive sputtering is not generally self-limiting, so the process may be performed for a duration that results in the desired thickness of ruthenium oxide for the source / drain-channel interface 40, 42. Examples of suitable thicknesses are less than or equal to about 10 nm, about 5 nm, about 3 nm, and 2 nm, and about 1 nm.

[0058] The native oxide removal and reactive sputtering may be performed in sequence in a chamber whose atmosphere is controlled to prevent inadvertent reformation of native oxide on the body of source / drain material 30, 32. The native oxide removal and reactive sputtering may be performed at about the same temperature.

[0059] Root mean square roughness (Rq) of the reactive sputtered source / drain-channel interface 40, 42 has been measured to be in the range of 0.2 - 0.3 nm. Lower roughness improves operational characteristics of the source / drain-channel interface 40, 42.

[0060] At block 108, after formation of the source / drain-channel interface 40, 42, a layer of semiconductor channel material 50 is formed over at least the source / drain-channel interface 40, 42 of the body of source and drain material 30, 32 and over the substrate 20 within the gap 68 between the bodies of source and drain material 30, 32.P14521PC00

[0061] The layer of channel material 50, e.g., tin oxide, may be formed by PEALD, T-ALD, or similar technique. In various examples, chlorine, fluorine, nitrogen, antimony, or other chemical species may be introduced during the deposition process, so that the layer of channel material 50 includes such species.

[0062] When tin oxide is used as the layer of channel material 50, annealing may be useful to develop and / or maintain the preferred crystallite orientation discussed above. Annealing may be performed immediately after deposition of the layer of channel material 50 or at a later stage. Example anneal parameters are given above.

[0063] At block 110, gate dielectric material is formed over the tin oxide channel material. This may be done in two separate deposition and patterning operations. After an initial deposition of gate dielectric material, the gate dielectric material and underlying channel material may be patterned together using the same mask. Then, to prevent the channel material from shorting to the body of gate material 54, a second layer of gate dielectric material may be deposited and patterned in a manner that encapsulates the channel material, as shown at 66 in FIG. 1.Alternatively, a single deposition and patterning operation may be used to form the gate dielectric material.

[0064] The initial layer of gate dielectric material is formed over the layer of channel material. A layer of hafnium oxide may be formed by PEALD, T-ALD, or similar technique. The initial layer of hafnium oxide may be deposited to a desired thickness, such as about 5 nm.

[0065] The layer of channel material 50 and initial layer of gate dielectric material are then patterned. Lithography and etching, such as ICP-RIE, may be used. The same mask may be used to give the same pattern to both layers. This patterning completes the body of channel material 50.

[0066] The second layer of gate dielectric material is then formed over the patterned initial layer of gate dielectric material. PEALD, T-ALD, etc. may be used, as discussed above. The second layer of hafnium oxide may be deposited to a desired thickness, such as about 7.5 nm.

[0067] The second layer of gate dielectric material is then patterned. Lithography and etching, such as ICP-RIE, may be used. This patterning is configured to form the second layer of gateP14521PC00dielectric material as longer than the initial layer of gate dielectric material and channel material, so that edges of the body of channel material 50 are covered by gate dielectric material, as shown at 66 in FIG. 1. This patterning completes the body of gate dielectric material 52.

[0068] Then, at block 112, a layer of gate material is formed. In this example, the layer of gate material ultimately forms the body of gate material 54 and the source and drain electrodes 60, 62. The layer of gate material may be formed by sputtering material mentioned above. The layer of gate material may then be patterned to form the separate body of gate material 54 and source and drain electrodes 60, 62. Lithography and etching, such as ICP-RIE, may be used. In other examples, the source and drain electrodes 60, 62 are formed in another manner.

[0069] Thus, a transistor 10 of the structure shown in FIG. 1 is formed.

[0070] Further forming may be performed, such as annealing, as may be required for the particular application of the TFT 10.

[0071] A channel interface may be formed using processes different to ozone oxidation and reactive sputtering discussed above. Described below are other processes that may be used with the method 100 at one or both of blocks 104, 106, as the case may be.

[0072] Peroxide oxidation may be used to form a source / drain-channel interface 40, 42.

[0073] First, at block 104, the native oxide is removed from the body of source / drain material 30, 32. This may include introducing a reducing agent, such as nitric acid or tin chloride, to the incomplete TFT 70 at a temperature of between about 20 to 70 °C or, in some examples, 40 to 50 °C. If the reducing agent is a liquid, a wafer or chip containing a multitude of the partially made TFTs 70 may be immersed in the reducing agent. In the case of a gas or vapor phase reducing agent, an enclosed chamber may be used. The reducing agent is then removed.

[0074] Next, at block 106, the partially made TFT 70 is immersed in hydrogen peroxide to form the oxidized source / drain-channel interface 40, 42. This peroxide treatment may be constrained to be at a temperature of between about 20 to 70 °C or, in some examples, 40 to 50 °C. This is a self-limiting process, in that the source / drain-channel interface 40, 42 will reach a thickness of no more than about 2 to 3 nm and cease forming regardless of how long the treatment continues.P14521PC00

[0075] The native oxide removal and peroxide treatment may be performed in sequence in a chemical wet deck or wet bench, within a controlled environment to prevent inadvertent reformation of native oxide on the body of source / drain material 30, 32. The native oxide removal and peroxide treatment may be performed at about the same temperature.

[0076] Nitrous oxidation may be used to form a source / drain-channel interface 40, 42.

[0077] At block 106, nitrous oxide is introduced to the TFT 70 under manufacture at a temperature of between about 20 to 300 °C for a duration of about a few seconds or longer, such as 5 to 10 minutes. No plasma is used in conjunction with the nitrous oxide. The nitrous oxide reacts with the body of source / drain material 30, 32 to form the oxidized source / drain-channel interface 40, 42. This is a self-limiting process, in that the source / drain-channel interface 40, 42 will reach a thickness of no more than about 2 to 3 nm and cease forming regardless of how long the treatment continues.

[0078] Nitrous oxidation may result in nitrogen being included in the source / drain-channel interface 40, 42, which can increase the stability of the source / drain-channel interface 40, 42 particularly its resistance to hydrogen.

[0079] The native oxide removal and nitrous oxide treatment may be performed in sequence in a closed environment whose atmosphere is controlled, such as by vacuum, to prevent inadvertent reformation of native oxide on the body of source / drain material 30, 32. The closed environment may be an ALD chamber or other tool previously used to form a film of the partially completed TFT 70. The native oxide removal and nitrous oxide treatment may be performed at about the same temperature.

[0080] Thermal ALD may be used to form a source / drain-channel interface 40, 42.

[0081] At block 106, a film of ruthenium oxide for the source / drain-channel interface 40, 42 is deposited using thermal ALD. Any suitable precursor and reactant may be used. An example precursor and reactant are bis-(ethylcyclopentadienyl)-ruthenium, also known as Ru(EtCp)2, and oxygen. The T-ALD process may be performed at a substrate temperature of between about 20 to 400 °C. T-ALD is generally not self-limiting. Hence, a number of deposition cycles may be performed to arrive at the desired thickness of ruthenium oxide for the source / drain-channelP14521PC00interface 40, 42. Examples of suitable thicknesses are less than or equal to about 10 nm, about 5 nm, about 3 nm, about 2 nm, and about 1 nm.

[0082] In some examples, a layer of platinum may first be formed over the body of source / drain material 30, 32 to promote the growth of ruthenium oxide using T-ALD.

[0083] The native oxide removal and T-ALD may be performed in sequence with a T-ALD tool with a chamber whose atmosphere is controlled to prevent inadvertent reformation of native oxide on the body of source / drain material 30, 32. The native oxide removal and T-ALD may be performed at about the same temperature.

[0084] PEALD Deposition may be used to form a source / drain-channel interface 40, 42.

[0085] At block 106, a film of ruthenium oxide for the source / drain-channel interface 40, 42 is deposited using plasma-enhanced atomic layer deposition. Any suitable precursor and reactant may be used. An example precursor and reactant are Ru(EtCp)2 and oxygen plasma. The PEALD process may be performed at a substrate temperature of between about 200 to 400 °C. PEALD is not generally self-limiting. Hence, a number of PEALD cycles may be performed to arrive at the desired thickness of ruthenium oxide for the source / drain-channel interface 40, 42. Examples of suitable thicknesses are less than or equal to about 10 nm, about 5 nm, about 3 nm, about 2 nm, and about 1 nm.

[0086] In some examples, a layer of platinum may first be formed over the body of source / drain material 30, 32 to promote the growth of ruthenium oxide using PEALD.

[0087] The native oxide removal and PEALD may be performed in sequence with a PEALD tool with a chamber whose atmosphere is controlled to prevent inadvertent reformation of native oxide on the body of source / drain material 30, 32. The native oxide removal and PEALD may be performed at about the same temperature.

[0088] Ozone ALD may be used to form a source / drain-channel interface 40, 42.

[0089] At block 106, a film of ruthenium oxide for the source / drain-channel interface 40, 42 is deposited using ALD. Any suitable precursor may be used with ozone as a reactant. An example precursor is Ru(EtCp)2. The ALD process may be performed at a substrate temperature ofP14521PC00between about 250 to 300 °C. As ALD is generally not self-limiting, a number of cycles may be performed to arrive at the desired thickness of ruthenium oxide for the source / drain-channel interface 40, 42. Examples of suitable thicknesses are less than or equal to about 10 nm, about 5 nm, about 3 nm, and 2 nm, and about 1 nm.

[0090] The native oxide removal and ALD may be performed in sequence with an ALD tool with a chamber whose atmosphere is controlled to prevent inadvertent reformation of native oxide on the body of source / drain material 30, 32. The native oxide removal and ALD may be performed at about the same temperature.

[0091] Thermal oxidation may be used to form a source / drain-channel interface 40, 42.

[0092] At block 106, a film of ruthenium oxide for the source / drain-channel interface 40, 42 is formed using thermal oxidation. The partially made TET 70 is introduced to a heated environment that contains oxygen. In various examples, flow of oxygen gas is introduced to the partially made TET 70 at about 300 to 600 °C or, in some examples, about 400 to 500 °C. This is a self-limiting process, in that the source / drain-channel interface 40, 42 will reach a thickness of no more than about 2 to 3 nm and cease forming regardless of how long the treatment continues.

[0093] The native oxide removal and thermal oxidation may be performed in sequence in a furnace whose atmosphere is controlled to prevent inadvertent reformation of native oxide on the body of source / drain material 30, 32. The native oxide removal and thermal oxidation may be performed at about the same temperature.

[0094] Ammonia water treatment may be used to form a source / drain-channel interface 40, 42.

[0095] At block 106, a film of ruthenium oxide for the source / drain-channel interface 40, 42 is formed using aqueous ammonia. A mixture of ammonia and water may be introduced as a vapor to a chamber that contains the partially made TET 70. Ammonia may be present in the mixture at a proportion of about 5% to 30%, such as about 5% to 10%. The process may be performed at 400 °C or below, such as betweenl50 and 275 °C or more specifically in certain examples, 190 and 235 °C.P14521PC00

[0096] Ammonia water treatment may result in nitrogen being included in the source / drain-channel interface 40, 42, which can increase the stability of the source / drain-channel interface 40, 42 particularly its resistance to hydrogen.

[0097] The native oxide removal and ammonia water treatment may be performed in sequence in chamber whose atmosphere is controlled to prevent inadvertent reformation of native oxide on the body of source / drain material 30, 32. The native oxide removal and ammonia water treatment may be performed at about the same temperature.

[0098] Other formation processes may be used to form a source / drain-channel interface 40, 42.

[0099] Other formation processes that may be used at block 106 to create the film of ruthenium oxide for the source / drain-channel interface 40, 42 include CVD, PECVD, electron beam evaporation, molecular beam epitaxy (MBE). Such processes may be performed after native oxide removal, as discussed above.

[0100] Auxiliary verbs “can” and “may” are used interchangeably herein to denote components, features, and / or aspects of the present invention that are capable, configurable, selectable, modifiable, or optional, as would be apparent to one of ordinary skill in the art given the benefit of this disclosure. These terms should not be taken as limiting the present invention, unless otherwise specified.

[0101] Spatial prepositions, such as “over”, “under”, “above”, “below”, “up”, “down”, “beside”, etc., are provided for sake of explanation and should not be taken as limiting the present invention to an absolute spatial orientation or arrangement, unless otherwise specified. For example, one of ordinary skill in the art would understand that a first element is above or below a second element depending on the perspective of the observer.

[0102] The articles “a”, “an”, “the”, “said”, etc. indicate singular and plural, unless otherwise specified.

[0103] The conjunction “or” is used inclusively and should be understood to mean “and / or”, unless otherwise specified.P14521PC00

[0104] Sets of elements A, B, C described as A, B, or C; A, B, and C; A, B, and / or C; or A, B, C should be considered open sets from which one or more elements or a combination of one or more elements may be selected, unless otherwise specified. Sets of elements are open, unless specified to be closed, for example, by use of the term “consist”, “consisting”, or similar closed language.

[0105] The above clarifications apply to both the specification and claims.

[0106] The figures are not to scale, unless otherwise specified.

[0107] The above-described embodiments of the invention are intended to be examples of the present invention and alterations and modifications may be effected thereto, by those of ordinary skill in the art, without departing from the scope of the invention which is defined solely by the claims appended hereto.

Claims

P14521PC00Claims1. A thin-film transistor comprising:a source including a body of ruthenium metal;a drain;a body of semiconductor channel material extending between the source and the drain; anda source-channel interface positioned between the source and the body of semiconductor channel material, the source-channel interface being in contact with the body of ruthenium metal of the source and the body of semiconductor channel material;wherein the source- channel interface is formed of ruthenium oxide; andwherein the source-channel interface has a root mean square roughness of less than or equal to 0.3 nm.

2. The thin-film transistor of claim 1 , wherein the source-channel interface has a root mean square roughness of less than or equal to 0.2 nm.

3. The thin-film transistor of claim 1, wherein the source-channel interface is a deposited layer of ruthenium oxide.

4. The thin-film transistor of claim 1 , wherein the source-channel interface is an oxidized portion of the body of ruthenium metal of the source.

5. The thin-film transistor of claim 1, wherein the semiconductor channel material is tin oxide.

6. The thin-film transistor of claim 1, wherein:the drain includes another body of ruthenium metal; andthe thin-film transistor further comprises:P14521PC00a drain-channel interface positioned between the drain and the body of semiconductor channel material, the drain-channel interface being in contact with the body of ruthenium metal of the drain and the body of semiconductor channel material;wherein the drain-channel interface is formed of ruthenium oxide; andwherein the drain-channel interface has a root mean square roughness of less than or equal to 0.3 nm.

7. A method of manufacturing a thin-film transistor, the method comprising:forming a source including a body of ruthenium metal;forming a drain;forming a source-channel interface of ruthenium oxide by exposing the body of ruthenium metal of the source to ozone at a temperature of 400 °C or lower; andforming a body of semiconductor channel material extending between the source and the drain, wherein the source-channel interface is positioned between the source and the body of semiconductor channel material, the source-channel interface being in contact with the body of ruthenium metal of the source and the body of semiconductor channel material.

8. The method of claim 7, comprising forming the source-channel interface of ruthenium oxide by exposing the body of ruthenium metal of the source to ozone at a temperature of between 190 and 235 °C.

9. The method of claim 7, further comprising removing a native oxide from the body of ruthenium metal of the source prior to forming the source-channel interface.

10. The method of claim 7, further comprising:forming a drain-channel interface of ruthenium oxide by exposing another body of ruthenium metal of the drain to ozone at a temperature of 400 °C or lower;P14521PC00wherein the drain-channel interface is positioned between the drain and the body of semiconductor channel material, the drain-channel interface being in contact with the body of ruthenium metal of the drain and the body of semiconductor channel material.

11. A method of manufacturing a thin-film transistor, the method comprising:forming a source including a body of ruthenium metal;forming a drain;forming a source-channel interface of ruthenium oxide on the body of ruthenium metal of the source using reactive sputtering at a temperature of 400 °C or lower, wherein the reactive sputtering includes using a ruthenium metal target and using oxygen as a reactant gas; andforming a body of semiconductor channel material extending between the source and the drain, wherein the source-channel interface is positioned between the source and the body of semiconductor channel material, the source-channel interface being in contact with the body of ruthenium metal of the source and the body of semiconductor channel material.

12. The method of claim 11, wherein the reactive sputtering is performed at a temperature of 300 °C or lower.

13. The method of claim 11, further comprising removing a native oxide from the body of ruthenium metal of the source prior to forming the source-channel interface.

14. The method of claim 11, further comprising:forming a drain-channel interface of ruthenium oxide on another body of ruthenium metal of the drain using the reactive sputtering at the temperature of 400 °C or lower;wherein the drain-channel interface is positioned between the drain and the body of semiconductor channel material, the drain-channel interface being in contact with the body of ruthenium metal of the drain and the body of semiconductor channel material.

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