Imaging element and imaging device

Abstract

Provided is a imaging element comprising: a first semiconductor substrate having a first pixel block among a plurality of pixel blocks including a plurality of photoelectric conversion units that convert light into electric charge, and a second pixel block arranged side by side with the first pixel block in a column direction among the plurality of pixel blocks; and a second semiconductor substrate laminated together with the first semiconductor substrate, and having a first circuit block disposed at a position facing the first pixel block and a second circuit block disposed at a position facing the second pixel block, wherein the first pixel block includes a first photoelectric conversion unit among the plurality of photoelectric conversion units and a second photoelectric conversion unit among the plurality of photoelectric conversion units, the first circuit block includes a first conversion unit that converts a first signal based on the electric charge converted by the first photoelectric conversion unit into a digital signal, and the second circuit block includes a second conversion unit that converts a second signal based on the electric charge converted by the second photoelectric conversion unit into a digital signal.

Description

Image pickup device and imaging apparatus

[0001] The present invention relates to an image pickup device and an imaging apparatus.

[0002] Patent Document 1 describes an image pickup device in which a plurality of pixels are arranged in a two-dimensional array. Conventionally, improvement in image quality has been desired. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-186894 General disclosure

[0003] In a first aspect of the present invention, an image pickup device is provided. The above image pickup device may include a first semiconductor substrate having a plurality of pixel blocks including a first photoelectric conversion unit that converts light into electric charges and a second photoelectric conversion unit that converts light into electric charges. The above image pickup device may include a second semiconductor substrate that is laminated together with the first semiconductor substrate and that has a first circuit block that processes a signal based on the electric charges converted by the first photoelectric conversion unit of the first pixel block among the plurality of pixel blocks, and a second circuit block that processes a signal based on the electric charges converted by the second photoelectric conversion unit of the first pixel block. In the above image pickup device, the first circuit block may be arranged at a position facing the first pixel block in a first direction in which the first semiconductor substrate and the second semiconductor substrate are laminated. In the above image pickup device, the second circuit block may be arranged at a position facing the second pixel block among the plurality of pixel blocks in the first direction.

[0004] In a second aspect of the present invention, an imaging apparatus including any of the above image pickup devices is provided.

[0005] Note that the above summary of the invention does not list all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

[0006] This is a block diagram of the imaging device 10 according to the first embodiment. This is a schematic diagram showing the overall functional block of the image sensor 100 according to the first embodiment. This schematically shows the positional relationship between the area where the pixel section 50 is located and the area where the processing circuit section 160 is located in the image sensor 100 according to the first embodiment. This schematically shows an example of the peripheral circuit section 500 and the pixel block 142 and signal processing block 162 connected to the peripheral circuit section 500 via various wirings in the first embodiment. This schematically shows an example of three of the multiple unit blocks 200 and the peripheral circuit section 500 in the first embodiment. This shows an example of the circuit configuration of a pixel 202. This is a diagram illustrating an example of a driving method for the image sensor 100 according to the first embodiment. This shows an example of the connection configuration between a typical pixel block row and the corresponding circuit block group 245-1, etc., in the image sensor 100 according to the first embodiment. This is a timing chart of an example of a driving method in which each pixel block row is driven sequentially in the image sensor 100 according to the first embodiment. This shows the process of sequentially driving each pixel block row in the example of Figure 8. Figure 8 shows the process of sequentially driving each pixel block row in the example. Figure 8 shows the process of sequentially driving each pixel block row in the example. Figure 8 shows the process of sequentially driving each pixel block row in the example. Figure 8 shows the process of sequentially driving each pixel block row in the example. Figure 8 shows the process of sequentially driving each pixel block row in the example. Figure 8 shows the process of sequentially driving each pixel block row in the example. Figure 8 shows the process of sequentially driving each pixel block row in the example. Figure 8 shows the process of sequentially driving each pixel block row in the example. Figure 8 shows the process of sequentially driving each pixel block row in the example. Another example of the peripheral circuit section 500 and the pixel block 142 and signal processing block 162 connected to the peripheral circuit section 500 via various wirings is schematically shown in the first embodiment. This figure illustrates another example of the driving method of the image sensor 100 according to the first embodiment. Another example of the connection configuration between a typical pixel block row and the corresponding circuit block group 245-1, etc., in the image sensor 100 according to the first embodiment is shown. Three of the multiple unit blocks 200 and another example of the peripheral circuit section 500 according to the first embodiment are schematically shown. This is a schematic diagram showing the functional blocks of the signal processing block 162-1 in the second embodiment.A schematic diagram shows three of the multiple unit blocks 201 and an example of the peripheral circuit section 500 in the second embodiment. An example of the circuit configuration of pixel 202-1 is shown. This is a timing chart of an example of a driving method in which each pixel block row is driven sequentially in the image sensor 100 according to the second embodiment.

[0007] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0008] Figure 1 is a block diagram of an imaging device 10 according to the first embodiment. The imaging device 10 includes an optical system 20, an image sensor 100, an image processing unit 24, a control unit 26, a recording unit 28, an operation unit 30, a display unit 32, and a power supply unit 34. The image sensor 100, image processing unit 24, control unit 26, recording unit 28, operation unit 30, display unit 32, and power supply unit 34 are interconnected via a bus line 36. Note that the imaging device 10 is an example of an electronic device.

[0009] The optical system 20 has a group of lenses and forms an image of the incident light from the subject onto the imaging surface of the image sensor 100 along the optical axis 22. In Figure 1, the Z-axis is shown parallel to the optical axis 22, and the X-axis and Y-axis are shown perpendicular to the Z-axis, and the same applies to subsequent figures.

[0010] The image sensor 100 comprises a plurality of stacked semiconductor substrates, as will be described in more detail later. The plurality of semiconductor substrates include a plurality of photoelectric conversion units that convert light emitted from the optical system 20 into electric charge. More specifically, the image sensor 100 converts the amount of incident light imaged onto the imaging surface by the optical system 20 into an electrical signal for each of the plurality of pixels, each of which includes at least one photoelectric conversion unit, to obtain an analog pixel signal. The image sensor 100 further outputs a pixel signal that has undergone signal processing, such as converting the analog signal into a digital signal. Unless otherwise specified, the "pixel signal" may be in either an analog or digital signal state.

[0011] In the following explanation, the basic time unit for obtaining data for one image may be referred to as 1 frame. 1 frame includes the exposure time of the photoelectric converter and the time for reading pixel values ​​from the photoelectric converter during a single imaging cycle.

[0012] The image sensor 100 also has a plurality of semiconductor substrates, which, as will be described in more detail later, include a plurality of conversion units that convert signals based on the charge converted by the plurality of photoelectric conversion units described above into digital signals.

[0013] The image processing unit 24 is, for example, an ISP (Image Signal Processor) and performs image processing on the pixel signals output from the image sensor 100. This image processing includes, for example, color interpolation, grayscale conversion, and compression.

[0014] The control unit 26 controls the entire imaging device 10, and controls the image sensor 100, image processing unit 24, recording unit 28, operation unit 30, display unit 32, and power supply unit 34 via the bus line 36.

[0015] The recording unit 28 records image data of a subject captured by the image sensor 100 onto a recording medium such as a hard disk or semiconductor memory. This image data may be, for example, moving image data. Alternatively, this image data may be, for example, still image data. The operation unit 30 receives user input. Based on the received input, the operation unit 30 issues operation commands for various functions of the imaging device 10. The display unit 32 is a panel-type display device such as a liquid crystal panel or an organic EL (Electroluminescence) panel. The display unit 32 displays images (moving images or still images) of a subject captured by the image sensor 100. The power supply unit 34 supplies various power sources to the image sensor 100, image processing unit 24, control unit 26, recording unit 28, operation unit 30, and display unit 32.

[0016] Figure 2 is a schematic diagram showing the overall functional block of the image sensor 100 according to the first embodiment. Figure 2 shows the relationship between each functional block and the transmission and reception of signals between them, and does not show the spatial arrangement of the image sensor 100.

[0017] The image sensor 100 comprises a pixel section 50, a drive control section 60, a vertical drive section 62, a signal processing section 64, a horizontal drive section 68, and an output section 70.

[0018] The pixel section 50 has a plurality of pixels. The plurality of pixels are arranged in the pixel section 50 along a first direction and a second direction. The second direction is a direction that intersects the first direction. The first direction is, for example, the row direction. The second direction is, for example, the column direction. Note that the first direction and the second direction may be orthogonal. The plurality of pixels are arranged in a two-dimensional manner in the pixel section 50. Each of the plurality of pixels includes at least one photoelectric conversion unit. The photoelectric conversion unit converts light emitted from the optical system 20 into electric charge.

[0019] The drive control unit 60 drives the image sensor 100. Specifically, the drive control unit 60 receives a clock signal output from the control unit 26 and a signal that commands the operating mode, etc., and drives the image sensor 100. For example, the drive control unit 60 generates a clock signal and control signal that serve as a reference for the operation of the vertical drive unit 62, the signal processing unit 64, and the horizontal drive unit 68, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, and outputs them to the vertical drive unit 62, the signal processing unit 64, and the horizontal drive unit 68. The drive control unit 60 may also receive signals based on charge converted photoelectrically from the pixel unit 50, phase difference information, etc., via the signal processing unit 64, and control multiple pixels of the pixel unit 50 via the vertical drive unit 62, etc., to change the exposure time for each pixel or for several groups of pixels.

[0020] The vertical drive unit 62 drives pixels, for example, in block units, based on the control signal. It can also be said that the vertical drive unit 62 controls the exposure of pixels by the control signal. Furthermore, it can also be said that the vertical drive unit 62 controls the storage time of the charge converted by the photoelectric conversion unit by the control signal. The signal processing unit 64 performs signal processing on the pixel signals from the pixels selected by the vertical drive unit 62. For example, the signal processing unit 64 converts the analog pixel signals read from the pixels into digital pixel signals. The signal processing unit 64 has a conversion unit that converts the analog pixel signals read from the pixels into digital pixel signals. The signal processing unit 64 also has a noise reduction unit that removes noise contained in the pixel signals read from the pixels. The signal processing unit 64 also has a storage unit that temporarily stores the pixel signals after signal processing. The horizontal drive unit 68 sequentially reads the pixel signals stored in the storage unit of the signal processing unit 64 and outputs them to the output unit 70.

[0021] The output unit 70 outputs the pixel signal. The output unit 70 sends the pixel signal read from the storage unit of the signal processing unit 64 to the image processing unit 24. The output unit 70 may perform specific processing on the pixel signal read from the storage unit of the signal processing unit 64 and output it to the image processing unit 24. The specific processing performed by the output unit 70 is, for example, buffering.

[0022] Figure 3 schematically shows the positional relationship between the region where the pixel section 50 is located and the region where the processing circuit section 160 is located in the image sensor 100 according to the first embodiment. The image sensor 100 has a first semiconductor substrate 140 and a second semiconductor substrate 150. The first semiconductor substrate 140 and the second semiconductor substrate 150 are stacked in the Z-axis direction in Figure 3.

[0023] The pixel unit 50 is arranged on the first semiconductor substrate 140. In the following description, the first semiconductor substrate 140 may be referred to as a pixel chip. The pixel unit 50 has a plurality of pixel blocks 142. The plurality of pixel blocks 142 are arranged in the pixel unit 50 along a first direction (for example, the row direction) and a second direction (for example, the column direction). The plurality of pixel blocks 142 are arranged two-dimensionally in the pixel unit 50. In this embodiment, the pixel unit 50 has 81 pixel blocks 142 arranged in a two-dimensional arrangement of 9 rows and 9 columns. Each of the pixel blocks 142 contains a plurality of pixels. The plurality of pixels are arranged in the pixel block 142 along a first direction (for example, the row direction) and a second direction (for example, the column direction). The plurality of pixels are arranged two-dimensionally in the pixel block 142. Each of the plurality of pixels contains at least one photoelectric conversion unit.

[0024] The first semiconductor substrate 140 can be said to have, for example, a plurality of pixel blocks 142 arranged in two dimensions, including a first pixel block and a second pixel block arranged in a column direction with respect to the first pixel block, and each of the plurality of pixel blocks 142 includes a plurality of photoelectric conversion units that convert light into electric charge. Furthermore, the plurality of photoelectric conversion units of the first pixel block can be said to include a first photoelectric conversion unit and a second photoelectric conversion unit.

[0025] The processing circuit section 160, the drive control section 60, the output section 58, the global vertical drive section 152, and the global horizontal drive section 154 are arranged on the second semiconductor substrate 150. The second semiconductor substrate 150 is sometimes referred to as a signal processing chip.

[0026] The processing circuit unit 160 has a plurality of signal processing blocks 162. The plurality of signal processing blocks 162 are arranged in the processing circuit unit 160 along a first direction (for example, the row direction) and a second direction (for example, the column direction). The plurality of signal processing blocks 162 are arranged two-dimensionally in the processing circuit unit 160. In this embodiment, the processing circuit unit 160 has 81 signal processing blocks 162 arranged in a two-dimensional arrangement of 9 rows and 9 columns. The signal processing blocks 162 include circuits that perform drive and signal processing on the pixel blocks 142, and may include, for example, some or all of the vertical drive unit 62, signal processing unit 64, and horizontal drive unit 68 in Figure 2.

[0027] In this example, the processing circuit unit 160 is positioned on the second semiconductor substrate 150 opposite the pixel unit 50. That is, the processing circuit unit 160 is positioned so as to overlap with the pixel unit 50 in the stacking direction in which the first semiconductor substrate 140 and the second semiconductor substrate 150 are stacked. The processing circuit unit 160 may also be positioned so as to overlap with the pixel unit 50 in the stacking direction in which the first semiconductor substrate 140 and the second semiconductor substrate 150 are stacked, with at least a portion overlapping. In this case, with respect to the stacking direction, one of the pixel unit 50 and the processing circuit unit 160 may overlap in such a way that it encompasses the other. The stacking direction may also be parallel to the Z-axis.

[0028] Furthermore, the signal processing block 162 is positioned on the second semiconductor substrate 150 opposite at least one pixel block 142. That is, the signal processing block 162 is positioned so as to at least partially overlap one pixel block 142 in the stacking direction. In this case, in the stacking direction, one of the pixel block 142 and the corresponding signal processing block 162 may overlap so as to encompass the other.

[0029] The processing circuit section 160 includes both signal processing blocks 162 that perform drive and signal processing on pixel blocks 142 located at opposing positions in the stacking direction, and signal processing blocks 162 that perform drive and signal processing on pixel blocks 142 that are not located at opposing positions in the stacking direction. In other words, a signal processing block 162 may perform drive and signal processing on pixel blocks 142 located at opposing positions in the stacking direction, or it may perform drive and signal processing on pixel blocks 142 that are not located at opposing positions in the stacking direction.

[0030] Figure 4 schematically shows an example of a peripheral circuit section 500 and a pixel block 142 and a signal processing block 162 connected to the peripheral circuit section 500 via various wiring in the first embodiment. Figure 5 schematically shows an example of three of the multiple unit blocks 200 and the peripheral circuit section 500 in the first embodiment. In Figures 4, 5, and subsequent figures, functional blocks included in the unit block 200 and the peripheral circuit section 500 that are not described in the drawing, as well as signal lines connected to those functional blocks, may be omitted for the purpose of making the drawings easier to understand.

[0031] As an example of signal processing for the pixel block 142, the signal processing block 162 converts the charge-based signal converted by the photoelectric conversion unit of the pixel block 142 into a digital signal. More specifically, as shown in Figure 4, the signal processing block 162 has a signal conversion unit 164 that converts the charge-based signal converted by the photoelectric conversion unit of the pixel block 142 into a digital signal. The signal processing block 162 further has a signal holding unit 165 that holds the charge-based signal converted by the photoelectric conversion unit of the pixel block 142 until it is read out by the signal conversion unit 164, and a signal storage unit 166 that stores the digital signal output from the signal conversion unit 164. The signal holding unit 165 may include, for example, a current source that supplies current to the signal conversion unit 164. The signal processing block 162 does not necessarily have to have a signal holding unit 165.

[0032] Note that the signal conversion unit 164 is an example of a conversion unit, and the signal processing block 162 is an example of a circuit block including a conversion unit. Furthermore, from the above description, it can be said that the second semiconductor substrate has a first circuit block positioned opposite to the first pixel block of the first semiconductor substrate 140, and a second circuit block positioned opposite to the second pixel block of the first semiconductor substrate 140. Moreover, it can be said that the first circuit block includes a first conversion unit that converts a first signal based on the charge converted by the first photoelectric conversion unit of the first pixel block into a digital signal. The second circuit block includes a second conversion unit that converts a second signal based on the charge converted by the second photoelectric conversion unit of the first pixel block, which is not positioned opposite to the second pixel block, into a digital signal.

[0033] The drive control unit 60, output unit 58, global vertical drive unit 152, and global horizontal drive unit 154 are arranged around the processing circuit unit 160 on the second semiconductor substrate 150. Here, the global vertical drive unit 152, global horizontal drive unit 154, and output unit 58 provide common control to multiple pixel blocks 142, and may be, for example, parts of the vertical drive unit 62, horizontal drive unit 68, and output unit 70 other than those included in the signal processing block 162.

[0034] Furthermore, the image sensor 100 may have a third semiconductor substrate stacked in addition to the first semiconductor substrate 140 and the second semiconductor substrate 150. For example, the third semiconductor substrate performs image processing according to the signal output by the second semiconductor substrate 150. Also, the structure of the image sensor 100 may be back-illuminated or front-illuminated.

[0035] As described above, in this embodiment, the pixel unit 50 has 81 pixel blocks 142 arranged in a two-dimensional array of 9 rows and 9 columns. These pixel blocks 142 have, for example, the same configuration as one another. In Figure 4, six of the nine pixel blocks 142 included in one column are shown by dashed lines: 142A, 142B, 142C, 142D, 142E, and 142F. In the following, only some of the pixel blocks 142A etc. included in one column of the pixel unit 50 and the corresponding signal processing blocks 162A etc. may be described representatively, or only some of the pixel blocks 142A etc. included in one row of the pixel unit 50 and the corresponding signal processing blocks 162A etc. may be described representatively. Unless otherwise specified, the pixel blocks 142A etc. included in other columns and rows of the pixel unit 50 are assumed to have similar circuit configurations, functions, and configurations, and redundant explanations will be omitted.

[0036] As shown in Figure 4, the pixel blocks 142A and the like are connected in parallel to the peripheral circuit section 500 that controls the pixel blocks 142A and the like via a common pixel control line 230. Note that the pixel control line 230 is an example of a common control line, and the peripheral circuit section 500 is an example of a control circuit.

[0037] As described above, in this embodiment, the processing circuit unit 160 has 81 signal processing blocks 162 arranged in a two-dimensional 9x9 grid. These signal processing blocks 162 have, for example, the same configuration as one another. In Figure 4, six signal processing blocks 162A, 162B, 162C, 162D, 162E, and 162F are shown as dashed lines as representative examples. The six signal processing blocks 162A, 162B, 162C, 162D, 162E, and 162F are arranged opposite the six pixel blocks 142A, 142B, 142C, 142D, 142E, and 142F in the stacking direction.

[0038] As shown in Figure 4, the signal processing block 162A, etc., is connected in parallel to the peripheral circuit section 500 that controls the signal processing block 162A, etc., via a common circuit control line 240. The signal processing block 162A, etc., is an example of the first circuit block and second circuit block described above. The circuit control line 240 is an example of a common control line.

[0039] In the following explanation, multiple signal processing blocks 162A etc. arranged in a row may be collectively referred to as circuit block group 245-1 etc. More specifically, as shown in Figure 4, three signal processing blocks 162A, 162B, and 162C arranged in a row, which are positioned opposite each other in the stacking direction to the three pixel blocks 142A, 142B, and 142C arranged in a row, may be referred to as circuit block group 245-1. Similarly, three signal processing blocks 162D, 162E, and 162F arranged in a row, which are positioned opposite each other in the stacking direction to the three pixel blocks 142D, 142E, and 142F arranged in a row, may be referred to as circuit block group 245-2. The same applies to other signal processing blocks 162 not shown in Figure 4, and redundant explanations are omitted.

[0040] From the above description, it can be said that the second semiconductor substrate 150 has a control circuit for controlling the first pixel block of the first semiconductor substrate 140. The second semiconductor substrate 150 also has a first group of circuit blocks including the first and second circuit blocks described above, and a second group of circuit blocks including a plurality of circuit blocks other than these first and second circuit blocks.

[0041] Figure 5 shows details of the three pixel blocks 142A, 142B, and 142C, and the three signal processing blocks 162A, 162B, and 162C shown in Figure 4. Each of the three unit blocks 200 shown in Figure 5 includes one of the pixel blocks 142A, etc., and a so-called local circuit portion that is positioned opposite to the pixel block 142A, etc., in the stacking direction described above. Therefore, there will be a number of unit blocks 200 corresponding to the number of pixel blocks 142A, etc., for example, the same number. The local circuit portion included in the unit block 200 may be a signal processing block 162A, etc., as shown in Figure 5. On the other hand, the peripheral circuit portion 500 is a global circuit portion that is provided in common to the multiple unit blocks 200.

[0042] Each pixel block 142A, etc., contains multiple pixels 202. In this embodiment, each pixel block 142A, etc., contains, for example, nine pixels 202 arranged in a two-dimensional 3x3 grid. For simplification of notation, pixels 202 may be denoted as Aij (where i is the row number and j is the column number). The number of rows, columns, and total number of pixels 202 are not limited to those above. For example, pixels 202 may have 16 rows and 16 columns or 32 rows and 32 columns, etc. In this embodiment, as will be described in detail later with reference to Figure 6, each of the multiple pixels 202 included in the pixel block 142A, etc., contains one photoelectric conversion unit. Therefore, in the following, instead of describing the electrical connection state of the photoelectric conversion unit in the pixel unit 50, the electrical connection state of the pixels 202 containing the photoelectric conversion unit may be described.

[0043] The signal processing blocks 162A and the like each have a plurality of signal processing circuits 222-1 and the like. In the present embodiment, the signal processing block 162A has three signal processing circuits 222-1, 222-2, and 222-3, the signal processing block 162B has three signal processing circuits 222-4, 222-5, and 222-6, and the signal processing block 162C has three signal processing circuits 222-7, 222-8, and 222-9. The same applies to other signal processing blocks 162 not shown in FIG. 5, and duplicate explanations are omitted. The signal processing circuits 222-1 and the like are circuits that read and process the pixel signals of the pixels 202 based on the control signals from the peripheral circuit unit 500, and include the above-described signal conversion unit 164, signal holding unit 165, and signal storage unit 166.

[0044] In one pixel block 142A or the like, one pixel 202 can be configured to be processed for pixel signals in one signal processing circuit 222-1 or the like in one signal processing block 162A or the like disposed at a position facing the pixel block 142A or the like in the stacking direction. In this case, another pixel 202 in the pixel block 142A or the like can be configured to be processed for pixel signals in one signal processing circuit 222-4 or the like in another signal processing block 162B or the like instead of the signal processing block 162A or the like.

[0045] For example, in Figure 5, pixel 202 of pixel block 142A, indicated as A11, is connected to the signal processing circuit 222-1 of signal processing block 162A via signal line 122-1, and the pixel signal output by this pixel 202 is processed in the signal processing circuit 222-1. In contrast, another pixel 202 of pixel block 142A, indicated as A21 in Figure 5, which is arranged in the same column direction as pixel 202 of A11, is connected to the signal processing circuit 222-4 of signal processing block 162B via signal line 122-2, which is different from signal line 122-1, and the pixel signal output by pixel 202 of A21 is processed in the signal processing circuit 222-4. Another pixel 202 in the pixel block 142A, shown as A31 in Figure 5, which is arranged in the column direction with the pixel 202 of A11, is connected to the signal processing circuit 222-7 of the signal processing block 162C via a signal line 122-3, which is different from the signal line 122-1, and the pixel signal output by the pixel 202 of A31 is processed in the signal processing circuit 222-7.

[0046] Referring again to Figure 4, in Figure 4, the PD (photodiode) included in each pixel 202 is shown at the respective positions of the multiple pixels 202 in each pixel block 142A, etc. For pixel block 142D, which is not adjacent to pixel block 142A but is arranged in the same column direction as pixel block 142A, it is understood that the multiple pixels 202 include three pixels 202 arranged in the same column direction as the pixels 202 at A11 and A21 of pixel block 142A. Of these three pixels 202 in pixel block 142D, one pixel 202 is connected to the signal processing circuit 222-1 of signal processing block 162A via signal line 122-1, similar to the pixel 202 at A11 of pixel block 142A. Of the three pixels 202 in pixel block 142D, the other pixel 202 is connected to the signal processing circuit 222-4 of signal processing block 162B via a signal line 122-2, which is different from the signal line 122-1, similar to the pixel 202 of A21 in pixel block 142A.

[0047] For example, in pixel block 142A, pixel 202 of A12 and pixel 202 of A13 arranged side by side in the row direction with pixel 202 of A11 are connected to signal processing circuits 222-2 and 222-3 of signal processing block 162A via signal lines 122-4 and 122-7 different from signal line 122-1, respectively. The pixel signal output from pixel 202 of A12 is processed in signal processing circuit 222-2, and the pixel signal output from pixel 202 of A13 is processed in signal processing circuit 222-3.

[0048] As described above, pixel blocks 142A and the like are connected in parallel to peripheral circuit unit 500 that controls pixel blocks 142A and the like via common pixel control line 230. More specifically, as shown in FIG. 5, a plurality of pixels 202 included in pixel blocks 142A and the like are connected in parallel to peripheral circuit unit 500 via common pixel control line 230. As will be described in detail later, peripheral circuit unit 500 selects any one of a plurality of pixel blocks 142A and the like, and controls so that a plurality of signals based on charges converted by a plurality of pixels 202 of the selected one pixel block 142A and the like are read out collectively.

[0049] Signal processing circuits 222-1 and the like include a holding unit 225 that holds an analog pixel signal, a conversion unit 224 that converts the analog pixel signal into a digital pixel signal, and a storage unit 226 that stores the digital pixel signal. In each figure after FIG. 4, holding unit 225, conversion unit 224, and storage unit 226 may be denoted as MEM, ADC, and SRAM. Signal processing circuits 222-1 and the like also include a circuit selection unit 223 that controls the electrical connection between signal lines 122-1 and the like and holding unit 225.

[0050] As shown in Figure 5, in the circuit block group 245-1 which includes the signal processing block 162A, etc., the multiple circuit selection units 223, including the multiple signal processing blocks 162A, are connected in parallel to the peripheral circuit unit 500 via a common circuit control line 240. The circuit selection unit 223 is, for example, an N-channel FET, but the type of transistor is not limited to this. A selection control signal φADC-SEL, which is common to the circuit block group 245-1 which includes the signal processing block 162A, etc., i.e., a global selection control signal, is input from the vertical drive unit 62 to the gate terminal of the circuit selection unit 223. As a result, the signal line 122-1, etc., and all the holding units 225 included in the circuit block group 245-1 are electrically connected by each circuit selection unit 223. At the same time, when any one pixel block 142A, etc., is selected by the peripheral circuit unit 500 and electrically connected to the signal line 122-1, etc., a pixel signal is output from the pixel 202 of that one pixel block 142A, etc., to all the holding units 225 via the signal line 122-1, etc. The circuit selection unit 223 is an example of a switch that connects or disconnects the pixel 202 and the signal conversion unit 164.

[0051] The holding unit 225 is an example of a signal holding element that holds the signal based on the charge converted by the pixel 202 of the pixel block 142 until it is read out by the signal conversion unit 164. Three holding units 225 included in one signal processing block 162A, etc., may be included in the signal holding unit 165 shown in Figure 4.

[0052] The conversion unit 224 may be, for example, a single-slope system, but other systems may also be used. Three conversion units 224 included in one signal processing block 162A, etc., may be included in the signal conversion unit 164 shown in Figure 4.

[0053] The memory unit 226 is an example of a semiconductor element that stores the digital signal output from the signal conversion unit 164. Three memory units 226 included in one signal processing block 162A, etc., may be included in the signal storage unit 166 shown in Figure 4.

[0054] Furthermore, the signal processing circuit 222-1, etc., may also include other processing circuits such as digital and / or analog CDS circuits (correlated double sampling).

[0055] Each signal processing block 162A, etc., is provided with three signal processing circuits 222-1, etc., corresponding to the three rows of pixels 202 in each pixel block 142A, etc. That is, each signal processing block 162A, etc., contains the same number of signal processing circuits 222-1, etc. as the total number of pixels 202 arranged in the row direction in each pixel block 142A, etc. However, each signal processing block 162A, etc., may contain a number of signal processing circuits 222-1, etc. that is different from the total number of pixels 202 arranged in the row direction in each pixel block 142A, etc.

[0056] The pixel signals from the signal processing circuit 222-1, etc., are output to the peripheral circuit section 500 via the horizontal line 502. It can also be said that the signal processing block 162A, etc., constitutes at least a part of the signal processing unit 64 and the horizontal drive unit 68 shown in Figure 2.

[0057] Figure 6 shows an example of the circuit configuration of a pixel 202. As shown in Figure 6, in this embodiment, the pixel 202 has a photoelectric conversion unit 120 and a readout unit 124. The photoelectric conversion unit 120 converts light into electric charge. The photoelectric conversion unit 120 converts light emitted from the optical system 20 into electric charge. The photoelectric conversion unit 120 stores the photoelectrically converted charge. Specifically, the charge converted by the photoelectric conversion unit 120 is stored in the circuit when the output side circuit of the photoelectric conversion unit 120 is closed, and flows to the low potential side when the circuit is open. The photoelectric conversion unit 120 is, for example, a photodiode. The photoelectric conversion unit 120 is an example of a first photoelectric conversion unit, a second photoelectric conversion unit, etc. The readout unit 124 reads a signal based on the charge converted by the photoelectric conversion unit 120 to the signal line 122.

[0058] As shown in Figure 6, the readout unit 124 includes a transfer unit 123, a storage unit 125, a reset unit 126, and a pixel output unit 127. The pixel output unit 127 includes an amplification unit 128 and a selection unit 129. In this example, the transfer unit 123, reset unit 126, amplification unit 128, and selection unit 129 are described as N-channel FETs, but the type of transistor is not limited to this.

[0059] The transfer unit 123-1 transfers the charge converted by the photoelectric conversion unit 120. The transfer unit 123-1 is an example of a transfer gate that transfers the charge from the photoelectric conversion unit 120. In other words, the transfer unit 123-1 acts as the gate, the photoelectric conversion unit 120 as the source, and the storage unit 125 as the drain, and these together constitute a so-called transfer transistor.

[0060] The storage unit 125 receives charge from the photoelectric conversion unit 120 via the transfer unit 123-1. The storage unit 125 is an example of floating diffusion (FD). The reset unit 126 discharges the charge from the storage unit 125 to the power supply wiring to which the power supply voltage VDD is supplied.

[0061] The pixel output unit 127 outputs a pixel signal based on the potential of the storage unit 125 to the signal line 122. The pixel output unit 127 includes an amplification unit 128 and a selection unit 129.

[0062] The amplification unit 128 has its gate terminal connected to the storage unit 125, its drain terminal connected to the power supply wiring that is supplied with the power supply voltage VDD, and its source terminal connected to the drain terminal of the selection unit 129.

[0063] The selection unit 129 controls the electrical connection between the pixel 202 and the signal line 122. When the selection unit 129 electrically connects the pixel 202 and the signal line 122, a pixel signal is output from the pixel 202 to the signal line 122. A selection control signal φSEL common to the pixel block row is input to the gate terminal of the selection unit 129 from the vertical drive unit 62. The source terminal of the selection unit 129 is connected to the load current source 121.

[0064] The load current source 121 supplies current to the signal line 122. Here, we will describe an example of a series of processing flows in which the vertical drive unit 62 controls the pixel 202 to read out the pixel signal.

[0065] Just before the photoelectric conversion unit 120 begins accumulating charge, the vertical drive unit 62 inputs a common control signal φTX1 for the pixel block row to the gate terminal of the transfer unit 123-1, and simultaneously inputs a common reset control signal φRST for the pixel block row to the gate terminal of the reset unit 126. As a result, the reset unit 126 and the transfer unit 123-1 are turned on simultaneously, and the charge in the photoelectric conversion unit 120 and the charge in the accumulation unit 125 are discharged into the power supply wiring to which the power supply voltage VDD is supplied. This starts the exposure of the photoelectric conversion unit 120.

[0066] The vertical drive unit 62 inputs a common control signal φTX1 for the pixel block row to the gate terminal of the transfer unit 123-1. This turns on the transfer unit 123-1, and the charge stored in the photoelectric conversion unit 120 is transferred to the storage unit 125.

[0067] The vertical drive unit 62 inputs a selection control signal φSEL to the gate terminal of the selection unit 129 according to a common reading timing for the pixel block row in order to read the pixel signal of the pixel 202. As a result, the selection unit 129 turns on, and the pixel signal based on the charge converted by the photoelectric conversion unit 120 is output to the signal line 122.

[0068] With the above configuration, it can also be said that the vertical drive unit 62 controls the exposure time with the reset control signal φRST and the control signal φTX1, and controls the readout timing with the control signal φTX1 and the selection control signal φSEL.

[0069] Figure 7 illustrates an example of a driving method for the image sensor 100 according to the first embodiment. With the image sensor 100 having the configuration described above, the charge-based signals converted by multiple pixels 202 contained in one pixel block 142 among multiple pixel blocks 142 arranged in two dimensions are read out all at once. The image sensor 100 further converts the read-out signals into digital signals.

[0070] More specifically, the peripheral circuit section 500 of the image sensor 100 sequentially reads out the signals of multiple pixels 202 included in one pixel block row, i.e., multiple pixels 202 included in one pixel block row, in a single operation, in the column direction.

[0071] In this embodiment, the image sensor 100 has 81 pixel blocks 142 arranged in a two-dimensional 9x9 grid, and each pixel block 142 has 9 pixels 202 arranged in a two-dimensional 3x3 grid. The peripheral circuit unit 500 sequentially reads out the signals of multiple pixels 202 included in three pixel block rows in the column direction.

[0072] In other words, the image sensor 100 according to this embodiment performs global shutter control, reading out the pixel signals of multiple pixels 202 within a pixel block 142 from the negative Y-axis side of the pixel section 50, while performing rolling shutter control in units of multiple pixel block rows, i.e., every three pixel block rows, for the entire pixel section 50. Alternatively, the image sensor 100 may read out the pixel signals of multiple pixels 202 within a pixel block 142 from a direction other than the negative Y-axis side of the pixel section 50.

[0073] More specifically, as shown in Figure 7, during the first 1H period, global shutter control is performed to read out the pixel signals of multiple pixels 202 included in the 3-pixel block rows from the 1st to the 3rd row located at the negative end of the Y-axis. Then, during the next 1H period, the pixel signals of multiple pixels 202 included in the 3-pixel block rows from the 4th to the 6th row are read out all at once. Finally, during the last 1H period, the pixel signals of multiple pixels 202 included in the 3-pixel block rows from the 7th to the 9th row are read out all at once. In this way, with the image sensor 100 of this embodiment, driving and signal processing of 3-pixel block rows takes 1H, resulting in a signal processing time of 3H per frame.

[0074] When reading out the pixel signals of multiple pixels 202 contained in multiple rows of pixel blocks 142 within a period of 1H, a set of one pixel block 142A, etc. and one circuit block group 245-1, etc. sequentially uses the signal line 122 for reading out the pixel signals, so that a small time difference can be provided between the multiple rows. In other words, one circuit block group 245-1, etc. finishes reading out the pixel signal from the corresponding pixel block 142A, etc. via the signal line 122, and only then does the next circuit block group 245-1, etc. begin reading out the pixel signal from the corresponding pixel block 142A, etc. via the signal line 122. Note that the period during which one circuit block group 245-1, etc. performs AD conversion of the pixel signals and at least one of the period during which another circuit block group 245-1, etc. reads out the pixel signals and performs AD conversion may overlap.

[0075] Furthermore, referring to Figures 3, 4, 5, and 7, it is understood that the plurality of pixel blocks 142 of the first semiconductor substrate 140 further include a fourth pixel block arranged in the row direction with the first pixel block, and the second semiconductor substrate 150 further includes a third circuit block group that includes a plurality of conversion units that convert signals based on charge converted by the plurality of pixels 202 of the fourth pixel block into digital signals. When the peripheral circuit section 500 of the image sensor 100 reads signals from both the first pixel block and the fourth pixel block included in the same pixel block row, it outputs the same timing signal via a common circuit control line 240 to the first circuit block group corresponding to the first pixel block and the third circuit block group corresponding to the fourth pixel block.

[0076] More specifically, the peripheral circuit unit 500 globally controls multiple pixel blocks 142 for one pixel block row via a common pixel control line 230, and also globally controls the corresponding multiple signal processing blocks 162 via a common circuit control line 240. That is, the peripheral circuit unit 500 simultaneously drives nine pixel blocks 142 included in one pixel block row and simultaneously processes the pixel signals output from each of the nine pixel blocks 142 by a group of circuit blocks 245-1 etc., which are provided at opposing positions in the stacking direction for each column.

[0077] As explained using Figure 7, in this application, reading out the signals of multiple pixels 202 in the pixel section 50 all at once may also include simultaneously reading out the signals of all pixels 202 included in multiple pixel blocks 142 arranged in a single row.

[0078] Figure 8 shows an example of a connection configuration between a circuit block group 245-1, etc., provided at a position opposite a typical pixel block row in the stacking direction in the image sensor 100 according to the first embodiment. As described above, both the multiple circuit selection units 223 included in one circuit block group 245-1, etc., and the multiple selection units 129 included in one pixel block 142A, etc., are globally controlled by the peripheral circuit unit 500. Therefore, in Figure 8, simply to clarify the explanation, only one circuit selection unit 223, which is provided in each of the signal processing circuits 222-1, etc. in Figure 5, is shown as a representative example for one circuit block group 245-1, etc. Also in Figure 8, for the same purpose, only one selection unit 129, which is provided for each pixel 202 in Figure 5, is shown as a representative example for one pixel block 142A, etc.

[0079] The peripheral circuit section 500 inputs a common, or global, selection control signal φSEL to the gate terminals of each selection unit 129 shown in Figure 8, in order to individually select each of the nine pixel block rows from row 1 to row 9 shown in Figure 7.

[0080] The peripheral circuit section 500 inputs a global selection control signal φADC-SEL, common to one of the circuit block groups 245-1, 245-2, and 245-3 shown in Figure 8, to the gate terminal of each circuit selection unit 223 in order to individually select each of the three circuit block groups 245-1, 245-2, and 245-3 shown in Figure 8. As shown in Figure 8, circuit block group 245-1 includes three signal processing blocks 162A, 162B, and 162C, circuit block group 245-2 includes three signal processing blocks 162D, 162E, and 162F, and circuit block group 245-3 includes three signal processing blocks 162G, 162H, and 162I.

[0081] Figure 9 is a timing chart of an example of a driving method in which each pixel block row is driven sequentially in the image sensor 100 according to the first embodiment. Figures 10 to 18 show the process of sequentially driving each pixel block row in the example of Figure 8.

[0082] As an example, when reading out multiple signals based on the charge converted by multiple pixels 202 of the first pixel block, the peripheral circuit section 500 of the image sensor 100 controls the connection between the first circuit block group, which includes the first circuit block located opposite the first pixel block, and the first pixel block, and the disconnection between the second circuit block group, which does not include the first circuit block, and the first pixel block.

[0083] In this case, when the peripheral circuit unit 500 reads out multiple signals based on the charge converted by multiple pixels 202 of the second pixel block which is arranged in a column with the first pixel block, it may control the connection between the first circuit block group and the second pixel block to be disconnected and the connection between the second circuit block group and the second pixel block to be connected.

[0084] When the peripheral circuit unit 500 starts reading signals from the second pixel block after the signal reading from the first pixel block is completed, it generates and outputs timing signals with time differences to the first and second circuit block groups individually. By controlling each pixel block and each circuit block group in this way, the peripheral circuit unit 500 causes the signal line 122 to be used sequentially for reading pixel signals from a set of one pixel block 142A and one circuit block group 245-1 within a period of 1H. That is, the peripheral circuit unit 500 drives the three circuit block groups 245-1, 245-2, and 245-3 provided in each column with a small time difference between them, and drives and processes signals for three pixel block rows with a small time difference between them. As a result, the peripheral circuit unit 500 reads out the pixel signals of multiple pixels 202 included in multiple rows of pixel blocks 142 all at once within a period of 1H.

[0085] Specifically, during the first 1H period in frame 1 shown in Figure 9, SEL[0] and ADC-SEL[0] are first turned on, that is, as shown in Figure 10, both the selection unit 129 of all pixel blocks 142I included in the first row of pixel blocks and the circuit selection unit 223 of the circuit block group 245-3 are connected. The time for which they are connected may be the same as a settling time of, for example, about 1 μsec. Also, in the circuit block group 245-3, the pixel signal transferred from the pixel 202 of the pixel block 142I is temporarily held and then AD converted.

[0086] During the first 1H period, SEL[0] and ADC-SEL[0] are then set to low, and SEL[1] and ADC-SEL[1] are turned on. That is, as shown in Figure 11, both the selection unit 129 of all pixel blocks 142H included in the second row of pixel blocks and the circuit selection unit 223 of the circuit block group 245-2 are connected. In the circuit block group 245-2, the pixel signal transferred from the pixel 202 of the pixel block 142H is temporarily held before being converted to AD.

[0087] During the first 1H period, SEL[1] and ADC-SEL[1] are then set to low, and SEL[2] and ADC-SEL[2] are turned on. That is, as shown in Figure 12, both the selection unit 129 of all pixel blocks 142G included in the third row of pixel blocks and the circuit selection unit 223 of the circuit block group 245-1 are connected. In the circuit block group 245-1, the pixel signal transferred from the pixel 202 of the pixel block 142G is temporarily held before being converted to AD.

[0088] During the initial 1H period, SEL[2] and ADC-SEL[2] are then set low, and after the AD conversion in circuit block group 245-1 is completed, the pixel signals converted by the three circuit block groups 245-1, 245-2, and 245-3 are transferred to the SRAM all at once. The pixel signals temporarily stored in the SRAM may be provided to the peripheral circuit section 500.

[0089] During the initial 1H period, SEL[0] and ADC-SEL[0] are then turned on again, thereby transferring a signal based on the photoelectrically converted charge from the pixel 202 of the pixel block 142I to the circuit block group 245-3. In the circuit block group 245-3, the exposure-based pixel signal transferred from the pixel 202 of the pixel block 142I is temporarily held before being AD converted.

[0090] During the initial 1H period, SEL[0] and ADC-SEL[0] are then set to low, and SEL[1] and ADC-SEL[1] are turned on again, thereby transferring a signal based on the photoelectrically converted charge from the pixel 202 of the pixel block 142H to the circuit block group 245-2. In the circuit block group 245-2, the exposure-based pixel signal transferred from the pixel 202 of the pixel block 142H is temporarily held before being AD converted.

[0091] During the initial 1H period, SEL[1] and ADC-SEL[1] are then set to low, and SEL[2] and ADC-SEL[2] are turned on again, thereby transferring a signal based on the photoelectrically converted charge from the pixel 202 of the pixel block 142G to the circuit block group 245-1. In the circuit block group 245-1, the exposure-based pixel signal transferred from the pixel 202 of the pixel block 142G is temporarily held and then AD converted.

[0092] During the first 1H period, SEL[2] and ADC-SEL[2] are then set low, and after the AD conversion in circuit block group 245-1 is completed, the pixel signals converted by AD in the three circuit block groups 245-1, 245-2, and 245-3 are transferred to the SRAM in a single operation. The pixel signals temporarily stored in the SRAM may be provided to the peripheral circuit section 500. This SRAM transfer only needs to be completed before the first AD conversion in the next 1H is completed, and the next 1H period begins immediately after the start of this SRAM transfer.

[0093] The peripheral circuit section 500 controls the subsequent 2H in 1frame in the same way as the first 1H described above. That is, in the next 1H, the peripheral circuit section 500 sequentially switches to the connection states shown in Figures 13 to 15, and in the final 1H, it sequentially switches to the connection states shown in Figures 16 to 18.

[0094] As explained above using Figures 7 to 18, the image sensor 100 according to this embodiment performs global shutter control, reading out the pixel signals of multiple pixels 202 in a single operation within a pixel block 142 from the negative Y-axis side of the pixel section 50, while performing rolling shutter control for each of the multiple pixel block rows in the entire pixel section 50.

[0095] For example, let's assume that multiple pixel blocks 142 in the pixel section 50 are arranged in a two-dimensional array of N rows and M columns, and multiple pixels 202 in one pixel block 142 are arranged in a two-dimensional array of n rows and m columns, and that one signal processing block 162 is provided with m signal processing circuits 222-1, etc. If N is an integer multiple of n, then the N rows of signal processing blocks 162 can be used exactly for each n row in the pixel block 142. N / n is the number of circuit block groups 245-1, etc., and is also the number of pixel block rows included in 1H. In the examples from Figures 4 to 18, N is three times n, so N=9 is used each time n=3 is used, resulting in N / n=3 circuit block groups 245-1, etc.

[0096] According to the image sensor 100 of this embodiment, driving and signal processing of three pixel block rows is performed in 1H, resulting in a signal processing time of 3H per frame. Therefore, with the image sensor 100, distortion at block boundaries can be reduced compared to the case where rolling shutter readout is performed for each block.

[0097] Furthermore, if rolling shutter readout is performed simultaneously on all pixel blocks, there can be a readout time difference of up to one frame even within a single pixel block. In this case, even if you want to apply some signal processing to only one pixel block, you must wait until the readout of all pixel signals from all pixel blocks for one frame is complete, due to the readout order.

[0098] In contrast, with the image sensor 100 of this embodiment, signals are read out in units of pixel blocks 142, that is, the pixel signals of all pixels 202 contained in a pixel block 142 are read out all at once, so there is no time difference in reading within a single pixel block 142. Furthermore, with the image sensor 100 of this embodiment, signal processing can be applied to each pixel block 142 after reading is complete, without having to wait for the reading of all pixel signals of all pixel blocks for one frame to be completed, as in the case where rolling shutter readout is performed simultaneously for all pixel blocks.

[0099] Figure 19 schematically shows another example of the peripheral circuit section 500 and the pixel block 142 and signal processing block 162 connected to the peripheral circuit section 500 via various wiring in the first embodiment. As shown in Figure 19, a group of circuit blocks 245-1 and a group of pixel blocks 142A etc. located opposite the group of circuit blocks, for example, three pixel blocks 142A, 142B, and 142C may be treated as one set, and multiple sets included in the image sensor 100 may be divided. More specifically, the three pixel blocks 142A, 142B, and 142C included in one set may be driven and signal processed by a group of circuit blocks 245-1 located opposite the group of circuit blocks 142A, 142B, and 142C included in that set.

[0100] Figure 20 illustrates another example of the driving method for the image sensor 100 according to the first embodiment. Figure 21 shows another example of the connection configuration between a typical pixel block row and the corresponding circuit block group 245-1, etc., in the image sensor 100 according to the first embodiment. The driving method example shown in Figure 20 and the connection configuration example shown in Figure 21 correspond to the example in Figure 19.

[0101] In the example described using Figures 7 to 18, the pixel signals of multiple pixels 202 within a pixel block 142 are read out collectively from the negative Y-axis side of the pixel unit 50, while the rolling shutter control is performed on multiple pixel block rows, i.e., every three pixel block rows, for the entire pixel unit 50. Instead, in the present example shown in Figures 19 to 21, the pixel signals of multiple pixels 202 within a pixel block 142 are read out collectively from the negative Y-axis side of the pixel unit 50, while the rolling shutter control is performed on every pixel block row for the entire pixel unit 50. With the image sensor 100 in this example, driving and signal processing of one pixel block row takes 1H, resulting in a signal processing time of 9H per frame. In this case, the RS distortion between adjacent pixel blocks 142 in the Y-axis direction, i.e., in the column direction, is 1H.

[0102] Therefore, even with the image sensor 100 of this example, the RS distortion can be reduced to one-third compared to the case in the comparative example described above, where the image sensor performs control to read out all pixel blocks simultaneously, sequentially one pixel row at a time from the negative Y-axis side within the pixel block. Furthermore, the signal processing time per frame can be reduced to one-third compared to the case in the comparative example, where the image sensor performs the column-parallel control described above.

[0103] Figure 22 schematically shows three of the multiple unit blocks 200 and another example of the peripheral circuit section 500 in the first embodiment. As shown in Figure 22, the connection method to the signal lines 122-1, etc. of each pixel 202 may differ between two pixel blocks 142 arranged in a row.

[0104] Figure 23 is a schematic diagram showing the functional blocks of the signal processing block 162-1 in the second embodiment. In addition to the functional blocks of the signal processing block 162 in the first embodiment, the signal processing block 162-1 in the second embodiment may also have a block control unit 167 that locally controls the corresponding pixel block 142. The block control unit 167 controls, for example, the exposure time for each pixel block 142.

[0105] Figure 24 schematically shows an example of three of the multiple unit blocks 201 and a peripheral circuit section 500 in the second embodiment. Figure 25 shows an example of the circuit configuration of pixel 202-1. Figure 26 is a timing chart of an example of a driving method in which each pixel block row is driven sequentially in the image sensor 100 according to the second embodiment.

[0106] As shown in Figure 24, the unit block 201 in the second embodiment may include a block vertical drive unit 210 in addition to the configuration of the unit block 200 in the first embodiment. As shown in Figure 24, the pixel block 142A of the unit block 201 may have multiple pixels 202-1 instead of multiple pixels 202.

[0107] The block vertical drive unit 210 locally controls the pixels 202-1 included in the unit block 201 to be driven independently of other unit blocks 201, based on control signals from the peripheral circuit unit 500, such as drive pulses. Therefore, it can be said that the block vertical drive unit 210 constitutes at least a part of the vertical drive unit 62 in Figure 2.

[0108] In the second embodiment, the unit block 201 may be controlled so that the exposure time differs for each pixel 202-1 or each pixel block 142.

[0109] As shown in Figure 25, pixel 202-1 may include an ejection unit 123-2 in addition to the configuration of pixel 202. The ejection unit 123-2 ejects the charge accumulated in the photoelectric conversion unit 120 to the power supply wiring to which the power supply voltage VDD is supplied. Immediately before exposure of the photoelectric conversion unit 120, a local ejection control signal φTX2, specific to the pixel block 142 corresponding to the block vertical drive unit 210, is input to the gate terminal of the ejection unit 123-2 from the block vertical drive unit 210.

[0110] More specifically, immediately before exposure of the photoelectric conversion unit 120, an emission control signal φTX2 is input to the gate terminal of the emission unit 123-2 according to the exposure time specific to the pixel block 142. This turns on the emission unit 123-2, and the charge remaining in the photoelectric conversion unit 120 is discharged to the power supply wiring. The block vertical drive unit 210 may also vary the exposure time for each pixel 202-1 or pixel block 142 by locally controlling the time and timing for turning on the emission unit 123-2 for each pixel 202-1 or pixel block 142, as shown in Figure 26.

[0111] In this embodiment, the discharge unit 123-2 was described as discharging the charge from the photoelectric conversion unit 120 to the power supply wiring supplied with the power supply voltage VDD. However, it may also be discharged to the power supply wiring supplied with a power supply voltage different from the power supply voltage VDD.

[0112] In the examples shown in Figures 23 to 26 above, the multiple pixels 202-1 of the first pixel block may include AF pixels 202-1. For example, in the example in Figure 24, the pixel block 142A may include AF pixels 202-1 instead of some image-providing pixels 202-1, for example, A12, A21, A23, and A32 may be AF pixels 202-1. In this case, the AF pixels 202-1 are connected to the peripheral circuit section 500 via control lines separate from the control lines connected to the image pixels 202-1, and are controlled independently of the image pixels 202-1.

[0113] In this case, furthermore, a plurality of pixels 202-1 of the second pixel block, which is arranged in a column direction with the first pixel block, may also include AF pixels 202-1, and the AF pixels 202-1 of the second pixel block may be arranged in a column direction with the AF pixels 202-1 of the first pixel block. In this case, the second semiconductor substrate 150 may have a plurality of circuit blocks including a conversion unit that converts the charge-based signal converted by the AF pixels 202-1 into a digital signal. In this case, the AF pixels 202-1 of the first pixel block and the AF pixels 202-1 of the second pixel block may be connected to different circuit blocks from the plurality of circuit blocks via different signal lines.

[0114] For example, in the example in Figure 24, if pixel block 142A includes AF pixels 202-1 for A12, A21, A23, and A32, pixel block 142B may use pixels 202-1 for AF of B11, B31, B22, B13, and B33 that are connected to signal lines 122-1, 122-3, 122-5, 122-7, and 122-9, other than signal lines 122-4, 122-2, 122-8, and 122-6 that are connected to AF pixels 202-1 for A12, A21, A23, and A32.

[0115] In this case, the AF pixels 202-1 of the first pixel block and the AF pixels 202-1 of the second pixel block are further connected in parallel to the peripheral circuit section 500 via the separate control lines described above. In this case, the peripheral circuit section 500 selects only the AF pixels 202-1 of the first pixel block and the AF pixels 202-1 of the second pixel block from among the multiple pixels 202-1 of the first pixel block and the multiple pixels 202-1 of the second pixel block, and controls the system so that multiple signals based on the charge converted by the selected multiple AF pixels 202-1 are read out all at once.

[0116] In the examples shown in Figures 23 to 26 above, some of the multiple pixels 202-1 included in the pixel block 142 may be thinned out. For example, taking the Bayer array into consideration, the other pixels 202-1 may be thinned out so that pairs of adjacent pixels 202-1 remain in each pixel block 142.

[0117] The image sensor 100 in the multiple examples of the second embodiment described above also has the same effects as the image sensor 100 in the first embodiment.

[0118] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0119] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order. [Other possible items] [Item 1] A semiconductor substrate having a plurality of pixel blocks, each including a plurality of photoelectric conversion units that convert light into electric charge, comprising: a first semiconductor substrate having a first pixel block among the plurality of pixel blocks and a second pixel block among the plurality of pixel blocks arranged in a column direction with the first pixel block; and a second semiconductor substrate stacked together with the first semiconductor substrate, comprising a first circuit block positioned opposite to the first pixel block and a second circuit block positioned opposite to the second pixel block, wherein the first pixel block includes a first photoelectric conversion unit among the plurality of photoelectric conversion units and a second photoelectric conversion unit among the plurality of photoelectric conversion units, the first circuit block includes a first conversion unit that converts a first signal based on the electric charge converted by the first photoelectric conversion unit into a digital signal, and the second circuit block includes a second conversion unit that converts a second signal based on the electric charge converted by the second photoelectric conversion unit into a digital signal, an image sensor. [Item 2] The image sensor according to Item 1, wherein the second photoelectric conversion unit is arranged in the row direction with respect to the first photoelectric conversion unit. [Item 3] The image sensor according to Item 2, wherein the first photoelectric conversion unit is connected to the first conversion unit via a first signal line, and the second photoelectric conversion unit is connected to the second conversion unit via a second signal line different from the first signal line.[Item 4] The image sensor according to Item 3, wherein the plurality of pixel blocks of the first semiconductor substrate further include a third pixel block arranged in the column direction with respect to the first pixel block but not adjacent to it, and the plurality of photoelectric conversion units of the third pixel block include a fourth photoelectric conversion unit and a fifth photoelectric conversion unit arranged in the column direction with respect to the first photoelectric conversion unit, the fourth photoelectric conversion unit is connected to the first conversion unit via a first signal line, and the fifth photoelectric conversion unit is connected to the second conversion unit via a second signal line. [Item 5] The image sensor according to Item 2, wherein the plurality of photoelectric conversion units of the first pixel block further include one or more photoelectric conversion units arranged in the row direction with respect to the first photoelectric conversion unit, and the first circuit block includes the same number of conversion units as the total number of the first photoelectric conversion unit and the one or more photoelectric conversion units arranged in the row direction. [Item 6] The image sensor according to Item 1, wherein the second semiconductor substrate further comprises a control circuit for controlling the first pixel block, and the first photoelectric conversion unit and the second photoelectric conversion unit are connected in parallel to the control circuit via a common control line. [Item 7] The image sensor according to Item 1, wherein the second semiconductor substrate further comprises a control circuit for controlling the first pixel block and the second pixel block, and the control circuit selects either the first pixel block or the second pixel block and controls the selection so that a plurality of signals based on the charges converted by the plurality of photoelectric conversion units of the selected pixel block are read out collectively. [Item 8] The image sensor according to Item 1, wherein the first circuit block further comprises a switch for connecting or disconnecting the first photoelectric conversion unit and the first conversion unit, and a signal holding element for holding the first signal until it is read out by the first conversion unit, and the second circuit block further comprises a switch for connecting or disconnecting the second photoelectric conversion unit and the second conversion unit, and a signal holding element for holding the second signal until it is read out by the second conversion unit.[Item 9] The image sensor according to Item 8, wherein the first circuit block further includes a signal storage element for storing the digital signal output from the first conversion unit, and the second circuit block further includes a signal storage element for storing the digital signal output from the second conversion unit. [Item 10] The image sensor according to Item 8, wherein the second semiconductor substrate further comprises a control circuit for controlling the first circuit block and the second circuit block, and the switches of the first circuit block and the switches of the second circuit block are connected in parallel to the control circuit via a common control line. [Item 11] The image sensor according to Item 10, wherein the second semiconductor substrate further comprises a first circuit block group including the first circuit block and the second circuit block, and a second circuit block group including a plurality of circuit blocks other than the first circuit block and the second circuit block, and the control circuit controls the connection between the first circuit block group and the first pixel block, and the disconnection between the second circuit block group and the first pixel block when reading out a plurality of signals based on the charges converted by the plurality of photoelectric conversion units of the first pixel block. [Item 12] The image sensor according to Item 11, wherein the control circuit, when reading out a plurality of signals based on the charge converted by the plurality of photoelectric conversion units of the second pixel block, controls the connection between the first circuit block group and the second pixel block to be disconnected and the connection between the second circuit block group and the second pixel block to be connected, and when the control circuit starts reading out the signal of the second pixel block after the completion of reading out the signal of the first pixel block, it generates and outputs timing signals with a time difference to the first circuit block group and the second circuit block group individually.[Item 13] The image sensor according to Item 12, wherein the plurality of pixel blocks of the first semiconductor substrate further include a fourth pixel block arranged in the row direction with respect to the first pixel block, the second semiconductor substrate further includes a third circuit block group which includes a plurality of conversion units that convert signals based on charge converted by the plurality of photoelectric conversion units of the fourth pixel block into digital signals, and the control circuit outputs the same timing signal to the first circuit block group and the third circuit block group via a common control line when reading out the signal of the fourth pixel block together with the signal of the first pixel block. [Item 14] The image sensor according to Item 1, wherein the plurality of photoelectric conversion units of the first pixel block include a photoelectric conversion unit for AF, the second semiconductor substrate further includes a control circuit for controlling the first pixel block, and the photoelectric conversion unit for AF is connected to the control circuit via a control line separate from the control lines connected to the first photoelectric conversion unit and the second photoelectric conversion unit. [Item 15] The image sensor according to Item 14, wherein the plurality of photoelectric conversion units of the second pixel block include photoelectric conversion units for autofocus, the photoelectric conversion units for autofocus of the second pixel block are arranged in the column direction with the photoelectric conversion units for autofocus of the first pixel block, the second semiconductor substrate has a plurality of circuit blocks including a conversion unit that converts a signal based on the charge converted by the photoelectric conversion units for autofocus into a digital signal, and the photoelectric conversion units for autofocus of the first pixel block and the photoelectric conversion units for autofocus of the second pixel block are connected to different circuit blocks among the plurality of circuit blocks via different signal lines. [Item 16] The image sensor according to Item 15, wherein the photoelectric conversion units for autofocus of the first pixel block and the photoelectric conversion units for autofocus of the second pixel block are connected in parallel to the control circuit via separate control lines.[Item 17] The image sensor according to Item 16, wherein the control circuit selects only the photoelectric conversion unit for AF of the first pixel block and the photoelectric conversion unit for AF of the second pixel block from among the plurality of photoelectric conversion units of the first pixel block and the plurality of photoelectric conversion units of the second pixel block, and controls the plurality of signals based on the charge converted by the selected plurality of photoelectric conversion units for AF to be read out all at once. [Item 18] An image sensor comprising a first semiconductor substrate having a plurality of pixel blocks arranged in two dimensions, each of the plurality of pixel blocks including a plurality of photoelectric conversion units that convert light into charge, a second semiconductor substrate stacked together with the first semiconductor substrate and having a plurality of circuit blocks arranged opposite to the plurality of pixel blocks, and a control circuit for controlling the plurality of pixel blocks, wherein the control circuit sequentially repeats in the column direction the signals of the plurality of photoelectric conversion units included in a plurality of pixel blocks arranged in the row direction among the plurality of pixel blocks. [Item 19] An electronic device comprising the image sensor according to any one of Items 1 to 18. [Item 20] An imaging method for an image sensor having a plurality of pixel blocks arranged in two dimensions, each of which includes a plurality of photoelectric conversion units that convert light into electric charge, comprising: reading out a signal based on the electric charge converted by the plurality of photoelectric conversion units included in one of the plurality of pixel blocks; and converting the read-out signal into a digital signal. [Item 21] The imaging method according to Item 20, wherein the reading out includes sequentially repeating in the column direction the reading out of a plurality of photoelectric conversion units included in a plurality of pixel blocks arranged in the row direction.

[0120] 10 Imaging device 20 Optical system 22 Optical axis 24 Image processing unit 26 Control unit 28 Recording unit 30 Operation unit 32 Display unit 34 Power supply unit 36 ​​Bus line 50 Pixel unit 58 Output unit 60 Drive control unit 62 Vertical drive unit 64 Signal processing unit 68 Horizontal drive unit 100 Image sensor 120 Photoelectric conversion unit 121 Load current source 122, 122-1, 122-2, 122-3, 122-4, 122-5, 122-6, 122-7, 122-8, 122-9 Signal line 123-1 Transfer unit 123-2 Ejection unit 124 Read unit 125 Storage unit 126 Reset unit 127 Pixel output unit 128 Amplification unit 129 Selection unit 140 First semiconductor substrate 142, 142A, 142B, 142C, 142D, 142E, 142F, 142G, 142H, 142I Pixel block 150 Second semiconductor substrate 152 Global vertical drive unit 154 Global horizontal drive unit 162, 162A, 162B, 162C, 162D, 162E, 162F, 162G, 162H, 162I Signal processing block 200, 201 Unit block 202, 202-1 Pixel 210 Block vertical drive unit 220 Signal processing circuit group 222-1, 222-2, 222-3, 222-4, 222-5, 222-6, 222-7, 222-8, 222-9 Signal processing circuit 223 Circuit selection unit 224 Conversion unit 225, Holding unit 226, Memory unit 230, Pixel control line 240, Circuit control lines 245-1, 245-2, 245-3, Circuit block group 500, Peripheral circuit unit 502, Horizontal line 70, Output unit

Claims

1. An image sensor comprising: a first semiconductor substrate having a plurality of pixel blocks including a first photoelectric conversion unit that converts light into electric charge and a second photoelectric conversion unit that converts light into electric charge; and a second semiconductor substrate stacked together with the first semiconductor substrate, the second semiconductor substrate having a first circuit block that processes a signal based on the charge converted by the first photoelectric conversion unit of the first pixel block, and a second circuit block that processes a signal based on the charge converted by the second photoelectric conversion unit of the first pixel block, wherein the first circuit block is positioned opposite to the first pixel block in a first direction in which the first semiconductor substrate and the second semiconductor substrate are stacked, and the second circuit block is positioned opposite to the second pixel block in the plurality of pixel blocks in the first direction.

2. An image sensor according to claim 1, wherein the first pixel block is arranged in the column direction alongside the second pixel block.

3. The image sensor according to claim 2, wherein the first photoelectric conversion unit is arranged in the row direction alongside the second photoelectric conversion unit.

4. An image sensor according to claim 3, wherein the first photoelectric conversion unit is electrically connected to the first circuit block via a first signal line, and the second photoelectric conversion unit is electrically connected to the second circuit block via a second signal line.

5. The image sensor according to claim 3, wherein the first circuit block processes a signal based on the charge converted by the first photoelectric conversion unit when the second circuit block is processing a signal based on the charge converted by the second photoelectric conversion unit.

6. The image sensor according to claim 3, wherein the first circuit block has a first conversion unit that converts a signal based on the charge converted by the first photoelectric conversion unit into a digital signal, and the second circuit block has a second conversion unit that converts a signal based on the charge converted by the second photoelectric conversion unit into a digital signal.

7. An image sensor according to claim 6, wherein the first conversion unit converts the charge-based signal converted by the first photoelectric conversion unit into a digital signal when the second conversion unit is converting the charge-based signal converted by the second photoelectric conversion unit into a digital signal.

8. The image sensor according to claim 6, wherein the first circuit block has a first holding unit for holding the digital signal converted by the first conversion unit, and the second circuit block has a second holding unit for holding the digital signal converted by the second conversion unit.

9. The image sensor according to claim 8, wherein the first holding unit holds the digital signal converted by the first conversion unit when the second holding unit holds the digital signal converted by the second conversion unit.

10. The image sensor according to claim 3, wherein the second semiconductor substrate has a control unit that controls the electrical connection state between the first photoelectric conversion unit and the first circuit block.

11. The image sensor according to claim 10, wherein the control unit switches between a state in which the first photoelectric conversion unit and the first circuit block are electrically connected and a state in which the first photoelectric conversion unit and the first circuit block are electrically disconnected.

12. The image sensor according to claim 11, wherein the control unit switches between a state in which the second photoelectric conversion unit and the second circuit block are electrically connected and a state in which the second photoelectric conversion unit and the second circuit block are electrically disconnected.

13. The image sensor according to claim 3, wherein the second semiconductor substrate has a drive control unit that controls the driving of the first pixel block and the second pixel block.

14. The image sensor according to claim 13, wherein the drive control unit controls the first pixel block so that a plurality of pixels having the first pixel block output a signal during a first period.

15. The image sensor according to claim 14, wherein the drive control unit controls the second pixel block so that a plurality of pixels in the second pixel block output a signal during a second period that is later than the first period.

16. The image sensor according to claim 15, wherein the drive control unit controls the first pixel block so that a plurality of pixels in the first pixel block are driven by the global shutter during the first period.

17. The image sensor according to claim 16, wherein the drive control unit controls the second pixel block so that a plurality of pixels in the second pixel block are driven by the global shutter during the second period.

18. An image sensor according to claim 3, wherein the first circuit block has a first drive control unit that controls the driving of a plurality of pixels having the first pixel block, and the second circuit block has a second drive control unit that controls the driving of a plurality of pixels having the second pixel block.

19. An image sensor according to claim 18, wherein the first drive control unit controls the first pixel block so that a plurality of pixels in the first pixel block output a signal during a first period, and the second drive control unit controls the second pixel block so that a plurality of pixels in the second pixel block output a signal during a second period following the first period.

20. The image sensor according to claim 19, wherein the first drive control unit controls the first pixel block so that a plurality of pixels in the first pixel block are driven by the global shutter during the first period, and the second drive control unit controls the first pixel block so that a plurality of pixels in the second pixel block are driven by the global shutter during the second period.

21. An imaging device comprising an image sensor according to any one of claims 1 to 20.

Images