Decision feedback equalization method and device

Abstract

A decision feedback equalizer according to an embodiment of the provided invention may comprise: a sampler circuit configured to receive an input analog signal having passed through a channel, and convert the input analog signal into a digital signal; and a feedback circuit configured to feed back, to an input terminal of the sampler circuit, the digital signal output from the sampler circuit. Here, the sampler circuit includes a first circuit for a track mode and a second circuit for a regeneration mode, and the second circuit may further include at least one first-type adder circuit based on a P-type metal-oxide-semiconductor (PMOS) transistor and at least one second-type adder circuit based on an N-type metal-oxide-semiconductor (NMOS) transistor.

Description

Decision Feedback Illumination Method and Device

[0001] The present invention relates to a decision feedback equalization method and apparatus, and more specifically, to a decision feedback equalization method and apparatus with an improved structure that can minimize feedback delay in order to match the timing margin during the process of feeding back a high-speed signal.

[0002] A Decision Feedback Equalizer (DFE) is an electrical dispersion compensation technology that reduces inter-symbol errors caused by signal distortion by summing a decision value and a weight to a received signal and then equalizing the feedback.

[0003] Specifically, the Decision Feedback Equalizer (DFE) consists of a decision circuit and a transverse filter of the feedback section, and feeds back an amount that depends on the determined bit and weighting ratio to the actual bit according to the decision of the previous bit.

[0004] This can be implemented as a type of nonlinear filter capable of overcoming even very severe distortion.

[0005] Conventional decision feedback equalizers can detect digital signals, such as the output of a sampler or slicer, from a high-speed serial link and feed them back to the decision feedback equalizer circuit. At this time, the decision feedback equalizer can receive the bits of the previous UI (unit interval) that were sampled as input to eliminate Inter-Symbol Interference (ISI) occurring in the channel.

[0006] However, as data rates increase, there is a problem in that it becomes difficult to meet the conditions for the timing margin related to feedback.

[0007] The technical problem of the present disclosure is to provide a decision feedback equalization method and apparatus with an improved structure that can minimize feedback delay in order to match the timing margin during the process of feeding back a high-speed signal.

[0008] The technical problem of the present disclosure is to provide a decision feedback equalization method and apparatus having a structure including a sampler circuit combined with an adder circuit.

[0009] A decision feedback equalization device according to one aspect of the present disclosure may include: a sampler circuit configured to receive an input analog signal passing through a channel and convert it into a digital signal; and a feedback circuit configured to feed back a digital signal output from the sampler circuit to an input terminal of the sampler circuit. Herein, the sampler circuit includes a first circuit for a track mode and a second circuit for a regenerate mode, and the second circuit may further include at least one first-type adder circuit based on a PMOS (P-type Metal-Oxide-Semiconductor) transistor and at least one second-type adder circuit based on an NMOS (N-type Metal-Oxide-Semiconductor) transistor.

[0010] A method for performing decision feedback equalization according to an additional aspect of the present disclosure may include: receiving an input analog signal that has passed through a channel by a sampler circuit and converting it into a digital signal; and feeding back the digital signal output from the sampler circuit to an input terminal of the sampler circuit by a feedback circuit. Herein, the sampler circuit includes a first circuit for a track mode and a second circuit for a regenerate mode, and the second circuit may further include at least one first-type adder circuit based on a PMOS (P-type Metal-Oxide-Semiconductor) transistor and at least one second-type adder circuit based on an NMOS (N-type Metal-Oxide-Semiconductor) transistor.

[0011] A decision feedback equalization device according to a further aspect of the present disclosure may include: a sampler circuit configured to receive an input analog signal passing through a channel and convert it into a digital signal; and a feedback circuit configured to feed back a digital signal output from the sampler circuit to an input terminal of the sampler circuit. Herein, the sampler circuit includes a first circuit for a track mode and a second circuit for a regenerate mode, and the second circuit may further include at least one first-type adder circuit based on a PMOS (P-type Metal-Oxide-Semiconductor) transistor and at least one second-type adder circuit based on an NMOS (N-type Metal-Oxide-Semiconductor) transistor. Additionally, during the regenerate mode, a pull-up operation and a pull-down operation by the first-type adder circuit and the second-type adder circuit may be performed simultaneously.

[0012] In various aspects of the present disclosure, during the regeneration mode, the first-type adder circuit may be designed to operate in pair with the second-type adder circuit.

[0013] Additionally, in various aspects of the present disclosure, based on the second circuit including two first-type adder circuits and two second-type adder circuits, depending on the value of a digital signal previously sampled by the sampler circuit, one of the two first-type adder circuits and one of the two second-type adder circuits may operate in an ON state, or the other of the two first-type adder circuits and the other of the two second-type adder circuits may operate in an ON state.

[0014] Additionally, in various aspects of the present disclosure, based on the fact that the second circuit includes two first-type adder circuits and two second-type adder circuits, the two first-type adder circuits may be connected one by one to the output P terminal and the output N terminal of the sampler circuit, and the two second-type adder circuits may be connected one by one to the output P terminal and the output N terminal of the sampler circuit.

[0015] Additionally, in various aspects of the present disclosure, the first-type adder circuit and the second-type adder circuit, respectively, may each include a cross-coupled inverter and an inverter.

[0016] Additionally, in various aspects of the present disclosure, based on the fact that the track mode is initiated after the regeneration mode according to a clock value, the at least one first-type adder circuit may operate in an ON state in relation to the output terminal reset of the sampler circuit.

[0017] In addition, in various aspects of the present disclosure, the PMOS transistor and the NMOS transistor are designed to be digitally calibrated within a certain range, and the intensity of the decision feedback equalization device can be controlled based on the digital calibration in the PMOS transistor and the NMOS transistor.

[0018] Additionally, in various aspects of the present disclosure, the sampler circuit may include a first sampler circuit that receives an odd component of an input analog signal; and a second sampler circuit that receives an even component of an input analog signal.

[0019] In addition, in various aspects of the present disclosure, the sampler circuit may be configured as a quarter-rate sampler circuit.

[0020] The decision feedback equalization method and apparatus according to the embodiment of the present disclosure have the technical effect of securing a timing margin for feedback by performing compensation at the last stage of the sampler circuit.

[0021] The decision feedback equalization method and apparatus according to the embodiment of the present disclosure have the technical effect of efficiently performing a reset of the output node of the circuit based on the fact that pull-up and pull-down are performed simultaneously as the PMOS and NMOS operate simultaneously.

[0022] The decision feedback equalization method and apparatus according to the embodiment of the present disclosure drive the decision feedback equalization inverter based on previous data values, so there is a technical effect of obtaining a fast CLK-to-Q delay even in sections with many data transitions.

[0023] Figure 1 is a diagram showing the basic structure of a judgment feedback equalizer (DEF) according to the prior art.

[0024] Figure 2 is a diagram in which a resistive load in the adder circuit of a decision feedback equalizer (DEF) according to the prior art shown in Figure 1 is implemented as a single current mode logic (CML) circuit.

[0025] Figure 3 is a diagram showing an example of a sampler circuit in which an adder circuit according to the prior art is combined.

[0026] Figure 4 is a diagram showing an example of applying a sampler circuit, which is a combined adder circuit according to the prior art, to a regeneration mode.

[0027] FIG. 5 is a diagram showing an example of a track-and-regenerate slicer according to the prior art.

[0028] FIG. 6 is a diagram showing a full-rate operation structure based on a sampler circuit combined with an adder circuit according to an embodiment of the present disclosure.

[0029] FIG. 7 is a diagram showing an example of a calibration circuit according to an embodiment of the present disclosure.

[0030] Figure 8 is a diagram showing the simulation results in the case where the decision feedback equalizer (DEF) is not operating in a sampler circuit operating at full rate.

[0031] Figure 9 is a diagram showing the simulation results when the decision feedback equalizer (DEF) is in operation in a sampler circuit operating at full rate.

[0032] FIG. 10 is a diagram showing a half-rate operation structure based on a sampler circuit combined with an adder circuit according to an embodiment of the present disclosure.

[0033] Figure 11 is a diagram showing the simulation results in the case where the decision feedback equalizer (DEF) is not operating in a sampler circuit operating at half-rate.

[0034] Figure 12 is a diagram showing the simulation results when the decision feedback equalizer (DEF) is in operation in a sampler circuit operating at half-rate.

[0035] FIG. 13 illustrates a flowchart of the operation of a decision feedback equalizer including a sampler circuit combined with an adder circuit according to an embodiment of the present disclosure.

[0036] The embodiments described in this specification and the configurations illustrated in the drawings are merely preferred examples of the disclosed invention, and various modifications that may replace the embodiments and drawings of this specification may exist at the time of filing this application.

[0037] Additionally, the same reference numerals or symbols presented in each drawing of this specification represent parts or components that perform substantially the same function.

[0038] Furthermore, the terms used herein are for describing embodiments and are not intended to limit or / or restrict the disclosed invention. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0039] In this specification, terms such as “comprising” or “having” are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and do not preclude the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0040] Additionally, terms including ordinal numbers, such as "first," "second," etc., used in this specification may be used to describe various components, but said components are not limited by said terms, and said terms are used solely for the purpose of distinguishing one component from another.

[0041] For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0042] Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.

[0043] FIG. 1 is a diagram showing the basic structure of a decision feedback equalizer (DEF) according to the prior art. FIG. 2 is a diagram showing the summer circuit of the decision feedback equalizer (DEF) according to the prior art shown in FIG. 1 implemented as a current mode logic (CML) circuit with a resistive load.

[0044] Referring to FIG. 1, a decision feedback equalizer (DEF) according to the prior art is a non-linear equalizer that can be configured to quantize input analog data into digital when a sampler (SAMP) determines symbol or bit data.

[0045] In this case, the quantized data passes through a type of digital logic and can directly remove ISI from a signal mixed with ISI due to the channel.

[0046] In addition, the decision feedback equalizer shown in Fig. 2 can compensate for post-cursor ISI by using the difference in current in a summer circuit with a resistor as the load.

[0047] More specifically, the decision feedback equalizer illustrated in FIG. 2 can implement a method in which analog signals from the OUTP node and OUTN node are transmitted to a sampler circuit, and the sampler circuit quantizes the corresponding signals into digital signals and then sends them to the gates of transistors through the H1 node and H1B node.

[0048] The judgment feedback equalizer according to this conventional technology can compensate according to the characteristics of the channel, and its magnitude can be adjusted by controlling the current of the H1 node.

[0049] At this time, the output values ​​of the H1 node and H1B node are digitally determined to be 1 (VDD) or 0 (GND).

[0050] Therefore, the decision feedback equalizer according to the prior art receives data of the previous signal through a sampler circuit, thereby creating a difference in current between the OUTP node and the OUTN node, and accordingly, can effectively eliminate ISI caused by the data of the previous symbol.

[0051] As shown in Fig. 2, the decision feedback equalizer utilizing a separate summer circuit must be settled before the summer circuit samples the subsequent bit.

[0052] FIG. 3 is a diagram showing an example of a sampler circuit with an adder circuit combined according to the prior art. FIG. 4 is a diagram showing an example of a sampler circuit with an adder circuit combined according to the prior art applied to a regeneration mode.

[0053] The circuit illustrated in Fig. 3 may correspond to a conventional technology utilizing a sampler circuit combined with the most basic summer circuit.

[0054] The circuit illustrated in FIG. 4 may correspond to a circuit in which decision feedback equalization (DFE) is performed in the regeneration stage, which is the second stage of the circuit, to reduce the latency of the input pair as much as possible. In this case, the timing margin required for the feedback of the sampler circuit can be significantly reduced compared to the prior art.

[0055] FIG. 5 is a diagram showing an example of a track-and-regenerate slicer according to the prior art.

[0056] The sampler circuit based on the track and regenerate slicer shown in Fig. 5 can perform operations over two stages, a track mode and a regenerate mode, and can be composed of a total of three stages.

[0057] In this regard, in track mode, the sampler circuit is turned on via the clock (e.g., CLKB) and two stages (i.e., the first stage (1 st stage) and second stage (2 nd The input analog signal can be amplified through the stage. Based on this, data can be overwritten on the output terminals, OUTP and OUTN. At this time, the PMOS and NMOS transistors in the header and footer of the regeneration stage can be turned on at a low intensity, which can help increase the difference between OUTP and OUTN. In this case, the PMOS and NMOS transistors are configured not to operate as cross-coupled inverters.

[0058] Additionally, in regeneration mode, the track mode can be terminated as the CLKB is activated. At this time, the output of the first stage is reset by the NMOS, and the second stage is turned off as the output of the first stage is reset. As the cross-coupled inverter performing the regeneration operation by the CKB is fully turned on, the circuit can operate in a positive feedback manner. Through this, data can be converted / represented as digital outputs of 0 and 1.

[0059] The circuit of the aforementioned conventional technology has the following problems.

[0060] The circuit shown in Figure 2 requires a separate summer circuit to be placed in front of the sampler circuit, and since the summer circuit must be settled before sampling, there is a possibility of consuming excessive power as needed.

[0061] In addition, the circuit shown in Fig. 3 reduces latency to some extent, but it has the disadvantage that latency increases compared to the case where the summer circuit is combined at the regeneration stage because the summer circuit is combined at the input pair stage.

[0062] In addition, the circuit shown in Fig. 4 relies solely on NMOS for the operation of the DFE, and there is a problem in that PMOS cannot be used for the operation of the DFE.

[0063]

[0064] In order to solve the aforementioned problems, the present disclosure proposes a sampler circuit that incorporates a summer circuit structure capable of utilizing both PMOS and NMOS in DFE operation, which can more efficiently reduce latency.

[0065] A sampler circuit with a combined summer circuit proposed in this disclosure can be configured by modifying the circuit shown in FIG. 5.

[0066] The sampler circuit combined with the summer circuit proposed in this disclosure has the effect of further reducing delay by applying the summer circuit at the second stage of the sampler circuit, that is, the regeneration stage. In addition, the sampler circuit combined with the summer circuit proposed in this disclosure has the effect of enabling faster compensation because it can perform DFE operations across the P / N node by using PMOS and NMOS together. Additionally, the DFE PMOS at the P / N node can be utilized for efficient reset operation.

[0067] Hereinafter, the judgment feedback equalization device proposed in the present disclosure will be described in detail.

[0068] The decision feedback equalization device proposed in the present disclosure may include a sampler circuit configured to receive an input analog signal passing through a channel and convert it into a digital signal. That is, the decision feedback equalization device according to the embodiment of the present disclosure is an embodiment in which an equalizer is configured for the sampler circuit. In addition, the decision feedback equalization device may include a feedback circuit configured to feed back the digital signal output from the sampler circuit to the input terminal of the sampler circuit.

[0069] In this regard, the sampler circuit may include a first circuit for track mode and a second circuit for regeneration mode.

[0070] At this time, unlike the existing case (i.e., the structure of Fig. 5), at least one first-type adder circuit based on a PMOS (P-type Metal-Oxide-Semiconductor) transistor and at least one second-type adder circuit based on an NMOS (N-type Metal-Oxide-Semiconductor) transistor may be additionally configured / included in the second circuit for the regeneration mode.

[0071] That is, in the case of the sampler circuit proposed in the present disclosure, an adder circuit based on PMOS and NMOS can be incorporated into the sampler circuit.

[0072] A sampler circuit according to the present disclosure receives an input analog signal and can operate in track mode to start sampling when the value of the clock (e.g., CLKB) becomes 1. In addition, it can widen / distinguish the voltage difference during the process of transmitting the input analog signal to the drain node. And, the second stage (2 nd The stage operates like a common source amplifier, but the DFE operates in conjunction to eliminate amplified 1-tap ISI. Therefore, the output of the sampler circuit through track mode is in a state where ISI has been removed. Subsequently, it enters regeneration mode, the CLK is activated, and the components that operated in track mode are turned off. At this time, the first stage (1 st The drain node of the stage is reset to 0, and the cross-couple inverter can expand / separate the value that was expanded / separated in track mode into a digital value.

[0073] FIG. 6 is a diagram showing a full-rate operation structure based on a sampler circuit combined with an adder circuit according to an embodiment of the present disclosure.

[0074] Referring to FIG. 6, two first-type adder circuits (610, 620) based on PMOS transistors and two second-type adder circuits (630, 640) based on NMOS transistors may be additionally configured in the regenerate stage of the sampler circuit.

[0075] Specifically, as shown in FIG. 6, each of the first-type adder circuit and the second-type adder circuit may be configured to include a cross-coupled inverter and an inverter in addition to a PMOS transistor or an NMOS transistor.

[0076] In this disclosure, for the sake of clarity of explanation, a representative example is described where two Type 1 adder circuits and two Type 2 adder circuits are merged into a sampler circuit, but the proposed method of this disclosure may be extended to apply to a range where the number of Type 1 adder circuits and Type 2 adder circuits exceeds two.

[0077] For example, if the circuit for the regeneration mode (i.e., the second circuit described above) includes two first-type adder circuits and two second-type adder circuits, the two first-type adder circuits are each connected to the output P terminal and the output N terminal of the corresponding sampler circuit, and similarly, the two second-type adder circuits can be each connected to the output P terminal and the output N terminal of the corresponding sampler circuit.

[0078] Based on the structure illustrated in FIG. 6, the cross-coupled inverter can operate such that each inverter connected to the output P terminal (e.g., OUTP) or output N terminal (e.g., OUTN) turns on only one NMOS or PMOS depending on the output value of the previous data. This allows 1 tap ISI to be eliminated in track mode.

[0079] For example, if the circuit for the regeneration mode (i.e., the second circuit described above) includes two first-type adder circuits and two second-type adder circuits, depending on the value of the digital signal previously sampled by the sampler circuit, one of the two first-type adder circuits and one of the two second-type adder circuits may operate in an ON state, or the other of the two first-type adder circuits and the other of the two second-type adder circuits may operate in an ON state.

[0080] As a specific example, the first type adder circuit (610) can operate in pair with the second type adder circuit (640), and the first type adder circuit (620) can operate in pair with the second type adder circuit (630).

[0081] Additionally, in the case of the decision feedback equalizer, when the clock (e.g., CLKB) is turned on, the PMOSs across the decision feedback equalizer (DFE) are turned on after the regeneration process, which can assist in the reset operation to VDD. In this regard, a reset-to-zero signal can be applied to the header and footer of the circuit for the regeneration mode so that the DFE operates as a reset circuit during the reset period.

[0082] For example, when a track mode is initiated after a regeneration mode according to a clock value, at least one first-type adder circuit (e.g., two first-type adder circuits (610, 620)) may operate in an ON state in relation to the output terminal reset of the corresponding sampler circuit. This is because a pull-up operation is performed as the PMOS operates as a DFE.

[0083] Additionally, the intensity adjustment of the judgment feedback equalizer can be performed through digital calibration based on the calibration circuits (615, 625, 635, 645) shown in FIG. 6, thereby enabling compensation for channels in various environments and various input voltage swings within the calibration range.

[0084] FIG. 7 is a diagram showing an example of a calibration circuit according to an embodiment of the present disclosure.

[0085] Referring to FIG. 7, the calibration circuit (615, 625) in FIG. 6 can be configured with the structure shown in FIG. 7 (a), and the calibration circuit (635, 645) in FIG. 6 can be configured with the structure shown in FIG. 7 (b).

[0086] For example, the aforementioned PMOS transistor and NMOS transistor are designed to enable digital calibration within a certain range, and the intensity of the decision feedback equalization device can be controlled based on the digital calibration in the PMOS transistor and the NMOS transistor.

[0087] Based on the structure illustrated in Fig. 6, the sampler circuit performs sampling at a full rate and may be in a form that compensates its own output node through DFE without odd paths and even paths.

[0088] For example, since twice the clock speed is required for a sampler circuit to operate at a full rate compared to when it operates at a half rate, the present disclosure explains the results of a simulation verification performed at a data rate of 12 Gbps as an example.

[0089] In this regard, as the data rate is lowered, a stronger 1-tap ISI and a smaller input swing environment are configured. In other words, as the data rate is lowered, an environment that is more difficult to sample can be configured.

[0090] FIG. 8 is a diagram showing the simulation results when the decision feedback equalizer (DEF) is not operating in a sampler circuit operating at full rate. FIG. 9 is a diagram showing the simulation results when the decision feedback equalizer (DEF) is operating in a sampler circuit operating at full rate.

[0091] Referring to FIG. 8, when the decision feedback equalizer is not operating, the clock-to-Q delay associated with sampling may be 19.6 ps for the first interval (810) and 27.5 ps for the second interval (820). Here, the second interval (820) may correspond to the worst case in terms of digital signal conversion. In this regard, the worst case may correspond to the case where an input with a small difference between VINN and VINP is received.

[0092] In contrast, referring to FIG. 9, when the decision feedback equalizer according to the present disclosure is in operation, the clock-to-Q delay associated with sampling may be 21.1 ps for the first interval (910) and 22.3 ps for the second interval (920). Here, the second interval (920) may correspond to the worst case in terms of digital signal conversion. In this regard, the worst case may correspond to the case where an input with a small difference between VINN and VINP is received.

[0093] That is, referring to the results of FIGS. 8 and FIGS. 9, by operating the decision feedback equalizer according to the present disclosure, the clock-to-Q delay can be secured / advanced by 5 ps at the time corresponding to the red box.

[0094] In addition, the embodiments of the decision feedback equalization device proposed in this disclosure are not limited to a sampler circuit operating at full rate, and the sampler circuit may be configured as a sampler circuit operating at half rate or quarter rate.

[0095] FIG. 10 is a diagram showing a half-rate operation structure based on a sampler circuit combined with an adder circuit according to an embodiment of the present disclosure.

[0096] Referring to FIG. 10, a sampler circuit operating at half-rate may be configured to include a first sampler circuit (1010a) that receives an odd component of an input analog signal and a second sampler circuit (1010b) that receives an even component of an input analog signal.

[0097] For example, the first sampler circuit (1010a) and the second sampler circuit (1010b) may be configured as a track-and-regenerate slicer structure as shown in FIG. 5.

[0098] In addition, two adder circuits (1020a, 1020b) may be connected in relation to the first sampler circuit and the second sampler circuit, and each adder circuit may be configured with a structure as described above in the present disclosure.

[0099] For example, each adder circuit may be based on a digitally calibrated adjustable PMOS or NMOS and may be configured to include a cross-coupled inverter and an inverter.

[0100] When the sampler circuit is configured for half-rate operation, a method of applying DFE to the odd path based on the data value sampled in the even path may be applied. Similarly, a method of applying DFE to the even path based on the data value sampled in the odd path may be applied.

[0101] For example, if the 1-tap ISI is removed based on the odd path, it may be possible to compensate for sampling the even path.

[0102] To verify the performance of the decision feedback equalizer (DFE) according to the present disclosure, a simulation environment can be configured to sample at a speed of 20 Gbps by applying a 10 GHz clock to two sampler circuits operating at half-rate. The simulation results depending on whether the decision feedback equalizer (DFE) is operating are as shown in FIGS. 11 and FIGS. 12.

[0103] Figure 11 is a diagram showing the simulation results when the decision feedback equalizer (DEF) is not operating in a sampler circuit operating at half-rate. In addition, Figure 12 is a diagram showing the simulation results when the decision feedback equalizer (DEF) is operating in a sampler circuit operating at half-rate.

[0104] Referring to FIG. 11, when an input with a large difference between VINN and VINP is received, such as the input in the first interval (1110) (i.e., at time 10.4ns), it can be seen that the cross-coupled inverter relatively quickly separates the digital values ​​(i.e., distinguishes and converts them). As an indicator for judging this, the clock-to-Q delay in the first interval (1110) is 16.8ps.

[0105] In contrast, the worst case, such as the input in the second interval (1120) (i.e., at time 11.2ns), is when an input with a small difference between VINN and VINP is received (i.e., the worst case), the conversion to a digital value takes longer because the information that needs to be spread out (i.e., separated and converted) in the regeneration mode is large. The clock-to-Q delay in the second interval (1120) is 38.6ps, which may mean that the ideal sampler operation fails.

[0106] On the other hand, referring to FIG. 12, when the DFE according to the present disclosure is operated, it can be seen that the regeneration operation is performed relatively quickly in the second section (1220), which corresponds to the worst case, i.e., the second section (1120) (i.e., at time 11.2ns), where regeneration took a long time due to the input where the difference between VINN and VINP in FIG. 11 was very small. At this time, the clock-to-Q delay in the second section (1220) is 22.5 ps, which may mean that the sampling performance has improved compared to the result in FIG. 11 (i.e., 38.6 ps).

[0107] Therefore, through the aforementioned simulation results, it can be confirmed that the use of the DFE proposed in this disclosure effectively eliminates ISI in relation to sampling.

[0108] FIG. 13 illustrates a flowchart of the operation of a decision feedback equalizer including a sampler circuit combined with an adder circuit according to an embodiment of the present disclosure.

[0109] The operation in FIG. 13 may be based on the operation of the decision feedback equalization device described through FIG. 1 to FIG. 12 of the present disclosure.

[0110] The sampler circuit included in the decision feedback equalization device can receive an input analog signal that has passed through the channel and convert it into a digital signal (S1310).

[0111] According to an embodiment of the present disclosure, the sampler circuit may include a first circuit for a track mode and a second circuit for a regenerate mode. Here, the second circuit may be configured to include at least one first-type adder circuit based on a PMOS (P-type Metal-Oxide-Semiconductor) transistor and at least one second-type adder circuit based on an NMOS (N-type Metal-Oxide-Semiconductor) transistor.

[0112] For example, if the second circuit includes two first-type adder circuits and two second-type adder circuits, the two first-type adder circuits may be connected one by one to the output P terminal and output N terminal of the corresponding sampler circuit, and the two second-type adder circuits may be connected one by one to the output P terminal and output N terminal of the corresponding sampler circuit.

[0113] In this regard, during the regeneration mode, pull-up and pull-down operations by the first-type adder circuit and the second-type adder circuit can be performed simultaneously.

[0114] For example, if the second circuit includes two first-type adder circuits and two second-type adder circuits, depending on the value of a digital signal previously sampled by a sampler circuit, one of the two first-type adder circuits and one of the two second-type adder circuits may operate in an ON state, or the other of the two first-type adder circuits and the other of the two second-type adder circuits may operate in an ON state.

[0115] In addition, the feedback circuit included in the decision feedback equalization device can feed back the digital signal output from the sampler circuit to the input terminal of the sampler circuit (S1320).

[0116] Additionally or alternatively, according to an embodiment of the present disclosure, when a track mode is initiated after a regeneration mode based on a clock value, the above-described at least one first-type adder circuit may operate in an ON state in relation to the reset of the output terminal of the sampler circuit. For example, the process of resetting the output terminal of the sampler circuit to VDD can be efficiently performed by performing a pull-up operation by the operation of a PMOS-based DFE.

[0117] Additionally or alternatively, according to embodiments of the present disclosure, the PMOS transistor and the NMOS transistor may be designed to be digitally calibrated within a certain range. Based on this, the intensity of the decision feedback equalization device may be controlled based on the digital calibration in the PMOS transistor and the NMOS transistor.

[0118]

[0119] The decision feedback equalizer proposed in this disclosure is a structure designed to overcome the decreasing timing margin / constraint required for a decision feedback equalizer (DFE) to perform feedback as the data rate required in high-speed interfaces increases. This is because the decision feedback equalizer (DFE) must complete feedback within 1 UI* unit interval for appropriate compensation.

[0120] In the case of the sampler circuit proposed in this disclosure (e.g., the structure of FIG. 6), the third stage, which is the last stage (3 rd Since the reward proceeds in the stage), the first stage (1 ststage) and second stage (2 nd There is a technical effect of securing additional time equivalent to the delay consumed in the stage.

[0121] Additionally, in the case of the sampler circuit proposed in this disclosure, unlike the prior art, the PMOS and NMOS operate simultaneously as a decision feedback equalizer (DFE), so the decision feedback equalizer (DFE) has the technical effect of being able to perform not only a pull-down operation but also a pull-up operation simultaneously.

[0122] Additionally, in the case of the sampler circuit proposed in this disclosure, there is a technical effect in that the operation of resetting the output node of the circuit can be efficiently performed by turning on the PMOS connected to the node OUTP / OUTN of the decision feedback equalizer (DFE) in the regeneration mode.

[0123] Additionally, in the case of a sampler circuit according to the prior art, since the always-on NMOS and PMOS simply assist in amplification based on the input analog signal in track mode, there is a problem in that the clock-to-Q delay of the sampler circuit becomes somewhat slow in sections with many data transitions. In contrast, the sampler circuit proposed in this disclosure drives the inverter of the decision feedback equalizer (DFE) based on the previous data value (i.e., the previously sampled value), so there is a technical effect of obtaining a fast clock-to-Q delay even in sections with many data transitions.

[0124]

[0125] The device described above may be implemented as a hardware component, a software component, and / or a combination of a hardware component and a software component. For example, the device and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications executed on the operating system. Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. In addition, other processing configurations, such as parallel processors, are also possible.

[0126] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or instruct the processing unit independently or collectively. Software and / or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0127] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., either alone or in combination. The program instructions recorded on the medium may be those specifically designed and configured for the embodiment, or they may be those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

[0128] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents. Therefore, other implementations, other embodiments, and equivalents to the claims below are also within the scope of the claims.

Claims

1. A sampler circuit configured to receive an input analog signal passing through a channel and convert it into a digital signal; and A feedback circuit configured to feed back a digital signal output from the sampler circuit to the input terminal of the sampler circuit, wherein The sampler circuit above includes a first circuit for track mode and a second circuit for regenerate mode, and The second circuit is characterized by further comprising at least one first-type adder circuit based on a PMOS (P-type Metal-Oxide-Semiconductor) transistor and at least one second-type adder circuit based on an NMOS (N-type Metal-Oxide-Semiconductor) transistor. Judgment feedback light device.

2. In Paragraph 1, Characterized in that, during the above regeneration mode, the first-type adder circuit is designed to operate in pair with the second-type adder circuit. Judgment feedback light device.

3. In Paragraph 1, Based on the fact that the above second circuit includes two first-type adder circuits and two second-type adder circuits, Depending on the value of the digital signal previously sampled by the sampler circuit, one of the two first-type adder circuits and one of the two second-type adder circuits operate in an ON state, or Characterized by the other of the two first-type adder circuits and the other of the two second-type adder circuits operating in an ON state. Judgment feedback light device.

4. In Paragraph 1, Based on the fact that the above second circuit includes two first-type adder circuits and two second-type adder circuits, The two first-type adder circuits are each connected to the output P terminal and output N terminal of the sampler circuit, respectively, and The above two second-type adder circuits are characterized by being connected one by one to the output P terminal and the output N terminal of the sampler circuit, Judgment feedback light device.

5. In Paragraph 1, Each of the above-mentioned first-type adder circuit and the above-mentioned second-type adder circuit is characterized by including a cross-coupled inverter and an inverter. Judgment feedback light device.

6. In Paragraph 1, Based on the fact that the track mode is initiated after the regeneration mode according to the clock value, the at least one first-type adder circuit is characterized by operating in an ON state in relation to the output terminal reset of the sampler circuit. Judgment feedback light device.

7. In Paragraph 1, The above PMOS transistor and the above NMOS transistor are designed to enable digital calibration within a certain range, and The intensity of the above decision feedback equalization device is characterized by being controlled based on digital calibration in the PMOS transistor and the NMOS transistor. Judgment feedback light device.

8. In Paragraph 1, The above sampler circuit is A first sampler circuit that receives the odd component of an input analog signal; and Characterized by including a second sampler circuit that receives the even component of the input analog signal, Judgment feedback light device.

9. In Paragraph 1, The above sampler circuit is characterized by being composed of a quarter-rate sampler circuit. Judgment feedback light device.

10. In a method for performing decision feedback equilibrium, A step of receiving an input analog signal that has passed through a channel and converting it into a digital signal by means of a sampler circuit; and The method includes the step of feeding back a digital signal output from the sampler circuit to the input terminal of the sampler circuit by means of a feedback circuit, The sampler circuit above includes a first circuit for track mode and a second circuit for regenerate mode, and A method characterized in that the second circuit further comprises at least one first-type adder circuit based on a PMOS (P-type Metal-Oxide-Semiconductor) transistor and at least one second-type adder circuit based on an NMOS (N-type Metal-Oxide-Semiconductor) transistor.

11. In Paragraph 10, Based on the fact that the above second circuit includes two first-type adder circuits and two second-type adder circuits, A method characterized by further comprising the step of operating one of the two first-type adder circuits and one of the two second-type adder circuits in an ON state according to the value of a digital signal previously sampled by the sampler circuit, or the step of operating the other of the two first-type adder circuits and the other of the two second-type adder circuits in an ON state.

12. In Paragraph 10, Based on the fact that the above second circuit includes two first-type adder circuits and two second-type adder circuits, The two first-type adder circuits are each connected to the output P terminal and output N terminal of the sampler circuit, respectively, and A method characterized in that the two second-type adder circuits are each connected to the output P terminal and the output N terminal of the sampler circuit.

13. In Paragraph 10, A method characterized by further including the step of the at least one first-type adder circuit operating in an ON state in relation to the output terminal reset of the sampler circuit, based on the fact that the track mode is initiated after the regeneration mode according to the clock value.

14. In Paragraph 10, The above PMOS transistor and the above NMOS transistor are designed to enable digital calibration within a certain range, and A method characterized by further including the step of controlling the intensity of the above-described decision feedback equalization device based on digital calibration in the PMOS transistor and the NMOS transistor.

15. A sampler circuit configured to receive an input analog signal passing through a channel and convert it into a digital signal; and A feedback circuit configured to feed back a digital signal output from the sampler circuit to the input terminal of the sampler circuit, wherein The sampler circuit above includes a first circuit for track mode and a second circuit for regenerate mode, and The second circuit further comprises at least one first-type adder circuit based on a PMOS (P-type Metal-Oxide-Semiconductor) transistor and at least one second-type adder circuit based on an NMOS (N-type Metal-Oxide-Semiconductor) transistor, and Characterized that, during the above regeneration mode, pull-up and pull-down operations by the first-type adder circuit and the second-type adder circuit are performed simultaneously. Judgment feedback light device.

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