Display panel and electronic apparatus comprising same

Abstract

An embodiment of the present invention provides a display panel comprising: a substrate including a display area and a non-display area located outside the display area; a driving voltage input unit disposed in the non-display area and including a horizontal driving voltage input unit extending in a first direction and a vertical driving voltage input unit extending in a second direction crossing the first direction; and a common voltage input unit disposed in the non-display area and spaced apart from the driving voltage input unit, wherein the vertical driving voltage input unit includes a first vertical driving voltage input unit having a side surface extending in the second direction, a second vertical driving voltage input unit having a side surface extending in a diagonal direction between the first direction and the second direction, and a third vertical driving voltage input unit having a side surface extending in the second direction, and the first vertical driving voltage input unit, the second vertical driving voltage input unit, and the third vertical driving voltage input unit are sequentially arranged in the second direction.

Description

Display panel and electronic device including the same

[0001] The present invention relates to a display panel and an electronic device including the same.

[0002] Generally, as display panels that visually represent electrical signals evolve, various display panels with excellent characteristics such as thinness, light weight, and low power consumption, as well as electronic devices containing them, are being introduced. Display panels can provide images using light-emitting diodes. The applications of display panels and electronic devices containing them are becoming increasingly diverse, and various design attempts are being made to improve the quality of these display panels and electronic devices.

[0003] Embodiments of the present invention aim to provide a display panel that implements an image of excellent quality and an electronic device including the same. However, these objectives are exemplary and do not limit the scope of the present invention.

[0004] One embodiment of the present invention provides a display panel comprising: a substrate including a display area and a non-display area located outside the display area; a driving voltage input unit disposed in the non-display area and including a horizontal driving voltage input unit extending along a first direction and a vertical driving voltage input unit extending along a second direction intersecting the first direction; and a common voltage input unit disposed in the non-display area and spaced apart from the driving voltage input unit; wherein the vertical driving voltage input unit comprises a first vertical driving voltage input unit having a side extending along the second direction, a second vertical driving voltage input unit having a side extending in a diagonal direction between the first direction and the second direction, and a third vertical driving voltage input unit having a side extending in the second direction, and wherein the first vertical driving voltage input unit, the second vertical driving voltage input unit, and the third vertical driving voltage input unit are sequentially disposed along the second direction.

[0005] In one embodiment, the horizontal driving voltage input unit, the first vertical driving voltage input unit, the second vertical driving voltage input unit, and the third vertical driving voltage input unit may be formed integrally.

[0006] In one embodiment, the second vertical driving voltage input may have a planar trapezoidal shape.

[0007] In one embodiment, the first vertical driving voltage input has a first width along the first direction, and the third vertical driving voltage input has a second width different from the first width along the first direction, and the second vertical driving voltage input may have the first width on one side close to the first vertical driving voltage input and the second width on the other side close to the third vertical driving voltage input.

[0008] In one embodiment, the common voltage input is provided as a plurality of common voltage inputs, and the vertical driving voltage input may be disposed between the common voltage inputs arranged adjacent to each other along the first direction.

[0009] In one embodiment, the non-display area includes a separation area in which the driving voltage input part and the common voltage input part are spaced apart from each other, and the separation area may include a portion extending in the diagonal direction, which exposes the upper surface of an insulating layer disposed below the driving voltage input part and the common voltage input part. In one embodiment, the non-display area includes a separation area in which the driving voltage input part and the common voltage input part are spaced apart from each other, and the separation area includes: a first separation area extending along the first direction between the horizontal driving voltage input part and the common voltage input part; a second separation area extending along the second direction between the first vertical driving voltage input part and the common voltage input part; and a third separation area extending in the diagonal direction between the second vertical driving voltage input part and the common voltage input part. and may include a fourth separation area extending in the second direction between the third vertical driving voltage input unit and the common voltage input unit. In one embodiment, it further includes dams disposed in the non-display area and disposed on the driving voltage input unit and the common voltage input unit; wherein the plurality of dams are disposed to surround the display area and the dams may be disposed to overlap the vertical driving voltage input unit and the common voltage input unit. In one embodiment, the display panel may further include dams disposed in the non-display area, disposed on the driving voltage input unit and the common voltage input unit, and disposed to surround the display area; and the dam among the dams disposed closest to the display area may be disposed to overlap the second vertical driving voltage input unit.

[0010] In one embodiment, the display panel further comprises: dams disposed in the non-display area and disposed on the driving voltage input unit and the common voltage input unit, and disposed to surround the display area in a planar manner; insulating layers disposed on the driving voltage input unit and the common voltage input unit; and a light-emitting diode disposed in the display area and electrically connected to a contact area of ​​the common voltage input unit; wherein the contact area is an area in which a portion of the insulating layers is removed to expose the upper surface of the common voltage input unit, and the contact area may be disposed closer to the display area than the plurality of dams. In one embodiment, the display panel comprises: dams disposed in the non-display area and disposed on the driving voltage input unit and the common voltage input unit, and disposed to surround the display area in a planar manner; and a light-emitting diode disposed in the display area. and further comprising an encapsulation layer covering the light-emitting diode; wherein the encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer and in direct contact with the first inorganic encapsulation layer on the dams.

[0011] Another embodiment of the present invention provides a display panel comprising: a substrate including a display area and a non-display area located outside the display area; a driving voltage input unit disposed in the non-display area and including a horizontal driving voltage input unit extending along a first direction and a vertical driving voltage input unit extending along a second direction intersecting the first direction; and a common voltage input unit disposed in the non-display area and spaced apart from the driving voltage input unit; wherein the non-display area is an area spaced apart from the driving voltage input unit and the common voltage input unit, and includes a spaced-away area including a portion extending in a diagonal direction between the first direction and the second direction.

[0012] In one embodiment, the separation area may expose the upper surface of an insulating layer disposed below the driving voltage input section and the common voltage input section.

[0013] In one embodiment, the common voltage input unit is positioned in the non-display area and spaced apart from the driving voltage input unit, and the vertical driving voltage input unit includes a first vertical driving voltage input unit having a side extending along the second direction toward the common voltage input unit, a second vertical driving voltage input unit having a trapezoidal shape in a planar form and extending in the diagonal direction toward the common voltage input unit, and a third vertical driving voltage input unit having a side extending along the second direction toward the common voltage input unit, and the first vertical driving voltage input unit, the second vertical driving voltage input unit, and the third vertical driving voltage input unit may be sequentially positioned along the second direction. In one embodiment, it further includes dams positioned in the non-display area, positioned on the driving voltage input unit and the common voltage input unit, and positioned to surround the display area in a planar form; and the dam positioned closest to the display area among the dams may overlap with a part of the spaced-away area extending in the diagonal direction. In one embodiment, positioned in the non-display area, It may further include dams disposed on the driving voltage input section and the common voltage input section and arranged to surround the display area in a planar plane; and a light-emitting diode disposed in the display area and electrically connected to a contact area of ​​the common voltage input section that is disposed closer to the display area than the dams in a planar plane.

[0014] Another embodiment of the present invention provides an electronic device comprising: a display panel; and a lower cover defining an opening that exposes a portion of the display panel as an exterior, wherein the display panel comprises: a substrate including a display area and a non-display area located outside the display area; a driving voltage input unit disposed in the non-display area and including a horizontal driving voltage input unit extending along a first direction and a vertical driving voltage input unit extending along a second direction intersecting the first direction; and a common voltage input unit disposed in the non-display area and spaced apart from the driving voltage input unit; wherein the vertical driving voltage input unit comprises a first vertical driving voltage input unit having a side extending along the second direction, a second vertical driving voltage input unit having a side extending diagonally between the first direction and the second direction, and a third vertical driving voltage input unit having a side extending in the second direction, wherein the first vertical driving voltage input unit, the second vertical driving voltage input unit, and the third vertical driving voltage input unit are sequentially disposed along the second direction.

[0015] In one embodiment, the non-display area includes a separation area in which the driving voltage input part and the common voltage input part are separated from each other, and the separation area may include a portion extending in the diagonal direction, which exposes the upper surface of an insulating layer disposed below the driving voltage input part and the common voltage input part.

[0016] In one embodiment, the electronic device further includes dams that are positioned in the non-display area, positioned on the driving voltage input unit and the common voltage input unit, and positioned to surround the display area in a planar manner; wherein the dam closest to the display area among the dams may be positioned to overlap with the second vertical driving voltage input unit in a planar manner.

[0017] In one embodiment, the electronic device may further include: dams disposed in the non-display area, disposed on the driving voltage input part and the common voltage input part, and disposed to surround the display area in a planar manner; and a light-emitting diode disposed in the display area and electrically connected to a contact area of ​​the common voltage input part disposed closer to the display area than the dams in a planar manner.

[0018] According to some embodiments of the present invention, a display panel and an electronic device that realize an image of excellent quality can be provided. The aforementioned effects are exemplary and the effects of the present invention are not limited to those described above.

[0019] FIG. 1a is a schematic perspective view of an electronic device according to one embodiment of the present invention.

[0020] FIG. 1b is a block diagram schematically illustrating an electronic device according to one embodiment of the present invention.

[0021] FIG. 2 is a schematic perspective view of a display panel according to one embodiment of the present invention.

[0022] FIG. 3 is a cross-sectional view schematically showing a display panel according to one embodiment of the present invention.

[0023] FIG. 4 is an equivalent circuit diagram of a pixel provided by a display panel according to one embodiment of the present invention.

[0024] FIG. 5 is a schematic plan view of a display panel according to one embodiment of the present invention.

[0025] Figure 6 is a cross-sectional view taken along the line A-A' of the display panel of Figure 5.

[0026] Figure 7 is a cross-sectional view taken along the line B-B' of the display panel of Figure 5.

[0027] FIGS. 8A and FIGS. 8B are schematic plan views showing a portion of a display panel according to one embodiment of the present invention.

[0028] FIG. 8c is an enlarged plan view schematically illustrating area D of the display panel of FIG. 8b.

[0029] Figure 9 is a cross-sectional view taken along the line E-E' of the display panel of Figure 8b.

[0030] Some embodiments of this specification and methods of implementation thereof may be more easily understood by referring to the detailed description of the embodiments below and the accompanying drawings. The described embodiments are merely examples intended to fully and completely explain the invention and to enable a person skilled in the art to fully understand various aspects of the invention. Accordingly, processes, elements, technical details, etc., that are not directly related to the description of the embodiments or are unnecessarily redundant may be omitted. Unless otherwise noted, the same reference numerals or letters (or combinations thereof) throughout the accompanying drawings and descriptions represent the same or similar components, and redundant descriptions thereof may be omitted.

[0031] The described embodiments are subject to various modifications and may be implemented in various forms, and should not be interpreted as being limited only to the embodiments illustrated herein. Expressions such as "can," "may," and "may not" in this specification indicate one or more embodiments of the present invention.

[0032] Considering the entirety of this specification, a person skilled in the art will understand that each suitable feature according to various embodiments of the invention may be combined or combined with one another, either partially or wholly, and may be technically interconnected to operate in various suitable ways. Furthermore, unless otherwise stated or implied, each embodiment may be implemented in a suitable manner, either independently or in a combined form.

[0033] The relative sizes of elements, layers, regions, etc., in the drawings may be exaggerated to aid clarity and understanding. That is, the size or thickness of each component depicted in the drawings is depicted arbitrarily for convenience of explanation and is not limited thereto. Furthermore, cross-hatching or shading used in the accompanying drawings is merely a general method of indication to clearly distinguish the boundaries between adjacent components. Therefore, unless specifically stated otherwise, the presence or absence of cross-hatching or shading does not imply or limit specific materials, material properties, dimensions, proportions, commonalities between depicted components, or other characteristics or attributes. Various embodiments disclosed herein are described with reference to schematic sectional illustrations, which schematically represent embodiments and / or intermediate structures. Therefore, differences may occur between the shapes depicted in the drawings and the actual shapes due to factors such as manufacturing processes or tolerances. Additionally, specific structural or functional descriptions disclosed herein are for illustrative purposes only to explain embodiments according to the concept of the present invention. Accordingly, the embodiments disclosed in this specification should not be interpreted as being limited to the shapes of the components, layers, or regions depicted in the drawings, and should be understood to include variations in shape that may occur, for example, due to the manufacturing process. For example, the implanted region depicted as a rectangle in the drawings may generally have curved or curved features at the corners or a gradient in which the implantation concentration gradually changes, rather than being dichotomously separated into an implanted region and a non-implanted region. Similarly, in the case of the buried region formed by ion implantation, some ions may also be implanted in the section between the implanted surface and the buried region.

[0034] For convenience of explanation, spatially relative terms such as "beneath," "below," "lower," "lower side," "under," "above," "upper," "over," "higher," "upper side," and "side" (e.g., "sidewall") may be used in this specification to describe the relationship between one component or feature and another component or feature as illustrated in the drawings. It should be understood that these spatially relative terms may apply not only to the directions illustrated in the drawings but also to various directions in which the device is actually used or operated. For example, if the device illustrated in the drawings is inverted, an element described as being "below" or "under" another component may be located "above." Therefore, terms such as "below" and "under" may encompass both vertical directions. Additionally, since the device may be rotated 90 degrees or oriented in a different direction, such spatial relative terms used in this specification should be interpreted accordingly. Likewise, when a first part is described as being placed "on" a second part, this does not necessarily mean that it is limited to the upper side with respect to the direction of gravity, but that the first part may be placed on either the upper or lower side of the second part.

[0035] Furthermore, the expression "in a plan view" refers to viewing the subject part from above, and the expression "in a schematic cross-sectional view" refers to viewing a schematic cross-section obtained by vertically cutting the subject part from the side. The terms "overlap" or "overlapped" mean that the first object may be located above, below, or to the side of the second object, and include the opposite case. Additionally, the term "overlap" may include meanings such as stack, face / facing, extending over, covering, and partly covering, as understood by a person skilled in the art. Conversely, the expression "not overlap" may include meanings such as "apart from," "set aside from," or "offset from," and includes other similar meanings understood by a person skilled in the art. Furthermore, the terms "face" and "facing" imply that the first object may directly or indirectly oppose the second object. Even when a third object is interposed between the first and second objects, they can still be understood as facing each other and indirectly opposing one another.

[0036] Where in this specification any component, layer, region, or part (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, etc.) is described as being "formed on," "on," "connected to," or "(operatively, functionally, or communicatively) coupled to" another component, layer, region, or part, this means that the component may be directly formed or connected to the other component, or indirectly formed or connected through one or more intermediate components, layers, or regions. Furthermore, such expressions may comprehensively refer to direct or indirect coupling or connection, as well as integral or non-integral coupling or connection. For example, when one layer, region, or component is described as being "electrically connected" or "electrically coupled" to another layer, region, or component, this may mean that the two components are directly electrically connected, or that one or more intermediate layers, regions, or components are interposed. These one or more intermediate components may include switches, transistors, resistors, inductors, capacitors, diodes, etc. Accordingly, the connection is not limited to the connection forms depicted in the drawings or detailed descriptions and may include various other forms of connection. When describing embodiments in this specification, the term "connection" refers to an electrical connection unless specifically stated to be a "direct connection."Furthermore, expressions such as "directly connected" or "directly coupled" mean that one component is directly connected to, coupled to, or formed upon another component without any intermediate components. Additionally, when it is stated in this specification that a part of a layer, film, area, plate, etc., is "formed on" another part, the direction of formation is not limited to the upward direction but includes cases where it is formed in the lateral or downward direction. Conversely, when it is stated that a part of a layer, film, area, plate, etc., is "under" another part, it includes not only cases where the part is located "directly beneath" the other part, but also cases where additional components exist between them. Meanwhile, other expressions indicating the relationship between components, such as "between," "immediately between," "adjacent to," and "directly adjacent to," may be interpreted similarly. That is, when it is said that an element or layer is located "between" two elements or two layers, that element or layer may be the only element between the two components, or one or more other elements or layers may exist between them.

[0037] In this specification, when expressions such as “at least one of,” “any one of,” or “one or more of” are used before a list of multiple elements, they are used to modify the entire set of elements, rather than each individual element. For example, expressions such as “at least one of X, Y, and Z,” “at least one of X, Y, or Z,” “at least one selected from the group consisting of X, Y, and Z,” or “at least one selected from the group consisting of X, Y, or Z” may include X only, Y only, Z only, or any combination of two or more of X, Y, and Z (XY, YZ, XZ, XYZ, etc.), or variations thereof. Likewise, “at least one of A and B” or “at least one of A or B” may include A, B, or both A and B. Additionally, in this specification, “or” is generally used to mean “and / or,” and “and / or” includes one or more of the related items or all combinations thereof. For example, the expression “A and / or B” may include only A, only B, or both A and B.Similarly, when expressions such as "at least one of," "a plurality of," or "one of" are used before a list of multiple elements, they modify the entire group of listed elements rather than the individual elements. Furthermore, when written as "C to D," it refers to a range from C to D, unless otherwise noted.

[0038] In this specification, terms such as "first," "second," and "third" may be used to describe various components, parts, regions, layers, and / or sections; however, these terms are not intended to limit such components. These terms do not imply a specific order, location, or hierarchy, but are merely for identification purposes to distinguish one component, part, section, region, layer, section, or part from other components. Accordingly, the first component, part, region, layer, or section described below may be named as the second component, part, region, layer, or section, provided that it does not depart from the technical spirit and scope of the present invention. Furthermore, the use of the expression "first" does not necessarily imply or suggest the existence or necessity of a "second" or higher component. Additionally, terms such as "first" and "second" may be used to distinguish components of different categories or sets. For brevity, terms such as "first," "second," etc. may represent "first category (first-category or first-set)" and "second category (second-category or second-set)," respectively. In the examples of this specification, the x-axis, y-axis, and / or z-axis are not limited to the three axes of an orthogonal coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other or may represent other directions that are not perpendicular to each other. This applies equally to the first direction, the second direction, and / or the third direction.

[0039] The terms used herein are for the purpose of describing the embodiments and are not intended to limit the invention. In this specification, the singular forms "a" or "an" are used to include the plural form unless the context clearly indicates otherwise, and conversely, the plural form may be used to include the singular form. Furthermore, terms used herein such as "comprises," "comprising," "have," "having," "includes," and "including" indicate the presence of the specified configurations, means, steps, actions, elements, and / or parts, but do not exclude the additional presence or inclusion of other configurations, means, steps, actions, elements, parts, and / or combinations thereof.

[0040] Terms such as "substantially," "about," and "approximately" and similar expressions used herein are not terms indicating degree but terms indicating approximation, intended to account for the inherent deviation of a measured or calculated value that a person skilled in the art can recognize. For example, the expression "substantially" may include a range of ±5% of the value. Furthermore, the expressions "about" or "approximately" in this specification include the specified value and mean that it is within an acceptable range of deviation that a person skilled in the art can judge by considering the uncertainty of the relevant measurement (i.e., the limitations of the measurement system). For example, "about" may include a range within ±30%, ±20%, ±10%, ±5% of the specified value, or within one or more standard deviations. Meanwhile, the term "may" used in this specification when describing embodiments means "one or more embodiments of the present disclosure." Additionally, the expression “being the same” may mean “being substantially the same,” that is, it includes the degree to which a person skilled in the art would determine them to be the same within an acceptable range. Similarly, other expressions in this specification may also be in a form where the word “substantially” is omitted.

[0041] In some embodiments, to avoid unnecessarily complicating the understanding of the various embodiments of this specification, well-known structures or devices may be described in the accompanying drawings in relation to one or more functional blocks (e.g., block diagrams), units, and / or modules. A person skilled in the art will understand that such blocks, units, and / or modules may be physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, other electronic circuits, etc. These may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or similar hardware may be programmed and controlled using software to perform the various functions described herein and may optionally be driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware that performs specific functions, or by a combination of dedicated hardware and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from the dedicated hardware. Furthermore, in some embodiments, blocks, units, and / or modules may be physically separated into two or more individual blocks, units, and / or modules that interact with each other, and this does not depart from the scope of the invention. Conversely, in some embodiments, blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules, and this also does not depart from the scope of the invention.

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by a person skilled in the art to which the present invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted in a meaning consistent with the relevant technical field and / or the context of this specification, and should not be interpreted in an ideal or overly formal sense unless explicitly defined so in this specification.

[0043] FIG. 1a is a schematic perspective view of an electronic device (1) according to one embodiment of the present invention, and FIG. 1b is a schematic block diagram of an electronic device (1) according to one embodiment of the present invention.

[0044] Referring to FIGS. 1a and 1b, an electronic device (1) having a display panel (10) according to one embodiment of the present invention is a device for displaying video or still images, and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs). An electronic device (1) according to one embodiment can be used in wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). An electronic device (1) according to one embodiment can be used as a center information display (CID) placed on the center fascia or dashboard of a vehicle, a room mirror display replacing the side mirror of a vehicle, and a display placed on the back of the front seat for entertainment for the rear seat of a vehicle.

[0045] FIG. 1a illustrates an electronic device (1) according to one embodiment being used as a smartphone. The electronic device (1) may include a display panel (10) and a lower cover (90) disposed below the display panel (10). The electronic device (1) may include a cover window covering the upper surface of the display panel (10).

[0046] The lower cover (90) forms the exterior of the electronic device (10) and may have an opening that exposes a portion of the display panel (10) on the front surface. The lower cover (90) may be assembled with the display panel (10) in a shape where the side corresponding to the display panel (10) is open. The lower cover (90) forms the exterior of the lower surface of the electronic device (1), and a display circuit board, components, a main circuit board, a battery, a driver, etc. may be placed between the display panel (10) and the lower cover (90). The lower cover (90) may include plastic, metal, or both plastic and metal.

[0047] The electronic device (1) may include a main processor (5100), a wireless communication unit (5200), an input unit (5300), a sensor unit (540), an output unit (550), an interface unit (560), a memory (570), and / or a power supply unit (580).

[0048] The main processor (5100) can control all functions of the electronic device (1). For example, the main processor (5100) can output digital video data to a data driver through a display circuit board so that the display panel (10) displays an image. The main processor (5100) can receive detection data from a touch sensor driver. The main processor (5100) can determine whether a user touches based on the detection data and execute an action corresponding to the user's direct touch or proximity touch. The main processor (5100) may be an application processor, a central processing unit, or a system chip made of an integrated circuit.

[0049] The camera device (531) processes image frames, such as still images or video, obtained by an image sensor in camera mode and outputs them to the main processor (5100). The camera device (531) may include at least one of a camera sensor (e.g., CCD, CMOS, etc.), a photo sensor (or image sensor), and a laser sensor. The camera device (531) may be connected to an image sensor and process an image input to the image sensor.

[0050] The wireless communication unit (5200) may include at least one of a broadcast reception module (521), a mobile communication module (522), a wireless internet module (523), a short-range communication module (524), and a location information module (525).

[0051] The broadcast receiving module (521) receives broadcast signals and / or broadcast-related information from an external broadcast management server through a broadcast channel. The broadcast channel may include a satellite channel and a terrestrial channel.

[0052] A mobile communication module (522) transmits and receives wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network built according to technical standards or communication methods for mobile communication (e.g., GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), CDMA2000 (Code Division Multi Access 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc.). The wireless signals may include various forms of data such as voice call signals, video call call signals, or text / multimedia message transmission and reception.

[0053] The wireless internet module (523) refers to a module for wireless internet access. The wireless internet module (523) may be configured to transmit and receive wireless signals in a communication network according to wireless internet technologies. Examples of wireless internet technologies include WLAN (Wireless LAN), Wi-Fi® (Wireless-Fidelity, Wi-Fi® is a registered trademark of the non-profit organization Wi-Fi Alliance), Wi-Fi (Wireless Fidelity) Direct, DLNA (Digital Living Network Alliance), etc.

[0054] The short-range communication module (524) is for short-range communication, and Bluetooth TMNear-field communication can be supported using at least one of the following technologies: RFID (Radio Frequency Identification), Infrared Communication (Infrared Data Association; IrDA), UWB (Ultra Wideband), Zigbee® (Zigbee® is a registered trademark of CONNECTIVITY STANDARDS ALLIANCE, Davis, California), NFC (Near Field Communication), Wi-Fi® (Wireless-Fidelity), Wi-Fi® Direct, and Wireless USB (Wireless Universal Serial Bus). The near-field communication module (524) can support wireless communication between the electronic device (1) and a wireless communication system, between the electronic device (1) and another electronic device, or between the electronic device (1) and a network where another electronic device (or an external server) is located, through a near-field wireless communication network (Wireless Area Networks). The near-field wireless communication network may be a near-field wireless personal communication network (Wireless Personal Area Networks). Other electronic devices may be wearable devices capable of exchanging data with (or interoperable with) the electronic device (1).

[0055] The location information module (525) is a module for obtaining the location (or current location) of the electronic device (1) and may include a GPS (Global Positioning System) module or a Wi-Fi® (Wireless Fidelity) module.

[0056] The input unit (5300) may include a video input unit such as a camera device (531) for inputting a video signal, an audio input unit such as a microphone (532) for inputting an audio signal, and an input device (533) for receiving information from a user.

[0057] The camera device (531) processes image frames, such as still images or video, obtained by an image sensor in video call mode or shooting mode. The processed image frames may be displayed on a display panel (10) or stored in memory (570).

[0058] The microphone (532) processes an external acoustic signal into electrical voice data. The processed voice data can be utilized in various ways depending on the function (or application) being performed on the electronic device (1).

[0059] The main processor (5100) can control the operation of the electronic device (1) to correspond to information input through the input device (533). The input device (533) may include mechanical input means or touch input means, such as a button, dome switch, jog wheel, jog switch, etc., located on the rear or side of the electronic device (1). The touch input means may be formed by a touchscreen layer of the display panel (10).

[0060] The sensor unit (540) may include one or more sensors that sense at least one of information within the electronic device (1), surrounding environment information surrounding the electronic device (1), and user information, and generate a corresponding sensing signal. Based on these sensing signals, the main processor (5100) may control the operation or function of the electronic device (1), or perform data processing, functions, or operations related to an application installed on the electronic device (1). The sensor unit (540) may include at least one of a proximity sensor, an illumination sensor, an acceleration sensor, a magnetic sensor, a gravity sensor (G-sensor), a gyroscope sensor, a motion sensor, an RGB sensor, an infrared sensor (IR sensor: infrared sensor), a fingerprint sensor, an ultrasonic sensor, an optical sensor, a battery gauge, an environmental sensor (e.g., a barometer, a hygrometer, a thermometer, a radiation detection sensor, a heat detection sensor, a gas detection sensor, etc.), and a chemical sensor (e.g., an electronic nose, a healthcare sensor, a biometric sensor, etc.).

[0061] The output unit (550) is for generating output related to sight, hearing, or touch, and may include at least one of a display panel (10), an acoustic output unit (551), a haptic module (552), and a light output unit (553).

[0062] The display panel (10) displays (outputs) information processed by the electronic device (1). For example, the display panel (10) can display information on the execution screen of an application running on the electronic device (1), or UI (User Interface) and GUI (Graphic User Interface) information based on the execution screen information. The display panel (10) may include a display layer that displays an image and a touchscreen layer that detects touch input from a user. As a result, the display panel (10) can function as one of the input devices (533) that provide an input interface between the electronic device (1) and the user, and at the same time, as one of the output units (550) that provide an output interface between the electronic device (1) and the user.

[0063] The sound output unit (551) can output sound data received from the wireless communication unit (5200) or stored in the memory (570) in signal reception, call mode or recording mode, voice recognition mode, broadcast reception mode, etc. The sound output unit (551) may also output sound signals related to functions performed by the electronic device (1) (e.g., call signal reception sound, message reception sound, etc.). The sound output unit (551) may include a receiver and a speaker. At least one of the receiver and the speaker may be a sound generating device attached to the lower part of the display panel (10) to vibrate the display panel (10) and output sound. The sound generating device may be a piezoelectric element or a piezoelectric actuator that contracts and expands according to an electrical signal, or an exciter that generates magnetic force using a voice coil to vibrate the display panel (10).

[0064] The haptic module (552) generates various tactile effects that the user can feel. The haptic module (552) can provide vibration to the user as a tactile effect. The haptic module (552) can not only transmit tactile effects through direct contact, but can also be implemented so that the user can feel tactile effects through the sense of touch of fingers or arms.

[0065] The light output unit (553) outputs a signal to indicate the occurrence of an event using light from a light source. Examples of events occurring in the electronic device (1) may include receiving a message, receiving a call signal, a missed call, an alarm, a schedule notification, receiving an email, receiving information through an application, etc. The signal output by the light output unit (553) is implemented as the electronic device (1) emits single-color or multiple-color light from the front or back. The signal output may be terminated when the electronic device (1) detects the user's confirmation of the event.

[0066] The interface section (560) serves as a passage for various types of external devices connected to the electronic device (1). The interface section (560) may include at least one of a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device equipped with an identification module, an audio I / O (Input / Output) port, a video I / O (Input / Output) port, and an earphone port. The electronic device (1) can perform appropriate control related to the connected external device in response to the external device being connected to the interface section (560).

[0067] The memory (570) stores data that supports various functions of the electronic device (1). The memory (570) can store a number of applications running on the electronic device (1), data for the operation of the electronic device (1), and commands. At least some of the applications can be downloaded from an external server via wireless communication. The memory (570) can store applications for the operation of the main processor (5100) and can temporarily store input / output data, such as phonebooks, messages, still images, videos, etc. Additionally, the memory (570) can store haptic data for various patterns of vibration provided to the haptic module (552) and acoustic data regarding various sounds provided to the sound output unit (551). The memory (570) may include at least one type of storage medium among flash memory type, hard disk type, SSD type (Solid State Disk type), SSD type (Silicon Disk Drive type), multimedia card micro type, card type memory (e.g., SD or XD memory, etc.), RAM (random access memory; RAM), SRAM (static random access memory), ROM (read-only memory; ROM), EEPROM (electrically erasable programmable read-only memory), PROM (programmable read-only memory), magnetic memory, magnetic disk, and optical disk.

[0068] The power supply unit (580), under the control of the main processor (5100), receives external power and internal power and supplies power to each component included in the electronic device (1). The power supply unit (580) may include a battery. Additionally, the power supply unit (580) is provided with a connection port, and the connection port may be configured as an example of an interface unit (560) to which an external charger that supplies power for charging the battery is electrically connected. Alternatively, the power supply unit (580) may be configured to charge the battery wirelessly without using the connection port.

[0069] FIG. 2 is a perspective view schematically showing a display panel according to one embodiment of the present invention.

[0070] Referring to FIG. 2, the display panel (10) may include a display area (DA) that displays an image and a non-display area (NDA) that does not display an image. The display panel (10) may provide an image to the outside using light emitted from the display area (DA).

[0071] FIG. 2 illustrates a display panel (10) in which the display area (DA) is rectangular, but in other embodiments, the display area (DA) may be circular, elliptical, or a polygon such as a triangle or a pentagon. Additionally, while FIG. 2 illustrates a flat display panel, the display panel (10) may be implemented in various forms such as a flexible, foldable, or rollable display panel.

[0072] In one embodiment, the display panel (10) may be an organic light-emitting display panel. In another embodiment, the display panel (10) may be an inorganic light-emitting display panel or a quantum dot light-emitting display panel. For example, the light-emitting layer of the display element included in the display panel may include an organic material, an inorganic material, a quantum dot, an organic material and a quantum dot, an inorganic material and a quantum dot, or an organic material, an inorganic material, and a quantum dot. For convenience of explanation, the following description will focus on the case where the display panel (10) is an organic light-emitting display panel.

[0073] A plurality of pixels (PX) may be arranged in the display area (DA). In this specification, each pixel (PX) refers to a sub-pixel that emits a different color, and each pixel (PX) may be, for example, one of a red sub-pixel, a green sub-pixel, or a blue sub-pixel.

[0074] The non-display area (NDA) is an area where pixels (PX) are not placed, and power supply wiring for driving the pixels (PX) may be located therein. Additionally, a printed circuit board including a driving circuit or a terminal section to which a driver IC is connected may be placed in the non-display area (NDA). Of course, the driving circuit may also be placed in the non-display area (NDA).

[0075] FIG. 3 is a cross-sectional view schematically showing a display panel according to one embodiment of the present invention.

[0076] Referring to FIG. 3, the display panel (10) may include a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3). The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may each be pixels that emit different colors. For example, the first pixel (PX1) may emit red light (Lr), the second pixel (PX2) may emit green light (Lg), and the third pixel (PX3) may emit blue light (Lb). In one embodiment, the display panel (10) may include a lower panel (10P) and an upper panel (20P). The lower panel (10P) may include a first substrate (100) and a light-emitting element. The light-emitting element may be, for example, an organic light-emitting diode. In one embodiment, the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may each include an organic light-emitting diode. For example, the first pixel (PX1) may include a first organic light-emitting diode (OLED1). The second pixel (PX2) may include a second organic light-emitting diode (OLED2). The third pixel (PX3) may include a third organic light-emitting diode (OLED3).

[0077] In one embodiment, the first organic light-emitting diode (OLED1), the second organic light-emitting diode (OLED2), and the third organic light-emitting diode (OLED3) can emit blue light. In another embodiment, the first organic light-emitting diode (OLED1), the second organic light-emitting diode (OLED2), and the third organic light-emitting diode (OLED3) can emit red light (Lr), green light (Lg), and blue light (Lb), respectively.

[0078] The upper panel (20P) may include a second substrate (400) and a filter section (FP). In one embodiment, the filter section (FP) may include a first filter section (FP1), a second filter section (FP2), and a third filter section (FP3). Light emitted from the first organic light-emitting diode (OLED1) may pass through the first filter section (FP1) and be emitted as red light (Lr). Light emitted from the second organic light-emitting diode (OLED2) may pass through the second filter section (FP2) and be emitted as green light (Lg). Light emitted from the third organic light-emitting diode (OLED3) may pass through the third filter section (FP3) and be emitted as blue light (Lb).

[0079] In one embodiment, the filter section (FP) may include a light conversion section and a color filter layer. In one embodiment, the functional layer included in the light conversion section may include a first quantum dot layer, a second quantum dot layer, and a transmission layer. In one embodiment, the color filter layer may include a first color filter, a second color filter, and a third color filter. The first filter section (FP1) may include a first quantum dot layer and a first color filter. The second filter section (FP2) may include a second quantum dot layer and a second color filter. The third filter section (FP3) may include a transmission layer and a third color filter.

[0080] The filter section (FP) can be positioned directly on the second substrate (400). At this time, "positioned directly on the second substrate (400)" may mean that the first color filter, the second color filter, and the third color filter are formed directly on the second substrate (400) to produce the upper panel (20P). That is, the filter section (FP) can be placed on the bottom surface of the second substrate (400). After that, the upper panel (20P) can be bonded to the lower panel (10P) so that the first filter section (FP1), the second filter section (FP2), and the third filter section (FP3) face the first organic light-emitting diode (OLED1), the second organic light-emitting diode (OLED2), and the third organic light-emitting diode (OLED3), respectively.

[0081] The lower panel (10P) and the upper panel (20P) can be connected through a sealing member (900). At this time, the sealing member (900) can be positioned to surround the display area (DA) of the lower panel (10P) (e.g., on a flat plane). For example, the sealing member (900) can be positioned at the outer edge of the display area (DA) when viewed on a flat plane and can form a closed loop. In this case, the sealing member (900) and the upper panel (20P) can completely block the display area (DA) from the outside. The sealing member (900) can be provided with a sealant, frit, etc.

[0082] In one embodiment, a filler material may be placed between the lower panel (10P) and the upper panel (20P).

[0083] FIG. 4 is an equivalent circuit diagram of a pixel provided by a display device according to one embodiment of the present invention.

[0084] Referring to FIG. 4, each pixel can be implemented by a pixel circuit (PC) connected to a scan line (SL) and a data line (DL), and an organic light-emitting diode (OLED) connected to the pixel circuit (PC). The pixel circuit (PC) may include a driving thin-film transistor (T1), a switching thin-film transistor (T2), and a storage capacitor (Cst). The switching thin-film transistor (T2) is connected to the scan line (SL) and the data line (DL), and can transmit a data signal (Dm) input through the data line (DL) to the driving thin-film transistor (T1) according to a scan signal (Sn) input through the scan line (SL).

[0085] The storage capacitor (Cst) is connected to the switching thin-film transistor (T2) and the driving voltage line (PL), and can store a voltage corresponding to the difference between the voltage received from the switching thin-film transistor (T2) and the first power supply voltage (ELVDD, or driving voltage) supplied to the driving voltage line (PL).

[0086] The driving thin-film transistor (T1) is connected to the driving voltage line (PL) and the storage capacitor (Cst), and can control the driving current flowing from the driving voltage line (PL) to the organic light-emitting diode (OLED) in correspondence with the voltage value stored in the storage capacitor (Cst). The organic light-emitting diode (OLED) can emit light having a predetermined brightness by the driving current.

[0087] Figure 4 describes a case where the pixel circuit (PC) includes two thin-film transistors and one storage thin-film transistor, but the present invention is not limited thereto, and the number and circuit design can be varied.

[0088] FIG. 5 is a schematic plan view of a display panel according to one embodiment of the present invention.

[0089] As previously explained with reference to FIG. 2, the display panel (10) may include a display area (DA) in which a plurality of pixels are arranged and a non-display area (NDA) outside the display area (DA). The non-display area (NDA) is an area that does not provide an image, and may include a pad (PAD) in which a driver or voltage wiring for providing electrical signals or power to pixel circuits may be arranged and an electronic component or printed circuit board may be electrically connected.

[0090] Referring to FIG. 5, a common voltage input unit (110), a driving voltage input unit (120), and a pad (PAD) may be located in a non-display area (NDA) adjacent to the first edge (E1) of the display area (DA).

[0091] A plurality of common voltage input sections (110) may be provided along the first edge (E1) of the display area (DA). In this regard, FIG. 5 illustrates that a first common voltage input section (110a) and a second common voltage input section (110b) are respectively arranged at both ends of the first edge (E1) of the display area (DA), and third to sixth common voltage input sections (110c, 110d, 110e, 110f) are arranged spaced apart from each other along the first edge (E1).

[0092] The first common voltage input section (110a) and the second common voltage input section (110b) can be connected by a main common voltage line (1110) that extends along the second edge (E2), the third edge (E3), and the fourth edge (E4) of the display area (DA). In other words, the first common voltage input section (110a), the second common voltage input section (110b), and the main common voltage line (1110) can be formed integrally.

[0093] The common voltage input sections (110) and the main common voltage line (1110) can be electrically connected to the opposing electrodes of the organic light-emitting diodes (OLEDs, FIG. 4). For example, the opposing electrodes of the organic light-emitting diodes (OLEDs, FIG. 4) can cover the entire display area (DA) and extend to the non-display area (NDA) to come into direct contact with a part of the common voltage input sections (110) and the main common voltage line (1110).

[0094] In the display area (DA), vertical common voltage lines (1120) and horizontal common voltage lines (1130) may be arranged to be electrically connected to the common voltage input section (110) and the main common voltage line (1110). The vertical common voltage lines (1120) may electrically connect the common voltage input section (110) and the main common voltage line (1110) across the display area (DA) in a second direction (e.g., the y direction). The horizontal common voltage lines (1130) may extend from the display area (DA) in a first direction (e.g., the x direction) and may be electrically connected to the vertical common voltage lines (1120). When the area of ​​the display area (DA) is large, the opposing electrode of the organic light-emitting diode (OLED, FIG. 4) may cause a voltage drop in parts within the display area (DA). For example, the central part of the display area (DA) is located far from the common voltage input sections (110) and the main common voltage line (1110), so that a voltage drop caused by the resistance of the opposing electrode itself may occur, which may degrade the display quality. The vertical common voltage line (1120) and the horizontal common voltage line (1130) crossing the display area (DA) are connected to the opposing electrode of the organic light-emitting diode in the display area (DA), thereby preventing the aforementioned problem of voltage drop.

[0095] A plurality of driving voltage input units (120) may be provided along the first edge (E1) of the display area (DA). As shown in FIG. 5, each of the driving voltage input units (120) may be placed between common voltage input units (110) that are spaced apart from each other. Pads (PADs) may be placed corresponding to the driving voltage input units (120). For example, one driving voltage input unit (120) and the common voltage input units (110) placed on both sides with the driving voltage input unit (120) in between may be connected to a single pad (PAD) through a connection line (CL).

[0096] The driving voltage input section (120) may be electrically connected to a vertical driving voltage line (121) that crosses the display area (DA) along a second direction (e.g., y direction) and a horizontal driving voltage line (123) that crosses the display area (DA) along a first direction (e.g., x direction). The vertical driving voltage line (121) may be the driving voltage line (PL) described above in FIG. 4. When the area of ​​the display area (DA) is large, the vertical driving voltage line (121) may cause a voltage drop in parts within the display area (DA). For example, a part adjacent to the third edge (E3) of the display area (DA) may be located far from the driving voltage input section (120), and a voltage drop may be caused by the resistance of the vertical driving voltage line (121) itself. Accordingly, horizontal driving voltage lines (123) crossing the display area (DA) along the first direction (e.g., x direction) are connected to vertical driving voltage lines (121) to prevent or reduce the problem of voltage drop mentioned above.

[0097] Figure 6 is a cross-sectional view taken along the line A-A' of the display panel of Figure 5.

[0098] Referring to FIG. 6, the display panel (10) may include a first pixel (PX1), a second pixel (PX2), and a third pixel (PX3) placed on a display area (DA). Of course, this is exemplary, and the display panel (10) may include more pixels. Although FIG. 6 illustrates the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) being adjacent to each other, in other embodiments, the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may not be adjacent pixels.

[0099] The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) can produce different light. For example, the first pixel (PX1) can produce red light, the second pixel (PX2) can produce green light, and the third pixel (PX3) can produce blue light.

[0100] In one embodiment, the display panel (10) may include a lower panel (10P) and an upper panel (20P). The lower panel (10P) may include a first substrate (100) and a light-emitting element disposed on the first substrate (100). The light-emitting element may include a light-emitting layer (220). In one embodiment, the lower panel (10P) may include a first organic light-emitting diode (OLED1), a second organic light-emitting diode (OLED2), and a third organic light-emitting diode (OLED3) disposed on the first substrate (100). The first organic light-emitting diode (OLED1), the second organic light-emitting diode (OLED2), and the third organic light-emitting diode (OLED3) may include a light-emitting layer (220).

[0101] The laminated structure of the lower panel (10P) will be described in detail below.

[0102] The first substrate (100) may include a glass material, a ceramic material, a metal material, or a material having flexible or bendable properties. If the first substrate (100) has flexible or bendable properties, the first substrate (100) may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The first substrate (100) may have a single layer or a multilayer structure of the above material, and in the case of a multilayer structure, may further include an inorganic layer. In one embodiment, the first substrate (100) may have an organic / inorganic / organic structure.

[0103] A barrier layer (not shown) may be further included between the first substrate (100) and the first buffer layer (111). The barrier layer may serve to prevent or minimize the penetration of impurities from the first substrate (100), etc., into the semiconductor layer (Act). The barrier layer may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0104] A bias electrode (BSM) may be placed on the first buffer layer (111) to correspond to a thin-film transistor (TFT). (Here, "located on" may mean "above.") In one embodiment, a voltage may be applied to the bias electrode (BSM). Additionally, the bias electrode (BSM) may serve to prevent or reduce external light from reaching the semiconductor layer (Act). Accordingly, the characteristics of the thin-film transistor (TFT) may be stabilized. Meanwhile, the bias electrode (BSM) may be omitted in some cases.

[0105] A semiconductor layer (Act) may be disposed on the second buffer layer (112). The semiconductor layer (Act) may include amorphous silicon or polysilicon. In another embodiment, the semiconductor layer (Act) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In some embodiments, the semiconductor layer (Act) may be formed of a Zn oxide-based material, such as Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In another embodiment, the semiconductor layer (Act) may be an IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) semiconductor containing metals such as indium (In), gallium (Ga), and tin (Sn) in ZnO. The semiconductor layer (Act) may include a channel region and source and drain regions disposed on either side of the channel region. The semiconductor layer (Act) may be composed of a single layer or multiple layers.

[0106] A gate electrode (GE) may be disposed on the semiconductor layer (Act) with the gate insulating layer (113) in between. The gate electrode (GE) may overlap at least partially with the semiconductor layer (Act). The gate electrode (GE) may be composed of a single layer or multiple layers, including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. As an example, the gate electrode (GE) may be a single layer of Mo. A first electrode (CE1) of a storage capacitor (Cst) may be disposed on the same layer as the gate electrode (GE). The first electrode (CE1) may be formed of the same material as the gate electrode (GE).

[0107] In FIG. 6, the gate electrode (GE) of the thin-film transistor (TFT) and the first electrode (CE1) of the storage capacitor (Cst) are shown as being arranged separately, but the storage capacitor (Cst) may overlap with the thin-film transistor (TFT). In this case, the gate electrode (GE) of the thin-film transistor (TFT) can function as the first electrode (CE1) of the storage capacitor (Cst).

[0108] An interlayer insulating layer (115) may be provided to cover the gate electrode (GE) and the first electrode (CE1) of the storage capacitor (Cst). The interlayer insulating layer (115) may include silicon oxide (SiO2), silicon nitride (SiNX), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO), etc.

[0109] The second electrode (CE2), source electrode (SE), and drain electrode (DE) of the storage capacitor (Cst) may be disposed on the upper part of the interlayer insulation layer (115).

[0110] The second electrode (CE2), source electrode (SE), and drain electrode (DE) of the storage capacitor (Cst) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the second electrode (CE2), source electrode (SE), and drain electrode (DE) may be formed as a multilayer structure of Ti / Al / Ti. The source electrode (SE) and drain electrode (DE) may be connected to the source region or drain region of the semiconductor layer (Act) through contact holes.

[0111] The second electrode (CE2) of the storage capacitor (Cst) may overlap with the first electrode (CE1) with an interlayer insulating layer (115) in between to form the storage capacitor (Cst). In this case, the interlayer insulating layer (115) may function as the dielectric layer of the storage capacitor (Cst).

[0112] A wiring protection layer (117) may be disposed on the second electrode (CE2), source electrode (SE), and drain electrode (DE) of the storage capacitor (Cst). In this case, the wiring protection layer (117) may include an inorganic insulating material such as silicon nitride, silicon oxide, and / or silicon oxynitride. The wiring protection layer (117) may prevent or reduce exposure of wiring containing metal (e.g., copper, etc.) that may be damaged by an etchant during the manufacturing process of the display device to an etching environment.

[0113] A flattening layer (118) may be disposed on the wiring protection layer (117). The flattening layer (118) may be formed as a single layer or a multilayer film made of organic material and may provide a flat upper surface. The flattening layer (118) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0114] A display element may be disposed on a planarization layer (118). In one embodiment, a first organic light-emitting diode (OLED1), a second organic light-emitting diode (OLED2), and a third organic light-emitting diode (OLED3) may be disposed on the planarization layer (118). The first organic light-emitting diode (OLED1), the second organic light-emitting diode (OLED2), and the third organic light-emitting diode (OLED3) may each include a first pixel electrode (210R), a second pixel electrode (210G), and a third pixel electrode (210B). In one embodiment, the first organic light-emitting diode (OLED1), the second organic light-emitting diode (OLED2), and the third organic light-emitting diode (OLED3) may commonly include a light-emitting layer (220) and a counter electrode (230).

[0115] The first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B) may be (semi)transparent electrodes or reflective electrodes. In some embodiments, the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B) may have a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or semitransparent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may comprise at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B) may be provided with ITO / Ag / ITO.

[0116] A pixel defining film (119) may be disposed on the flattening layer (118). The pixel defining film (119) may have openings that expose the central portions of the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B), respectively. The pixel defining film (119) may cover the edges of the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B), respectively. The pixel defining film (119) can prevent or reduce the occurrence of arcs, etc., at the edges of the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B) by increasing the distance between the edges of the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B) and the opposing electrode (230) above the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B).

[0117] The pixel definition film (119) can be formed by a method such as spin coating, using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene and phenolic resin.

[0118] The light-emitting layer (220) of the first organic light-emitting diode (OLED1), the second organic light-emitting diode (OLED2), and the third organic light-emitting diode (OLED3) may include an organic material comprising a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light-emitting layer (220) may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be optionally further disposed below and above the light-emitting layer (220). In FIG. 4, the light-emitting layer (220) is shown as being integrally formed across the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B), but is not limited thereto, and various variations are possible, such as the light-emitting layer (220) being arranged to correspond to each of the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B).

[0119] The light-emitting layer (220) may include a layer that is integral across the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B) as described above, but may also include a layer patterned to correspond to each of the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B) as needed. In one embodiment, the light-emitting layer (220) may be a first color light-emitting layer. The first color light-emitting layer may be integral across the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B), and may be patterned to correspond to each of the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B) as needed. The first color-emitting layer can emit light of a first wavelength band, for example, light of a wavelength ranging from about 450 nm to about 495 nm.

[0120] The counter electrode (230) may be positioned on the light-emitting layer (220) to correspond to the first pixel electrode (210R), the second pixel electrode (210G), and the third pixel electrode (210B). This counter electrode (230) may be formed integrally in a plurality of organic light-emitting elements. In some embodiments, the counter electrode (230) may be a transparent or translucent electrode and may be formed from a metal thin film having a low work function, comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Additionally, a transparent conductive oxide (TCO) film, such as ITO, IZO, ZnO, or In2O3, may be further disposed on the metal thin film.

[0121] In one embodiment, a first light may be generated in a first light-emitting region (EA1) of a first organic light-emitting diode (OLED1) and emitted to the outside. The first light-emitting region (EA1) may be defined as a portion exposed by an opening of the pixel defining film (119) of the first pixel electrode (210R). A second light may be generated in a second light-emitting region (EA2) of a second organic light-emitting diode (OLED2) and emitted to the outside. The second light-emitting region (EA2) may be defined as a portion exposed by an opening of the pixel defining film (119) of the second pixel electrode (210G). A third light may be generated in a third light-emitting region (EA3) of a third organic light-emitting diode (OLED3) and emitted to the outside. The third light-emitting region (EA3) can be defined as the part exposed by the opening of the pixel defining film (119) among the third pixel electrodes (210B).

[0122] The first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) may be spaced apart from each other. Areas within the display area (DA) that are not the first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) may be non-light-emitting areas. The first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) may be distinguished by the non-light-emitting areas. When viewed in a planar view, the first light-emitting region (EA1), the second light-emitting region (EA2), and the third light-emitting region (EA3) are arranged in a stripe array or a pentile array. TM (PENTILE TM (This is a registered trademark of Samsung Display Co., Ltd. of the Republic of Korea) It can be arranged in various arrangements, such as an array. When viewed in a planar view, the shape of the first light-emitting region (EA1), the shape of the second light-emitting region (EA2), and the shape of the third light-emitting region (EA3) may each be a polygon, a circle, or an ellipse.

[0123] A spacer (not shown) for preventing or reducing masking may be further included on the pixel defining film (119). The spacer may be formed integrally with the pixel defining film (119). For example, the spacer and the pixel defining film (119) may be formed simultaneously in the same process using a halftone mask process.

[0124] Since the first organic light-emitting diode (OLED1), the second organic light-emitting diode (OLED2), and the third organic light-emitting diode (OLED3) can be easily damaged by moisture or oxygen from the outside, they can be covered and protected by an encapsulation layer (300). The encapsulation layer (300) covers the display area (DA) and can extend to the outside of the display area (DA). The encapsulation layer (300) may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, the encapsulation layer (300) may include a first inorganic encapsulation layer (310), an organic encapsulation layer (320), and a second inorganic encapsulation layer (330).

[0125] Since the first inorganic sealing layer (310) is formed along the lower structure, its upper surface may not be flat (e.g., uneven). The organic sealing layer (320) covers this first inorganic sealing layer (310), and unlike the first inorganic sealing layer (310), its upper surface may be approximately flat.

[0126] The first inorganic encapsulation layer (310) and the second inorganic encapsulation layer (330) may include one or more inorganic materials selected from aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO), silicon oxide (SiO2), silicon nitride (SiNX), and silicon oxynitride (SiON). The organic encapsulation layer (320) may include a polymer-based material. Polymer-based materials may include acrylic resin, epoxy resin, polyimide, and polyethylene. In one embodiment, the organic encapsulation layer (320) may include acrylate.

[0127] Even if a crack occurs within the bag layer (300) through the aforementioned multilayer structure, such cracks can be prevented from connecting between the first inorganic bag layer (310) and the organic bag layer (320) or between the organic bag layer (320) and the second inorganic bag layer (330). This prevents or minimizes the formation of a path for moisture or oxygen from the outside to penetrate into the display area (DA).

[0128] Although not shown, other layers such as a capping layer may be interposed between the first inorganic sealing layer (310) and the counter electrode (230) as needed.

[0129] The upper panel (20P) may include a second substrate (400), a color filter layer (500), a refractive layer (RL), a first capping layer (CL1), a light conversion unit (LC), and a second capping layer (CL2). The second substrate (400) may be placed on the first substrate (100) such that a light-emitting element is interposed therein. The second substrate (400) may be placed on the first organic light-emitting diode (OLED1), the second organic light-emitting diode (OLED2), and the third organic light-emitting diode (OLED3).

[0130] The second substrate (400) may include a central region (CA) that overlaps with a display element. In one embodiment, the central region (CA) may include a first central region (CA1), a second central region (CA2), and a third central region (CA3). The first central region (CA1) may overlap with a first organic light-emitting diode (OLED1) and / or a first light-emitting region (EA1). The second central region (CA2) may overlap with a second organic light-emitting diode (OLED2) and / or a second light-emitting region (EA2). The third central region (CA3) may overlap with a third organic light-emitting diode (OLED3) and / or a third light-emitting region (EA3).

[0131] The second substrate (400) may include glass, metal, or polymer resin. If the second substrate (400) has flexible or bendable properties, the second substrate (400) may include a polymer resin such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. In one embodiment, the second substrate (400) may have a multilayer structure comprising two layers each containing such a polymer resin and a barrier layer containing an inorganic material such as silicon oxide (SiO2), silicon nitride (SiNX), or silicon oxynitride (SiON) interposed between the layers.

[0132] A color filter layer (500) may be disposed on the lower surface of the second substrate (400) facing from the second substrate (400) toward the first substrate (100). The color filter layer (500) may include a first color filter (510), a second color filter (520), and a third color filter (530). The first color filter (510) may be disposed on a first central region (CA1). The second color filter (520) may be disposed on a second central region (CA2). The third color filter (530) may be disposed on a third central region (CA3). The first color filter (510), the second color filter (520), and the third color filter (530) may be made of a photosensitive resin material. The first color filter (510), the second color filter (520), and the third color filter (530) may each include a dye that exhibits a unique color. The first color filter (510) may pass only light of a wavelength ranging from about 630 nm to about 780 nm, the second color filter (520) may pass only light of a wavelength ranging from about 495 nm to about 570 nm, and the third color filter (530) may pass only light of a wavelength ranging from about 450 nm to about 495 nm.

[0133] The color filter layer (500) can reduce external light reflection of the display panel (10). For example, when external light reaches the first color filter (510), only light of a preset wavelength as described above can pass through the first color filter (510), and light of other wavelengths can be absorbed by the first color filter (510). Therefore, among the external light incident on the display panel (10), only light of the preset wavelength passes through the first color filter (510), and a portion of it is reflected from the lower counter electrode (230) and / or the first pixel electrode (210R) and can be emitted outward again. Since only a portion of the external light incident on the location where the first pixel (PX1) is located is reflected outward, it can serve to reduce external light reflection. This explanation can also be applied to the second color filter (520) and the third color filter (530).

[0134] The first color filter (510), the second color filter (520), and the third color filter (530) may overlap each other. The first color filter (510), the second color filter (520), and the third color filter (530) may overlap between any one of the central areas (CA) and the other of the central areas (CA). For example, the first color filter (510), the second color filter (520), and the third color filter (530) may overlap between the first central area (CA1) and the second central area (CA2). In this case, the third color filter (530) may be placed between the first central area (CA1) and the second central area (CA2). The first color filter (510) may extend from the first central area (CA1) and overlap with the third color filter (530). The second color filter (520) can be extended from the second central area (CA2) and overlap with the third color filter (530).

[0135] The first color filter (510), the second color filter (520), and the third color filter (530) may overlap between the second central area (CA2) and the third central area (CA3). The first color filter (510) may be positioned between the second central area (CA2) and the third central area (CA3). The second color filter (520) may extend from the second central area (CA2) and overlap with the first color filter (510). The third color filter (530) may extend from the third central area (CA3) and overlap with the first color filter (510).

[0136] The first color filter (510), the second color filter (520), and the third color filter (530) may overlap between the third central area (CA3) and the first central area (CA1). The second color filter (520) may be positioned between the third central area (CA3) and the first central area (CA1). The third color filter (530) may extend from the third central area (CA3) and overlap with the second color filter (520). The first color filter (510) may extend from the first central area (CA1) and overlap with the second color filter (520).

[0137] As described above, the first color filter (510), the second color filter (520), and the third color filter (530) can be superimposed to define a light-blocking section (BP). Therefore, the color filter layer (500) can prevent or reduce color mixing without a separate light-blocking member.

[0138] The refractive layer (RL) may be placed in the central region (CA). The refractive layer (RL) may be placed in the first central region (CA1), the second central region (CA2), and the third central region (CA3), respectively. The refractive layer (RL) may contain an organic material. In one embodiment, the refractive index of the refractive layer (RL) may be smaller than the refractive index of the first capping layer (CL1). In one embodiment, the refractive index of the refractive layer (RL) may be smaller than the refractive index of the color filter layer (500). Thus, the refractive layer (RL) can concentrate light.

[0139] A first capping layer (CL1) may be disposed on the lower surface of the refractive layer (RL) and the color filter layer (500). In one embodiment, the first capping layer (CL1) may be disposed between the color filter layer (500) and the light conversion unit (LC). The first capping layer (CL1) can protect the refractive layer (RL) and the color filter layer (500). The first capping layer (CL1) can prevent or reduce the penetration of impurities, such as moisture and / or air, from the outside to damage or contaminate the refractive layer (RL) and / or the color filter layer (500). The first capping layer (CL1) may include an inorganic material.

[0140] The light conversion unit (LC) may include a bank layer (600) and a functional layer (700). The bank layer (600) may be disposed on the lower surface of the first capping layer (CL1). The bank layer (600) may include an organic material. In some cases, the bank layer (600) may include a light-blocking material to function as a light-blocking layer. The light-blocking material may include, for example, at least one of a black pigment, a black dye, black particles, or metal particles.

[0141] Multiple openings may be defined in the bank layer (600). For example, a central opening (COP) may be defined in the bank layer (600). The central opening (COP) may overlap with the central area (CA). In one embodiment, multiple central openings (COP) may overlap with the central area (CA). For example, the first central opening (COP1) may overlap with the first central area (CA1). The second central opening (COP2) may overlap with the second central area (CA2). The third central opening (COP3) may overlap with the third central area (CA3).

[0142] The functional layer (700) can fill the central opening (COP). In one embodiment, the functional layer (700) may include at least one of a quantum dot and a scatterer. In one embodiment, the functional layer (700) may include a first quantum dot layer (710), a second quantum dot layer (720), and a transparent layer (730).

[0143] The first quantum dot layer (710) may overlap with the first central region (CA1). The first quantum dot layer (710) may fill the first central opening (COP1). The first quantum dot layer (710) may overlap with the first light-emitting region (EA1). The first pixel (PX1) may include the first organic light-emitting diode (OLED1) and the first quantum dot layer (710).

[0144] The first quantum dot layer (710) can convert light of a first wavelength band generated in the light-emitting layer (220) on the first pixel electrode (210R) into light of a second wavelength band. For example, if light of a wavelength belonging to about 450 nm to about 495 nm is generated in the light-emitting layer (220) on the first pixel electrode (210R), the first quantum dot layer (710) can convert this light into light of a wavelength belonging to about 630 nm to about 780 nm. Accordingly, light of a wavelength belonging to about 630 nm to about 780 nm can be emitted to the outside through the second substrate (400) from the first pixel (PX1). In one embodiment, the first quantum dot layer (710) may include a first quantum dot (QD1), a first scatterer (SC1), and a first base resin (BR1). The first quantum dot (QD1) and the first scatterer (SC1) may be in a form dispersed within the first base resin (BR1).

[0145] The second quantum dot layer (720) may overlap with the second central region (CA2). The second quantum dot layer (720) may fill the second central opening (COP2). The second quantum dot layer (720) may overlap with the second light-emitting region (EA2). The second pixel (PX2) may include the second organic light-emitting diode (OLED2) and the second quantum dot layer (720).

[0146] The second quantum dot layer (720) can convert light of a first wavelength band generated in the light-emitting layer (220) on the second pixel electrode (210G) into light of a third wavelength band. For example, if light of a wavelength belonging to about 450 nm to about 495 nm is generated in the light-emitting layer (220) on the second pixel electrode (210G), the second quantum dot layer (720) can convert this light into light of a wavelength belonging to about 495 nm to about 570 nm. Accordingly, light of a wavelength belonging to about 495 nm to about 570 nm can be emitted to the outside through the second substrate (400) from the second pixel (PX2). In one embodiment, the second quantum dot layer (720) may include a second quantum dot (QD2), a second scatterer (SC2), and a second base resin (BR2). The second quantum dot (QD2) and the second scatterer (SC2) may be in a form dispersed within the second base resin (BR2).

[0147] The transparent layer (730) may overlap with the third central region (CA3). The transparent layer (730) may fill the third central opening (COP3). The transparent layer (730) may overlap with the third light-emitting region (EA3). The third pixel (PX3) may include the third organic light-emitting diode (OLED3) and the transparent layer (730).

[0148] The transparent layer (730) can emit light generated from the light-emitting layer (220) on the third pixel electrode (210B) to the outside without wavelength conversion. For example, if light of a wavelength ranging from about 450 nm to about 495 nm is generated from the light-emitting layer (220) on the third pixel electrode (210B), the transparent layer (730) can emit the light to the outside without wavelength conversion. In one embodiment, the transparent layer (730) may include a third scatterer (SC3) and a third base resin (BR3). The third scatterer (SC3) may be in a form dispersed in the third base resin (BR3). In an embodiment, the transparent layer (730) may not include quantum dots.

[0149] At least one of the first quantum dot (QD1) and the second quantum dot (QD2) may include a semiconductor material such as cadmium sulfide (CdS), cadmium telluride (CdTe), zinc sulfide (ZnS), or indium phosphide (InP). The quantum dots may have a size of several nanometers, and the wavelength of the light after conversion may vary depending on the size of the quantum dots.

[0150] In one embodiment, the core of the quantum dot may be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

[0151] Group II-VI compounds are diatomic compounds selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof; ternary compounds selected from the group consisting of AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, and mixtures thereof; and may be selected from the group consisting of four-element compounds selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0152] III-V compounds may be selected from the group consisting of diatomic compounds selected from GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; ternary compounds selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb, GaAlNP, and mixtures thereof; and quaternary compounds selected from the group consisting of GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof.

[0153] Group IV-VI compounds may be selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; ternary compounds selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; and quaternary compounds selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. Group IV elements may be selected from the group consisting of Si, Ge, and mixtures thereof. Group IV compounds may be ternary compounds selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0154] In this case, the binary, ternary, or quaternary compounds may exist within the particle at a uniform concentration, or they may exist within the same particle with concentration distributions partially divided into different states. Additionally, the structure may have a core / shell configuration where one quantum dot surrounds another. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases towards the center.

[0155] In some embodiments, the quantum dot may have a core-shell structure comprising a core containing the aforementioned nanocrystal and a shell surrounding the core. The shell of the quantum dot may serve as a protective layer to maintain semiconductor properties by preventing or reducing chemical degradation of the core and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell may be a single layer or a multilayer. The interface between the core and the shell may have a concentration gradient in which the concentration of elements present in the shell decreases toward the center. Examples of the shell of the quantum dot include oxides of metals or non-metals, semiconductor compounds, or combinations thereof.

[0156] For example, the oxide of the metal or nonmetal mentioned above may be exemplified as a binary compound such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, or a ternary compound such as MgAl2O4, CoFe2O4, NiFe2O4, CoMn2O4, but the present invention is not limited thereto.

[0157] In addition, the above semiconductor compounds may be examples of CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but the present invention is not limited thereto.

[0158] In addition, the shape of the quantum dots is not specifically limited to shapes commonly used in the field, but more specifically, shapes such as spherical, pyramidal, multi-arm, or cubic nanoparticles, nanotubes, nanowires, nanofibers, and nanoplate particles may be used.

[0159] Quantum dots can control the color of the light they emit depending on their particle size, and accordingly, they can have various emission colors such as blue, red, and green.

[0160] The first scatterer (SC1), the second scatterer (SC2), and the third scatterer (SC3) can scatter light to allow more light to be emitted. The first scatterer (SC1), the second scatterer (SC2), and the third scatterer (SC3) can increase the light emission efficiency. At least one of the first scatterer (SC1), the second scatterer (SC2), and the third scatterer (SC3) may be any material among metals or metal oxides for evenly scattering light. For example, at least one of the first scatterer (SC1), the second scatterer (SC2), and the third scatterer (SC3) may be at least one of TiO2, ZrO2, Al2O3, In2O3, ZnO, SnO2, Sb2O3, and ITO. Additionally, at least one of the first scatterer (SC1), the second scatterer (SC2), and the third scatterer (SC3) may have a refractive index of 1.5 or higher. Thus, the light emission efficiency of the functional layer (700) can be improved. In some embodiments, at least one of the first scatterer (SC1), the second scatterer (SC2), and the third scatterer (SC3) may be omitted.

[0161] The first base resin (BR1), the second base resin (BR2), and the third base resin (BR3) may be transparent materials. For example, at least one of the first base resin (BR1), the second base resin (BR2), and the third base resin (BR3) may include a polymer resin such as acrylic, BCB (Benzocyclobutene), or HMDSO (hexamethyldisiloxane).

[0162] A second capping layer (CL2) may be disposed on the lower surface of the light conversion unit (LC). That is, a second capping layer (CL2) may be disposed on the bank layer (600) and the functional layer (700). The second capping layer (CL2) can protect the bank layer (600) and the functional layer (700). The second capping layer (CL2) can prevent or reduce the penetration of impurities, such as moisture and / or air, from the outside to damage or contaminate the bank layer (600) and / or the functional layer (700). The second capping layer (CL2) may include an inorganic material.

[0163] The display panel (10) described above can emit light of a second wavelength band from a first pixel (PX1), emit light of a third wavelength band from a second pixel (PX2), and emit light of a first wavelength band from a third pixel (PX3). That is, the display panel (10) can display a full-color image.

[0164] Figure 7 is a cross-sectional view taken along the line B-B' of the display panel of Figure 5.

[0165] Referring to FIG. 7, the display panel (10) may include a dam portion (DAM) disposed at the edge of the first substrate (100). This dam portion (DAM) is disposed at the outer edge of the display area (DA) to define the boundary of the organic encapsulation layer (320) when the organic encapsulation layer (320) is formed. At this time, at least one dam portion (DAM) may be provided. For example, a plurality of dam portions (DAM) may be provided so as to be spaced apart from each other from the ends of the first substrate (100).

[0166] The dam (DAM) may be formed as an insulating layer. For example, the dam (DAM) may include a layer identical to at least one of the flattening layer (118) and the pixel defining film (119). Additionally, the dam (DAM) may include a wiring protection layer (117). As another embodiment, the dam (DAM) may further include a layer identical to a spacer disposed on the pixel defining film (119), although this is not shown in the drawing. In such cases, if the dam (DAM) includes multiple layers, the height of one of the multiple dam (DAM) may differ from the height of another of the multiple dam (DAM). For example, the height of the dam (DAM) that is closer to the end of the first substrate (100) among the multiple dam (DAM) may be greater than the height of another of the multiple dam (DAM).

[0167] At least one upper surface of a dam forming a dam portion (DAM) may be in direct contact with a first inorganic sealing layer (310) or a second inorganic sealing layer (330). In some embodiments, at least one upper surface of a dam forming a dam portion (DAM) on a flat surface may not overlap with an organic sealing layer (320). Additionally, the first inorganic sealing layer (310) and the second inorganic sealing layer (330) may be in direct contact with each other on the upper surface of at least one dam forming a dam portion (DAM). That is, the first inorganic sealing layer (310) and the second inorganic sealing layer (330) form an inorganic contact area, which can block or reduce the penetration of moisture and impurities into the light-emitting elements placed in the display area (DA, FIG. 6) from the outer edge of the display panel (10).

[0168] The display panel (10) may include a plurality of signal lines (131) disposed between the first substrate (100) and the first buffer layer (111). At this time, the plurality of signal lines (131) may include fan-out lines. In addition to the above locations, the plurality of signal lines (131) may also be disposed between the first buffer layer (111) and the second buffer layer (112). In another embodiment, some of the plurality of signal lines (131) may be disposed between the first buffer layer (111) and the first substrate (100), and other parts of the plurality of signal lines (131) may be disposed between the first buffer layer (111) and the second buffer layer (112).

[0169] As previously described, the display panel (10) may include a driving voltage input section (120). The driving voltage input section (120) may be placed on an interlayer insulating layer (115). For example, the driving voltage input section (120) may be placed on the same layer as the source electrode (SE, FIG. 6) and / or drain electrode (DE, FIG. 6) of the display area (DA, FIG. 6). Although not shown in FIG. 7, a common voltage input section (110, FIG. 5) may be placed on the same layer as the driving voltage input section (120).

[0170] The driving voltage input section (120) may extend outward within the non-display area (NDA). The display panel (10) may include a connecting wire (CM) connected to the driving voltage input section (120). At this time, the connecting wire (CM) may be connected to the driving voltage input section (120), and an extended portion of the opposing electrode (230) may be disposed on the upper part of the connecting wire (CM).

[0171] The display panel (10) may include a pad (PAD). The pad (PAD) may include a pad electrode exposed to the outside. The pad (PAD) may be positioned on the outer edge of the display panel (10) rather than the sealing member (900). An externally positioned flexible circuit board, etc., may be connected to the pad (PAD) by contact. Additionally, the pad (PAD) may be connected to a driving voltage input unit (120), a plurality of signal wires (131), etc. At this time, the pad (PAD) may include a plurality of terminals.

[0172] The upper panel (20P) may include a color filter layer (500) extending into a non-display area (NDA). The color filter layer (500) may include a first color filter (510), a second color filter (520), and a third color filter (530) stacked in the non-display area (NDA). As a plurality of color filters (510, 520, 530) are stacked overlapping each other, light emitted from the lower panel (10P) may not be able to pass through the color filter layer (500). Accordingly, the non-display area (NDA) may become an area that is not visible.

[0173] In addition to the refractive layer (RL) on the color filter layer (500), at least one of a first capping layer (CL1) and a second capping layer (CL2) may be disposed on the refractive layer (RL). That is, at least one of the first capping layer (CL1) and the second capping layer (CL2) may be disposed to extend from the portion of the second substrate (400) corresponding to the display area (DA, FIG. 6) of the lower panel (10P) to the end of the second substrate (400) so as to shield one side of the refractive layer (RL). At least one of the first capping layer (CL1) and the second capping layer (CL2) may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiNX), and / or silicon oxynitride (SiON).

[0174] A bank layer (600) may be disposed between the first capping layer (CL1) and the second capping layer (CL2). The bank layer (600) may be disposed to overlap a portion of the non-display area (NDA) with the display area (DA, FIG. 6). The bank layer (600) may include a dummy bank layer (600A) disposed in the non-display area (NDA). In some embodiments, the dummy bank layer (600A) may have additional openings that do not overlap with planar light-emitting elements. A functional layer (700, FIG. 6) may be disposed in a plurality of openings of the dummy bank layer (600A). For example, a transparent layer (730, FIG. 6) may be disposed in a plurality of openings of the dummy bank layer (600A).

[0175] The bank layer (600) may include a black matrix material or a light-blocking material such as a red pigment, a purple pigment, or a blue pigment. Alternatively, the bank layer (600) may include a metal oxide to increase the reflectivity on its surface, thereby effectively preventing or minimizing external light incident on the second substrate (400) from reaching the driving circuit, etc.

[0176] The sealing member (900) can combine the first substrate (100) and the second substrate (400). In other words, the sealing member (900) can be interposed between the lower panel (10P) and the upper panel (20P). The sealing member (900) can be positioned in the non-display area (NDA) to surround the outer edge of the display area (DA). For example, the sealing member (900) may have a hollow rectangular shape in a planar form. However, the shape of the sealing member (900) is not limited thereto. When the first substrate (100) and the second substrate (400) have various planar shapes such as a triangle, a rhombus, a polygon, a circle, or an ellipse, the sealing member (900) may have a planar shape such as a hollow triangle, a hollow rhombus, a hollow polygon, a hollow circle, or a hollow ellipse. In one embodiment, the sealing member (900) may be made of an organic material. For example, the sealing member (900) may be made of an epoxy resin. In another embodiment, the sealing member (900) may be applied in the form of a frit including glass, etc.

[0177] In some embodiments, a filling layer (30) containing a filling material may be disposed in the space between the lower panel (10P) and the upper panel (20P) surrounded by the sealing member (900). The filling layer (30) may fill the space between the lower panel (10P) and the upper panel (20P). The filling material included in the filling layer (30) may be made of a material capable of transmitting light. For example, the filling material may be made of an organic material including a silicone-based organic material, an epoxy-based organic material, or a mixture of a silicone-based organic material and an epoxy-based organic material.

[0178] FIGS. 8A and 8B are schematic plan views showing a portion of a display panel according to an embodiment of the present invention. FIG. 8C is an enlarged plan view schematically showing area D of the display panel of FIG. 8B. FIG. 9 is a cross-sectional view taken along the line E-E' of the display panel of FIG. 8B. For convenience of explanation, FIG. 8A schematically shows a driving voltage input section (120), a common voltage input section (110), and a plurality of signal wires (131), while other components are omitted. Likewise, FIG. 8B schematically shows a driving voltage input section (120), a common voltage input section (110), and a damper section (DAM), while other components are omitted.

[0179] Referring first to FIG. 8a, a signal wiring section (130) may be located in a non-display area (NDA). The signal wiring section (130) may include a plurality of signal wires (131) extending from a pad (PAD, FIG. 5) to be adjacent to a display area (DA, FIG. 5). These signal wires (131) may be wires for transmitting electrical signals to be applied to pixels located within the display area (DA, FIG. 5). Each of the plurality of signal wires (131) may include a first input line (IL1) adjacent to the display area (DA, FIG. 5), a second input line (IL2) adjacent to the pad (PAD, FIG. 5), and a fan-out wire (FL) electrically connecting the first input line (IL1) and the second input line (IL2). In one embodiment, the first input line (IL1), the second input line (IL2), and the fan-out wire (FL) may be provided as a single unit. In another embodiment, at least one of the first input line (IL1), the second input line (IL2) and the fan-out wiring (FL) may be formed on different layers and electrically connected.

[0180] The second input lines (IL2) are positioned adjacent to each other to be electrically connected to the pad (PAD, FIG. 5). The first input lines (IL1) may be positioned relatively further apart from each other compared to the second input lines (IL2). This is due to the position of the components receiving the electrical signals transmitted by each of the multiple signal lines (131). Accordingly, as illustrated in FIG. 8a, the spacing between the fan-out lines (FL) may vary depending on the position. For example, the distance between the fan-out lines (FL) adjacent to the first input line (IL1) may be wider than the distance between the fan-out lines (FL) adjacent to the second input line (IL2). This may be because the fan-out lines (FL) extend in a direction oblique to the second direction (e.g., the y-direction). The angle formed by a fan-out line (FL) near a virtual center line (CL) passing through the center of the fan-out lines (FL) with the second direction (e.g., y-direction) may be smaller than the angle formed by the outermost fan-out line (FL) among the fan-out lines (FL) with the second direction (e.g., y-direction).

[0181] Referring to FIG. 8a, the signal wiring section (130) may partially overlap with the common voltage input section (110) and the driving voltage input section (120) on a plane.

[0182] The driving voltage input section (120) may include a horizontal driving voltage input section (120h) extended in a first direction (e.g., x direction) and a vertical driving voltage input section (120v) extended in a second direction (e.g., y direction) with the center coinciding with a virtual center line (CL) passing through the center of the fan-out wiring (FL). For example, the driving voltage input section (120) may be arranged in a T-shape symmetrical with respect to a virtual center line (CL) passing through the center of the fan-out wiring (FL).

[0183] In one embodiment, the vertical driving voltage input section (120v) may include a first vertical driving voltage input section (120v1), a second vertical driving voltage input section (120v2), and a third vertical driving voltage input section (120v3) arranged sequentially along a second direction (e.g., the y-direction). The first vertical driving voltage input section (120v1), the second vertical driving voltage input section (120v2), and the third vertical driving voltage input section (120v3) may be formed as a single unit. In other words, the first vertical driving voltage input section (120v1) may be a part extending outward from the horizontal driving voltage input section (120h), the second vertical driving voltage input section (120v2) may be a part extending outward from the first vertical driving voltage input section (120v1), and the third vertical driving voltage input section (120v3) may be a part extending outward from the second vertical driving voltage input section (120v2).

[0184] In one embodiment, the first vertical driving voltage input section (120v1) and the third vertical driving voltage input section (120v3) may be areas extended along a second direction (e.g., the y-direction). That is, the side facing the common voltage input section (110) of each of the first vertical driving voltage input section (120v1) and the third vertical driving voltage input section (120v3) may be parallel to a virtual centerline (CL). For example, the first vertical driving voltage input section (120v1) and the third vertical driving voltage input section (120v3) may have a rectangular shape in a planar form.

[0185] However, the first vertical driving voltage input section (120v1) and the third vertical driving voltage input section (120v3) may have different widths in a first direction (e.g., x-direction). As shown in FIG. 8a, the first vertical driving voltage input section (120v1) may have a first width (D1) along the first direction (e.g., x-direction), and the third vertical driving voltage input section (120v3) may have a second width (D2) along the first direction (e.g., x-direction). In one embodiment, the second width (D2) of the third vertical driving voltage input section (120v3) may be larger than the first width (D1) of the first vertical driving voltage input section (120v1). However, this is not limited thereto, and in other embodiments, the first width (D1) of the first vertical driving voltage input section (120v1) may be larger than the second width (D2) of the third vertical driving voltage input section (120v3).

[0186] In one embodiment, the second vertical driving voltage input section (120v2), which is positioned between the first vertical driving voltage input section (120v1) and the third vertical driving voltage input section (120v3), may be an area (e.g., partially extended) that extends diagonally between the first direction (e.g., x-direction) and the second direction (e.g., y-direction). In this case, the diagonal direction may refer to the third direction (DR3) or the fourth direction (DR4). That is, the side of the second vertical driving voltage input section (120v2) facing the common voltage input section (110) may be extended diagonally. For example, the second vertical driving voltage input section (120v2) may have a trapezoidal shape in plan.

[0187] That is, the width of the upper side and the width of the lower side of the second vertical drive voltage input section (120v2) may be different. For example, one side of the second vertical drive voltage input section (120v2) that is close to the first vertical drive voltage input section (120v1) may have the same width as the first width (D1), and the other side of the second vertical drive voltage input section (120v2) that is close to the third vertical drive voltage input section (120v3) may have the same width as the second width (D2). In other words, the second vertical drive voltage input section (120v1) may be a bridge area connecting the first vertical drive voltage input section (120v1) and the third vertical drive voltage input section (120v3), each having different widths.

[0188] Meanwhile, the third common voltage input section (110c) and the fourth common voltage input section (110d) may be spaced apart with the driving voltage input section (120) in between. Specifically, a vertical driving voltage input section (120v) may be placed between the third common voltage input section (110c) and the fourth common voltage input section (110d). The third common voltage input section (110c) and the fourth common voltage input section (110d) may be symmetrical with respect to a virtual center line (CL) passing through the center of the fan-out wiring (FL).

[0189] In one embodiment, the common voltage input section (110) may be spaced apart from the vertical driving voltage input section (120v) while maintaining a certain distance. Additionally, the width along the first direction (e.g., x-direction) of a portion of the common voltage input section (110) that is positioned side-by-side (e.g., adjacently) with the first vertical driving voltage input section (120v1) may be larger than the width along the first direction (e.g., x-direction) of a portion of the common voltage input section (110) that is positioned side-by-side (e.g., adjacently) with the third vertical driving voltage input section (120v3). Accordingly, a portion of the side of the common voltage input section (110) facing the vertical driving voltage input section (120v) may be extended diagonally between the first direction (e.g., x-direction) and the second direction (e.g., y-direction). That is, some areas of the common voltage input section (110) that are arranged side by side (e.g., adjacently) with the second vertical driving voltage input section (120v2) may have a shape that gradually narrows in width along the second direction (e.g., y-direction).

[0190] As the driving voltage input section (120) and the common voltage input section (110) are spaced apart, the space between the driving voltage input section (120) and the common voltage input section (110) may be referred to as a spaced-apart area (SA). As previously described, the driving voltage input section (120) and the common voltage input section (110) may be placed on the same layer, and the driving voltage input section (120) and the common voltage input section (110) may be placed on the same layer as the source electrode (SE, FIG. 6) of the display area (DA, FIG. 6). That is, the driving voltage input section (120) and the common voltage input section (110) may be placed on the interlayer insulation layer (115). Accordingly, the spaced-apart area (SA) may expose the upper surface of the interlayer insulation layer (115) placed below the driving voltage input section (120) and the common voltage input section (110).

[0191] In one embodiment, a portion of the separation area (SA) may extend diagonally between a first direction (e.g., x direction) and a second direction (e.g., y direction). Specifically, the separation area (SA) may include a first separation area (SA1) between a horizontal driving voltage input unit (120h) and a common voltage input unit (110), a second separation area (SA2) between a first vertical driving voltage input unit (120v1) and a common voltage input unit (110), a third separation area (SA3) between a second vertical driving voltage input unit (120v2) and a common voltage input unit (110), and a fourth separation area (SA4) between a third vertical driving voltage input unit (120v3) and a common voltage input unit (110). The first separation area (SA1), the second separation area (SA2), the third separation area (SA3), and the fourth separation area (SA4) are distinguished for convenience of explanation, and the first to fourth separation areas (SA1, SA2, SA3, SA4) may be areas connected as a single unit.

[0192] Since the first separation area (SA1) refers to the area between the horizontal driving voltage input section (120h) and the common voltage input section (110), the first separation area (SA1) can be extended along the first direction (e.g., the x-direction). Since the second separation area (SA2) refers to the area between the first vertical driving voltage input section (120v1) and the common voltage input section (110), it can be extended along the second direction (e.g., the y-direction). Since the third separation area (SA3) refers to the area between the second vertical driving voltage input section (120v2) and the common voltage input section (110), it can be extended along the diagonal direction (e.g., the DR3 direction or the DR4 direction). Since the fourth separation area (SA4) refers to the area between the third vertical driving voltage input section (120v3) and the common voltage input section (110), it can be extended along the second direction (e.g., the y-direction).

[0193] Referring to FIG. 8b, a dam section (DAM) may be disposed on the driving voltage input section (120) and the common voltage input section (110). The dam section (DAM) may include a plurality of dams, and the dam section (DAM) may be disposed to surround the display area (DA, FIG. 5). In one embodiment, the dam section (DAM) may include a first dam (DAM1), a second dam (DAM2), and a third dam (DAM3). The first dam (DAM1) may refer to the dam closest to the display area (DA, FIG. 5) among the dam sections (DAM), and the third dam (DAM3) may refer to the dam disposed at the outermost edge among the dam sections (DAM). The second dam (DAM2) may refer to the dam disposed between the first dam (DAM1) and the third dam (DAM3).

[0194] A portion of the dam portion (DAM) may be positioned to overlap in a plane with the driving voltage input portion (120) and the common voltage input portion (110). Specifically, a portion of the dam portion (DAM) may be positioned to overlap in a plane with the vertical driving voltage input portion (120v) and the common voltage input portion (110). In one embodiment, a portion of the first dam portion (DAM1) may overlap in a plane with the second vertical driving voltage portion (120v2). In other words, a portion of the first dam portion (DAM1) may overlap in a plane with the third separation area (SA3). However, it is not limited thereto, and in another embodiment, the first dam portion (DAM1) may be positioned to pass through the boundary between the second vertical driving voltage input portion (120v2) and the third vertical driving voltage input portion (120v3).

[0195] Meanwhile, the common voltage input section (110) may further include a contact area (CTA) that can be electrically connected to the opposing electrode (230) of the organic light-emitting diode (OLED, FIG. 6). In one embodiment, the contact area (CTA) may be positioned closer to the display area (DA, FIG. 5) than to the damper section (DAM). The contact area (CTA) may be formed with an enlarged area so that it can be positioned close to a third separation area (SA3) that extends diagonally.

[0196] Referring to FIG. 9, a plurality of insulating layers disposed on the common voltage input section (110) may not be disposed on the contact area (CTA). Specifically, the contact area (CTA) may be an area in which a portion of the insulating layers that overlap in plane with the contact area (CTA) is removed, thereby exposing the upper surface of the common voltage input section (110). For example, a portion of the wiring protection layer (117), the flattening layer (118), and the pixel definition film (119) may be removed on the contact area (CTA) to expose the upper surface of the common voltage input section (110). Accordingly, the common voltage input section (110) may be electrically connected to an extended portion of the opposing electrode (230) by directly contacting the connecting wiring (CM) in the contact area (CTA).

[0197] Referring to FIG. 8c and FIG. 9, the dam portion (DAM) may be formed of a plurality of insulating layers. For example, the plurality of dams of the dam portion (DAM) may each include a layer identical to the flattening layer (118) and the pixel defining film (119). In another embodiment, the dam portion (DAM) may further include a wiring protection layer (117). The dam portion (DAM) may be positioned to surround the display area (DA, FIG. 6) in the non-display area (NDA) to function to prevent or reduce flooding of the organic encapsulation layer (320).

[0198] Meanwhile, as previously explained, the driving voltage input section (120) and the common voltage input section (110) may be placed on the same layer, and a separation area (SA) may be placed between the driving voltage input section (120) and the common voltage input section (110). In the separation area (SA), the conductive layer placed on the same layer as the driving voltage input section (120) and the common voltage input section (110) is not placed, and the upper surface of the interlayer insulation layer (115) may be exposed. Accordingly, the area of ​​the dam section (DAM) that overlaps with the separation area (SA) may have a lower height than the area of ​​the dam section (DAM) that overlaps with the driving voltage input section (120) or the common voltage input section (110).

[0199] The material of the organic encapsulation layer (320) is applied around the marked area (DA, FIG. 5), but can also flow outward in the non-marked area (NDA). At this time, the first dam (DAM1) can function to primarily obstruct the flow of the organic encapsulation layer (320). However, since the area of ​​the first dam (DAM1) that overlaps with the separated area (SA) has a relatively lower height compared to other areas, the organic encapsulation layer (320) can overflow through the first dam (DAM1) via that area.

[0200] At this time, a display panel (10) according to one embodiment of the present invention can control the flow (320F) of the organic encapsulation layer (320) through a separation area (SA) extending diagonally. Specifically, since the material of the organic encapsulation layer (320) can flow outward from the display area (DA, FIG. 5), the material of the organic encapsulation layer (320) passing through the second separation area (SA2) flows in the second direction (e.g., the y-direction). At this time, if a third separation area (SA3) is formed to extend diagonally (e.g., the DR3 direction or the DR4 direction), the flow (320F) of the organic encapsulation layer (320) can be changed to the diagonal direction.

[0201] In addition, when a contact area (CTA) is positioned adjacent to a third separation area (SA3) that extends diagonally (e.g., in the DR3 direction or DR4 direction) as described above, the material of the organic encapsulation layer (320) can be induced to flow from the third separation area (SA3) to the contact area (CTA). This is because, since the wiring protection layer (117), the flattening layer (118), and the pixel defining film (119) do not exist in the contact area (CTA), the contact area (CTA) forms a large step difference with the surrounding area. That is, the flow (320F) of the organic encapsulation layer (320) can be controlled in the direction of the arrows shown in FIG. 8c and FIG. 9.

[0202] In conclusion, a display panel (10) according to one embodiment of the present invention can prevent or reduce the phenomenon of an organic encapsulation layer (320) overflowing by forming a portion of the driving voltage input section (120) and the common voltage input section (110) in a diagonal direction and expanding the contact area (CTA) near the separation area (SA).

[0203] Although the present invention has been described with reference to an embodiment illustrated in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A substrate including a display area and a non-display area located outside the display area; A driving voltage input unit comprising a horizontal driving voltage input unit extending along a first direction and a vertical driving voltage input unit extending along a second direction intersecting the first direction, disposed in the above-mentioned non-display area; and A common voltage input unit disposed in the above non-display area and spaced apart from the driving voltage input unit; is included. The above vertical driving voltage input unit includes a first vertical driving voltage input unit having a side extending along the second direction, a second vertical driving voltage input unit having a side extending diagonally between the first direction and the second direction, and a third vertical driving voltage input unit having a side extending in the second direction. A display panel in which the first vertical driving voltage input section, the second vertical driving voltage input section, and the third vertical driving voltage input section are sequentially arranged along the second direction.

2. In Paragraph 1, A display panel in which the horizontal driving voltage input section, the first vertical driving voltage input section, the second vertical driving voltage input section, and the third vertical driving voltage input section are integrally formed.

3. In Paragraph 1, The above second vertical driving voltage input section is a display panel having a planar trapezoidal shape.

4. In Paragraph 1, The first vertical driving voltage input section has a first width along the first direction, The third vertical driving voltage input section has a second width different from the first width along the first direction, and A display panel in which one side of the second vertical driving voltage input section, which is close to the first vertical driving voltage input section, has the first width, and the other side, which is close to the third vertical driving voltage input section, has the second width.

5. In Paragraph 1, The above common voltage input section is provided with a plurality of common voltage input sections, and A display panel in which the vertical driving voltage input is disposed between common voltage inputs arranged adjacently along the first direction.

6. In Paragraph 1, The above non-display area includes a separation area which is an area separated from the driving voltage input part and the common voltage input part. A display panel comprising a portion of an insulating layer disposed below the driving voltage input section and the common voltage input section, wherein the above-mentioned separation area exposes the upper surface of the insulating layer and includes a portion extending in the diagonal direction.

7. In Paragraph 1, The above non-display area includes a separation area which is an area separated from the driving voltage input part and the common voltage input part. The above separation area is, A first separation area extending along the first direction between the horizontal driving voltage input part and the common voltage input part; A second separation area extending along the second direction between the first vertical driving voltage input part and the common voltage input part; A third separation area extending in the diagonal direction between the second vertical driving voltage input part and the common voltage input part; and A display panel comprising: a fourth separation area extending in the second direction between the third vertical driving voltage input section and the common voltage input section.

8. In Paragraph 1, It further includes dams disposed in the above-mentioned non-display area and disposed on the driving voltage input unit and the common voltage input unit, and A display panel in which the dams are arranged to surround the display area, and the dams are arranged to overlap the vertical driving voltage input section and the common voltage input section.

9. In Paragraph 1, It further includes dams disposed in the above-mentioned non-display area, disposed on the driving voltage input unit and the common voltage input unit, and disposed to surround the display area. Among the above dams, the dam positioned closest to the above-mentioned display area is, A display panel arranged to overlap with the above-mentioned second vertical driving voltage input section.

10. In Paragraph 1, Dams disposed in the above-mentioned non-display area, disposed on the driving voltage input unit and the common voltage input unit, and disposed to surround the above-mentioned display area in a planar manner; Insulating layers disposed on the above driving voltage input section and the above common voltage input section; and It further includes a light-emitting diode disposed in the above-mentioned display area and electrically connected to the contact area of ​​the above-mentioned common voltage input part; The above contact area is an area in which a portion of the insulating layers is removed to expose the upper surface of the common voltage input portion, and the contact area is positioned closer to the display area than to a plurality of dams, a display panel.

11. In Paragraph 1, Dams disposed in the above-mentioned non-display area, disposed on the driving voltage input unit and the common voltage input unit, and disposed to surround the above-mentioned display area in a planar manner; A light-emitting diode disposed in the above-mentioned display area; and It further includes an encapsulation layer covering the light-emitting diode; and A display panel comprising a first inorganic sealing layer, an organic sealing layer disposed on the first inorganic sealing layer, and a second inorganic sealing layer disposed on the organic sealing layer and in direct contact with the first inorganic sealing layer on the dams.

12. A substrate including a display area and a non-display area located outside the display area; A driving voltage input unit comprising a horizontal driving voltage input unit extending along a first direction and a vertical driving voltage input unit extending along a second direction intersecting the first direction, disposed in the above-mentioned non-display area; and A common voltage input unit disposed in the above non-display area and spaced apart from the driving voltage input unit; is included. A display panel comprising a non-display area which is an area separated from the driving voltage input part and the common voltage input part, and a separation area which includes a portion of the area extending diagonally between the first direction and the second direction.

13. In Paragraph 12, The above-mentioned separation area is a display panel that exposes the upper surface of an insulating layer disposed below the driving voltage input section and the common voltage input section.

14. In Paragraph 12, The above common voltage input unit is positioned in the above non-display area and is positioned spaced apart from the above driving voltage input unit, The above-described vertical driving voltage input section includes a first vertical driving voltage input section having a side extending along the second direction while facing the common voltage input section, a second vertical driving voltage input section having a planar trapezoidal shape and extending in the diagonal direction while facing the common voltage input section, and a third vertical driving voltage input section having a side extending along the second direction while facing the common voltage input section. A display panel in which the first vertical driving voltage input section, the second vertical driving voltage input section, and the third vertical driving voltage input section are sequentially arranged along the second direction.

15. In Paragraph 12, It further includes dams disposed in the above-mentioned non-display area, disposed on the driving voltage input unit and the common voltage input unit, and disposed to surround the display area on a plane. The dam among the above dams that is positioned closest to the display area is a display panel that overlaps with a part of the spaced-out area extending in the diagonal direction.

16. In Paragraph 12, Dams disposed in the above-mentioned non-display area, disposed on the driving voltage input unit and the common voltage input unit, and disposed to surround the display area in a planar manner; and A display panel further comprising: a light-emitting diode disposed in the above display area and electrically connected to a contact area of ​​the common voltage input portion disposed closer to the above display area than the dams on the plane.

17. Display panel; and As an exterior, it includes a lower cover defining an opening that exposes a part of the display panel; and The above display panel is, A substrate comprising a display area and a non-display area located outside the display area; A driving voltage input unit comprising a horizontal driving voltage input unit extending along a first direction and a vertical driving voltage input unit extending along a second direction intersecting the first direction, disposed in the above-mentioned non-display area; and A common voltage input unit disposed in the above non-display area and spaced apart from the driving voltage input unit; is included. The above vertical driving voltage input unit includes a first vertical driving voltage input unit having a side extending along the second direction, a second vertical driving voltage input unit having a side extending diagonally between the first direction and the second direction, and a third vertical driving voltage input unit having a side extending in the second direction. An electronic device in which the first vertical driving voltage input unit, the second vertical driving voltage input unit, and the third vertical driving voltage input unit are sequentially arranged along the second direction.

18. In Paragraph 17, The above non-display area includes a separation area which is an area separated from the driving voltage input part and the common voltage input part. The above-mentioned separation area exposes the upper surface of an insulating layer disposed below the driving voltage input section and the common voltage input section, and includes a portion of the area extending in the diagonal direction, an electronic device.

19. In Paragraph 17, It further includes dams disposed in the above-mentioned non-display area, disposed on the driving voltage input unit and the common voltage input unit, and disposed to surround the display area on a plane. The dam among the above dams that is positioned closest to the display area is an electronic device positioned to overlap with the second vertical driving voltage input section in a planar manner.

20. In Paragraph 17, Dams disposed in the above-mentioned non-display area, disposed on the driving voltage input unit and the common voltage input unit, and disposed to surround the display area in a planar manner; and An electronic device further comprising: a light-emitting diode disposed in the above-mentioned display area and electrically connected to a contact area of ​​the common voltage input portion disposed closer to the above-mentioned display area than to the dams in a plane.

Images