Instruction dispatcher

Abstract

The present application discloses an instruction dispatcher, comprising: a load control module configured to, in response to instruction requests from one or more PEs, on the basis of linked list information from a DDR, formulate a scheduling policy for scheduling instructions, wherein the linked list information comprises an SIMT mode and an MIMT mode used for dividing the instructions into instruction blocks; a request arbiter configured to generate corresponding scheduling information for the SIMT mode and the MIMT mode respectively on the basis of the scheduling policy; a DMA controller configured to, on the basis of the scheduling information, control a DMA module to load instruction information from the DDR; an instruction determination module configured to analyze the instruction information to obtain instructions; and an L2 cache configured to dispatch the instructions received from the instruction determination module to the one or more PEs.

Description

Instruction Distributor Technical Field

[0001] This application relates generally to the field of computers, and more specifically to instruction dispatch units (IDUs). Background Technology

[0002] In AI accelerators, the instruction loading process plays a crucial role in ensuring efficient data processing. Given the diverse parallel execution requirements of modern AI tasks, acceleration units are typically configured to operate in Single Instruction Multiple Threads (SIMT) or Multiple Instructions Multiple Threads (MIMT) modes. SIMT is generally used to execute the same instruction across multiple data threads, while MIMT is used to execute different instructions through different data threads.

[0003] As the complexity of artificial intelligence (AI) models increases, systems with automatic instruction loading management and compatibility with SIMT and MIMT configurations are crucial for improving system performance. Summary of the Invention

[0004] According to a first aspect of this disclosure, an instruction distributor is provided, comprising: a load control module, configured to, in response to an instruction request from one or more processing elements (PEs), formulate a scheduling strategy for scheduling instructions based on linked list information from a double data rate storage device (DDR), the linked list information including a SIMT mode and a MIMT mode for dividing instructions into instruction blocks; a request arbitrator, configured to generate corresponding scheduling information for the SIMT mode and the MIMT mode respectively based on the scheduling strategy; a direct memory access (DMA) controller, configured to, according to the scheduling information, control a direct memory access (DMA) module to load instruction information from the DDR; an instruction determination module, configured to analyze the instruction information to obtain instructions; and an L2 cache, configured to distribute the instructions received from the instruction determination module to the one or more processing elements (PEs).

[0005] According to a second aspect of this disclosure, a method for distributing instructions is provided, comprising: receiving an instruction request from one or more processing elements (PEs) at a load control module in an instruction distributor; obtaining linked list information from a double data rate (DDR) storage device at the load control module; formulating a scheduling strategy for scheduling instructions based on the linked list information in response to the instruction request at the load control module, the linked list information including a SIMT mode and a MIMT mode for dividing instructions into instruction blocks; generating corresponding scheduling information for the SIMT mode and the MIMT mode respectively at a request arbitrator based on the scheduling strategy; controlling a direct memory access (DMA) controller to load instruction information from the DDR based on the scheduling information at a direct memory access (DMA) controller; analyzing the instruction information to obtain instructions at an instruction determination module; and distributing the instructions received from the instruction determination module to the one or more processing elements (PEs) at an L2 cache.

[0006] According to a third aspect of this disclosure, a processor including the above-described instruction assigner is provided.

[0007] The operation and function of these and other features disclosed herein, as well as related structural elements and combinations thereof, will become more apparent upon consideration of the following description and appended claims with reference to the accompanying drawings (all of which form a part of this specification, wherein like reference numerals designate corresponding portions in the drawings). However, it should be clearly understood that the drawings are for illustrative and descriptive purposes only and not for limiting purposes. Attached Figure Description

[0008] Figure 1 shows a system schematic diagram of a processor core according to an embodiment of this application.

[0009] Figures 2A and 2B illustrate two conventional linked list patterns and two linked list patterns compatible with MIMT and SIMT according to embodiments of this application, respectively.

[0010] Figure 3 shows a schematic diagram of the operation of an IDU according to an embodiment of this application.

[0011] Figure 4 shows a schematic diagram of the structure of an IDU according to an embodiment of this application.

[0012] Figure 5 shows a flowchart of the workflow of an IDU according to an embodiment of this application.

[0013] Figure 6 shows a schematic diagram of the load control module in an IDU according to an embodiment of this application.

[0014] Figure 7 shows a schematic diagram of a request arbitrator in an IDU according to an embodiment of this application.

[0015] Figure 8 illustrates an example computing device in which the processor core of an embodiment of this disclosure can be used. Detailed Implementation

[0016] Embodiments of this application provide a system compatible with both SIMT and MIMT modes, utilizing a linked list structure to read instructions in segments, allowing flexible switching between SIMT and MIMT modes. An instruction allocator effectively manages the arbitration and scheduling of multiple requests, ensuring high-performance instruction loading.

[0017] The instruction allocator plays a crucial role in managing concurrent requests from various execution units. It effectively arbitrates these requests and schedules them in a way that maximizes resource utilization, ensuring that no execution unit is idle. By coordinating multiple requests, the instruction allocator prevents bottlenecks that could arise due to conflicting demands for shared resources, thus maintaining a smooth flow of instruction loading.

[0018] Figure 1 shows a system schematic diagram of a processor core 100 according to an embodiment of this application.

[0019] As shown in Figure 1, the processor core 100 includes: an array of multiple Processor Elements (PEs), a Last Level Cache (LLC), a Double Data Rate (DDR) memory device, an RVV (RSIC-V Vector Extension) module, a Core Level Scheduler (CoLS), and an instruction distributor. The RVV module is used for software control of the PEs to execute the software scheduler, and the CoLS is used for hardware control of the PEs. In some embodiments, the CoLS and the RVV module communicate with each other. Specifically, the CoLS can interrupt hardware control in response to an interrupt signal from the RVV module, and the RVV module can also interrupt software control in response to an interrupt signal from the CoLS.

[0020] In some embodiments, the RVV module acts as the master controller, and the CoLS acts as the slave controller. The RVV module and the CoLS collaborate to invoke software and hardware control for various dynamic or static scenarios. The IDU is used to receive instructions from the DDR and send the instructions to the processing unit array and the CoLS. Various details about the IDU will be described below.

[0021] In some embodiments, the processing unit array includes a 4×4 PE array and a 4×4 router (denoted by R in the figure) array. Each PE in the 4×4 PE array communicates directly with a corresponding router in the 4×4 router array and indirectly with other routers in the 4×4 router array via that router, and thus indirectly with other PEs in the 4×4 PE array. Each PE in the 4×4 PE array writes data to the LLC via one or more routers in the 4×4 router array, and then further stores the data in DDR. Those skilled in the art will understand that the processor core 100 may include more or fewer PEs, and the PE array in the processor core 100 is not limited to the layout shown in the figure.

[0022] Figure 2A illustrates two traditional linked list patterns. Figure 2B illustrates two linked list patterns compatible with MIMT and SIMT according to embodiments of this application.

[0023] In the embodiments of this application, IDU automatically loads instructions using a linked list. When reading instructions, the instructions are typically divided into multiple instruction blocks. These instruction blocks can be arranged in a linked list pattern. As shown in Figure 2A, in the tail-pointer linked list pattern, a pointer is placed at the end of each instruction block, and each pointer points to the next instruction block to be executed. In the independent pointer linked list pattern, each instruction block is assigned a pointer, which is separate from the instruction block; each pointer points to the instruction block and then to the next pointer.

[0024] The tail pointer linked list pattern and the independent pointer linked list pattern each have their own advantages. The tail pointer linked list pattern does not require additional pointer information retrieval, which can reduce read latency; the independent pointer linked list pattern does not insert pointers into instruction data, which facilitates dynamic processing.

[0025] Figure 2B illustrates how, according to an embodiment of this application, the conversion between SIMT and MIMT is implemented in a linked list mode. In the tail pointer linked list mode, when converting from SIMT to MIMT, a single pointer points to an instruction block with multiple pointers at the tail, and these multiple pointers each point to multiple other instruction blocks; when converting from MIMT to SIMT, the multiple instruction blocks each with a pointer at the tail all point to a different instruction block.

[0026] In the independent pointer list mode, when converting from SIMT to MIMT, one pointer of one instruction block points to multiple pointers of multiple other instruction blocks; when converting from MIMT to SIMT, multiple pointers of multiple instruction blocks point to one pointer of another instruction block. This hybrid instruction loading mode can be compatible with both SIMT and MIMT to maximize hardware utilization.

[0027] Figure 3 shows a schematic diagram of the operation of an IDU according to an embodiment of this application.

[0028] In Figure 3, the instruction allocation process of the IDU is completed in three levels: DDR, L2 cache, and L1 cache. Instructions or linked lists are usually stored in DDR. When the L2 cache in the IDU is empty, the IDU sends an instruction request to the DDR, and the L2 cache loads the instruction data from the DDR and stores the instruction data in the L2 cache. When the L1 cache in the PE is empty, the PE sends an instruction request to the L2 cache, and the L2 cache sends the instruction to the L1 cache in the PE according to the scheduling policy.

[0029] Communication between DDR and L2 cache, and communication between L2 cache and L1 cache, are two independent processes that do not affect each other. This independent instruction transfer process between DDR and L2 cache, and between L2 cache and L1 cache, allows new instruction data to be loaded as soon as the cache is empty, without considering other modules. This ensures the instruction pipeline remains full and reduces idle time for processing units.

[0030] Figure 4 shows a schematic diagram of the structure of an IDU according to an embodiment of this application. The IDU according to this application includes: a Direct Memory Access (DMA) module, a DMA controller, a load control module, an instruction judgment module, a request arbitrator, an L2 cache, etc. The DMA module is used to move instructions from DDR to the IDU.

[0031] The load control module formulates a scheduling policy for scheduling instructions based on requests from each PE, linked list information from the DDR, and configuration information from the Control and Status Register (CSR) in the PE. The DMA controller responds to the scheduling policy received from the load control module by controlling the DMA to load instructions from the DDR. The request arbitrator generates corresponding scheduling information for SIMT and MIMT modes based on the scheduling policy from the load control module and sends the scheduling information to the DMA controller. The instruction judgment module pre-judges the instruction information read from the DMA to determine whether the received instruction information is an instruction or a linked list. If the instruction judgment module receives an instruction that is a linked list, it sends the linked list information to the load control module so that the load control module can use the linked list for the next instruction load in the DMA. If the instruction judgment module receives an instruction, it determines which PE the instruction will be sent to and writes the instruction to the corresponding memory location in the L2 cache. The L2 cache stores instruction data and distributes the instruction data to the PEs.

[0032] Figure 5 shows a flowchart of the workflow of an IDU according to an embodiment of this application.

[0033] In box 502, when the L1 cache in the PE is empty, the PE sends a command to the IDU to start loading request.

[0034] Before loading instructions, at block 504, the load control module in the IDU reads configuration information from the CSR via the Advanced High Performance Bus (AHB) interface. In some embodiments, the configuration information includes source address, instruction length, configuration mode, etc. In some embodiments, the read length of the DMA module is stored in a linked list. Based on the configuration information read from the CSR and the read length of the DMA module in the linked list, the load control module configures the read length of the DMA module, slicing it into storage lengths adapted to the L2 cache.

[0035] In block 506, the load control module also receives linked list information from the DDR. In embodiments of this application, the linked list information includes SIMT mode and MIMT mode for dividing instructions into instruction blocks. In some embodiments, the linked list information also includes control information such as the address of the next instruction to be loaded, the instruction length, and the address of the next pointer.

[0036] At block 508, the load control module responds to instruction load start requests from each PE and formulates an instruction scheduling policy based on the linked list information, and sends the instruction scheduling policy to the request arbitrator. In some embodiments, the load control module is also configured to formulate a scheduling policy based on configuration information from CSRs in one or more PEs.

[0037] In block 510, the requesting arbitrator generates corresponding scheduling information for SIMT mode and MIMT mode based on the received scheduling policy, and sends the scheduling information to the DMA controller.

[0038] In block 512, the DMA controller controls the DMA to load instructions from DDR according to scheduling information. After the DMA completes loading the instructions, it sends the instructions to the instruction judgment module.

[0039] In block 514, the instruction judgment module analyzes the instruction information received from DMA and stores the instructions required by PE into the L2 cache.

[0040] In box 516, the L2 cache distributes instructions to each PE.

[0041] In addition, the load control module uses linked list information to determine whether to use SIMT or MIMT mode. If SIMT is used, the operations of each PE are synchronized. If MIMT is used, synchronization is not required.

[0042] It should be noted that those skilled in the art should understand that although the process is illustrated in Figure 5, it does not mean that it must be performed in the order shown in Figure 5. Rather, it can be performed in other orders or in parallel. For example, blocks 502, 506, and 508 can be performed in a different order than shown in Figure 5, or in parallel.

[0043] Figure 6 shows a schematic diagram of the load control module in the IDU shown in Figure 5 according to an embodiment of this application. As shown in Figure 6, the load control module specifically includes a synchronization circuit, a read circuit, and a slicing circuit. The synchronization circuit is configured to synchronize the operations of each PE according to whether the current mode is SIMT mode or MIMT mode. In SIMT mode, the synchronization circuit synchronizes the load requests of each PE that need to be broadcast, so that the IDU starts the load instruction operation only after receiving the load requests of all PEs. In MIMT mode, no synchronization operation is required. After performing the synchronization operation (if necessary), the synchronization circuit forwards the received start signal to the read circuit and the slicing circuit through a multiplexer. The read circuit is configured to read the configuration information from the CSR in response to the start signal from the synchronization circuit. The slicing circuit configures the read length of the DMA module according to the configuration information read from the CSR and the read length of the DMA module in the linked list information. If the length to be read is greater than the current remaining capacity, it slices it into storage lengths adapted to the L2 cache.

[0044] Figure 7 shows a schematic diagram of the request arbitrator in the IDU shown in Figure 5 according to an embodiment of this application. The request arbitrator is configured to distinguish between SIMT mode and MIMT mode, and generate corresponding scheduling information for the DMA controller to execute the scheduling policy.

[0045] Figure 8 illustrates an example computing device 800 in which a processor core according to an embodiment of the present disclosure may be used. As shown in Figure 8, the computing device 800 may include a bus 802 or other communication mechanism for transmitting information and one or more hardware processors 804 coupled to the bus 802 for processing information. The one or more hardware processors 804 may include, for example, one or more general-purpose microprocessors and / or one or more processor cores according to embodiments of the present disclosure.

[0046] As shown in Figure 8, in some embodiments, the computing device 800 may further include a main memory 806 coupled to a bus 802 for storing information and instructions executed by one or more processors 804, such as random access memory (RAM), cache, and / or other dynamic storage devices. The main memory 806 may also be used to store temporary variables or other intermediate information during the execution of instructions executed by one or more processors 804. These instructions, when stored in a storage medium accessible to one or more processors 804, can cause the computing device 800 to become a dedicated machine customized to perform the operations specified in the instructions. The main memory 806 may include non-volatile and / or volatile storage media. Non-volatile storage media may include, for example, optical discs or magnetic disks. Volatile storage media may include dynamic memory. Common forms of storage media may include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tape, or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, DRAM, PROM, and EPROM, FLASH-EPROM, NVRAM, any other memory chip or cartridge, or their networking versions.

[0047] As shown in Figure 8, in some embodiments, the computing device 800 may further include a communication interface 810 coupled to the bus 802. The communication interface 810 may provide bidirectional data communication coupling to one or more network links connected to one or more networks. As another example, the communication interface 810 may be a local area network (LAN) card to provide data communication connectivity to a LAN-compatible (or WAN component communicating with a WAN) network. A wireless link may also be implemented.

[0048] The execution of certain operations can be distributed across processors rather than residing within a single machine, but rather deployed across multiple machines. In some example embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other example embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0049] Each of the processes, methods, and algorithms described in the preceding sections may be embodied in code modules executed by one or more computer systems or computer processors including computer hardware, and may be fully or partially automated by these code modules. The processes and algorithms may be implemented, partially or fully, in dedicated circuit systems.

[0050] When the functions disclosed herein are implemented as software functional units and sold or used as standalone products, they may be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, may be embodied in the form of a software product. The software product may be stored in a storage medium and includes several instructions that cause a computing device (which may be a personal computer, server, network device, etc.) to perform all or some steps of the methods of the embodiments of this application. The storage medium may include a flash drive, portable hard disk drive, ROM, RAM, magnetic disk, optical disk, other media operable to store program code, or any combination thereof.

[0051] Specific embodiments further provide a system including a processor and a non-transitory computer-readable storage medium storing instructions executable by the processor to cause the system to perform operations corresponding to steps in any method of the embodiments disclosed above. Specific embodiments further provide a non-transitory computer-readable storage medium storing instructions executable by one or more processors to cause the one or more processors to perform operations corresponding to steps in any method of the embodiments disclosed above.

[0052] The embodiments disclosed herein can be implemented via a cloud platform, server, or server cluster (collectively referred to below as the "Service System") that interacts with a client. The client can be a terminal device or a client registered by a user at the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device that can have the platform application installed.

[0053] The various features and processes described above can be used independently of each other or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Additionally, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and their associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in an order other than that specifically disclosed, or multiple blocks or states may be combined into a single block or state. Example blocks or states may be executed sequentially, in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed example embodiments. The exemplary systems and components described herein may be configured differently than described. For example, components may be added to, removed from, or rearranged compared to the disclosed example embodiments.

[0054] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. The algorithm may be included in program code or instructions stored in memory (e.g., the aforementioned non-transitory computer-readable storage medium). This algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not explicitly refer to the computer as performing the function but may learn from training data to generate a predictive model of the function.

[0055] The various operations of the exemplary methods described herein can be performed, at least in part, by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, these processors can constitute an engine of processor implementation that operates to perform one or more of the operations or functions described herein.

[0056] Similarly, the methods described herein may be implemented at least in part by a processor, wherein one or more specific processors are instances of hardware. For example, at least some operations of the methods may be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors may also be operable to support the execution of related operations in a “cloud computing” environment or as the execution of related operations in a “Software as a Service” (SaaS) context. For example, at least some operations may be performed by a group of computers (as an example of a machine containing processors), wherein these operations are accessible via a network (e.g., the Internet) and via one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0057] The execution of certain operations can be distributed across processors rather than residing within a single machine, and can be deployed across multiple machines. In some example embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other example embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0058] Throughout this specification, multiple instances may be implemented as components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of these individual operations may be performed simultaneously, and not necessarily in the order illustrated. Structures and functions presented as separate components in the example configuration may be implemented as composite structures or components. Similarly, structures and functions presented as single components may be implemented as single components. These and other variations, modifications, additions, and improvements fall within the scope of this document.

[0059] As used herein, "or" is inclusive rather than exclusive unless explicitly indicated by the context. Therefore, in this document, "A, B, or C" means "A, B, A and B, A and C, B and C, or A, B, and C" unless explicitly indicated by the context. Furthermore, "and" is combined and separate unless explicitly indicated by the context. Therefore, in this document, "A and B" means "A and B, combined or separate" unless explicitly indicated by the context. Additionally, multiple instances of resources, operations, or structures described herein may be provided as a single instance. Furthermore, the boundaries between various resources, operations, engines, and data storage devices are somewhat arbitrary and specific operations are illustrated within the context of a particular illustrative configuration. Other functional assignments are foreseeable and fall within the scope of various embodiments of this disclosure. Generally, structures and functions presented as individual resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functions presented as single resources may be implemented as single resources. These and other changes, modifications, additions, and improvements fall within the scope of the embodiments of this disclosure as expressed in the appended claims. Therefore, this specification and drawings should be considered illustrative rather than restrictive.

[0060] The terms “comprising” or “including” are used to indicate the presence of a subsequently claimed feature, but do not preclude the addition of other features. Unless otherwise specifically stated or otherwise understood in the context in which they are used, conditional language such as “may,” “can,” “may,” and “can” is generally intended to convey that certain embodiments include certain features, components, and / or steps that are not included in other embodiments. Therefore, this conditional language is generally not intended to imply that one or more embodiments require features, components, and / or steps in any way, or that one or more embodiments must include logic for determining whether such features, components, and / or steps are included in or performed in any particular embodiment, with or without user input or prompts.

[0061] Although the general outline of the subject matter has been described with reference to specific exemplary embodiments, various modifications and changes may be made to these embodiments without departing from the broad scope of embodiments of this disclosure. Where more than one embodiment is disclosed, these embodiments of the subject matter may be referred to individually or collectively herein as the term "invention," this is for convenience only and is not intended to automatically limit the scope of this application to any single disclosure or concept.

[0062] The embodiments illustrated herein have been described in sufficient detail to enable those skilled in the art to practice the teachings disclosed. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. Therefore, the term "implementation" is not intended to be limiting, and the scope of the various embodiments is defined only by the appended claims and their full scope.

Claims

1. An instruction allocator, comprising: The load control module is used to respond to instruction requests from one or more processing elements (PEs) and formulate a scheduling strategy for scheduling instructions based on linked list information from the double data rate storage device (DDR). The linked list information includes SIMT mode and MIMT mode for dividing instructions into instruction blocks. An arbitrator is requested to generate corresponding scheduling information for the SIMT mode and the MIMT mode, respectively, based on the scheduling policy. A direct memory access DMA controller is used to control the direct memory access DMA module to load instruction information from the DDR according to the scheduling information; The instruction determination module is used to analyze the instruction information to obtain the instruction; as well as The L2 cache is used to distribute the instructions received from the instruction determination module to the one or more processing elements (PEs).

2. The instruction distributor according to claim 1, wherein, The load control module further includes formulating the scheduling strategy based on configuration information from the status registers (CSRs) in the one or more processing elements (PEs).

3. The instruction distributor according to claim 1, wherein, The linked list information also includes: the address of the next instruction to be loaded, the instruction length, and the address of the next pointer.

4. The instruction distributor according to claim 1, wherein, The instruction judgment module analyzes the instruction information by determining whether the instruction information is an instruction or a linked list.

5. The instruction distributor according to claim 3, wherein, The instruction determination module is configured to send the linked list information to the load control module in response to determining that the instruction information is a linked list.

6. The instruction distributor according to any one of claims 1-5, wherein, The load control module is also configured to configure the read length of the DMA module based on the linked list information.

7. The instruction distributor according to any one of claims 1-5, wherein, The load control module is also configured to determine whether the instruction block is in the SIMT mode or the MIMT mode based on the linked list information.

8. The instruction distributor of claim 7, wherein if it is determined that the instruction block is in SIMT mode, the load control module is configured to synchronize the instruction requests received from the one or more PEs to synchronize the operation of each of the one or more PEs.

9. A method for assigning instructions, comprising: At the load control module in the instruction distributor, instruction requests are received from one or more processing elements (PEs). At the load control module, linked list information is obtained from the double data rate storage device DDR; At the load control module, in response to the instruction request, a scheduling strategy for the scheduling instruction is formulated based on the linked list information, wherein the linked list information includes a SIMT mode and a MIMT mode for dividing the instruction into instruction blocks; At the request arbitrator, corresponding scheduling information is generated for the SIMT mode and the MIMT mode respectively, according to the scheduling policy. At the Direct Memory Access DMA controller, the Direct Memory Access DMA module is controlled to load instruction information from the DDR according to the scheduling information. At the instruction judgment module, the instruction information is analyzed to obtain the instruction; as well as At the L2 cache, the instruction received from the instruction determination module is distributed to the one or more processing elements (PEs).

10. The method according to claim 9, wherein, Developing the scheduling policy also includes developing the scheduling policy based on configuration information from the status registers (CSRs) in the one or more processing elements (PEs).

11. The method according to claim 10, wherein, The linked list information also includes: the address of the next instruction to be loaded, the instruction length, and the address of the next pointer.

12. The method according to claim 10, wherein, Analyzing the instruction information includes determining whether the received instruction information is an instruction or a linked list.

13. The method of claim 12, further comprising: In response to determining that the received instruction information is a linked list, the linked list information is sent to the load control module.

14. The method according to any one of claims 9-13, further comprising: Configure the read length of the DMA module based on the linked list information.

15. The method according to any one of claims 9-13, further comprising: The linked list information is used to determine whether the instruction block is in the SIMT mode or the MIMT mode.

16. The method according to claim 15, wherein, In response to determining that the instruction block is in SIMT mode, the instruction requests received from the one or more PEs are synchronized to synchronize the operation of each of the one or more PEs.

17. A processor comprising an instruction dispatcher according to any one of claims 1-8.

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