Two-step MBE growth procedure for deep, high mobility quantum well proximitized with epitaxial metal

Abstract

Methods for a low-disorder two-step molecular beam epitaxy ("MBE") growth procedure for deep,high mobility quantum well proximitized with epitaxial metal. Shallow quantum wells ("QWs")of InAs- or InSb-based materials are grown using MBE, topped with a layer of epitaxially matched metal after a thin (~ 10 nm) barrier layer for a strong proximity effect. A second MBE step grows an additional layer forming a deep, proximitized quantum well.

Description

Atty. Dkt. No.: 046434-0873TWO-STEP MBE GROWTH PROCEDURE FOR DEEP, HIGH MOBILITY QUANTUM WELL PROXIMITIZED WITH EPITAXIAL METALCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of U.S. Provisional Patent App. No. 63 / 602,958, filed November 27, 2023, the contents of which is incorporated by reference in its entirety.STATEMENT OF GOVERNMENT INTEREST

[0002] This invention was made with government support under N000142212764 awarded by the Office of Naval Research. The government has certain rights in the invention.TECHNICAL FIELD

[0003] The present disclosure relates generally to a two-step MBE growth procedure for deep, high mobility quantum well proximitized with epitaxial metal.BACKGROUND

[0004] In recent years, there has been significant interest in the development of hybrid superconductor-semiconductor systems, with the goal of using the unique combination of resulting properties to access topologically non-trivial states for use in quantum computation. One way of creating these hybrid materials is by forming a two-dimensional electron gas (“2DEG”) based on heterostructures which exhibit a strong spin-orbit interaction (e.g., InAs quantum wells) with superconductivity introduced into the picture via the proximity effect.

[0005] In order to attempt the creation of a hard-gapped p-wave-like superconducting state, shallow quantum wells of InAs- or InSb-based materials have been grown using molecular beam epitaxy (“MBE”), topped with a layer of epitaxially matched Al after a thin (~ 10 nm) barrier layer for a strong proximity effect.

[0006] These proximitized 2DEGs are already grown by multiple academic groups. However, the main goal of these proximitized systems is the creation of extended, topologically nontrivial states, which remain elusive. Both experimental and theoretical14921 -5057-4336.1Atty. Dkt. No.: 046434-0873 efforts in the field point towards a main disadvantage of proximitized 2DEG structures which hinders the emergence of topology - limited carrier mobility.

[0007] The need for shallow quantum wells (necessary for proximity effect) leaves the quantum wells subject to damage induced by fabrication, with scattering at the semiconductor / dielectric interface contributing significantly to disorder in the system. The highest mobilities measured in existing shallow quantum well structures are on the order of 100,000 cm2 / (V»s). On the other hand, deep quantum well structures, in which the well is buried underneath at least 100 nm of semiconductor layers, have exhibited much larger mobilities, with values close to and even in excess of 106cm2 / (V»s) observed, but these are not suitable for experiments which require proximity to a superconductor.

[0008] Despite these advances, there remains several problems in the superconductorsemiconductor hybrid space. In particular, the limited mobility of proximitized structures and proven an intractable problem. Thus, there remains a need for a process and resultant materials that address the issues of superconductor-semiconductor hybrids, particular as relates to the limited mobility issue.SUMMARY

[0009] Described herein are systems and methods for a low-disorder two-step molecular beam epitaxy (“MBE”) growth procedure for deep, high mobility quantum well proximitized with epitaxial aluminum. In order to attempt the creation of a hard-gapped p-wave-like superconducting state, shallow quantum wells (“QWs”) of InAs- or InSb-based materials have been grown using MBE, topped with a layer of epitaxially matched Al after a thin (~ 10 nm) barrier layer for a strong proximity effect.

[0010] It should be appreciated that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the subject matter disclosed herein. In particular, all combinations of claimed subj ect matter appearing at the end of this disclosure are contemplated as being part of the subject matter disclosed herein.24921 -5057-4336.1Atty. Dkt. No.: 046434-0873BRIEF DESCRIPTION OF THE FIGURES

[0011] The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understanding that these drawings depict only several implementations in accordance with the disclosure and are therefore not to be considered limiting of its scope, the disclosure will be described with additional specificity and detail through use of the accompanying drawings.

[0012] FIG. 1 is a summary of the fabrication steps.

[0013] FIG. 2 is an example of heterostructure grown in the initial MBE step.

[0014] FIG. 3 illustrates a computer system for use with certain implementations.

[0015] Reference is made to the accompanying drawings throughout the following detailed description. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative implementations described in the detailed description, drawings, and claims are not meant to be limiting. Other implementations may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and made part of this disclosure.DETAILED DESCRIPTION

[0016] Embodiments described herein relate generally to systems and methods for a low- disorder two-step molecular beam epitaxy (“MBE”) growth procedure for a deep, high mobility quantum well proximitized with epitaxial metal, such as aluminum, lead and / or tin. By introducing a second MBE growth step with a thorough in-situ cleaning, the described processes harness the positive aspects of both of the currently existing two-dimensional electron gases (“2DEGs”) variations — shallow and deep wells. It is believed that this will lead to a proximitized quantum well which is protected by multiple layers of lattice-matched semiconductor, removing the need for a dielectric interface and potentially significantly increasing carrier mobility.34921 -5057-4336.1Atty. Dkt. No.: 046434-0873

[0017] In some embodiments, the material combination achieves two of the main objectives which are desirable for an attempt at a topological system: spin-orbit coupling from the semiconductor quantum well and superconductivity from the nearby superconductor. These 2D structures have an additional advantage of facilitating a more scalable approach to fabrication than previous systems. Prior approaches for vapor-solid-liquid grown nanowires need to be deposited individually with a micromanipulator. This method provides little control over their exact placement. 2DEGs can be patterned into any desired device pattern, enabling complex, repeatable structures with gate tunable carrier density.

[0018] With all of these advantages, clear signatures of topological phases remain elusive. Both experimental and theoretical efforts in the field point towards a main disadvantage of proximitized 2DEG structures which hinders the emergence of topology — limited carrier mobility. The need for shallow quantum wells (“QWs”) leaves them subject to damage induced by fabrication, with scattering at the semiconductor / dielectric interface contributing significantly to disorder in the system. The highest mobilities measured in shallow quantum well structures are on the order of 100,000 cm2 / (V»s). On the other hand, deep quantum well structures, in which the well is buried underneath at least 100 nm of semiconductor layers, have exhibited much larger mobilities, with values close to and even in excess of 106cm2 / (V»s) observed.

[0019] Described herein is a method which will take advantage of the high mobilities provided by the protection of a deep quantum well and the lack of a dielectric interface, while maintaining the ability to proximitize the quantum well. In one embodiment, a method includes two MBE steps, with wet bench fabrication in between. In such a method, the structure would first be MBE grown as a shallow, proximitized quantum well. Following this first MBE step, the shape of the desired junctions would then be defined via selective wet etching of the epitaxial layer, such as epitaxial Al. After this, instead of applying dielectric, the structure would be returned to the MBE chamber for a second MBE step where the surface would be cleaned and then topped with a further semiconductor layer, encasing the quantum well as well as the remaining epitaxial layer. One implementation of these steps is illustrated in FIG. 1 and described in more detail below.44921 -5057-4336.1Atty. Dkt. No.: 046434-0873Growth Procedure.

[0020] As shown in FIG. 1, at Step (a), the samples are grown using a MBE system. An example of the specific measurements for the initial grown structure is shown in FIG. 2. The grown occurs on a standard substrate, such as a semiconductor wafer. For example, in one embodiment, an InP (001) wafer is introduced to the system on an In-free block and heated to 150°C to remove water residues from the wafer. Alternative substrate include GaAs, InSb, and GaSb. The quantum well maybe grown as a lattice-matched system. A quantum well may be formed utilizing various combinations of barrier layer semiconductor material surrounding the thin layer of a semiconductor well layer. A well barrier defining the quantum well materials as separate from the barrier layer on each side maybe utilized, for example a well barrier or wall may be InAlAs. The sample is then transferred to the growth chamber via UHV track. In one example embodiment, a sample is then heated to the growth temperature (500°C) and a superlattice of InGaAs / InAlAs superlattice is grown to achieve a smooth InAlAs surface. The sample temperature is then decreased 350-400°C, such as to 370°C and an ImAh-x. As graded buffer 10 is grown to increase the In content from x=0.52 to x=0.81. The sample temperature is increased to 430-460°C, such as 450°C, to grow highly ordered quantum well 30, such as InAs with thickness of 4-7 nm, enclosed by first barrier 20 and second barrier layer 40, such InGaAs barriers with thicknesses of 4-10 nm. The sample is cooled to cryo temperatures (for example, at least below 0°C, preferably below -15°C) and epitaxial metal layer 50, such as Al, is deposited on the surface.

[0021] Following the first MBE step forming the quantum well 20, a fabrication step is performed. For example, the etch step may be defined by, as illustrated in FIG. 1, Steps (b)- (f) as well-established top-down fabrication techniques. In a particular embodiment, the sample is coated in a resist 60 (such as, but not limited to, polymethyl methacrylate (“PMMA”) A4) (Step (b)). In such an embodiment, this is a positive tone resist 61, so electron beam lithography can then be used to expose the regions where the epitaxial Al is to be etched away (Step (c)).

[0022] In the embodiment of FIG. 1, the exposed resist 61 is then removed by immersing the sample in a developer, for example a solution of methyl isobutyl ketone (“MIBK”):isopropyl alcohol (“IP A”). This leaves the regions of the epitaxial metal layer 51, such as Al, which should be etched away (Step (d)). In one embodiment, the developer used in this step only comes into contact with the surface of the remaining resist, that is the material54921 -5057-4336.1Atty. Dkt. No.: 046434-0873 which will be removed before reintroduction to the MBE, and with the superconductor in the exposed regions, which will be etched away. The developer does not come into contact with any part of the sample which will be reintroduced to the MBE.

[0023] The epitaxial Al can then be selectively removed using one of several possible and established methods (Step (e)). For example, an etch can be performed using Al etchant D (Transene ™), which is composed of Phosphoric Acid H3PO4 (55-65%), Sodium-M- Nitrobenzene Sulfonate (5-10%) Acetic Acid C2H4O2 64-19-7 (1-5%) and distilled water, at room temperature or at elevated temperatures using a hot water bath. Further, metal ion free (“MIF”)-type photoresist developer (e.g., MIF 917) containing Tetramethylammonium hydroxide may be used for the etch. Dry etching is also possible.

[0024] Following the etch step, the remaining resist on the sample is preferable be removed. This may be done using established wet bench practices (e.g., stripping it away with 1,3 Dioxolane or, alternatively, acetone). A rinsing step should be performed to attempt to remove remaining pieces of resist, for example a dip in Acetone, followed by a dip in IPA to remove any Acetone residues (Step (f)). In some embodiments, surface cleaning alternative or in addition takes place in the second MBE (Step (g)).

[0025] In a typical prior art process, following lithography in a standard top-down fabrication procedure, the proximitized shallow quantum wells would usually introduce a layer of dielectric before depositing electrostatic gates. In contrast, as shown in the process of FIG. 1, the sample is further cleaned to remove residues to prepare for a further MBE step. In one embodiment, the fabricated sample is instead mounted once more on the Indium free block and introduced to the ultra-high vacuum (“UHV”) environment.

[0026] For example, the post-fabrication cleaning may include the use of an atomic hydrogen source (or any other in situ cleaning) is used to clean the surface that exposes (and maintains) the epitaxial layer for deposition (Step (g)). The cleaned sample is then transferred to the growth chamber, such as while maintained in the UHV environment, for example transferred by way of a UHV track, for a second stage of growth. The second MBE step then further grows a layer substantially thicker than the quantum well 20, grown on the remaining epitaxial layer 50 and the exposed second barrier layer 41. For example, at least 20 nm, in one embodiment at least lOOnm. In one embodiment, an additional barrier layer 80 is grown. This barrier layer is a thick layer (relative to the barrier layers of the first MBE step), a64921 -5057-4336.1Atty. Dkt. No.: 046434-0873 deposited InGaAs in the example, is grown on the surface to bury the fabricated structure. The second MBE step occurs at a temperature of 150°C to 350° C. This second MBE step occurs at a temperature typically cooler than that of the first MBE step, i.e., for the growth of the quantum well, in order to preserve the epitaxial Al layer that was a deposited after the quantum well in the first MBE growth step. The second layer grown by this second MBE step can be the same or may be of a different composition, i.e. InAlAs or InGaAs, than the layers, such as first barrier layer and second barrier layer, formed by the first MBE growth step.

[0027] In one embodiment, a capping layer 90 may be deposited. For example, a capping layer of InAlAs can be grown at higher temperature (400°C), without impact upon the epitaxial layer that is buried by the second MBE step’s growth, to preserve the transport properties of the sample.

[0028] The described processes result in a quantum well which is deep, but also proximitized in the desired regions. The idea behind such a system is to combine proximity, so far only available in shallow QWs, with the increased mobility of a buried well. The need for dielectric, the interface with which introduces significant amounts of disorder, is removed.Definitions.

[0029] As used herein, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, the term “a member” is intended to mean a single member or a combination of members, “a material” is intended to mean one or more materials, or a combination thereof.

[0030] As used herein, the terms “about” and “approximately” generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, about 1000 would include 900 to 1100.

[0031] It should be noted that the term “exemplary” as used herein to describe various embodiments is intended to indicate that such embodiments are possible examples, representations, and / or illustrations of possible embodiments (and such term is not intended to connote that such embodiments are necessarily extraordinary or superlative examples).

[0032] As used herein, the terms “coupled,” “connected,” and the like mean the joining of two additional intermediate members being integrally formed as a single unitary body with74921 -5057-4336.1Atty. Dkt. No.: 046434-0873 one another or with the two members or the two members and any additional intermediate members being attached to one another.

[0033] As shown in FIG. 3, e.g., a computer-accessible medium 120 (e.g., as described herein, storage members directly or indirectly to one another. Such joining may be stationary (e.g., permanent) or moveable (e.g., removable or releasable). Such joining may be achieved with the two members or the two members and any device such as a hard disk, floppy disk, memory stick, CD-ROM, RAM, ROM, etc., or a collection thereof) can be provided (e.g., in communication with the processing arrangement 110). The computer-accessible medium 120 may be a non-transitory computer-accessible medium. The computer-accessible medium 120 can contain executable instructions 130 thereon. In addition or alternatively, a storage arrangement 140 can be provided separately from the computer-accessible medium 120, which can provide the instructions to the processing arrangement 110 so as to configure the processing arrangement to execute certain exemplary procedures, processes and methods, as described herein, for example. The instructions may include a plurality of sets of instructions.

[0034] System 100 may also include a display or output device, an input device such as a keyboard, mouse, touch screen or other input device, and may be connected to additional systems via a logical network. Many of the embodiments described herein may be practiced in a networked environment using logical connections to one or more remote computers having processors. Logical connections may include a local area network (“LAN”) and a wide area network (“WAN”) that are presented here by way of example and not limitation. Such networking environments are commonplace in office-wide or enterprise- wide computer networks, intranets and the Internet and may use a wide variety of different communication protocols. Those skilled in the art can appreciate that such network computing environments can typically encompass many types of computer system configurations, including personal computers, hand-held devices, multi-processor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, mainframe computers, and the like. Embodiments of the invention may also be practiced in distributed computing environments where tasks are performed by local and remote processing devices that are linked (either by hardwired links, wireless links, or by a combination of hardwired or wireless links) through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.84921 -5057-4336.1Atty. Dkt. No.: 046434-0873

[0035] Various embodiments are described in the general context of method steps, which may be implemented in one embodiment by a program product including computerexecutable instructions, such as program code, executed by computers in networked environments. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer-executable instructions, associated data structures, and program modules represent examples of program code for executing steps of the methods disclosed herein. The particular sequence of such executable instructions or associated data structures represents examples of corresponding acts for implementing the functions described in such steps.

[0036] Software and web implementations of the present invention could be accomplished with standard programming techniques with rule-based logic and other logic to accomplish the various database searching steps, correlation steps, comparison steps and decision steps. It should also be noted that the words “component” and “module,” as used herein and in the claims, are intended to encompass implementations using one or more lines of software code, and / or hardware implementations, and / or equipment for receiving manual inputs.

[0037] It is important to note that the construction and arrangement of the various exemplary embodiments are illustrative only. Although only a few embodiments have been described in detail in this disclosure, those skilled in the art who review this disclosure will readily appreciate that many modifications are possible (e.g., variations in sizes, dimensions, structures, shapes and proportions of the various elements, values of parameters, mounting arrangements, use of materials, colors, orientations, etc.) without materially departing from the novel teachings and advantages of the subject matter described herein. Other substitutions, modifications, changes and omissions may also be made in the design, operating conditions and arrangement of the various exemplary embodiments without departing from the scope of the present invention.

[0038] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any inventions or of what may be claimed, but rather as descriptions of features specific to particular implementations of particular inventions. Certain features described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be94921 -5057-4336.1Atty. Dkt. No.: 046434-0873 implemented in multiple implementations separately or in any suitable sub combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.104921 -5057-4336.1

Claims

Atty. Dkt. No.: 046434-0873CLAIMS:

1. A process for producing a quantum well heterostructure comprising: growing a quantum well enclosed by a first barrier and a second barrier; depositing an epitaxial metal layer on the second barrier; etching the epitaxial layer, forming an etched epitaxial layer and exposing a portion of the second barrier; and growing a third barrier layer on the etched epitaxial metal layer and the exposed second barrier portion.

2. The process of claim 1, wherein at least one of the first barrier and the second barrier comprise InGaAs.

3. The process of claim 1 wherein the quantum well is a InAs quantum well.

4. The process of claim 1, wherein growing the quantum well is by molecular beam epitaxy.

5. The process of claim 1, wherein prior to growing the quantum well, comprising: forming a superlattice of InGaAs / InAl As having an InAl As surface; and growing a In.Al / As buffer on the InAlAs surface.

6. The process of claim 1, wherein the epitaxial metal layer comprises aluminum.

7. The process of claim 1, wherein growing the third barrier layer is by molecular beam epitaxy.

8. A quantum well heterostructure comprising: a quantum well positioned between a first barrier layer and a second barrier layer; an epitaxial metal layer positioned on one of the first barrier layer and the second barrier layer; and a semiconductor capping layer disposed on the epitaxial metal layer.

9. The quantum well heterostructure of claim 8, wherein the epitaxial metal layer is a partial layer.

10. The quantum well heterostructure of claim 8, wherein a third barrier layer is disposed on the epitaxial metal layer.114921 -5057-4336.1Atty. Dkt. No.: 046434-087311. The quantum well heterostructure of claim 10, wherein the capping layer is in direct contact with the third barrier layer.

12. The quantum well heterostructure of claim 8, wherein the first barrier layer is disposed upon a buffer material and wherein the second barrier layer is disposed opposite of the first barrier layer and the buffer material relative to the epitaxial metal layer.

13. The quantum well heterostructure of claim 8, wherein the epitaxial metal layer comprises aluminum.

14. The quantum well heterostructure of claim 8, wherein the quantum well comprises a In As quantum well.

15. The quantum well heterostructure of claim 10, wherein at least one of the first barrier layer, the second barrier layer, and the third barrier layer comprise InGaAs.124921 -5057-4336.1

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