Array substrate and display apparatus

Abstract

An array substrate (1) and a display apparatus (1000). An inorganic stack (50) of the array substrate (1) is provided with first via holes (501) at the positions corresponding to a first source contact portion (31) and a first drain contact portion (32) of a first active layer (30). A metal light-shielding layer (20) comprises first auxiliary portions (21) arranged corresponding to at least part of the first via holes (501), and the orthographic projection of each first auxiliary portion (21) on a substrate (10) covers the orthographic projection of the corresponding first via hole (501) on the substrate (10), thereby reducing the risk of cracks forming in an inorganic layer at the bottom of the first via holes (501).

Description

Array substrate and display device Technical Field

[0001] This application relates to the field of display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Foldable displays have become a major development direction in the display industry. With the iteration of display technology, the bending performance of foldable displays is no longer a bottleneck. Improving the impact resistance of foldable displays while ensuring their bending performance has become a research focus. According to the force analysis and experimental results of a pen impact on the front of a foldable display, when the foldable display is subjected to a pen impact from the front, the inorganic layer in the flexible display panel of the foldable display fails preferentially. Invention Overview

[0003] This application provides an array substrate and a display device to improve the impact resistance of foldable display devices and reduce the risk of failure of inorganic layers in flexible display panels.

[0004] The technical solution provided in this application is as follows:

[0005] In a first aspect, embodiments of this application provide an array substrate, which includes a substrate and a plurality of sub-pixels arranged in an array on the substrate, each sub-pixel including at least one first transistor; the array substrate further includes:

[0006] A metal light-shielding layer is disposed above the substrate;

[0007] A first active layer is disposed above the metal light-shielding layer. The first active layer includes a first active portion of the first transistor. The first active portion includes a first source contact portion, a first drain contact portion, and a first channel portion connecting the first source contact portion and the first drain contact portion.

[0008] An inorganic stack is disposed above the first active layer, and the inorganic stack has a first via at the position corresponding to the first source contact portion and the first drain contact portion.

[0009] A first conductive layer is disposed above the inorganic stack. The first conductive layer includes a first source and a first drain of the first transistor. Each first source and the first drain corresponds to a first via. The first source portion located in the first via is electrically connected to the first source contact portion, and the first drain portion located in the first via is electrically connected to the first drain contact portion.

[0010] The metal light-shielding layer includes a first auxiliary portion corresponding to at least a portion of the first via, wherein the orthographic projection of the first auxiliary portion on the substrate covers the orthographic projection of the corresponding first via on the substrate.

[0011] Secondly, embodiments of this application also provide a display device, which includes:

[0012] Display panel, including array substrate;

[0013] A cover plate assembly is disposed on the light-emitting side of the display panel, and the cover plate assembly is bonded to the display panel through a first transparent adhesive layer;

[0014] A support component is disposed on the side of the display panel opposite to the cover plate assembly;

[0015] Wherein, the thickness of the first transparent adhesive layer is greater than or equal to 20 micrometers; the array substrate includes a substrate and a plurality of sub-pixels arranged in an array on the substrate, each sub-pixel including at least one first transistor; the array substrate further includes:

[0016] A metal light-shielding layer is disposed above the substrate;

[0017] A first active layer is disposed above the metal light-shielding layer. The first active layer includes a first active portion of the first transistor. The first active portion includes a first source contact portion, a first drain contact portion, and a first channel portion connecting the first source contact portion and the first drain contact portion.

[0018] An inorganic stack is disposed above the first active layer, and the inorganic stack has a first via at the position corresponding to the first source contact portion and the first drain contact portion.

[0019] A first conductive layer is disposed above the inorganic stack. The first conductive layer includes a first source and a first drain of the first transistor. Each first source and the first drain corresponds to a first via. The first source portion located in the first via is electrically connected to the first source contact portion, and the first drain portion located in the first via is electrically connected to the first drain contact portion.

[0020] The metal light-shielding layer includes a first auxiliary portion corresponding to at least a portion of the first via, wherein the orthographic projection of the first auxiliary portion on the substrate covers the orthographic projection of the corresponding first via on the substrate. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 is a schematic diagram of part of the film layer structure of the flexible display panel in a foldable display device.

[0023] Figure 2 is a partial planar structure schematic diagram of the array substrate provided in an embodiment of this application.

[0024] Figure 3 is a schematic diagram of a portion of the film structure of a sub-pixel region on the array substrate in Figure 2.

[0025] Figure 4 is a schematic diagram of the planar structure of the metal light-shielding layer within a sub-pixel in Figure 2.

[0026] Figure 5 is a partial cross-sectional structural diagram of the display device provided in the embodiment of this application. Embodiments of the present invention

[0027] The following descriptions of the embodiments are based on the accompanying illustrations, illustrating specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustration and understanding of this application, and not for limiting this application. In the figures, structurally similar units are denoted by the same reference numerals. In the figures, the thickness of some layers and regions is exaggerated for clarity and ease of description. That is, the dimensions and thicknesses of each component shown in the figures are arbitrarily shown, but this application is not limited thereto.

[0028] To address the issue of preferential failure of the inorganic layer in the flexible display panel of a foldable display device when subjected to a frontal impact from a pen, the inventors of this application discovered in their research: Referring to Figure 1, which is a schematic diagram of a portion of the film structure of the flexible display panel in a foldable display device, the flexible display panel includes a substrate 10' and a first active layer 20', a first conductive layer 30', and an inorganic stack 40' disposed above the substrate 10'. The inorganic stack 40' has multiple first vias 41' at positions corresponding to the first active layer 20'. The structural portion formed by the first conductive layer 30' is located within the first vias 41' and electrically connected to the first active layer 20'. Through analysis of the failure locations of the inorganic layer in the flexible display panel, the inventors of this application found that the failure locations are mainly concentrated at the bottom of the first vias 41', that is, at the position of the first vias 41' close to the first active layer 20'.

[0029] The inventors of this application, through further analysis, discovered that: the inorganic stack 40' is usually formed by stacking multiple inorganic layers. The inorganic layers are formed by inorganic materials, which usually contain elements such as Si, N, O, and H. When the first via 41' is formed on the inorganic stack 40', the inorganic stack 40' is drilled by using a dry etching process. The dry etching process itself will cause the chemical bonds in the etched area to break, thereby forming micro-defects. This makes the bottom of the first via 41' a weak point in terms of strength. When subjected to external impact, it will undergo large deformation and cracks, causing the inorganic layer to fail, which in turn leads to the failure of the transistor device.

[0030] Therefore, this application provides an array substrate and a display device to improve the impact resistance of foldable display devices and reduce the risk of failure of inorganic layers in flexible display panels.

[0031] Please refer to Figures 1 to 4. Figure 2 is a partial planar structural diagram of the array substrate provided in this embodiment of the application. Figure 3 is a partial film layer structure diagram of a sub-pixel region on the array substrate in Figure 2. Figure 4 is a planar structural diagram of the metal light-shielding layer within a sub-pixel in Figure 2. Referring to Figure 2, the array substrate 1 includes a substrate 10 and a plurality of sub-pixels SP arranged in an array on the substrate 10. Specifically, the array substrate 1 includes a plurality of data lines DL arranged at intervals along a first direction X on the substrate 10 and a plurality of scan lines GL arranged at intervals along a second direction Y on the substrate 10. The data lines DL and the scan lines GL intersect to define a plurality of pixel regions PD, and each sub-pixel SP is located within a pixel region PD. The first direction X and the second direction Y are different; for example, the first direction X is a row direction and the second direction Y is a column direction, and the first direction X and the second direction Y are perpendicular. Of course, this application is not limited to this; in this application, the first direction X and the second direction Y may also intersect to form other angles.

[0032] Referring to Figure 3, each sub-pixel SP includes at least one first transistor. The array substrate 1 further includes a metal light-shielding layer 20, a first active layer 30, an inorganic stack 50, and a first conductive layer 41 disposed above the substrate 10. The first active layer 30 is disposed above the metal light-shielding layer 20 and includes a first active portion of the first transistor. The first active portion includes a first source contact portion 31, a first drain contact portion 32, and a first channel portion 33 connecting the first source contact portion 31 and the first drain contact portion 32.

[0033] The inorganic stack 50 is disposed above the first active layer 30. The inorganic stack 50 has first vias 501 at positions corresponding to the first source contact 31 and the first drain contact 32. The first conductive layer 41 is disposed above the inorganic stack 50. The first conductive layer 41 includes a first source 411 and a first drain 412 of the first transistor. Each first source 411 and first drain 412 corresponds to a first via 501. The portion of the first source 411 located within the first via 501 is electrically connected to the first source contact 31, and the portion of the first drain 412 located within the first via 501 is electrically connected to the first drain contact 32.

[0034] The metal light-shielding layer 20 includes a first auxiliary portion 21 corresponding to at least a portion of the first via 501. The orthographic projection of the first auxiliary portion 21 on the substrate 10 covers the orthographic projection of the corresponding first via 501 on the substrate 10. By providing the first auxiliary portion 21 below the first via 501, the first via 501 is formed on the inorganic stack 50. The first auxiliary portion 21 is formed by the metal light-shielding layer 20. The modulus of the metal is relatively high compared to the inorganic material, and the deformation of the metal is small under impact load. This results in a certain constraint on the deformation of the inorganic stack 50 above the first auxiliary portion 21. Thus, the deformation of the inorganic layer at the bottom of the first via 501 is also reduced accordingly, thereby reducing the risk of cracks in the inorganic layer at the bottom of the first via 501 and further reducing the risk of inorganic layer failure.

[0035] Each sub-pixel SP further includes at least one second transistor, which is electrically connected to the first transistor. The array substrate 1 further includes a second active layer 60 disposed between the first active layer 30 and the first conductive layer 41. The second active layer 60 includes a second active portion of the second transistor. The second active portion includes a second source contact portion 61, a second drain contact portion 62, and a second channel portion 63 connecting the second source contact portion 61 and the second drain contact portion 62.

[0036] The inorganic stack 50 has second vias 502 at positions corresponding to the second source contact 61 and the second drain contact 62. The first conductive layer 41 also includes a second source 413 and a second drain 414 of the second transistor. Each second source 413 and the second drain 414 corresponds to a second via 502. The portion of the second source 413 located within the second via 502 is electrically connected to the second source contact 61, and the portion of the second drain 414 located within the second via 502 is electrically connected to the second drain contact 62.

[0037] The metal light-shielding layer 20 includes a second auxiliary portion 22 corresponding to at least a portion of the second via 502. The orthographic projection of the second auxiliary portion 22 on the substrate 10 covers the orthographic projection of the corresponding second via 502 on the substrate 10. By providing the second auxiliary portion 22 below the second via 502, the second via 502 is formed on the inorganic stack 50. The second auxiliary portion 22 is formed by the metal light-shielding layer 20. The metal has a relatively high modulus compared to the inorganic material, resulting in less deformation of the metal under impact load. This constrains the deformation of the inorganic stack 50 above the second auxiliary portion 22, thereby reducing the deformation of the inorganic layer at the bottom of the second via 502. This reduces the risk of cracks in the inorganic layer at the bottom of the second via 502, and consequently reduces the risk of inorganic layer failure.

[0038] Optionally, the second drain 414 also corresponds to a first via 501, and the portion of the second drain 414 located in the first via 501 is electrically connected to the first drain contact portion 32 to realize the electrical connection between the second transistor and the first transistor.

[0039] The orthographic projections of the first source 411 portion, the first drain 412 portion, and the second drain 414 portion located within the first via 501 onto the substrate 10 are all within the orthographic projections of the corresponding first auxiliary portion 21 onto the substrate 10. Similarly, the orthographic projections of the second source 413 portion and the second drain 414 portion located within the second via 502 onto the substrate 10 are all within the orthographic projections of the corresponding second auxiliary portion 22 onto the substrate 10. In other words, the orthographic projection of the first source 411 portion located within the first via 501 onto the substrate 10 is within the orthographic projection of its corresponding first auxiliary portion 21 onto the substrate 10, and the orthographic projection of the first drain 412 portion located within the first via 501 onto the substrate 10... The first auxiliary part 21 located within its corresponding orthographic projection on the substrate 10, the second drain 414 portion located within the first via 501, has its orthographic projection on the substrate 10 within the orthographic projection of its corresponding first auxiliary part 21 on the substrate 10, the second source 413 portion located within the second via 502, has its orthographic projection on the substrate 10 within the orthographic projection of its corresponding second auxiliary part 22 on the substrate 10, and the second drain 414 portion located within the second via 502, has its orthographic projection on the substrate 10 within the orthographic projection of its corresponding second auxiliary part 22 on the substrate 10, so that the first auxiliary part 21 can completely cover the first via 501, and the second auxiliary part 22 can completely cover the second via 502.

[0040] Referring again to FIG3, the array substrate 1 further includes a second conductive layer 42, a third conductive layer 43, and a fourth conductive layer 44. The second conductive layer 42 is disposed between the first active layer 30 and the second active layer 60, and the second conductive layer 42 includes a first gate 421 of the first transistor, the first gate 421 being disposed corresponding to the first channel portion 33.

[0041] The third conductive layer 43 is disposed between the second conductive layer 42 and the second active layer 60. The third conductive layer 43 includes the second gate 432 of the second transistor and the first electrode 71 plate 431 disposed opposite to the first gate 421. The first electrode 71 plate 431 and the first gate 421 form a capacitor.

[0042] The fourth conductive layer 44 is disposed between the second active layer 60 and the first conductive layer 41. The fourth conductive layer 44 includes the third gate 441 of the second transistor, and the third gate 441 is correspondingly disposed with respect to the second channel portion 63. The first transistor is a polysilicon transistor, and the second transistor is an oxide transistor. The material of the first active layer 30 includes a silicon semiconductor material, specifically low-temperature polysilicon. The material of the second active layer 60 includes an oxide semiconductor material, specifically a metal oxide semiconductor material, more specifically, indium gallium zinc oxide.

[0043] The array substrate 1 further includes a first electrode 71 disposed above the first conductive layer 41, and the first electrode 71 is electrically connected to the first drain 412 of the first transistor. Optionally, the array substrate 1 further includes a fifth conductive layer 45 disposed between the first electrode 71 and the first conductive layer 41, the fifth conductive layer 45 having a bridging electrode 451, and the first electrode 71 being electrically connected to the first drain 412 through the bridging electrode 451.

[0044] Multiple insulating layers are also disposed between the conductive layers on the array substrate 1. Specifically, the multiple insulating layers include a first buffer layer 11 and a second buffer layer 12 located between the metal light-shielding layer 20 and the first active layer 30, an inorganic stack 50 located between the first active layer 30 and the first conductive layer 41, a first planarization layer 13 located between the first conductive layer 41 and the fifth conductive layer 45, a second planarization layer 14 located between the fifth conductive layer 45 and the first electrode 71, a pixel definition layer 15 located above the first electrode 71 and the second planarization layer 14, and a barrier 16 located above the pixel definition layer 15. The materials of the first buffer layer 11, the second buffer layer 12, and the inorganic stack 50 include inorganic materials such as silicon oxide and silicon nitride. The materials of the first planarization layer 13, the second planarization layer 14, the pixel definition layer 15, and the barrier 16 are organic materials.

[0045] The inorganic stack 50 includes at least a first insulating layer 51 located between the first active layer 30 and the second active layer 60, and a second insulating layer 52 located between the second active layer 60 and the first conductive layer 41. A first via 501 penetrates the second insulating layer 52 and the first insulating layer 51, and a second via 502 penetrates the second insulating layer 52. Specifically, the first insulating layer 51 covers the first active layer 30 and the second buffer layer 12. The inorganic stack 50 also includes a third insulating layer 53 covering the second conductive layer 42 and the first insulating layer 51, a fourth insulating layer 54 covering the third conductive layer 43 and the third insulating layer 53, and a fifth insulating layer 55 covering the second active layer 60 and the fourth insulating layer 54. The second insulating layer 52 covers the fourth conductive layer 44 and the fifth insulating layer 55.

[0046] The metal light-shielding layer 20 is disposed above the substrate 10, which includes a flexible substrate such as polyimide, for example, the substrate 10 may be formed using a double layer of polyimide. The first buffer layer 11 covers the metal light-shielding layer 20 and the substrate 10. The metal light-shielding layer 20 also includes a first light-shielding portion 23 corresponding to the first channel portion 33 and a second light-shielding portion 24 corresponding to the second channel portion 63. The first light-shielding portion 23 is used to shield the first channel portion 33 from light, and the second light-shielding portion 24 is used to shield the second channel portion 63 from light. The material of the metal light-shielding layer 20 includes a metallic material with light-shielding properties, electrical conductivity, and high modulus.

[0047] Optionally, the first light-shielding part 23, the second light-shielding part 24, the first auxiliary part 21, and the second auxiliary part 22 are integrally disposed to form the structure shown in FIG4.

[0048] Referring to FIG4, within a sub-pixel SP, the number of second vias 502 is less than the number of first vias 501, and the number of second auxiliary portions 22 is less than the number of first auxiliary portions 21. Within a sub-pixel SP, some first vias 501 are not provided with the first auxiliary portion 21 below them, and some second vias 502 are not provided with the second auxiliary portion 22 below them. Furthermore, the number of second vias 502 without the corresponding second auxiliary portion 22 is greater than the number of first vias 501 without the corresponding first auxiliary portion 21. For example, within a sub-pixel SP, the maximum number of first vias 501 without the first auxiliary portion 21 is two, and the maximum number of second vias 502 without the second auxiliary portion 22 is four. This is to make reasonable use of the space of the sub-pixel SP and prevent the first auxiliary portion 21 and the second auxiliary portion 22 from affecting the layout of the sub-pixel SP. Simultaneously, the first auxiliary portion 21 or the second auxiliary portion 22 is preferentially not provided at relatively important transistor locations within the sub-pixel SP to avoid the first auxiliary portion 21 and the second auxiliary portion 22 affecting the electrical properties of the transistors. Moreover, not providing the first auxiliary portion 21 or the second auxiliary portion 22 at certain special locations can also reduce reflectivity.

[0049] Based on the same inventive concept, this application also provides a display device. Referring to Figures 1 to 5, Figure 5 is a partial cross-sectional structural schematic diagram of the display device provided in an embodiment of this application. Referring to Figure 5, the display device 1000 includes a display panel 100, a cover plate assembly 200 disposed on the light-emitting side of the display panel 100, and a support assembly 300 disposed on the side of the display panel 100 opposite to the cover plate assembly 200.

[0050] The display panel 100 includes an array substrate 1 as described in one of the foregoing embodiments. The display panel 100 includes a flexible organic light-emitting diode display panel 100. The display panel 100 also includes a light-emitting functional layer and an encapsulation layer disposed on the array substrate 1.

[0051] The cover plate assembly 200 is bonded to the display panel 100 via a first transparent adhesive layer 401. The cover plate assembly 200 includes a first protective layer 201, a second protective layer 202, and a third protective layer 203. The first protective layer 201 is bonded to the display panel 100 via the first transparent adhesive layer 401, the second protective layer 202 is bonded to the first protective layer 201 via the second transparent adhesive layer 402, and the third protective layer 203 is bonded to the second protective layer 202 via the third transparent adhesive layer 403. The materials of the first protective layer 201, the second protective layer 202, and the third protective layer 203 include PET, CPI, UTG, etc., and the materials of the first transparent adhesive layer 401, the second transparent adhesive layer 402, and the third transparent adhesive layer 403 include OCA, etc. The thickness of the first transparent adhesive layer 401 is greater than or equal to 20 micrometers to improve the mechanical properties of the display device 1000 and reduce the risk of failure of the array substrate 1 due to strain under external loads.

[0052] The support assembly 300 is disposed on the back side of the display panel 100. The support assembly 300 includes a first support layer 301, a second support layer 302, and an auxiliary support layer 303. The first support layer 301 is bonded to the display panel 100 via a first adhesive layer 601. The second support layer 302 is bonded to the first support layer 301 via a second adhesive layer 602. The auxiliary support layer 303 is bonded to the second support layer 302 via a third adhesive layer 603. The materials of the first support layer 301 and the second support layer 302 include PET, PI, etc., and the material of the auxiliary support layer 303 includes SUS, etc. The materials of the first adhesive layer 601, the second adhesive layer 602, and the third adhesive layer 603 include PSA, etc.

[0053] Optionally, the display device 1000 further includes a repair layer 600, which is bonded to the third protective layer 203 via a fourth transparent adhesive layer 404.

[0054] As can be seen from the above embodiments:

[0055] This application provides an array substrate and a display device. The array substrate includes a substrate and a metal light-shielding layer, a first active layer, an inorganic stack, and a first conductive layer disposed on the substrate. The inorganic stack has a first via at a position corresponding to the first source contact and the first drain contact of the first active layer. The first conductive layer forms the first source and the first drain of a first transistor. The first source and the first drain are electrically connected to the first source contact and the first drain contact through the corresponding first via. The metal light-shielding layer includes a first auxiliary portion disposed corresponding to at least a portion of the first via. The orthographic projection of the first auxiliary portion on the substrate covers the orthographic projection of the corresponding first via on the substrate, thereby reducing the risk of cracks in the inorganic layer at the bottom of the first via and thus reducing the risk of inorganic layer failure.

[0056] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0057] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate, each sub-pixel comprising at least one first transistor; The array substrate further includes: A metal light-shielding layer is disposed above the substrate; A first active layer is disposed above the metal light-shielding layer. The first active layer includes a first active portion of the first transistor. The first active portion includes a first source contact portion, a first drain contact portion, and a first channel portion connecting the first source contact portion and the first drain contact portion. An inorganic stack is disposed above the first active layer, and the inorganic stack has a first via at the position corresponding to the first source contact portion and the first drain contact portion. A first conductive layer is disposed above the inorganic stack. The first conductive layer includes a first source and a first drain of the first transistor. Each first source and the first drain corresponds to a first via. The first source portion located in the first via is electrically connected to the first source contact portion, and the first drain portion located in the first via is electrically connected to the first drain contact portion. The metal light-shielding layer includes a first auxiliary portion corresponding to at least a portion of the first via, wherein the orthographic projection of the first auxiliary portion on the substrate covers the orthographic projection of the corresponding first via on the substrate.

2. The array substrate according to claim 1, wherein, Each sub-pixel further includes at least one second transistor, the second transistor being electrically connected to the first transistor; the array substrate further includes: The second active layer is disposed between the first active layer and the first conductive layer. The second active layer includes a second active portion of the second transistor. The second active portion includes a second source contact portion, a second drain contact portion, and a second channel portion connected between the second source contact portion and the second drain contact portion. The inorganic stack has a second via at the position corresponding to the second source contact portion and the second drain contact portion; The first conductive layer further includes a second source and a second drain of the second transistor. Each second source and the second drain corresponds to a second via. The second source portion located in the second via is electrically connected to the second source contact portion, and the second drain portion located in the second via is electrically connected to the second drain contact portion. The metal light-shielding layer includes a second auxiliary portion corresponding to at least a portion of the second via, and the orthographic projection of the second auxiliary portion on the substrate covers the orthographic projection of the corresponding second via on the substrate.

3. The array substrate according to claim 2, wherein, The second drain also corresponds to a first via, and the portion of the second drain located within the first via is electrically connected to the contact portion of the first drain.

4. The array substrate according to claim 3, wherein, The orthographic projection of the first source portion located within the first via onto the substrate lies within the orthographic projection of its corresponding first auxiliary portion onto the substrate. The orthographic projection of the first drain portion located within the first via onto the substrate lies within the orthographic projection of its corresponding first auxiliary portion onto the substrate. The orthographic projection of the second drain portion located within the first via onto the substrate lies within the orthographic projection of its corresponding first auxiliary portion onto the substrate. The orthographic projection of the second source portion located within the second via onto the substrate lies within the orthographic projection of its corresponding second auxiliary portion onto the substrate. The orthographic projection of the second drain portion located within the second via onto the substrate lies within the orthographic projection of its corresponding second auxiliary portion onto the substrate.

5. The array substrate according to claim 2, wherein, Within a sub-pixel, the number of second vias is less than the number of first vias, and the number of second auxiliary portions is less than the number of first auxiliary portions.

6. The array substrate according to claim 5, wherein, Within a sub-pixel, some of the first vias do not have the first auxiliary portion below them, some of the second vias do not have the second auxiliary portion below them, and the number of second vias without a corresponding second auxiliary portion is greater than the number of first vias without a corresponding first auxiliary portion.

7. The array substrate according to claim 6, wherein, Within a sub-pixel, the maximum number of first vias without the first auxiliary portion is two, and the maximum number of second vias without the second auxiliary portion is four.

8. The array substrate according to claim 2, wherein, The metal light-shielding layer includes a first light-shielding part disposed corresponding to the first channel portion and a second light-shielding part disposed corresponding to the second channel portion, wherein the first light-shielding part, the second light-shielding part, the first auxiliary part and the second auxiliary part are integrally disposed.

9. The array substrate according to claim 2, wherein, The inorganic stack includes at least a first insulating layer located between the first active layer and the second active layer, and a second insulating layer located between the second active layer and the first conductive layer. The first via penetrates the second insulating layer and the first insulating layer, and the second via penetrates the second insulating layer.

10. The array substrate according to any one of claims 2 to 9, wherein, The array substrate further includes: A second conductive layer is disposed between the first active layer and the second active layer. The second conductive layer includes a first gate of the first transistor, and the first gate is disposed corresponding to the first channel portion. A third conductive layer is disposed between the second conductive layer and the second active layer, the third conductive layer including the second gate of the second transistor and a first electrode plate disposed opposite to the first gate; A fourth conductive layer is disposed between the second active layer and the first conductive layer. The fourth conductive layer includes a third gate of the second transistor, and the third gate is disposed corresponding to the second channel portion. The first transistor is a polysilicon transistor, and the second transistor is an oxide transistor.

11. A display device comprising: Display panel, including array substrate; A cover plate assembly is disposed on the light-emitting side of the display panel, and the cover plate assembly is bonded to the display panel through a first transparent adhesive layer; A support component is disposed on the side of the display panel opposite to the cover plate assembly; Wherein, the thickness of the first transparent adhesive layer is greater than or equal to 20 micrometers; the array substrate includes a substrate and a plurality of sub-pixels arranged in an array on the substrate, each sub-pixel including at least one first transistor; the array substrate further includes: A metal light-shielding layer is disposed above the substrate; A first active layer is disposed above the metal light-shielding layer. The first active layer includes a first active portion of the first transistor. The first active portion includes a first source contact portion, a first drain contact portion, and a first channel portion connecting the first source contact portion and the first drain contact portion. An inorganic stack is disposed above the first active layer, and the inorganic stack has a first via at the position corresponding to the first source contact portion and the first drain contact portion. A first conductive layer is disposed above the inorganic stack. The first conductive layer includes a first source and a first drain of the first transistor. Each first source and the first drain corresponds to a first via. The first source portion located in the first via is electrically connected to the first source contact portion, and the first drain portion located in the first via is electrically connected to the first drain contact portion. The metal light-shielding layer includes a first auxiliary portion corresponding to at least a portion of the first via, wherein the orthographic projection of the first auxiliary portion on the substrate covers the orthographic projection of the corresponding first via on the substrate.

12. The display device according to claim 11, wherein, Each sub-pixel further includes at least one second transistor, the second transistor being electrically connected to the first transistor; the array substrate further includes: The second active layer is disposed between the first active layer and the first conductive layer. The second active layer includes a second active portion of the second transistor. The second active portion includes a second source contact portion, a second drain contact portion, and a second channel portion connected between the second source contact portion and the second drain contact portion. The inorganic stack has a second via at the position corresponding to the second source contact portion and the second drain contact portion; The first conductive layer further includes a second source and a second drain of the second transistor. Each second source and the second drain corresponds to a second via. The second source portion located in the second via is electrically connected to the second source contact portion, and the second drain portion located in the second via is electrically connected to the second drain contact portion. The metal light-shielding layer includes a second auxiliary portion corresponding to at least a portion of the second via, and the orthographic projection of the second auxiliary portion on the substrate covers the orthographic projection of the corresponding second via on the substrate.

13. The display device according to claim 12, wherein, The second drain also corresponds to a first via, and the portion of the second drain located within the first via is electrically connected to the contact portion of the first drain.

14. The display device according to claim 13, wherein, The orthographic projection of the first source portion located within the first via onto the substrate lies within the orthographic projection of its corresponding first auxiliary portion onto the substrate. The orthographic projection of the first drain portion located within the first via onto the substrate lies within the orthographic projection of its corresponding first auxiliary portion onto the substrate. The orthographic projection of the second drain portion located within the first via onto the substrate lies within the orthographic projection of its corresponding first auxiliary portion onto the substrate. The orthographic projection of the second source portion located within the second via onto the substrate lies within the orthographic projection of its corresponding second auxiliary portion onto the substrate. The orthographic projection of the second drain portion located within the second via onto the substrate lies within the orthographic projection of its corresponding second auxiliary portion onto the substrate.

15. The display device according to claim 12, wherein, Within a sub-pixel, the number of second vias is less than the number of first vias, and the number of second auxiliary portions is less than the number of first auxiliary portions.

16. The display device according to claim 15, wherein, Within a sub-pixel, some of the first vias do not have the first auxiliary portion below them, some of the second vias do not have the second auxiliary portion below them, and the number of second vias without a corresponding second auxiliary portion is greater than the number of first vias without a corresponding first auxiliary portion.

17. The display device according to claim 16, wherein, Within a sub-pixel, the maximum number of first vias without the first auxiliary portion is two, and the maximum number of second vias without the second auxiliary portion is four.

18. The display device according to claim 12, wherein, The metal light-shielding layer includes a first light-shielding part disposed corresponding to the first channel portion and a second light-shielding part disposed corresponding to the second channel portion, wherein the first light-shielding part, the second light-shielding part, the first auxiliary part and the second auxiliary part are integrally disposed.

19. The display device according to claim 12, wherein, The inorganic stack includes at least a first insulating layer located between the first active layer and the second active layer, and a second insulating layer located between the second active layer and the first conductive layer. The first via penetrates the second insulating layer and the first insulating layer, and the second via penetrates the second insulating layer.

20. The display device according to any one of claims 12 to 19, wherein, The array substrate further includes: A second conductive layer is disposed between the first active layer and the second active layer. The second conductive layer includes a first gate of the first transistor, and the first gate is disposed corresponding to the first channel portion. A third conductive layer is disposed between the second conductive layer and the second active layer, the third conductive layer including the second gate of the second transistor and a first electrode plate disposed opposite to the first gate; A fourth conductive layer is disposed between the second active layer and the first conductive layer. The fourth conductive layer includes a third gate of the second transistor, and the third gate is disposed corresponding to the second channel portion. The first transistor is a polysilicon transistor, and the second transistor is an oxide transistor.

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