Display substrate and display apparatus

Abstract

The present application discloses a display substrate and a display apparatus. The display substrate comprises a base, a display region, a transition region, and a hole region. The transition region surrounds the hole region, and the display region surrounds the transition region. The display substrate further comprises a plurality of first signal lines and second signal lines located on one side of the base. Each of some of the first signal lines comprises a first section, a first connection section, and a second section which are sequentially connected. The first section and the second section are located in the display region and both extend in a first direction, and the first connection section is located in the transition region. The first section and the first connection section of each of some of the first signal lines are located in different film layers, and the first section and the second section are located in a same film layer. Each of some of the second signal lines comprises a third section, a second connection section, and a fourth section which are sequentially connected. The third section and the fourth section are located in the display region and both extend in a second direction, and the second connection section is located in the transition region. The first direction intersects the second direction. In part of the driving time period of one image frame, the first signal lines and the second signal lines receive driving signals simultaneously.

Description

Display substrate and display device Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] With the development of mobile smart terminal devices such as smartphones and tablets, users have increasingly higher requirements for screen-to-body ratio. In order to improve the screen-to-body ratio of display devices, openings are usually set in the display devices, and cameras or sensors are placed below the openings.

[0003] However, one of the problems with this design is that the display device being located near the opening can cause display mura (a phenomenon where the brightness of the display is uneven, producing various marks). Summary of the Invention

[0004] The purpose of this application is to provide a display substrate with uniform display brightness and a display device.

[0005] This application discloses a display substrate, which includes a display area, a transition area, and an aperture area, wherein the transition area surrounds the aperture area, and the display area surrounds the transition area;

[0006] The display substrate includes:

[0007] Base;

[0008] A plurality of first signal lines are located on one side of the substrate; some of the first signal lines include a first segment, a first connecting segment and a second segment connected in sequence, the first segment and the second segment are located in the display area and both extend along a first direction, and the first connecting segment is located in the transition area; some of the first signal lines have the first segment and the first connecting segment located in different film layers, and the first segment and the second segment located in the same film layer;

[0009] Multiple second signal lines are located on the same side of the substrate as the first signal line; some of the second signal lines include a third segment, a second connecting segment, and a fourth segment connected in sequence, the third segment and the fourth segment being located in the display area and both extending along a second direction, and the second connecting segment being located in the transition area; the first direction intersects the second direction;

[0010] During a portion of the driving period of a frame, the first signal line receives the first driving signal while the second signal line receives the second driving signal.

[0011] Optionally, the first signal line includes a data signal line; the second signal line includes a light emission control signal line.

[0012] Optionally, the display substrate includes a substrate, a first source / drain metal layer located on one side of the substrate, and a second source / drain metal layer located on the side of the first source / drain metal layer away from the substrate; the first source / drain metal layer and the second source / drain metal layer are insulated from each other;

[0013] In some of the first signal lines, the first segment and the second segment are located in the first source-drain metal layer, and the first connection segment is located in the second source-drain metal layer; or, in some of the first signal lines, the first segment and the second segment are located in the second source-drain metal layer, and the first connection segment is located in the first source-drain metal layer.

[0014] The second signal line is disposed between the substrate and the first source / drain metal layer.

[0015] Optionally, the first signal line includes a data signal line; the second signal line includes a light emission control signal line; two adjacent data signal lines control the same column of pixels, wherein one data signal line is connected to pixels located in odd-numbered rows, and the other data signal line is connected to pixels located in even-numbered rows;

[0016] For all data signal lines, at least partially connected to pixels in odd-numbered rows, the first segment and the second segment of the data signal line are located in the first source-drain metal layer, and the first connecting segment is located in the second source-drain metal layer; for all data signal lines, at least partially connected to pixels in even-numbered rows, the first segment and the second segment are located in the second source-drain metal layer, and the first connecting segment is located in the first source-drain metal layer; or

[0017] The first and second segments of all data signal lines that are at least partially connected to odd-numbered rows of pixels are located in the second source-drain metal layer, and the first connecting segment is located in the first source-drain metal layer; the first and second segments of all data signal lines that are at least partially connected to even-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting segment is located in the second source-drain metal layer.

[0018] Optionally, for all the data signal lines, the first and second segments of the data signal lines connected to the odd-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting segment is located in the second source-drain metal layer; for the data signal lines connected to the even-numbered rows of pixels, the first and second segments are located in the second source-drain metal layer, and the first connecting segment is located in the first source-drain metal layer; or

[0019] The first and second segments of the data signal lines connected to the odd-numbered rows of pixels are located in the second source-drain metal layer, and the first connecting segment is located in the first source-drain metal layer; the first and second segments of the data signal lines connected to the even-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting segment is located in the second source-drain metal layer.

[0020] Optionally, the data signal lines of the display substrate are divided into multiple data signal line groups, each data signal line group including eight data signal lines. The same data signal line group includes data signal lines 8k-7 to 8k, which are arranged sequentially along a second direction within the display area. In the same data signal line group, data signal lines 8k-7 and 8k-6 are connected to the same column of pixels, data signal lines 8k-5 and 8k-4 are connected to the same column of pixels, data signal lines 8k-3 and 8k-2 are connected to the same column of pixels, and data signal lines 8k-1 and 8k are connected to the same column of pixels. Data signal lines 8k-7, 8k-5, 8k-2, and 8k are connected to pixels in odd-numbered rows, and data signal lines 8k-6, 8k-4, 8k-3, and 8k-1 are connected to pixels in even-numbered rows.

[0021] Within the display area, the first and second segments of the data signal lines 8k-7, 8k-5, 8k-3, and 8k-1 are disposed on the first source-drain metal layer; the first and second segments of the data signal lines 8k-6, 8k-4, 8k-2, and 8k are disposed on the second source-drain metal layer.

[0022] Within the transition region, the first connection segments of the data signal lines 8k-7, 8k-5, 8k-2, and 8k are disposed on the first source-drain metal layer, and the first connection segments of the data signal lines 8k-6, 8k-4, 8k-3, and 8k-1 are disposed on the second source-drain metal layer; k is an integer greater than 0.

[0023] Optionally, the display substrate further includes:

[0024] A source drive circuit, wherein the source drive circuit includes a plurality of source drive transistors;

[0025] Multiple source signal lines are divided into multiple source signal line groups. Each source signal line group includes a first source signal line and a second source signal line. In the same data signal line group, four adjacent data signal lines are connected to the first source signal line, and another four adjacent data signal lines are connected to the second source signal line. The first source signal line and the second source signal line connected to the data line of the same data signal line group belong to the same source signal line group. Each data signal line is connected to the source signal line through a source driving transistor.

[0026] First multiplexed signal lines to fourth multiplexed signal lines; in the same group of data signal lines, the source driving transistors corresponding to the four data signal lines connected to the first source signal line are respectively connected to one of the first multiplexed signal lines to the fourth multiplexed signal line, and the gates of the source driving transistors corresponding to different data signal lines are connected to different multiplexed signal lines; the gates of the source driving transistors corresponding to the four data signal lines connected to the second source signal line are respectively connected to one of the first multiplexed signal lines to the fourth multiplexed signal line, and the source driving transistors corresponding to different data signal lines are connected to different multiplexed signal lines.

[0027] Optionally, in the same data signal line group, the 8k-7 data signal line is connected to the first source signal line under the control of the first multiplexed signal line; the 8k-6 data signal line is connected to the first source signal line under the control of the third multiplexed signal line; the 8k-5 data signal line is connected to the first source signal line under the control of the second multiplexed signal line; and the 8k-4 data signal line is connected to the first source signal line under the control of the fourth multiplexed signal line.

[0028] The 8k-3 data signal line is connected to the second source signal line under the control of the third multiplexed signal line; the 8k-2 data signal line is connected to the second source signal line under the control of the first multiplexed signal line; the 8k-1 data signal line is connected to the second source signal line under the control of the fourth multiplexed signal line; and the 8k data signal line is selectively connected to the second source signal line under the control of the second multiplexed signal line.

[0029] Optionally, within the transition zone, the first connecting segment disposed on the first source / drain metal layer and the first connecting segment disposed on the second source / drain metal layer have no overlapping regions on the substrate by their orthogonal projections.

[0030] Optionally, within the transition zone, the first connecting segment disposed on the first source / drain metal layer and the first connecting segment disposed on the second source / drain metal layer at least partially overlap on the substrate.

[0031] Optionally, the display substrate further includes a second conductive layer located between the substrate and the first source / drain metal layer;

[0032] The display substrate further includes a plurality of scan signal lines; some of the scan signal lines include a fifth segment, a third connecting segment, and a sixth segment connected in sequence, the fifth segment and the sixth segment are located in the display area and both extend along the second direction, and the third connecting segment is located in the transition area; the scan signal lines are disposed on the second conductive layer;

[0033] Within the transition zone, there is no overlap between the orthographic projections of the third connecting segments and the first connecting segments disposed on the first source / drain metal layer on the substrate.

[0034] Optionally, the display substrate further includes a first conductive layer located on the side of the substrate near the first source / drain metal layer and a second conductive layer located on the side of the first conductive layer near the first source / drain metal layer.

[0035] The light emission control signal line is disposed on the first conductive layer; within the transition region, the second connection segment and the orthographic projection of the first connection segment disposed on the first source / drain metal layer onto the substrate at least partially overlap.

[0036] Optionally, the display substrate further includes a first conductive layer located on the side of the substrate near the first source / drain metal layer and a second conductive layer located on the side of the first conductive layer near the first source / drain metal layer.

[0037] Some of the light-emitting control signal lines are disposed in the first conductive layer; some of the light-emitting control signal lines are disposed in the second conductive layer;

[0038] Within the transition zone, the second connecting segment disposed on the first conductive layer at least partially overlaps with the orthographic projection of the first connecting segment on the substrate; there is no overlap between the second connecting segment disposed on the second conductive layer and the orthographic projection of the first connecting segment on the substrate.

[0039] Optionally, the display substrate further includes a first conductive layer located on the side of the substrate near the first source / drain metal layer and a second conductive layer located on the side of the first conductive layer near the first source / drain metal layer.

[0040] The display substrate further includes a plurality of scanning signal lines; some of the scanning signal lines include a fifth segment, a third connecting segment and a sixth segment connected in sequence, the fifth segment and the sixth segment are located in the display area and both extend along the second direction, and the third connecting segment is located in the transition area;

[0041] Some of the scan signal lines are disposed in the first conductive layer; some of the scan signal lines are disposed in the second conductive layer;

[0042] Within the transition region, the third connecting segment disposed on the first conductive layer at least partially overlaps with the orthographic projection of the first connecting segment onto the substrate; the third connecting segment disposed on the second conductive layer has no overlapping area with the orthographic projection of the first connecting segment onto the substrate.

[0043] This application also provides a display device, which includes the display substrate described above.

[0044] Compared with related technologies, this application improves the display effect of the display panel by setting the first signal line on different film layers in the display area and the transition area, thereby controlling the interference of the second signal line on the first signal line.

[0045] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0047] Figure 1 is a planar schematic diagram of the display substrate of this application.

[0048] Figure 2 is a schematic diagram of the layer hierarchy of the display substrate of this application.

[0049] Figure 3 is a timing diagram of the operation of the display substrate of this application.

[0050] Figure 4 is a schematic diagram of partial circuit connections of the display substrate of this application.

[0051] Figure 5 is a schematic diagram of a cross section along line AA in Figure 1 in the related technology.

[0052] Figure 6 is a schematic diagram of a cross section along line AA in Figure 1 in the related technology.

[0053] Figure 7 is a schematic diagram of the circuit at the junction of the second section and the first connecting section of the display substrate in one embodiment of this application.

[0054] Figure 8 is a schematic diagram of the circuit at the junction of the first section and the first connecting section of the display substrate in one embodiment of this application.

[0055] Figure 9 is a cross-sectional schematic diagram along line AA in Figure 1 in one embodiment of this application.

[0056] Figure 10 is a cross-sectional schematic diagram along line AA in Figure 1 in one embodiment of this application.

[0057] Figure 11 is a cross-sectional schematic diagram along line AA in Figure 1 in one embodiment of this application.

[0058] Figure 12 is a cross-sectional schematic diagram along line AA in Figure 1 in one embodiment of this application. Detailed Implementation

[0059] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0060] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movements between components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0061] As shown in Figure 1, a display substrate typically includes a display area 1000 and a bezel area 4000. Some display substrates have holes punched within the display area 1000 to form hole areas 3000. These hole areas 3000 can be used to house front-facing cameras or other sensors. The display panel also includes a transition area 2000 located between the display area 1000 and the hole areas. The traces on the display substrate are located within the transition area 2000 surrounding the hole areas 3000 to avoid them.

[0062] As shown in Figure 2, the display substrate may include a substrate 10, an active layer 11 located on the side of the substrate 10 near the display side, a first gate insulating layer 12 located on the side of the active layer 11 away from the substrate 10, a first conductive layer 20 (GT1) located on the side of the first gate insulating layer 12 away from the active layer 11, a second gate insulating layer 21 located on the side of the first conductive layer 20 away from the first gate insulating layer 12, a second conductive layer 30 (GT2) located on the side of the second gate insulating layer 21 away from the first conductive layer 20, and interlayer insulation located on the side of the second conductive layer 30 away from the second gate insulating layer 21. The system comprises: layer 31; a first source / drain metal layer 40 (SD1) located on the side of interlayer insulating layer 31 away from the second conductive layer 30; a passivation layer 41 located on the side of the first source / drain metal layer 40 away from the interlayer insulating layer 31; a first planarization layer 42 located on the side of the passivation layer 41 away from the first source / drain metal layer 40; a second source / drain metal layer 50 (SD2) located on the side of the first planarization layer 42 away from the passivation layer 41; a second planarization layer 51 located on the side of the second source / drain metal layer 50 away from the first planarization layer 42; a light-emitting device located on the side of the second planarization layer 51 away from the second source / drain metal layer 50; and a packaging structure 60. The third direction F3 can be the thickness direction of the display substrate.

[0063] As shown in Figures 1 and 2, the display substrate includes a plurality of first signal lines 100 extending along a first direction F1. Some of the first signal lines 100 include a first segment 110, a first connecting segment 120, and a second segment 130 connected in sequence. The first segment 110 and the second segment 130 are both located in the display area 1000 and both extend along the first direction F1. The first connecting segment 120 is located in the transition area 2000 and is disposed around the hole area 3000, and its shape matches the shape of a portion of the edge of the hole area 3000.

[0064] The display substrate also includes a plurality of second signal lines 200 extending along the second direction F2. Some of the second signal lines 200 include a third segment 210, a second connecting segment 220 and a fourth segment 230 connected in sequence. The third segment 210 and the fourth segment 230 are both located in the display area 1000 and both extend along the second direction F2. The second connecting segment 220 is located in the transition area 2000 and is disposed around the hole area 3000, and its shape matches the shape of a portion of the edge of the hole area 3000.

[0065] Optionally, the display substrate also includes a plurality of scan signal lines 300 extending along the second direction F2. Some of the scan signal lines 300 include a fifth segment 310, a third connecting segment 320 and a sixth segment 330 connected in sequence. The fifth segment 310 and the sixth segment 330 are both located in the display area 1000 and both extend along the second direction F2. The third connecting segment 320 is located in the transition area 2000 and is disposed around the hole area 3000.

[0066] The first direction F1 intersects with the second direction F2. The first direction F1 can be the length direction of the display substrate, and the second direction can be the width direction of the display substrate.

[0067] In one embodiment, the first signal line 100 can be a data signal line, and the second signal line 200 can be a light emission control signal line. The first signal line 100 can be disposed on the first source / drain metal layer 40 and the second source / drain metal layer 50. The second signal line 200 can be disposed on the first conductive layer 20 and / or the second conductive layer 30. The scan signal line 300 can be disposed on the first conductive layer 20 and / or the second conductive layer 30.

[0068] Figure 3 shows the timing diagram of the data signal Data, the light emission control signal EM, and the gate drive signal GT of the display substrate. The data signal Data is transmitted via the data signal line, the light emission control signal EM is transmitted via the light emission control signal line, and the gate drive signal GT is transmitted via the scan signal line 300. In the pixel driving circuit, the gate drive signal GT is used to control whether the data signal Data is written to the control electrode of the driving transistor, the data signal Data is used to control the conduction of the driving transistor, and the light emission control signal EM is used to control the conduction between the power supply and the light-emitting element.

[0069] In the transition zone 2000, both the first connecting segment 120 and the second connecting segment 220 are positioned around the aperture region 3000. The first connecting segment 120 and the second connecting segment 220 partially overlap on the third direction F3, resulting in parasitic capacitance between the first signal line 100 and the second signal line 200. Specifically, when the first signal line 100 is a data signal line and the second signal line 200 is a light emission control signal line, the light emission control signal EM will experience potential changes during periods ①, ②, ③, ④, ⑤, and ⑥. At this time, the light emission control signal EM will interfere with the data signals on some data signal lines, causing fluctuations in some data signals. Specifically, as shown in Figure 3 from Dataj-1 to Dataj+2, the solid lines in the figure represent the original timing sequence, and the dashed lines represent the timing sequence after interference. The interfered data signal Data, after being written to the control electrode of the driving transistor, will cause abnormalities in the display substrate's image.

[0070] During periods ①, ②, and ③, the gate drive signal GT of display area 1000 controls the data signal Data, which is not written to the control electrode of the driving transistor. However, the gate drive signal GT of transition area 2000 controls the data signal Data, which is written to the control electrode of the driving transistor. When there are no pixels in transition area 2000, the interfered data signal Data during periods ①, ②, and ③ will not cause abnormalities in the display substrate's image. During periods ④, ⑤, and ⑥, the gate drive signal GT of display area 1000 controls the data signal Data, which is written to the control electrode of the driving transistor. Therefore, the interfered data signal Data during periods ④, ⑤, and ⑥ will cause abnormalities in the display substrate's image.

[0071] As shown in Figure 4, the data signal lines of the display substrate are divided into multiple data signal line groups. Each data signal line group includes eight data signal lines. The same data signal line group includes data signal lines 8k-7 to 8k, which are arranged sequentially along the second direction F2 within the display area. Within the same data signal line group, data signal lines 8k-7 and 8k-6 are connected to the same column of pixels; data signal lines 8k-5 and 8k-4 are connected to the same column of pixels; data signal lines 8k-3 and 8k-2 are connected to the same column of pixels; and data signal lines 8k-1 and 8k are connected to the same column of pixels. Data signal lines 8k-7, 8k-5, 8k-2, and 8k are connected to pixels in odd-numbered rows, while data signal lines 8k-6, 8k-4, 8k-3, and 8k-1 are connected to pixels in even-numbered rows, where k is an integer greater than 0.

[0072] The display substrate also includes multiple source signal lines, divided into multiple source signal line groups. Each source signal line group includes a first source signal line and a second source signal line. In the same data signal line group, four adjacent data signal lines are connected to the first source signal line, and another four adjacent data signal lines are connected to the second source signal line. The first and second source signal lines connected to the data line numbers of the same data signal line group belong to the same source signal line group. Each data signal line is connected to the source signal line through a source drive transistor.

[0073] The display substrate also includes first multiplexed signal lines MUX1 to fourth multiplexed signal lines MUX4. In the same group of data signal lines, the source driving transistors corresponding to the four data signal lines connected to the first source signal line are respectively connected to one of the first multiplexed signal lines MUX1 to fourth multiplexed signal lines MUX4, and the gates of the source driving transistors corresponding to different data signal lines are connected to different multiplexed signal lines. Similarly, the gates of the source driving transistors corresponding to the four data signal lines connected to the second source signal line are respectively connected to one of the first multiplexed signal lines MUX1 to fourth multiplexed signal lines MUX4, and the source driving transistors corresponding to different data signal lines are connected to different multiplexed signal lines.

[0074] In the same data signal line group, data signal line 8k-7 is connected to the first source signal line under the control of the first multiplexed signal line MUX1. Data signal line 8k-6 is connected to the first source signal line under the control of the third multiplexed signal line MUX3. Data signal line 8k-5 is connected to the first source signal line under the control of the second multiplexed signal line MUX2. Data signal line 8k-4 is connected to the first source signal line under the control of the fourth multiplexed signal line MUX4.

[0075] Data signal line 8k-3 is connected to the second source signal line under the control of the third multiplexed signal line MUX3. Data signal line 8k-2 is connected to the second source signal line under the control of the first multiplexed signal line MUX1. Data signal line 8k-1 is connected to the second source signal line under the control of the fourth multiplexed signal line MUX4. Data signal line 8k is selectively connected to the second source signal line under the control of the second multiplexed signal line MUX2.

[0076] Specifically, as shown in Figure 4, the multiplexed signal line MUX is connected to the control terminal of the source drive transistor, the source signal line is connected to the first terminal of the source drive transistor, and the data signal line is connected to the second terminal of the source drive transistor. One source signal line is connected to the first terminal of each of the four source drive transistors, the control terminals of the four source drive transistors are connected to MUX1, MUX2, MUX3, and MUX4 respectively, and the second terminals of the four source drive transistors are connected to four different data signal lines. For example, one set of data signal lines includes D1 to D8, one set of source signal lines includes S1 and S2, and the multiplexed signal line MUX includes the first multiplexed signal line MUX1 to the fourth multiplexed signal line MUX4.

[0077] The source signal line S1 is connected to the data signal lines D1 to D4 respectively through four source drive transistors. The gates of the four source drive transistors are connected to MUX1, MUX3, MUX2 and MUX4 in sequence. That is, MUX1 controls the conduction of the source signal line S1 and the data signal line D1, MUX3 controls the conduction of the source signal line S1 and the data signal line D2, MUX2 controls the conduction of the source signal line S1 and the data signal line D3, and MUX4 controls the conduction of the source signal line S1 and the data signal line D4. The source signal line S2 is connected to the data signal lines D5 to D8 via four source drive transistors. The gates of these four source drive transistors are connected sequentially to MUX3, MUX1, MUX4, and MUX2. Specifically, MUX3 controls the conduction of source signal line S2 and data signal line D5; MUX1 controls the conduction of source signal line S2 and data signal line D6; MUX4 controls the conduction of source signal line S2 and data signal line D7; and MUX2 controls the conduction of source signal line S2 and data signal line D8. Subsequent source signal lines, data signal lines, and multiplexed signal lines are connected in the same manner. Specifically, D1 and D2 are connected to the first column of pixels; D3 and D4 are connected to the second column of pixels; D5 and D6 are connected to the third column of pixels; and D7 and D8 are connected to the fourth column of pixels. D1, D3, D6, and D8 are connected to pixels in odd-numbered rows, and D2, D4, D5, and D7 are connected to pixels in even-numbered rows.

[0078] As shown in Figure 5, which is a cross-sectional view along line AA in Figure 1, in related technologies, the first segment, the first connecting segment, and the second segment of the data signal line are located in the same film layer. The specific connection method of the signal line is the same as described above and will not be repeated here. In a set of data signal lines, data signal lines 8k-7, 8k-5, 8k-3, and 8k-1 are located in the first source / drain metal layer SD1, and data signal lines 8k-6, 8k-4, 8k-2, and 8k are located in the second source / drain metal layer SD2. The data signal lines are arranged in ascending order of their serial numbers, and the orthogonal projections of the data signal lines in the first source / drain metal layer SD1 and the second source / drain metal layer SD2 onto the substrate do not overlap. The numbers on the data signal lines in Figure 5 indicate which multiplexed signal line (MUX) controls their conduction. For example, number 1 indicates that it is connected to the source signal line through the first multiplexed signal line MUX1, and number 3 indicates that it is connected to the source signal line through the third multiplexed signal line MUX3. The first conductive layer GT1 and the second conductive layer GT2 are sequentially provided with scan signal lines and light emission control signal lines, wherein one light emission control signal line is provided for every three signal lines, and the remaining positions are for scan signal lines. The orthographic projections of the signal lines in the first conductive layer GT1 and the second conductive layer GT2 onto the substrate do not overlap. Similarly, the orthographic projections of the signal lines in the first conductive layer GT1 and the second source / drain metal layer SD2 onto the substrate do not overlap.

[0079] Table 1

[0080] The following explanation of Figure 5 is based on Table 1. The Data routing layer row in the table indicates the layer in which the data signal line is located. MUX indicates which multiplexed signal line controls the data signal line. For example, in the second column, MUX is 1, and the Data routing layer is SD1, indicating that the data signal line controlled by the first multiplexed signal line is located in the first source-drain metal layer SD1. The GOA signal routing layer row in the table indicates the layer in which the scan signal line and the light emission control signal line are located. The GOA signal row indicates whether the location is a scan signal line or a light emission control signal line. For example, in the second column, the GOA signal routing layer is GT1, and the GOA signal is Scan, indicating that this is a scan signal line located in the first conductive layer GT1.

[0081] The luminescence control signal EM on the luminescence control signal line interferes with the data signals on the data signal lines located close to it on the first source-drain metal layer SD1. Due to the shielding effect of the first source-drain metal layer SD1, the luminescence control signal EM on the luminescence control signal line does not interfere with the data signal lines located on the second source-drain metal layer SD2. Referring to Figure 5 and Table 1, it can be seen that the luminescence control signal EM interferes with the data signals on the data signal lines controlled by MUX1, MUX2, MUX3, and MUX4. This means that display abnormalities will appear unevenly in the odd-numbered and even-numbered rows of pixels, resulting in severe X-shaped mura (uniformity) defects in the areas where display abnormalities are stacked.

[0082] As shown in Figure 6, which is a cross-sectional view along line AA in Figure 1, in related technologies, the first segment, the first connecting segment, and the second segment of the data signal line are located in the same film layer. The specific connection method of the signal line is the same as described above and will not be repeated here. The arrangement of the data signal line and the meaning of the numbers in the figure are the same as in the above embodiments and will not be repeated here. The first conductive layer GT1 is sequentially provided with scan signal lines and light emission control signal lines, wherein one light emission control signal line is provided for every three signal lines, and the remaining positions are scan signal lines. The orthogonal projections of the signal lines of the first conductive layer GT1 and the signal lines of the first source / drain metal layer SD1 on the substrate do not overlap.

[0083] Table 2

[0084] As shown in Figure 6 and Table 2, the luminous emission control signal EM interferes with the data signals on the control data signal lines of MUX1, MUX2, MUX3, and MUX4. This means that display abnormalities will appear unevenly in the odd-numbered and even-numbered rows of pixels, resulting in severe X-shaped mura (uniformity) defects in the areas where display abnormalities are stacked.

[0085] As shown in Figures 7 to 9, the interference between the first signal line 100 and the second signal line 200 is related to the distance between the two lines. This application addresses this by placing the first signal line 100 in different film layers in the display area 1000 and the transition area 2000, thereby controlling the distance between the first signal line 100 and the second signal line 200 in the transition area 2000, and thus controlling the interference of the second signal line 200 on the first signal line 100, thereby improving the display effect of the display panel. Specifically, in this application, the first segment 110 and the second segment 130 of the first signal line 100 are located in the same film layer, while the first connecting segment 120 is located in a different film layer than the first segment 110 and the second segment 130. Optionally, the first segment 110 and the second segment 130 can be located in the first source / drain metal layer SD1, and the first connecting segment 120 can be located in the second source / drain metal layer SD2. Alternatively, the first segment 110 and the second segment 130 can be located in the second source-drain metal layer SD2, and the first connection segment 120 can be located in the first source-drain metal layer SD1. Specifically, taking the first signal line 100 as a data signal line as an example.

[0086] The first segment 110 and the second segment 130 of all data signal lines that are at least partially connected to odd-numbered rows of pixels are located in the first source-drain metal layer SD1, and the first connecting segment 120 is located in the second source-drain metal layer SD2. The first segment 110 and the second segment 130 of all data signal lines that are at least partially connected to even-numbered rows of pixels are located in the second source-drain metal layer SD2, and the first connecting segment 120 is located in the first source-drain metal layer SD1. Alternatively, the first segment 110 and the second segment 130 of all data signal lines that are at least partially connected to odd-numbered rows of pixels are located in the second source-drain metal layer SD2, and the first connecting segment 120 is located in the first source-drain metal layer SD1. The first segment 110 and the second segment 130 of all data signal lines that are at least partially connected to even-numbered rows of pixels are located in the first source-drain metal layer SD1, and the first connecting segment 120 is located in the second source-drain metal layer SD2. At least some of the data signal lines may be data signal lines that pass through the transition region 2000.

[0087] As shown in Figures 7 to 9, Figure 7 is a schematic diagram of the data signal line at the junction of the second segment 130 and the first connecting segment 120. Figure 8 is a schematic diagram of the data signal line at the junction of the second segment 110 and the first connecting segment 120. Figure 9 is a cross-sectional schematic diagram along line AA in Figure 1.

[0088] In a set of data signal lines, within the display area 1000, the first segment 110 and the second segment 130 of data signal lines 8k-7, 8k-5, 8k-3, and 8k-1 are disposed on the first source-drain metal layer SD1. The first segment 110 and the second segment 130 of data signal lines 8k-6, 8k-4, 8k-2, and 8k are disposed on the second source-drain metal layer SD2. Within the transition area 2000, the first connecting segment 120 of data signal lines 8k-7, 8k-5, 8k-2, and 8k are disposed on the first source-drain metal layer SD1, and the first connecting segment 120 of data signal lines 8k-6, 8k-4, 8k-3, and 8k-1 are disposed on the second source-drain metal layer SD2. The data signal lines controlled by the third multiplexed signal line MUX3 and the fourth multiplexed signal line MUX4 are disposed in the transition region 2000 on the second source-drain metal layer SD2, and the data signal lines controlled by the first multiplexed signal line MUX1 and the second multiplexed signal line MUX2 are disposed in the transition region 2000 on the second source-drain metal layer SD2. Thus, within the transition region 2000, only the data signal lines controlled by the first multiplexed signal line MUX1 and the second multiplexed signal line MUX2 will be interfered with; that is, only the pixels in the odd-numbered rows will be interfered with. Display abnormalities will appear evenly in the odd-numbered rows, thus preventing display abnormalities from stacking in a certain area and avoiding severe X-shaped Mura (non-uniformity) defects on the display substrate.

[0089] As shown in Figures 7, 8, and 9, Figure 9 is a cross-sectional view along line AA in Figure 1. In an optional embodiment, the connection method of a set of data signal lines, source signal lines, and multiplexed signal lines is the same as in the above embodiment, and will not be described in detail here. Within the display area 1000, the first segment 110 and the second segment 130 of the 8k-7, 8k-5, 8k-3, and 8k-1 data signal lines are sequentially disposed on the first source-drain metal layer SD1. The first segment 110 and the second segment 130 of the 8k-6, 8k-4, 8k-2, and 8k data signal lines are sequentially disposed on the second source-drain metal layer SD2. Within the transition zone 2000, the first connection segments 120 of the 8k-7, 8k-5, 8k-2, and 8k data signal lines are sequentially disposed on the first source-drain metal layer SD1, and the first connection segments 120 of the 8k-6, 8k-4, 8k-3, and 8k-1 data signal lines are sequentially disposed on the second source-drain metal layer SD2.

[0090] The data signal lines in the first source / drain metal layer SD1 and the second source / drain metal layer SD2 are arranged alternately, that is, the orthogonal projections of the data signal lines in the first source / drain metal layer SD1 and the data signal lines in the second source / drain metal layer SD2 on the substrate have no overlapping area, and the orthogonal projection of the data signal lines in the first source / drain metal layer SD1 on the substrate falls between the orthogonal projections of the two data signal lines in the second source / drain metal layer SD2 on the substrate.

[0091] The first conductive layer GT1 and the second conductive layer GT2 are respectively provided with a light emission control signal line and a scan signal line. The orthographic projection of the light emission control signal line in the first conductive layer GT1 onto the substrate has no overlapping area with the orthographic projection of the data signal line in the second source / drain metal layer SD2 onto the substrate, and at least partially overlaps with the orthographic projection of the data signal line in the first source / drain metal layer SD1 onto the substrate. The orthographic projection of the scan signal line in the second conductive layer GT2 onto the substrate has no overlapping area with the orthographic projection of the data signal line in the first source / drain metal layer SD1 onto the substrate, and at least partially overlaps with the orthographic projection of the data signal line in the second source / drain metal layer SD2 onto the substrate.

[0092] Table 3

[0093] As shown in Figure 9 and Table 3, the light emission control signal EM only interferes with the data signals on the data signal lines controlled by MUX1 and MUX2. That is, only the pixels in the odd-numbered rows will be interfered with, and the display abnormalities will appear evenly in the odd-numbered rows. Thus, the display abnormalities will not be stacked in a certain area, and the display substrate will not produce severe X-shaped Mura (non-uniformity) defects.

[0094] As shown in Figures 7, 8, and 10, Figure 10 is a cross-sectional view along line AA in Figure 1. In an optional embodiment, the connection method of a set of data signal lines, source signal lines, and multiplexed signal lines is the same as in the above embodiment, and will not be described in detail here. Within the display area 1000, the first segment 110 and the second segment 130 of the 8k-7, 8k-5, 8k-3, and 8k-1 data signal lines are sequentially disposed on the first source-drain metal layer SD1. The first segment 110 and the second segment 130 of the 8k-6, 8k-4, 8k-2, and 8k data signal lines are sequentially disposed on the second source-drain metal layer SD2. Within the transition zone 2000, the first connection segments 120 of the 8k-7, 8k-5, 8k-2, and 8k data signal lines are sequentially disposed on the first source-drain metal layer SD1, and the first connection segments 120 of the 8k-6, 8k-4, 8k-3, and 8k-1 data signal lines are sequentially disposed on the second source-drain metal layer SD2.

[0095] The data signal lines in the first source-drain metal layer SD1 and the second source-drain metal layer SD2 are stacked, that is, the orthogonal projections of the data signal lines in the first source-drain metal layer SD1 and the data signal lines in the second source-drain metal layer SD2 on the substrate at least partially overlap.

[0096] The first conductive layer GT1 and the second conductive layer GT2 are sequentially provided with scan signal lines and light emission control signal lines, wherein one light emission control signal line is provided for every three signal lines, and the remaining positions are for scan signal lines. The orthographic projections of the signal lines in the first conductive layer GT1 and the second conductive layer GT2 onto the substrate have no overlapping area. The orthographic projections of the signal lines in the first conductive layer GT1, the first source / drain metal layer SD1, and the second source / drain metal layer SD2 onto the substrate at least partially overlap. The orthographic projections of the signal lines in the second conductive layer GT2, the first source / drain metal layer SD1, and the second source / drain metal layer SD2 onto the substrate have no overlapping area.

[0097] Table 4

[0098] As shown in Figure 10 and Table 4, the light emission control signal EM only interferes with the data signals on the data signal lines controlled by MUX1 and MUX2. That is, only the pixels in the odd-numbered rows will be interfered with, and the display abnormalities will appear evenly in the odd-numbered rows. Thus, the display abnormalities will not be stacked in a certain area, and the display substrate will not produce severe X-shaped Mura (non-uniformity) defects.

[0099] As shown in Figures 7, 8, and 11, Figure 11 is a cross-sectional view along line AA in Figure 1. In an optional embodiment, the connection method of a set of data signal lines, source signal lines, and multiplexed signal lines is the same as in the above embodiments, and will not be described in detail here. The arrangement of data signal lines in this embodiment is the same as that in the embodiment corresponding to Figure 10, and will not be described in detail here either.

[0100] In this embodiment, the first conductive layer GT1 and the second conductive layer GT2 are respectively provided with light emission control signal lines and scanning signal lines. The orthographic projection of the light emission control signal lines in the first conductive layer GT1 onto the substrate at least partially overlaps with the orthographic projections of the data signal lines in the first source / drain metal layer SD1 and the second source / drain metal layer SD2 onto the substrate. The orthographic projection of the light emission control signal lines in the second conductive layer GT2 onto the substrate has no overlap with the orthographic projections of the data signal lines in the first source / drain metal layer SD1 and the second source / drain metal layer SD2 onto the substrate.

[0101] Table 5

[0102] As shown in Figure 11 and Table 5, the light emission control signal EM only interferes with the data signals on the data signal lines controlled by MUX1 and MUX2. That is, only the pixels in the odd-numbered rows will be interfered with, and the display abnormalities will appear evenly in the odd-numbered rows. Thus, the display abnormalities will not be stacked in a certain area, and the display substrate will not produce severe X-shaped Mura (non-uniformity) defects.

[0103] As shown in Figures 7 and 8 (i.e., Figure 12), Figure 12 is a cross-sectional view along line AA in Figure 1. In an optional embodiment, the connection method of a set of data signal lines, source signal lines, and multiplexed signal lines is the same as in the above embodiments, and will not be described in detail here. The arrangement of the data signal lines in this embodiment is the same as that in the embodiment corresponding to Figure 11, and will not be described in detail here either. The light emission control signal line in this embodiment is located at the position of the scan signal line in the embodiment corresponding to Figure 11, and the scan signal line in this embodiment is located at the position of the light emission control signal line in the embodiment corresponding to Figure 11.

[0104] Table 6

[0105] As shown in Figure 12 and Table 6, the light emission control signal EM only interferes with the data signals on the data signal lines controlled by MUX1 and MUX2. That is, only the pixels in the odd-numbered rows will be interfered with, and the display abnormalities will appear evenly in the odd-numbered rows. Thus, the display abnormalities will not be stacked in a certain area, and the display substrate will not produce severe X-shaped Mura (non-uniformity) defects.

[0106] In an optional embodiment, the positions of the data signal lines of the first source / drain metal layer SD1 and the second source / drain metal layer SD2 in the embodiments shown in Figures 9-12 can be interchanged. In this way, the light emission control signal EM will only interfere with the data signals on the data signal lines controlled by MUX3 and MUX4. That is, only pixels in even-numbered rows will be interfered with, and display abnormalities will appear evenly in even-numbered rows. Thus, display abnormalities will not accumulate in a certain area, and the display substrate will not produce severe X-shaped Mura (non-uniformity) defects.

[0107] This application also provides a display device, which includes the display substrate described above.

[0108] In one embodiment, the display device further includes a housing, and the display panel is disposed within the housing.

[0109] The display device provided in this application embodiment can be any device with display function, such as a mobile phone, tablet computer, television, laptop computer, or vehicle-mounted equipment.

[0110] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display substrate, characterized in that, The display substrate includes a display area, a transition area, and a hole area, wherein the transition area surrounds the hole area, and the display area surrounds the transition area; The display substrate includes: Base; A plurality of first signal lines are located on one side of the substrate; some of the first signal lines include a first segment, a first connecting segment and a second segment connected in sequence, the first segment and the second segment are located in the display area and both extend along a first direction, and the first connecting segment is located in the transition area; some of the first signal lines have the first segment and the first connecting segment located in different film layers, and the first segment and the second segment located in the same film layer; Multiple second signal lines are located on the same side of the substrate as the first signal line; some of the second signal lines include a third segment, a second connecting segment, and a fourth segment connected in sequence, the third segment and the fourth segment being located in the display area and both extending along a second direction, and the second connecting segment being located in the transition area; the first direction intersects the second direction; During a portion of the driving period of a frame, the first signal line receives the first driving signal while the second signal line receives the second driving signal.

2. The display substrate according to claim 1, characterized in that, The first signal line includes a data signal line; the second signal line includes a light emission control signal line.

3. The display substrate according to claim 1, characterized in that, The display substrate includes a substrate, a first source / drain metal layer located on one side of the substrate, and a second source / drain metal layer located on the side of the first source / drain metal layer away from the substrate; the first source / drain metal layer and the second source / drain metal layer are insulated from each other; In some of the first signal lines, the first segment and the second segment are located in the first source-drain metal layer, and the first connection segment is located in the second source-drain metal layer; or, in some of the first signal lines, the first segment and the second segment are located in the second source-drain metal layer, and the first connection segment is located in the first source-drain metal layer. The second signal line is disposed between the substrate and the first source / drain metal layer.

4. The display substrate according to claim 3, characterized in that, The first signal line includes a data signal line; the second signal line includes a light emission control signal line; two adjacent data signal lines control the same column of pixels, wherein one data signal line is connected to pixels located in odd-numbered rows, and the other data signal line is connected to pixels located in even-numbered rows; The first and second segments of all the data signal lines that are at least partially connected to the odd-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting segment is located in the second source-drain metal layer; the first and second segments of the data signal lines that are at least partially connected to the even-numbered rows of pixels are located in the second source-drain metal layer, and the first connecting segment is located in the first source-drain metal layer. or The first and second segments of all data signal lines that are at least partially connected to odd-numbered rows of pixels are located in the second source-drain metal layer, and the first connecting segment is located in the first source-drain metal layer; the first and second segments of all data signal lines that are at least partially connected to even-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting segment is located in the second source-drain metal layer.

5. The display substrate according to claim 4, characterized in that, The first and second segments of the data signal lines connected to the odd-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting segment is located in the second source-drain metal layer; the first and second segments of the data signal lines connected to the even-numbered rows of pixels are located in the second source-drain metal layer, and the first connecting segment is located in the first source-drain metal layer. or The first and second segments of the data signal lines connected to the odd-numbered rows of pixels are located in the second source-drain metal layer, and the first connecting segment is located in the first source-drain metal layer; the first and second segments of the data signal lines connected to the even-numbered rows of pixels are located in the first source-drain metal layer, and the first connecting segment is located in the second source-drain metal layer.

6. The display substrate according to claim 5, characterized in that, The data signal lines of the display substrate are divided into multiple data signal line groups. Each data signal line group includes eight data signal lines. The same data signal line group includes data signal lines 8k-7 to 8k, which are arranged sequentially along a second direction within the display area. In the same data signal line group, data signal lines 8k-7 and 8k-6 are connected to the same column of pixels, data signal lines 8k-5 and 8k-4 are connected to the same column of pixels, data signal lines 8k-3 and 8k-2 are connected to the same column of pixels, and data signal lines 8k-1 and 8k are connected to the same column of pixels. Data signal lines 8k-7, 8k-5, 8k-2, and 8k are connected to pixels in odd-numbered rows, while data signal lines 8k-6, 8k-4, 8k-3, and 8k-1 are connected to pixels in even-numbered rows. Within the display area, the first and second segments of the data signal lines 8k-7, 8k-5, 8k-3, and 8k-1 are disposed on the first source-drain metal layer; the first and second segments of the data signal lines 8k-6, 8k-4, 8k-2, and 8k are disposed on the second source-drain metal layer. Within the transition region, the first connection segments of the data signal lines 8k-7, 8k-5, 8k-2, and 8k are disposed on the first source-drain metal layer, and the first connection segments of the data signal lines 8k-6, 8k-4, 8k-3, and 8k-1 are disposed on the second source-drain metal layer; k is an integer greater than 0.

7. The display substrate according to claim 6, characterized in that, The display substrate further includes: A source drive circuit, wherein the source drive circuit includes a plurality of source drive transistors; Multiple source signal lines are divided into multiple source signal line groups. Each source signal line group includes a first source signal line and a second source signal line. In the same data signal line group, four adjacent data signal lines are connected to the first source signal line, and another four adjacent data signal lines are connected to the second source signal line. The first source signal line and the second source signal line connected to the data line of the same data signal line group belong to the same source signal line group. Each data signal line is connected to the source signal line through a source driving transistor. First multiplexed signal lines to fourth multiplexed signal lines; in the same group of data signal lines, the source driving transistors corresponding to the four data signal lines connected to the first source signal line are respectively connected to one of the first multiplexed signal lines to the fourth multiplexed signal line, and the gates of the source driving transistors corresponding to different data signal lines are connected to different multiplexed signal lines; the gates of the source driving transistors corresponding to the four data signal lines connected to the second source signal line are respectively connected to one of the first multiplexed signal lines to the fourth multiplexed signal line, and the source driving transistors corresponding to different data signal lines are connected to different multiplexed signal lines.

8. The display substrate according to claim 7, characterized in that, In the same data signal line group, the 8k-7 data signal line is connected to the first source signal line under the control of the first multiplexed signal line; the 8k-6 data signal line is connected to the first source signal line under the control of the third multiplexed signal line; the 8k-5 data signal line is connected to the first source signal line under the control of the second multiplexed signal line; and the 8k-4 data signal line is connected to the first source signal line under the control of the fourth multiplexed signal line. The 8k-3 data signal line is connected to the second source signal line under the control of the third multiplexed signal line; the 8k-2 data signal line is connected to the second source signal line under the control of the first multiplexed signal line; the 8k-1 data signal line is connected to the second source signal line under the control of the fourth multiplexed signal line; and the 8k data signal line is selectively connected to the second source signal line under the control of the second multiplexed signal line.

9. The display substrate according to claim 5, characterized in that, Within the transition zone, the orthographic projections of the first connecting segment disposed on the first source / drain metal layer and the first connecting segment disposed on the second source / drain metal layer on the substrate do not overlap.

10. The display substrate according to claim 5, characterized in that, Within the transition zone, the first connecting segment disposed on the first source / drain metal layer and the first connecting segment disposed on the second source / drain metal layer at least partially overlap on the substrate.

11. The display substrate according to claim 9 or 10, characterized in that, The display substrate further includes a second conductive layer located between the substrate and the first source / drain metal layer; The display substrate further includes a plurality of scan signal lines; some of the scan signal lines include a fifth segment, a third connecting segment, and a sixth segment connected in sequence, the fifth segment and the sixth segment are located in the display area and both extend along the second direction, and the third connecting segment is located in the transition area; the scan signal lines are disposed on the second conductive layer; Within the transition zone, there is no overlap between the orthographic projections of the third connecting segments and the first connecting segments disposed on the first source / drain metal layer on the substrate.

12. The display substrate according to claim 9 or 10, characterized in that, The display substrate further includes a first conductive layer located on the side of the substrate near the first source / drain metal layer and a second conductive layer located on the side of the first conductive layer near the first source / drain metal layer. The light emission control signal line is disposed on the first conductive layer; within the transition region, the second connection segment and the orthographic projection of the first connection segment disposed on the first source / drain metal layer onto the substrate at least partially overlap.

13. The display substrate according to claim 10, characterized in that, The display substrate further includes a first conductive layer located on the side of the substrate near the first source / drain metal layer and a second conductive layer located on the side of the first conductive layer near the first source / drain metal layer. Some of the light-emitting control signal lines are disposed in the first conductive layer; Some of the light-emitting control signal lines are disposed in the second conductive layer; Within the transition region, the second connecting segment disposed on the first conductive layer at least partially overlaps with the orthographic projection of the first connecting segment on the substrate; The second connecting segment disposed on the second conductive layer has no overlapping area with the orthographic projection of the first connecting segment on the substrate.

14. The display substrate according to claim 10, characterized in that, The display substrate further includes a first conductive layer located on the side of the substrate near the first source / drain metal layer and a second conductive layer located on the side of the first conductive layer near the first source / drain metal layer. The display substrate further includes a plurality of scanning signal lines; some of the scanning signal lines include a fifth segment, a third connecting segment and a sixth segment connected in sequence, the fifth segment and the sixth segment are located in the display area and both extend along the second direction, and the third connecting segment is located in the transition area; Some of the scan signal lines are disposed in the first conductive layer; some of the scan signal lines are disposed in the second conductive layer; Within the transition region, the third connecting segment disposed on the first conductive layer at least partially overlaps with the orthographic projection of the first connecting segment onto the substrate; The third connecting segment disposed on the second conductive layer has no overlapping area with the orthographic projection of the first connecting segment on the substrate.

15. A display device, characterized in that, The display device includes a display substrate as described in any one of claims 1-14.

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