Solar cell and manufacturing method therefor

Abstract

Disclosed in the present invention are a solar cell and a manufacturing method therefor. The solar cell comprises a semiconductor substrate, wherein the semiconductor substrate has two opposite surfaces; a first transparent conductive layer, a metal seed layer, and a second transparent conductive layer sequentially stacked on at least one surface of the semiconductor substrate, wherein the second transparent conductive layer has a plurality of grid line grooves arranged at intervals, and the grid line grooves run through the second transparent conductive layer in a stacking direction; and a metal electrode layer, wherein the grid line grooves are filled with the metal electrode layer, and the metal electrode layer is electrically connected to the metal seed layer to jointly form an electrode structure. The solar cell of the present invention has a multi-level hybrid embedded electrode structure. Such a structure can reduce the thickness of the transparent conductive layer without degrading the conductivity due to the reduction of the thickness of the transparent conductive layer. In addition, the metal composite electrode structure is embedded between two transparent conductive layers, thereby protecting metal electrodes, achieving the effects of oxidation resistance, corrosion resistance, etc., and further significantly increasing the contact area between the metal electrodes and the transparent conductive layers, so that the series resistance is significantly reduced and the conductivity is further improved.

Description

Solar cells and their preparation methods

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese patent application No. 202411726428.4, filed on November 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of solar cells, and more specifically, to a solar cell and a method for its fabrication. Background Technology

[0004] Currently, the mainstream transparent conductive film materials for heterojunction solar cell technology are tin-doped indium oxide (ITO), tungsten-doped indium oxide (IWO), and cerium-doped indium oxide (ICO). However, as a rare metal, indium is expensive, resulting in high costs for heterojunction solar cells, which to some extent limits the large-scale mass production of heterojunction solar cell technology.

[0005] On the other hand, heterojunction solar cells consume far more silver paste than other types of solar cells, and the low-temperature silver paste used is imported, resulting in persistently high non-silicon costs for heterojunction solar cells. The industry has attempted to replace existing conventional materials with other transparent conductive and metallic materials, but these methods suffer from incompatibility with the cells, leading to reduced conversion efficiency and performance degradation. For example, attempts to use low-cost metals (such as copper) face problems such as easy oxidation and poor adhesion to TCOs (Transparent Conductive Oxides); while seeking other high-performance materials often results in a sharp increase in cost.

[0006] Therefore, designing and developing a new electrode structure that reduces material costs while improving conductivity and avoiding efficiency reduction is a problem that urgently needs to be solved in this field. Summary of the Invention

[0007] This invention aims to address, to a certain extent, one of the technical problems in related technologies. To this end, this invention provides a solar cell and its fabrication method. This solar cell, through an innovative embedded electrode structure, can be compatible with and optimize various metal seed layer materials, thereby reducing the thickness of the transparent conductive layer without causing a decrease in conductivity. Furthermore, it significantly increases the contact area between the metal electrode and the transparent conductive layer, resulting in a significant reduction in series resistance and further improvement in conductivity.

[0008] To achieve the above objectives, as a first aspect of the present invention, a solar cell is disclosed, the solar cell comprising:

[0009] A semiconductor substrate; the semiconductor substrate has two opposing surfaces;

[0010] A first transparent conductive layer, a metal seed layer, and a second transparent conductive layer are sequentially stacked on at least one surface of the semiconductor substrate; the second transparent conductive layer has a plurality of spaced gate grooves that penetrate the second transparent conductive layer along the stacking direction.

[0011] A metal electrode layer; the metal electrode layer fills the grid groove and is electrically connected to the metal seed layer, together forming an electrode structure.

[0012] Furthermore, the material of the metal seed layer includes at least one of silver, copper, gold, nickel, tin, titanium, and aluminum.

[0013] Furthermore, the material of the metal electrode layer includes at least one of silver, copper, gold, nickel, tin, titanium, and aluminum.

[0014] Furthermore, the metal seed layer has a higher metal reactivity than the metal electrode layer.

[0015] Furthermore, there is a contact interface between the metal electrode layer and the metal seed layer along the stacking direction and / or along the extension direction of the second transparent conductive layer.

[0016] Furthermore, the metal seed layer is a conductive network layer composed of silver nanowires.

[0017] Furthermore, the diameter of the silver nanowires is between 20 nm and 50 nm, and the length is between 10 μm and 50 μm.

[0018] Furthermore, the sheet resistance of the silver nanowire seed layer is less than 15 Ω / sq.

[0019] Furthermore, the thickness of the metal seed layer is between 5 nm and 80 nm.

[0020] Furthermore, the thickness of the first transparent conductive layer is between 20 nm and 120 nm.

[0021] Furthermore, the thickness of the second transparent conductive layer is between 5 nm and 30 nm.

[0022] Furthermore, the metal electrode layer includes a plurality of metal electrodes, the height of which is the same as the height of the second transparent conductive layer.

[0023] Furthermore, the semiconductor substrate has a first transparent conductive layer, a metal seed layer, a second transparent conductive layer, and a metal electrode layer respectively disposed on its two opposite surfaces.

[0024] Furthermore, the semiconductor substrate comprises, from top to bottom, the following layers stacked sequentially: a first doped semiconductor layer, a first intrinsic semiconductor layer, a silicon substrate, a second intrinsic semiconductor layer, and a second doped semiconductor layer.

[0025] As a second aspect of the present invention, a method for preparing a solar cell is disclosed, comprising:

[0026] A semiconductor substrate is provided, the semiconductor substrate having two opposing surfaces;

[0027] A first transparent conductive layer, a metal seed layer, and an initial second transparent conductive layer are sequentially stacked on at least one surface of the semiconductor substrate;

[0028] The initial second transparent conductive layer is graphically represented to form a second transparent conductive layer having a plurality of gate grooves; the plurality of gate grooves are arranged at intervals and penetrate the second transparent conductive layer along the stacking direction;

[0029] A metal electrode layer is formed that fills the grid grooves; the metal electrode layer is electrically connected to the metal seed layer, and the two together constitute the electrode structure, thus preparing the above-mentioned solar cell.

[0030] Further, the step of forming a metal electrode layer that fills the gate grooves includes:

[0031] The structure obtained after forming the second transparent conductive layer is immersed in a metal salt solution of a predetermined concentration to undergo chemical and / or electrochemical reactions, thereby growing the metal electrode layer based on the surface of the metal seed layer; wherein...

[0032] The metal ions in the metal salt solution correspond to the metals in the metal electrode layer;

[0033] The metal seed layer has a higher metal reactivity than the metal electrode layer.

[0034] Further, the step of patterning the initial second transparent conductive layer to form a second transparent conductive layer having a plurality of gate grooves includes:

[0035] A patterned mask is formed on the initial second transparent conductive layer, wherein the patterned mask includes an opening area and a protection area, and the opening area corresponds to the formation position of the gate groove;

[0036] The initial second transparent conductive layer in the opening region is removed to form a plurality of spaced gate grooves to obtain the second transparent conductive layer, wherein the opening width of the gate grooves is between 10 μm and 20 μm; and the thickness of the second transparent conductive layer is between 5 nm and 30 nm.

[0037] Further, the semiconductor substrate comprises, from top to bottom, the following layers stacked sequentially: a first doped semiconductor layer, a first intrinsic semiconductor layer, a silicon substrate, a second intrinsic semiconductor layer, and a second doped semiconductor layer; the fabrication method further includes:

[0038] A first transparent conductive layer, a metal seed layer, a second transparent conductive layer, and a metal electrode layer are respectively formed on the surfaces of the first doped semiconductor layer and the second doped semiconductor layer that are away from the silicon substrate.

[0039] The solar cell structure of the present invention comprises a first transparent conductive layer, a metal seed layer, and a second transparent conductive layer sequentially stacked on the surface of a semiconductor substrate. A metal electrode layer is filled in multiple grid slots that are spaced apart and penetrate through the second transparent conductive layer and is electrically connected to the metal seed layer exposed from the grid slots, forming a multi-level hybrid embedded electrode structure. This structure can reduce the thickness of the transparent conductive layer without causing a decrease in conductivity due to the reduction in the thickness of the transparent conductive layer. The key is that the use of a metal composite electrode structure embedded between the two transparent conductive layers can significantly improve the transport of lateral and longitudinal charge carriers and improve conductivity.

[0040] On the other hand, the second transparent conductive layer can cover and protect the metal seed layer, as well as the sides of the metal electrode layer, preventing lateral oxidation or corrosion. Furthermore, embedding this composite metal electrode between the two transparent conductive layers not only protects the metal electrode, providing oxidation and corrosion resistance, but also significantly increases the contact area between the metal electrode and the transparent conductive layer. Compared to conventional battery structures, the sidewalls of the grid groove structure in this invention increase the contact area between the metal electrode and the transparent conductive layer, and both the upper and lower surfaces of the metal seed layer are in close contact with the transparent conductive layer, far exceeding the contact area between conventional metal electrodes and transparent conductive layers. This significantly reduces series resistance and further improves conductivity.

[0041] Furthermore, the grid grooves of the second transparent conductive layer provide a location for the formation of the metal electrodes in the subsequent metal electrode layer. The metal electrodes are filled in the grid grooves, which can improve the morphology of the metal electrodes, making the size of the metal electrodes more uniform and the morphology more flat. Moreover, by making the grid grooves of the second transparent conductive layer super-fine, the linewidth of the metal electrodes can be effectively reduced, thereby reducing the shading area and improving the conversion efficiency.

[0042] The metal electrode layer is electrically connected to the metal seed layer, and the upper metal electrode layer further protects the metal seed layer. This allows the metal seed layer to use low-cost metals instead of conventional silver paste, and avoids the oxidation problems of low-cost metals, improving the lifespan and reliability of solar cells while significantly reducing costs. Furthermore, the composite metal structure itself has higher conductivity compared to a single metal electrode.

[0043] The solar cell fabrication method of this invention can significantly reduce the amount of precious metal electrodes such as indium, thereby reducing the non-silicon cost of heterojunction cells. The upper metal electrode layer and the second transparent conductive layer can protect the lower metal seed layer, reducing the risk of power decay caused by oxidation and other problems. The metal seed layer can thus use low-cost metals without worrying about their easy oxidation. The patterned second transparent conductive layer can provide positions for the formation of metal electrodes in the metal electrode layer, thereby controlling and reducing the linewidth of the metal electrodes, reducing the shading area, and improving the cell conversion efficiency. In addition, the grid grooves, metal electrode layer, and metal seed layer can increase the contact area between the metal electrodes and the transparent conductive layer, reduce the series resistance, and improve the short-circuit current, fill factor, and cell conversion efficiency of heterojunction cells.

[0044] These features and advantages of the present invention will be disclosed in detail in the following specific embodiments and accompanying drawings. The preferred embodiments or means of the present invention will be shown in detail in conjunction with the accompanying drawings, but are not intended to limit the technical solutions of the present invention. In addition, each of these features, elements and components appearing in the following text and drawings is a plurality of, and different symbols or numbers are used for convenience of representation, but all represent parts with the same or similar construction or function. Attached Figure Description

[0045] The present invention will be further described below with reference to the accompanying drawings:

[0046] Figure 1 is a schematic diagram of one embodiment of the solar cell provided by the present invention;

[0047] Figure 2 is a schematic diagram of another embodiment of the solar cell provided by the present invention;

[0048] Figure 3(a) is an enlarged schematic diagram of a partial structure of the solar cell provided by the present invention;

[0049] Figure 3(b) is an enlarged schematic diagram of another embodiment of the partial structure of the solar cell provided by the present invention;

[0050] Figure 4 is a flowchart of one embodiment of the solar cell fabrication method provided by the present invention;

[0051] Figure 5 is a structural flowchart of one embodiment of the solar cell fabrication method provided by the present invention;

[0052] Figure 6 is a schematic diagram of another embodiment of the solar cell provided by the present invention.

[0053] Explanation of reference numerals in the attached figures: 1: Solar cell; 10: Semiconductor substrate; 11: First transparent conductive layer; 12: Metal seed layer; 13: Second transparent conductive layer; 131: Grid groove; 14: Metal electrode layer; 141: Metal electrode; 13a: Initial second transparent conductive layer; 21: Silicon substrate; 22a: First intrinsic semiconductor layer; 22b: Second intrinsic semiconductor layer; 23: First doped semiconductor layer; 24: Second doped semiconductor layer. Detailed Implementation

[0054] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described are intended to explain the present invention and should not be construed as limiting the invention.

[0055] The terms "an embodiment," "example," or "example" used in this specification refer to a particular feature, structure, or characteristic described in connection with the embodiment itself that may be included in at least one embodiment disclosed in this application. The phrase "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.

[0056] It should be noted that in this invention, "inner side" refers to the side closer to the initial substrate, and "outer side" refers to the side away from the initial substrate.

[0057] As a first aspect of the present invention, a solar cell is disclosed, as shown in FIG1. ​​The solar cell 1 includes:

[0058] Semiconductor substrate 10;

[0059] A first transparent conductive layer 11, a metal seed layer 12, and a second transparent conductive layer 13 are stacked on at least one surface of a semiconductor substrate 10. The second transparent conductive layer 13 includes a plurality of spaced gate grooves 131 that penetrate the second transparent conductive layer 13 along the stacking direction.

[0060] The metal electrode layer 14 is filled in the grid groove 131 and electrically connected to the metal seed layer 12 to form an electrode structure. As an optional embodiment, the metal electrode layer 14 includes a plurality of metal electrodes 141, which correspond one-to-one with the plurality of grid grooves 131. The metal electrodes 141 are located in the corresponding grid grooves 131 and are electrically connected to the metal seed layer 12.

[0061] The solar cell structure of the present invention comprises a first transparent conductive layer, a metal seed layer, and a second transparent conductive layer sequentially stacked on the surface of a semiconductor substrate. Multiple metal electrodes of the metal electrode layer are disposed in multiple grid slots that are spaced apart and penetrate through the second transparent conductive layer. The metal electrodes correspond one-to-one with the grid slots and are electrically connected to the metal seed layer exposed from the grid slots, thus forming a multi-level hybrid embedded electrode structure.

[0062] This structure reduces the thickness of the transparent conductive layer without compromising conductivity. The key lies in the use of a metal composite electrode structure embedded between the two transparent conductive layers, significantly improving lateral and longitudinal carrier transport and thus enhancing conductivity. This invention does not impose specific limitations on the thickness of the first and second transparent conductive layers; they can be the same as conventional transparent conductive layers or further reduced. Preferably, the thickness of the first transparent conductive layer is between 20 nm and 120 nm, and the thickness of the second transparent conductive layer is between 5 nm and 30 nm. Conventional transparent conductive layers are generally over 100 nm thick. This invention divides the transparent conductive layer into two layers and designs an embedded metal composite electrode between them, significantly reducing its thickness. Further preferably, the sum of the thicknesses of the first transparent conductive layer, the metal seed layer, and the second transparent conductive layer is between 30 nm and 140 nm. This invention also does not impose specific limitations on the material of the transparent conductive layer, as long as it meets the requirement of transparency and conductivity. Preferably, the first and second transparent conductive layers include at least one of ITO, IWO, ICO, and AZO. To ensure both electrical performance and light transmittance, the thickness of the metal seed layer is preferably between 5 nm and 80 nm. When the metal seed layer is a silver nanowire layer, its thickness can be controlled by the diameter of the silver nanowires and the number of coating layers, preferably between 20 nm and 100 nm. The diameter of the silver nanowires is between 20 nm and 50 nm, preferably between 35 nm ± 5 nm, and the length is between 10 μm and 50 μm, preferably between 20 μm and 40 μm. This preferred size range of silver nanowires achieves an optimal balance between high light transmittance and low sheet resistance, while its moderate aspect ratio ensures excellent stability and processability when forming a conductive network.

[0063] By selecting silver nanowires with a diameter of approximately 35nm ± 5nm, a sheet resistance of less than 15Ω / sq can be achieved, while maintaining a transmittance of over 95% at a wavelength of 550nm for the composite structure containing the seed layer. Simultaneously, the selection of silver nanowires with a length of 20-40μm, with their large aspect ratio (approximately 667:1 to 1333:1), ensures the formation of a robust three-dimensional conductive network. This provides abundant nucleation sites and a strong adhesion base for subsequent electroplating of metal electrodes, which is crucial for achieving low interfacial resistance and a high fill factor. This ensures excellent lateral conductivity while maintaining high transmittance (>95%).

[0064] On the other hand, the second transparent conductive layer can cover and protect the metal seed layer, as well as the sides of the metal electrode layer, preventing lateral oxidation or corrosion. Furthermore, embedding this composite metal electrode between the two transparent conductive layers not only protects the metal electrode, providing oxidation and corrosion resistance, but also significantly increases the contact area between the metal electrode and the transparent conductive layer. Compared to conventional battery structures, the sidewalls of the grid groove structure in this invention increase the contact area between the metal electrode and the TCO, and both the upper and lower surfaces of the metal seed layer are in close contact with the transparent conductive layer, far exceeding the contact area between conventional metal electrodes and transparent conductive layers. This significantly reduces the series resistance and further improves conductivity.

[0065] The metal electrode layer is electrically connected to the metal seed layer. The upper metal electrode layer further protects the metal seed layer, allowing the use of low-cost metals instead of conventional silver paste and avoiding the oxidation problems associated with low-cost metals. This improves the lifespan and reliability of the solar cell while significantly reducing costs. Furthermore, the composite metal structure itself has higher conductivity compared to a single metal electrode. Preferably, the metal seed layer and the metal electrode layer include at least one of silver, copper, gold, nickel, tin, titanium, and aluminum.

[0066] Preferably, copper can be used as the metal seed layer. Copper has comparable conductivity to silver and is less expensive. However, copper is easily oxidized. The structure of this invention effectively prevents copper oxidation. Silver can be used as the metal electrode layer. Silver has stronger oxidation resistance and is suitable as the upper metal electrode layer. In addition, copper, as the first metal layer, has higher light transmittance, thereby improving the light absorption of the battery. In other words, when copper is used as the metal seed layer, its advantages are low cost and conductivity comparable to silver. This invention, by embedding it between two TCO layers and covering it with an upper silver electrode, perfectly solves the industry problem of copper's easy oxidation, making the large-scale application of low-cost copper possible.

[0067] As another preferred option, the metal seed layer can be made of silver nanowires. The silver nanowire layer, due to its one-dimensional nanostructure, forms a three-dimensional conductive network, achieving extremely high lateral conductivity while ensuring high light transmittance, allowing for further thinning of the first TCO layer to save on indium usage. It not only provides excellent conductivity, but its large specific surface area also provides more nucleation sites for the subsequent growth of the metal electrode layer, resulting in a stronger contact between the metal electrode layer and the seed layer, and a significant reduction in interfacial resistance. Simultaneously, the excellent oxidation resistance of the silver nanowires themselves ensures the stability of the seed layer during the process.

[0068] In this invention, silver nanowires are selected as the metal seed layer. Compared with bulk silver materials, they have a higher specific surface area and surface activity, that is, greater metal activity. On the one hand, this provides abundant high-energy nucleation sites for the subsequent electrochemical deposition of the metal electrode layer, promoting the formation of a dense, uniform, and firmly attached metal electrode and achieving excellent low interfacial contact resistance. On the other hand, by embedding them between two transparent conductive layers, this invention effectively avoids the instability problems of silver nanowires being easily oxidized and sulfided in the environment, thus maximizing their advantages and minimizing their disadvantages, and allowing their high conductivity and high surface activity to be fully utilized.

[0069] The electrode structure of this invention provides an optimal platform for the development of metal seed layer materials with different properties: for copper, it mainly addresses the issue of "stability"; for silver nanowires, it maximizes their advantages in "conductivity and interface". These two approaches together constitute the two core technical paths of this invention in reducing costs and improving performance.

[0070] In some embodiments, the metal in the metal seed layer 12 is more reactive than the metal in the metal electrode layer 14, allowing the metal electrode layer to be formed in situ on the surface of the metal seed layer 12 through chemical and / or electrochemical reactions. The advantage of this method of forming the metal electrode layer is that the in-situ formation and growth of the metal electrode layer allows for a strong bond with the metal seed layer, improving adhesion. Furthermore, it ensures sufficient contact with the metal seed layer, reducing porosity and defects at the interface between the two metal layers, resulting in a larger contact area and thus improved conductivity. This invention does not specifically limit the metal material; however, preferably, the metal seed layer and the metal electrode layer include at least one of silver, copper, gold, nickel, tin, titanium, and aluminum.

[0071] Furthermore, the width of the metal electrode formed in situ is consistent with the width of the grid groove. The grid groove of the second transparent conductive layer provides a location for the in-situ formation and growth of the subsequent metal electrode layer. This metal electrode is formed in situ and fills the grid groove. The grid groove can improve the morphology of the metal electrode, making the size of the metal electrode more uniform and the morphology more flat. Moreover, by refining the grid groove of the second transparent conductive layer, the linewidth of the metal electrode can be effectively reduced, thereby reducing the shading area and improving the conversion efficiency. Preferably, the width of the grid groove is between 10 μm and 15 μm, and the corresponding width of the metal electrode is also between 10 μm and 15 μm, which is much lower than the linewidth of the metal electrode in existing metallization technologies (above 25 μm).

[0072] This invention does not impose a specific limitation on the thickness of the metal electrode. For example, the height of the metal electrode may be the same as the height of the second transparent conductive layer, or the height of the metal electrode may be greater than the height of the second transparent conductive layer. To ensure that the sidewalls of the grid slots effectively protect the metal electrode and have sufficient contact area with it, preferably, the height of the second transparent conductive layer away from the surface of the metal seed layer matches the height of the metal electrode away from the surface of the metal seed layer.

[0073] In some embodiments, as shown in Figures 3(a) and 3(b), the metal seed layer is formed by a chemical reaction, such as a displacement reaction, between the metal electrode layer and the metal seed layer via a metal salt solution, resulting in the consumption of metal in the seed layer. In this case, the thickness of the metal seed layer corresponding to the gate groove is less than the thickness of the metal seed layer covered by the second transparent conductive layer. This creates a contact interface between the metal electrode layer and the metal seed layer along the stacking direction and / or along the extension direction of the second transparent conductive layer, further increasing the contact area between the metal electrode layer and the metal seed layer, and improving the adhesion and conductivity between the two metals. In other embodiments, a small amount of etching can be performed on the metal seed layer during the formation of the gate groove, which also increases the contact area between the metals.

[0074] In some embodiments, after the electrode structure is formed, a sintering process is performed. Sintering can reduce the porosity of the metal, making the metal more compact, and further increasing adhesion and conductivity.

[0075] The present invention does not impose any special restrictions on the position of the electrode structure. It can be a top electrode, a bottom electrode, or both a top electrode and a bottom electrode. As an optional implementation, the solar cell provided by the present invention is shown in FIG2. The solar cell 1 has a first transparent conductive layer 11, a metal seed layer 12, a second transparent conductive layer 13, and a metal electrode layer 14 disposed on two opposite surfaces of the semiconductor substrate 10.

[0076] As a second aspect of the present invention, a method for preparing a solar cell is disclosed, the process of which is shown in Figure 4, and the steps include:

[0077] Step S100: Provide a semiconductor substrate having two opposing surfaces;

[0078] Step S110: A first transparent conductive layer, a metal seed layer, and an initial second transparent conductive layer are sequentially stacked on at least one surface of a semiconductor substrate;

[0079] Step S120: Graphicalize the initial second transparent conductive layer to form a second transparent conductive layer with multiple gate grooves. The multiple gate grooves are arranged at intervals and penetrate the second transparent conductive layer along the stacking direction.

[0080] Step S130: A metal electrode layer is formed that fills the grid grooves. The metal electrode layer is electrically connected to the metal seed layer, and the two together constitute the electrode structure, thus preparing the solar cell described above.

[0081] In step S100, the present invention does not specifically limit the type of semiconductor substrate, as long as it is a solar cell without electrodes. For example, the semiconductor substrate can be a tunnel oxide passivated contact (TOPCon) cell, an intrinsic thin-film heterojunction (HJT) cell, or an emitter and rear passivated cell (PERC). It is not limited to crystalline silicon cells; it can also be other types of cells and tandem cells using the above-mentioned cells, such as perovskite tandem cells. The present invention does not specifically limit the method of obtaining the semiconductor substrate; for example, it can be obtained by purchasing it externally. Another example is that it can be obtained through a fabrication method.

[0082] For ease of understanding, the structural flowchart of the solar cell fabrication method of the present invention is shown in Figure 5.

[0083] In step S110, the electrode structure of the present invention can be formed on both the front and / or back of the battery. As an optional embodiment, a first transparent conductive layer 11, a metal seed layer 12, an initial transparent conductive layer 13a, and a metal electrode layer 14 are formed on both the front and back surfaces of the semiconductor substrate 10, as shown in FIG5.

[0084] In step S120, the present invention does not impose any special limitation on how the gate groove is formed. For example, the gate groove can be formed by selectively etching on the initial second transparent conductive layer by laser ablation, or the initial transparent conductive layer can be selectively removed by setting a patterned mask to form the gate groove.

[0085] Preferably, the initial second transparent conductive layer is patterned to form a second transparent conductive layer having multiple gate grooves, including:

[0086] S121. A patterned mask is formed on the initial second transparent conductive layer. The patterned mask includes an opening area and a protection area. The opening area corresponds to the position of the gate line groove area. The width of the opening area is between 10 μm and 20 μm. Specifically, the opening area of ​​the patterned mask corresponds to the gate line formation area. It can be understood that this setting transforms the unmasked area (i.e., the opening area) of the patterned mask into the subsequent gate line formation position, and the morphology and width of the gate line are affected by the shape and width of the opening area of ​​the patterned mask.

[0087] The present invention does not impose any special limitation on the formation method of the patterned mask. At least one of the following methods can be used to form the patterned mask on the initial second transparent conductive layer: screen printing ink, spraying ink, and photoresist development and exposure. Preferably, the patterned mask is formed on the initial second transparent conductive layer by screen printing acid ink, which has lower cost and higher printing accuracy and smaller line width.

[0088] In some embodiments, the screen used in forming the patterned mask by screen printing is completely different from the screen used for conventional printing of metal electrodes. Its open and closed areas are completely opposite to those of a conventional screen. This eliminates concerns about the screen obstructing the ink during printing, as the closed areas of the screen provided in this embodiment correspond to the formation positions of the grid lines. This reduces printing difficulty, provides a large process window, and facilitates operation. The width of the closed area of ​​the screen can be extremely fine, further refining the width of the open area of ​​the patterned mask. Preferably, the width of the open area of ​​the patterned mask is between 10 μm and 20 μm, resulting in a metal electrode width of 10 μm to 20 μm, significantly lower than the electrode width of conventional screen printing (above 25 μm). Furthermore, acidic inks are easier to print than metal pastes.

[0089] S122. Remove the initial second transparent conductive layer in the opening area to form multiple spaced grid grooves, thereby obtaining the second transparent conductive layer. Specifically, it can be removed by at least one of wet etching, dry etching, and laser etching. The transparent conductive layer is generally a metal oxide. For easier removal, it is preferable to use an acidic solution for etching. The acidic solution can be at least one of hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, and hydrofluoric acid, with a concentration between 5wt% and 20wt%, an etching temperature between 20 and 50°C, and an etching time between 30s and 6000s. The acidic solution etching method for removing the initial second transparent conductive layer is lower in cost and more efficient. Furthermore, the acidic solution has poor isotropy for TCO (Transparent Conductive Oxides) materials, resulting in a shorter lateral etching distance and higher dimensional accuracy of the grid grooves.

[0090] In some embodiments, the patterned mask is formed on the initial second transparent conductive layer with acidic ink. To facilitate the subsequent removal of the acidic ink, it can be removed by etching with an alkaline solution. The alkaline solution can be at least one of KOH, NaOH, and NH4OH, with a concentration between 3 wt% and 12 wt%. Hydrogen peroxide can also be used to assist in the removal of the acidic ink, with a hydrogen peroxide concentration between 0.5 wt% and 6 wt%, a removal temperature between 20 and 60°C, and a removal time between 50 s and 500 s.

[0091] In step S130, the present invention does not specifically limit how the metal electrode layer is formed; it can be formed using at least one of chemical plating, electroplating, laser transfer, and screen printing. Preferably, chemical plating or electroplating is used. As an optional implementation, the structure obtained after forming the second transparent conductive layer is immersed in a metal salt solution of a preset concentration, and a chemical and / or electrochemical reaction is performed within a set time to grow the metal electrode layer based on the surface of the metal seed layer. The metal ions in the metal salt solution correspond to the metal in the metal electrode layer. Preferably, the set concentration is between 0.05 mol / L and 5 mol / L, and the set time is the reaction time. This set time determines the height of the metal electrode layer and can be adjusted according to specific performance requirements. For example, to ensure that the sidewall height of the grid groove is sufficiently high to effectively protect the metal electrode and provide sufficient contact area, the reaction time is preferably set so that the height of the metal electrode matches the height of the second transparent conductive layer.

[0092] To increase the reaction rate, the solution pH can be adjusted, or an electroplating device can be added to perform a combined chemical plating and electroplating reaction, thereby increasing the generation rate and content of the reaction products.

[0093] To achieve the structural advantages of in-situ formation, the metal seed layer is made more reactive than the metal electrode layer. This allows for a chemical displacement reaction between the metal salt solution and the metal seed layer. In some embodiments, the metal seed layer is a copper layer, and the metal salt solution is a silver nitrate solution. Silver grows in situ at the contact points between the copper and silver nitrate solution. Over time, the silver layer thickens until it completely encapsulates the exposed copper layer in the grid slots. This not only increases the contact area and the adhesion of the silver layer but also provides comprehensive protection for the copper layer to prevent oxidation. Furthermore, due to the chemical reaction between the metal salt solution and the metal seed layer, such as a displacement reaction, the metal in the metal seed layer is consumed. In this case, the thickness of the metal seed layer at the grid slots is less than the thickness of the metal seed layer covered by the second transparent conductive layer. This creates a contact interface between the metal electrode layer and the metal seed layer along the stacking direction and / or along the extension direction of the second transparent conductive layer, further increasing the contact area between the metal electrode layer and the metal seed layer, improving adhesion and conductivity. In other embodiments, when forming the gate grooves, a small amount of etching can be performed on the metal seed layer, which can also increase the contact area between the metals.

[0094] Furthermore, conventional screen printing methods cannot further reduce linewidth, while this in-situ metal electrode fabrication method allows the width of the metal electrode to match the width of the grid grooves. Moreover, a more refined fabrication method can reduce the linewidth of the grid grooves, thereby correspondingly reducing the width of the metal electrode, decreasing the obstruction area, and improving conversion efficiency. Preferably, the width of the grid grooves is between 10 μm and 15 μm, and the corresponding width of the metal electrode is also between 10 μm and 15 μm, significantly lower than the linewidth of the metal electrode in existing metallization technologies (above 25 μm).

[0095] In some embodiments, forming a metal electrode layer in the gate groove of the second transparent conductive layer further includes:

[0096] Sintering the metal electrode layer reduces the porosity of the metal and makes the contact between metal particles closer, thus forming a denser contact interface between the metal electrode layer and the metal seed layer, further increasing adhesion and conductivity.

[0097] The present invention does not impose special restrictions on the position of the electrode structure. It can be a top electrode, a bottom electrode, or both. In some embodiments, a first transparent conductive layer, a metal seed layer, a second transparent conductive layer, and a metal electrode layer are formed on two opposite surfaces of the semiconductor substrate to form a solar cell with electrodes having the above-described structure on both the front and back sides.

[0098] The present invention will be further explained and illustrated below with reference to the embodiments.

[0099] Example 1 (Copper Seed Layer Scheme)

[0100] S1. Providing a semiconductor substrate, wherein the specific fabrication steps of the semiconductor substrate include:

[0101] We provide N-type silicon substrates with dimensions of 182*105mm that have undergone chain- or tubular phosphorus diffusion getter treatment. The silicon wafers are texturized to form a double-sided pyramid structure. The texturing agent consists of 1.5wt% NaOH solution and 0.5wt% texturing additive. The texturing temperature is 82℃, the texturing time is 450s, and the additive is TS53V01. After texturing, the silicon substrate loses 0.4g in weight, has a reflectivity of 10%, a pyramid edge length of 1.7μm, a height of 1.6μm, and a specific surface area of ​​1.6m². 2 / g, the silicon substrate has a textured surface, and the number of pyramids per unit area is 250,000 / mm. 2 ;

[0102] Using a chemical vapor deposition (CVD) device, a first intrinsic semiconductor layer is deposited on the front side of a texturized and cleaned silicon substrate, and a second intrinsic semiconductor layer is deposited on the back side. Specifically, an RF power supply is used to deposit intrinsic amorphous silicon and hydrogen-rich amorphous silicon sequentially, which effectively improves the passivation effect. The total thickness of the first intrinsic semiconductor layer on the front side is 3 nm, and the total thickness of the second intrinsic semiconductor layer on the back side is 5 nm.

[0103] A first process gas is introduced, a VHF power supply is used, and an N-type microcrystalline silicon oxide layer is chemically vapor-deposited on the surface of the first intrinsic semiconductor layer on the front side as the first doped semiconductor layer. The process temperature is set to 190°C, and the power density is 200 mW·cm³. -2 The process pressure is 5 mbar. The first process gas includes CO2, H2, PH3, and SiH4, with a gas flow ratio of 0.6:200:0.036:1. The thickness of the N-type microcrystalline silicon oxide layer is 15 nm. A second process gas is introduced to perform chemical vapor deposition on the second intrinsic semiconductor layer on the back side, forming a P-type microcrystalline silicon oxide layer as the second doped semiconductor layer. The process temperature is set to 170℃, and the power density is 250 mW·cm³. -2 The process pressure is 7 mbar, and the second process gas includes H2, B2H6 and SiH4, wherein the gas flow ratio of H2, B2H6 and SiH4 is 200:0.005:1, and the film thickness of the P-type doped microcrystalline layer is 25 nm.

[0104] S2. A first transparent conductive layer, a metal seed layer, and an initial second transparent conductive layer are stacked on the surface of the aforementioned semiconductor substrate, specifically including:

[0105] A third process gas is introduced, and a first transparent conductive layer, a metal seed layer, and an initial second transparent conductive layer are stacked on the front and back surfaces of the aforementioned microcrystalline silicon oxide layer in a direction away from the silicon substrate. The first transparent conductive layer includes ITO with a thickness of 60 nm, the metal seed layer is a base metal film, which may be copper, with a thickness of 20 nm, and the initial second transparent conductive layer includes ITO with a thickness of 10 nm. The process temperature is set to 180 °C, the power supply is 10 kW, the process pressure is 0.6 Pa, and the process gas includes Ar, O2, and H2, wherein the flow rate ratio of Ar, O2, and H2 is 1:0.04:0.02.

[0106] S3. The initial second transparent conductive layer is patterned to form multiple spaced grid grooves. The grid grooves penetrate the initial second transparent conductive layer along the stacking direction to form a second transparent conductive layer, thereby obtaining a first substrate. Specifically, this includes:

[0107] Acid ink was screen-printed on the surface of the initial second transparent conductive layer. The printing height was 10 μm. The screen parameters were the standard screen parameters. The printed pattern corresponded to the metal electrode pattern. That is, the opening area of ​​the printing screen was the non-grid line area. The non-opening area of ​​the printing screen corresponded to the grid line forming area. The width of the non-opening area was 10-15 μm, which was much lower than the metal electrode line width of existing metallization technology (above 25 μm).

[0108] The printed silicon wafer was placed in an inorganic acid solution to selectively remove the initial second transparent conductive layer in the non-opening areas not covered by ink. The etching solution was hydrochloric acid with a mass concentration of 15wt%, and the treatment time was 300s at room temperature. An industrial camera confirmed that the initial second transparent conductive layer not covered by ink was completely etched.

[0109] S4. A metal electrode layer is formed in the grid grooves of the second transparent conductive layer, wherein the metal electrode layer includes multiple metal electrodes, each corresponding to one of the multiple grid grooves, and the metal electrodes are located in the corresponding grid grooves and electrically connected to the metal seed layer, thereby fabricating a solar cell. Specifically, this includes:

[0110] The etched silicon wafer is placed in a 0.1 mol / L silver nitrate solution for displacement reaction. The metal seed layer is used as the anode. With the help of an electrochemical device, the thickness of the metal seed layer at the grid groove is close to the thickness of the metal seed layer covered by the second transparent conductive layer, forming multiple metal electrodes and preparing a metal electrode layer.

[0111] The silicon wafer was placed in an alkaline mixed solution to remove ink. The alkaline mixed solution contained 6 wt% KOH and 2.7 wt% hydrogen peroxide. The wafer was treated at 50°C for 150 s. After standard processes of sintering (210°C, 30 min) and light injection (210°C, 70 s), a solar cell 1 was finally prepared. The structure is shown in Figure 6. The solar cell 1 includes the following layers stacked from top to bottom: a second transparent conductive layer 13, a metal electrode layer 14, a metal seed layer 12, a first transparent conductive layer 11, a first doped semiconductor layer 23, a first intrinsic semiconductor layer 22a, a silicon substrate 21, a second intrinsic semiconductor layer 22b, a second doped semiconductor layer 24, a first transparent conductive layer 11, a metal seed layer 12, a metal electrode layer 14, and a second transparent conductive layer 13. The metal electrode layer 14 includes a plurality of metal electrodes 141, and the height of the metal electrodes 141 is the same as the height of the second transparent conductive layer 13.

[0112] Example 2 (Silver Nanowire Seed Layer Scheme)

[0113] The semiconductor substrate was prepared using the same steps as in Example 1, S1.

[0114] S2. A first transparent conductive layer, a silver nanowire seed layer, and an initial second transparent conductive layer are stacked on the surface of the aforementioned semiconductor substrate, specifically including:

[0115] A third process gas is introduced to deposit a first transparent conductive layer on the front and back surfaces of the microcrystalline silicon oxide layer in a direction away from the silicon substrate. The first transparent conductive layer includes ITO and has a thickness of 50 nm [thinner than in Example 1].

[0116] Subsequently, a silver nanowire seed layer was prepared on the first transparent conductive layer using the slit coating method. The specific steps are as follows:

[0117] • A dispersion of silver nanowires (solid content 0.5wt%, solvent is a mixture of deionized water and ethanol) was uniformly coated onto the surface of the first transparent conductive layer at a coating speed of [5mm / s].

[0118] • Dry on a heating plate at 120°C for 2 minutes to evaporate the solvent;

[0119] • Subsequently, a heat treatment of 10 minutes at 180°C under nitrogen protection is performed to remove surfactants and strengthen the welding between the silver nanowires, forming a stable and dense two-dimensional conductive network.

[0120] The sheet resistance of the silver nanowire seed layer is [12Ω / sq], and the thickness is approximately [40nm].

[0121] Finally, a third process gas is introduced to deposit an initial second transparent conductive layer (ITO, 10 nm thick) on the silver nanowire seed layer, with the same process parameters as in Example 1.

[0122] S3. The initial second transparent conductive layer is patterned to form multiple spaced grid grooves.

[0123] This step is exactly the same as in Example 1, using screen printing of acidic ink and hydrochloric acid wet etching to form grid grooves with a width of 10-15 μm.

[0124] S4. A metal electrode layer is formed in the grid groove of the second transparent conductive layer.

[0125] The etched silicon wafer is placed in a 0.05 mol / L silver nitrate solution for electroless plating. Due to the large specific surface area and abundant active sites of the silver nanowires, metallic silver is rapidly and selectively reduced and grown on the silver nanowire network, achieving a metallurgical bond between the metal electrode layer and the seed layer. The reaction time is controlled to match the height of the metal electrode with the height of the second transparent conductive layer.

[0126] The subsequent ink removal, sintering, and photoinjection steps are exactly the same as in Example 1.

[0127] Comparative Example 1

[0128] The solar cell was fabricated using the same method as in Example 1, except that a transparent conductive layer and a metal electrode were stacked on the surface of the semiconductor substrate. Specifically, this included:

[0129] A transparent conductive layer was prepared by magnetron sputtering on the front and back surfaces of the aforementioned microcrystalline silicon oxide layer in a direction away from the silicon substrate. The process temperature was set to 180℃, the power supply was 10kW, the process pressure was 0.6pa, and the process gases included Ar, O2, and H2, wherein the flow rate ratio of Ar, O2, and H2 was 1:0.04:0.02, and the thickness of the transparent conductive layer was 90nm.

[0130] Metal electrodes were fabricated on the surface of the aforementioned transparent conductive layer by screen printing, curing, and photoinjection, resulting in a conventional solar cell with a linewidth of 35 μm.

[0131] Comparative Example 2

[0132] Solar cells were prepared using the same method as Comparative Example 1, except that the metal electrodes used a silver-clad copper structure with a silver content of 54%.

[0133] Test case

[0134] The examples and comparative examples were tested using a Halm high-precision IV tester according to the STC standard. Electrical performance tests included photoelectric conversion efficiency (Eff), open-circuit voltage (Uoc), short-circuit current (Isc), and fill factor (FF). Test conditions: solar irradiance of 1000 W / m². 2 The spectrum was AM1.5 (atmospheric mass), the solar cell temperature was 25℃, and the test results are shown in Table 1. It can be seen that the solar cell prepared by the method of the present invention has better short-circuit current, fill factor and photoelectric conversion efficiency.

[0135] Table 1

[0136] As can be seen from the table above, the solar cell and its preparation method of the present invention effectively solve the industry problem that traditional electrodes cannot simultaneously achieve high conductivity, low cost and long-term reliability by introducing an embedded composite electrode structure composed of a first transparent conductive layer, a metal seed layer, a second transparent conductive layer with grid grooves and a metal electrode layer filled in the grooves.

[0137] Test results show that, compared to traditional single-material electrode structures (Comparative Examples 1 and 2), the electrode structure of this invention, as a unified platform, significantly improves the short-circuit current, fill factor, and final photoelectric conversion efficiency of the battery, regardless of the specific metal seed layer material used, and effectively reduces the series resistance. This demonstrates the fundamental performance gains brought about by this innovative structure itself.

[0138] Furthermore, the present invention provides two preferred technical paths, each with its own advantages: the scheme of using copper as a metal seed layer (Example 1) successfully applies low-cost metals to high-performance heterojunction cells. While achieving efficiency improvement, it is expected to significantly reduce the cost of electrode materials to about 65% of the traditional scheme, demonstrating excellent cost performance and potential for large-scale application.

[0139] In the scheme using silver nanowires as the metal seed layer (Example 2), the three-dimensional conductive network constructed by the silver nanowires provides excellent lateral conductivity, and the huge contact interface formed between the silver nanowires and the upper electroplated silver electrode significantly reduces the contact resistance, resulting in a series resistance reduction from 0.38 mΩ·cm. 2 (Example 1) Reduced to 0.30 mΩ·cm 2 (Example 2) The reduction in series resistance directly led to an increase in the fill factor. Simultaneously, the high light transmittance of the silver nanowire network allowed the first transparent conductive layer to be thinned to 50 nm without sacrificing conductivity, reducing optical losses and thus increasing the short-circuit current. Example 2 fully utilizes the high conductivity and large specific surface area of ​​nanomaterials, pushing the battery conversion efficiency to a top level of 26.45%, providing a clear technical direction for realizing ultra-high efficiency heterojunction batteries.

[0140] In summary, the electrode structure provided by this invention not only boasts excellent performance but also possesses high material compatibility and design flexibility. It can be flexibly optimized according to different market positioning (cost priority or peak performance), providing a key and effective solution for the diversified development and cost control of heterojunction battery technology, and has significant industrial application value.

[0141] These are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Those skilled in the art should understand that the present invention includes, but is not limited to, the content described in the accompanying drawings and the specific embodiments above. Any modifications that do not depart from the functional and structural principles of the present invention will be included within the scope of the claims.

Claims

1. A solar cell, characterized in that, The solar cell includes: A semiconductor substrate having two opposing surfaces; A first transparent conductive layer, a metal seed layer, and a second transparent conductive layer are sequentially stacked on at least one surface of the semiconductor substrate. The second transparent conductive layer has a plurality of spaced gate grooves that penetrate the second transparent conductive layer along the stacking direction. A metal electrode layer is also stacked, filling the gate grooves and electrically connected to the metal seed layer to form an electrode structure.

2. The solar cell according to claim 1, characterized in that, The material of the metal seed layer includes at least one of the following: silver, copper, gold, nickel, tin, titanium, and aluminum; The material of the metal electrode layer includes at least one of the following: silver, copper, gold, nickel, tin, titanium, and aluminum; and / or, The metal seed layer exhibits greater metallic reactivity than the metal electrode layer; and / or, There is a contact interface between the metal electrode layer and the metal seed layer along the stacking direction and / or along the extension direction of the second transparent conductive layer.

3. The solar cell according to claim 1, characterized in that, The metal seed layer is a conductive network layer composed of silver nanowires; and / or, The diameter of the silver nanowires is between 20 nm and 50 nm, and the length is between 10 μm and 50 μm; and / or, The sheet resistance of the silver nanowire seed layer is less than 15 Ω / sq.

4. The solar cell according to claim 1, characterized in that, The semiconductor substrate has a first transparent conductive layer, a metal seed layer, a second transparent conductive layer, and a metal electrode layer respectively disposed on two opposite surfaces; and / or, The thickness of the metal seed layer is between 5 nm and 80 nm; and / or, The thickness of the first transparent conductive layer is between 20 nm and 120 nm; and / or, The thickness of the second transparent conductive layer is between 5 nm and 30 nm.

5. The solar cell according to claim 1, characterized in that, The metal electrode layer includes a plurality of metal electrodes, the height of which is the same as the height of the second transparent conductive layer.

6. The solar cell according to claim 1, characterized in that, The semiconductor substrate comprises, from top to bottom, the following layers stacked sequentially: a first doped semiconductor layer, a first intrinsic semiconductor layer, a silicon substrate, a second intrinsic semiconductor layer, and a second doped semiconductor layer.

7. A method for preparing a solar cell, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having two opposing surfaces; A first transparent conductive layer, a metal seed layer, and an initial second transparent conductive layer are sequentially stacked on at least one surface of the semiconductor substrate; The initial second transparent conductive layer is graphically represented to form a second transparent conductive layer having a plurality of gate grooves, wherein the plurality of gate grooves are arranged at intervals and penetrate the second transparent conductive layer along the stacking direction; A metal electrode layer is formed that fills the grid grooves. The metal electrode layer is electrically connected to the metal seed layer, and the two together constitute the electrode structure.

8. The preparation method according to claim 7, characterized in that, The step of forming a metal electrode layer filling the grid grooves includes: immersing the structure obtained after forming the second transparent conductive layer in a metal salt solution of a predetermined concentration, and performing a chemical and / or electrochemical reaction to grow the metal electrode layer based on the surface of the metal seed layer; wherein... The metal ions in the metal salt solution correspond to the metal in the metal electrode layer; and / or The metal seed layer has a higher metal reactivity than the metal electrode layer.

9. The preparation method according to claim 7, characterized in that, The step of graphically representing the initial second transparent conductive layer to form a second transparent conductive layer having multiple gate grooves includes: A patterned mask is formed on the initial second transparent conductive layer, wherein the patterned mask includes an opening area and a protection area, and the opening area corresponds to the formation position of the gate groove; The initial second transparent conductive layer in the opening region is removed to form a plurality of spaced-apart gate grooves, thereby obtaining the second transparent conductive layer; wherein, The opening width of the grid groove is between 10 μm and 20 μm; The thickness of the second transparent conductive layer is between 5 nm and 30 nm.

10. The preparation method according to claim 7, characterized in that, The semiconductor substrate comprises, from top to bottom, the following layers stacked sequentially: a first doped semiconductor layer, a first intrinsic semiconductor layer, a silicon substrate, a second intrinsic semiconductor layer, and a second doped semiconductor layer; the fabrication method further includes: A first transparent conductive layer, a metal seed layer, a second transparent conductive layer, and a metal electrode layer are respectively formed on the surfaces of the first doped semiconductor layer and the second doped semiconductor layer that are away from the silicon substrate.

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