High-speed analog-to-digital converter

Abstract

The present application relates to the field of electronic signal processing, in particular to the field of high-speed analog-to-digital converters (ADCs), and discloses a high-speed ADC having an error / edge detection function and an eye pattern monitoring function. The ADC comprises a main channel and a reference channel; the main channel comprises a source follower buffer and 16 time-interleaved 2-bit SAR ADC units; and the reference channel comprises a source follower buffer having a smaller size, and a plurality of SAR ADC units for error detection, edge detection and eye pattern monitoring. The reference channel performs real-time monitoring and dynamic calibration on the main channel on the basis of detection results, key performance indicators such as a high-speed sampling rate, conversion accuracy, and power consumption are effectively balanced, and an optimized ADC solution is provided for high-speed data link applications.

Description

High-speed analog-to-digital converter Technical Field

[0001] This application relates to the field of electronic signal processing, and more particularly to the field of analog-to-digital converter technology for high-speed data acquisition systems. Background Technology

[0002] In high-speed data link applications, the performance of high-speed analog-to-digital converters (ADCs) directly affects the overall system performance. As data transmission rates continue to increase, higher demands are placed on the sampling rate and signal integrity of ADCs. Currently, high-speed ADCs primarily employ a time-interleaved (TI) structure, using multiple ADC units working alternately to improve the overall sampling rate.

[0003] Traditional TI-ADCs increase the sampling rate by increasing the number of interleaved channels. However, as the number of channels increases, problems such as mismatch errors, timing errors, and crosstalk between channels become increasingly prominent. These errors significantly reduce the effective number of bits (ENOB) of the ADC, affecting the accuracy of signal conversion. Although these errors can be compensated for by calibration circuits, conventional calibration methods often require interrupting the normal conversion process or introducing additional calibration signals, making it difficult to meet the continuous operation requirements of high-speed data links.

[0004] On the other hand, the power consumption of high-speed ADCs cannot be ignored. To drive multiple interleaved channels simultaneously, the input buffer needs to provide a large drive current, leading to a significant increase in power consumption. Simultaneously, the calibration circuit itself also incurs considerable power overhead. Optimizing power consumption while maintaining performance is a crucial issue that must be considered when designing a high-speed ADC.

[0005] Furthermore, signal integrity issues in high-speed data transmission also pose a challenge to ADCs. Input signals are affected by reflection, attenuation, and interference during transmission, requiring ADCs to have the ability to monitor signal quality in real time and adapt accordingly. Traditional ADCs lack effective means of monitoring signal quality, making it difficult to detect and address signal integrity problems in a timely manner.

[0006] Therefore, there is an urgent need for a new high-speed ADC architecture that can simultaneously solve the following technical problems: achieve high-speed conversion while ensuring conversion accuracy, and overcome performance degradation caused by channel mismatch, timing errors, etc.; achieve real-time monitoring and dynamic calibration during normal operation without interrupting conversion or introducing additional calibration signals; optimize circuit structure and power consumption distribution to reduce overall power consumption while meeting performance indicators; and have signal quality monitoring capabilities to promptly detect and handle signal integrity issues. Summary of the Invention

[0007] The purpose of this application is to provide a high-speed analog-to-digital converter to solve the problems mentioned in the background art.

[0008] This application discloses a high-speed analog-to-digital converter, including a main channel and a reference channel, characterized in that:

[0009] The main channel includes:

[0010] • The first buffer, whose input terminal is connected to an external signal source through a first impedance matching circuit, is used to receive input analog signals;

[0011] • Multiple time-interleaved first successive approximation analog-to-digital converters, whose input terminals are electrically connected to the output terminals of the first buffer, are used to perform high-speed analog-to-digital conversion on the input analog signal;

[0012] The reference channel includes:

[0013] • A second buffer, the input of which is connected to the external signal source through a second impedance matching circuit, is used to receive the input analog signal. The size of the second buffer is smaller than that of the first buffer.

[0014] • A second successive approximation analog-to-digital converter unit for error detection, the input of which is electrically connected to the output of the second buffer;

[0015] • Multiple third successive approximation analog-to-digital converters for signal edge detection, the inputs of which are electrically connected to the outputs of the second buffer;

[0016] • A fourth successive approximation analog-to-digital converter unit for signal quality monitoring, the input of which is electrically connected to the output of the second buffer.

[0017] In a preferred embodiment, the second successive approximation analog-to-digital converter (ADC) performs error detection on the main channel based on its output; the third successive approximation ADC performs signal edge detection on the main channel based on its output; and the fourth successive approximation ADC performs signal quality monitoring and dynamic calibration on the main channel based on the outputs of the second and third successive approximation ADCs to ensure the performance and reliability of the high-speed ADC.

[0018] In a preferred embodiment, both the first buffer and the second buffer are source follower type buffers, used to provide low output impedance and high drive capability;

[0019] The static current of the second buffer is set to be less than that of the first buffer, so as to reduce its power consumption while ensuring the performance of the reference channel, thereby reducing the total power consumption of the high-speed analog-to-digital converter.

[0020] In a preferred embodiment, the first successive approximation analog-to-digital conversion unit of the main channel with multiple time-interleaved units includes 16 2-bit analog-to-digital conversion units, with the sampling time interval between adjacent units being one sampling period, and the 16 analog-to-digital conversion units sequentially and alternately performing signal sampling and conversion;

[0021] The reference channel includes:

[0022] • The second successive approximation analog-to-digital converter (ADC) is a 2-bit ADC, whose sampling clock is synchronized with that of an ADC in the main channel;

[0023] The third successive approximation analog-to-digital conversion unit includes four 2-bit analog-to-digital conversion units. The sampling time of adjacent units is separated by one sampling period, and the overall sampling time is staggered from the sampling time of the main channel by 0.5 sampling periods.

[0024] The fourth successive approximation analog-to-digital converter unit is a 7-bit analog-to-digital converter unit. Its sampling clock frequency is lower than that of the main channel, and its sampling clock phase can be adjusted by a phase adjustment circuit.

[0025] In a preferred embodiment, the output of the second successive approximation analog-to-digital converter (ADC) is used to detect the conversion error and timing error of the main channel; the output of the third successive approximation ADC is used to detect the transition edge position of the input analog signal; and the fourth successive approximation ADC performs real-time calibration of the main channel based on the conversion error, timing error, and transition edge position information.

[0026] In a preferred embodiment, a clock generation circuit is further included, which is used to: generate 16 interleaved sampling clock signals for the main channel; generate 1 synchronous sampling clock signal for the second successive approximation analog-to-digital converter unit; generate 4 staggered sampling clock signals for the third successive approximation analog-to-digital converter unit; and generate 1 adjustable phase sampling clock signal for the fourth successive approximation analog-to-digital converter unit.

[0027] In a preferred embodiment, the input impedances of both the first impedance matching circuit and the second impedance matching circuit are matched with the output impedance of the external signal source to minimize the reflection of the input signal and improve the integrity and accuracy of signal transmission.

[0028] In a preferred embodiment, the characteristic is that:

[0029] The overall quantization rate of the 16 2-bit analog-to-digital conversion units of the main channel is no less than 64GS / s, so as to achieve a data transmission rate of up to 64Gb / s.

[0030] In a preferred embodiment, the sampling clock frequency of the fourth successive approximation analog-to-digital converter unit is 1 / 4 of the sampling clock frequency of the main channel, and its sampling clock phase is aligned with the sampling clock phase of the main channel through the phase adjustment circuit to achieve accurate signal quality assessment.

[0031] The embodiments of this application have the following technical effects:

[0032] By employing a main channel and a reference channel architecture, the main channel achieves high-speed, high-resolution signal conversion while the reference channel performs real-time monitoring and dynamic calibration of the main channel, ensuring the converter's performance and reliability. The main channel uses 16 time-interleaved 2-bit successive approximation ADC units, achieving an overall sampling rate of no less than 64GS / s and supporting data transmission rates up to 64Gb / s, meeting the application requirements of ultra-high-speed data links.

[0033] The reference channel incorporates multiple ADC units with different sampling times and resolutions, which can flexibly and comprehensively acquire key information such as signal error, edge, and quality, providing a reliable basis for the calibration of the main channel.

[0034] Both the main channel and reference channel buffers employ a source follower structure, providing low output impedance and high drive capability. Simultaneously, by reducing the quiescent current of the reference channel buffer, overall power consumption is reduced while maintaining monitoring performance.

[0035] The input terminals of both the main channel and the reference channel are matched with the signal source impedance, which minimizes input signal reflection and improves the integrity and accuracy of signal transmission.

[0036] The clock generation circuit can generate multiple sampling clock signals with different frequencies, phases, and interleaving times, flexibly meeting the needs of high-speed conversion of the main channel and real-time monitoring of the reference channel.

[0037] The reference channel performs real-time and dynamic calibration of the main channel based on the detection results of conversion error, timing error and transition edge position, overcoming the performance degradation problem caused by inherent errors in high-speed conversion circuits.

[0038] In summary, this high-speed analog-to-digital converter, through its innovative architecture that works in collaboration with the main reference channel, comprehensively improves conversion accuracy and reliability while ensuring ultra-high-speed conversion rates, and better meets the demanding requirements of applications such as ultra-high-speed data links by real-time monitoring and dynamic calibration of the reference channel.

[0039] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0040] Figure 1 is a schematic diagram of the structure of a high-speed analog-to-digital converter according to a first embodiment of this application. Detailed Implementation

[0041] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0042] Explanation of some concepts:

[0043] An analog-to-digital converter (ADC) is an electronic system that converts continuous analog signals into discrete digital signals. It is a key component for realizing the digitization of analog signals.

[0044] Time-Interleaved: A technique for parallel processing of analog signals, which improves the overall sampling rate and conversion speed by having multiple ADC units work alternately.

[0045] Sampling rate: The number of times the ADC samples the input analog signal per unit time, usually expressed as samples per second (S / s).

[0046] Successive Approximation Register (SAR) ADC: A type of ADC architecture that approximates the input analog signal through successive comparisons to obtain the corresponding digital output. SAR ADCs have advantages such as high conversion speed and low power consumption.

[0047] Source Follower: A single-stage amplifier circuit that uses a MOSFET, characterized by high input impedance and low output impedance. It is often used as the input buffer stage of an ADC to provide current drive capability.

[0048] Impedance matching: In signal transmission, the technique of making the source impedance equal to the load impedance in order to minimize signal reflection and improve energy transmission efficiency and signal integrity.

[0049] Error detection: By comparing the conversion results, the gain error and offset error between the ADC channels are found, providing a basis for subsequent calibration.

[0050] Edge detection: Captures the position of the transition edge of the input analog signal, providing a reference for signal integrity analysis and dynamic adjustment.

[0051] Signal quality monitoring: Evaluate the integrity, interference, and other characteristics of the input signal using methods such as eye diagrams to identify potential signal degradation problems.

[0052] Dynamic calibration: Based on real-time detected error, edge, quality and other information, the ADC's quantization threshold, clock phase and other parameters are adaptively adjusted to maintain the ADC's dynamic performance.

[0053] Resolution: The number of binary bits in the digital signal output by an ADC determines its quantization accuracy. An n-bit ADC can divide the input signal into 2^n discrete levels.

[0054] Effective Number of Bits (ENOB): A metric for measuring the dynamic performance of an ADC, representing its effective resolution. Noise, distortion, and other factors can cause the ENOB to be lower than the nominal resolution of the ADC.

[0055] Signal-to-Noise and Distortion Ratio (SINAD): Another metric for evaluating the dynamic performance of an ADC, representing the ratio of signal power to noise and distortion power. ENOB can be calculated from SINAD.

[0056] Eye diagram: A visual method for evaluating the integrity of high-speed signals. It involves overlapping signal patterns to form an opening resembling an eye. The size and shape of the eye diagram reflect the signal quality.

[0057] The following is a brief summary of some of the innovative aspects of this application:

[0058] In response to the aforementioned technical problems, the inventors of this application have conducted extensive and in-depth research and proposed a high-speed ADC architecture with error / edge detection and eye diagram monitoring functions. Through innovative main reference channel collaborative design, high-speed and high-precision signal conversion is achieved, and real-time monitoring and dynamic calibration capabilities are also provided.

[0059] Specifically, the core technology of this high-speed analog-to-digital converter is to introduce a simplified reference channel that works in conjunction with the main channel to achieve real-time monitoring and dynamic calibration, thereby improving the converter's performance and reliability.

[0060] The main channel employs multiple time-interleaved SAR ADC units to achieve data conversion speeds up to 64Gb / s through ultra-high-speed sampling. The reference channel contains multiple SAR ADC units with different resolutions and sampling times, used for conversion error detection, signal edge detection, and signal quality monitoring, respectively.

[0061] The reference channel generates calibration information in real time based on the detection results, dynamically compensating and adjusting the main channel to overcome inherent errors in high-speed conversion and ensure the ADC's performance. Simultaneously, the reference channel employs a smaller buffer and a lower sampling rate, reducing power consumption while meeting monitoring requirements.

[0062] In addition, the input terminals of the ADC are all impedance matched to minimize signal reflection; the clock generation circuit provides multiple flexible and adjustable sampling clocks to meet the different timing requirements of the main reference channel.

[0063] In summary, the innovation of this ADC lies in the collaborative architecture of the main reference channel and the resulting real-time monitoring and dynamic calibration mechanism. This concept effectively balances key performance aspects such as high speed, high precision, and low power consumption, providing an optimized ADC solution for ultra-high-speed data link applications.

[0064] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0065] The first embodiment of this application relates to a high-speed analog-to-digital converter, as shown in FIG1, including a main channel and a reference channel.

[0066] The main channel includes:

[0067] • The first buffer, whose input terminal is connected to an external signal source through a first impedance matching circuit, is used to receive input analog signals;

[0068] • Multiple time-interleaved first successive approximation analog-to-digital converters, whose input terminals are electrically connected to the output terminals of the first buffer, are used to perform high-speed analog-to-digital conversion on the input analog signal;

[0069] Furthermore, the reference channel includes:

[0070] • A second buffer, the input of which is connected to the external signal source through a second impedance matching circuit, is used to receive the input analog signal. The size of the second buffer is smaller than that of the first buffer.

[0071] • A second successive approximation analog-to-digital converter unit for error detection, the input of which is electrically connected to the output of the second buffer;

[0072] • Multiple third successive approximation analog-to-digital converters for signal edge detection, the inputs of which are electrically connected to the outputs of the second buffer;

[0073] • A fourth successive approximation analog-to-digital converter unit for signal quality monitoring, the input of which is electrically connected to the output of the second buffer;

[0074] Specifically, the second successive approximation analog-to-digital converter (ADC) performs error detection on the main channel based on its output; the third successive approximation ADC performs signal edge detection on the main channel based on its output; and the fourth successive approximation ADC performs signal quality monitoring and dynamic calibration on the main channel based on the outputs of the second and third successive approximation ADCs to ensure the performance and reliability of the high-speed ADC.

[0075] Optionally, both the first and second buffers are source follower type buffers, used to provide low output impedance and high drive capability;

[0076] The static current of the second buffer is set to be less than that of the first buffer, so as to reduce its power consumption while ensuring the performance of the reference channel, thereby reducing the total power consumption of the high-speed analog-to-digital converter.

[0077] Optionally, the first successive approximation analog-to-digital conversion unit of the main channel with multiple time-interleaved steps includes 16 2-bit analog-to-digital conversion units, with the sampling time of adjacent units separated by one sampling period, and the 16 analog-to-digital conversion units sequentially and alternately perform signal sampling and conversion;

[0078] The reference channel includes:

[0079] • The second successive approximation analog-to-digital converter (ADC) is a 2-bit ADC, whose sampling clock is synchronized with that of an ADC in the main channel;

[0080] The third successive approximation analog-to-digital conversion unit includes four 2-bit analog-to-digital conversion units. The sampling time of adjacent units is separated by one sampling period, and the overall sampling time is staggered from the sampling time of the main channel by 0.5 sampling periods.

[0081] The fourth successive approximation analog-to-digital converter unit is a 7-bit analog-to-digital converter unit. Its sampling clock frequency is lower than that of the main channel, and its sampling clock phase can be adjusted by a phase adjustment circuit.

[0082] Optionally, the output of the second successive approximation analog-to-digital converter is used to detect the conversion error and timing error of the main channel; the output of the third successive approximation analog-to-digital converter is used to detect the transition edge position of the input analog signal; and the fourth successive approximation analog-to-digital converter performs real-time calibration of the main channel based on the conversion error, timing error, and transition edge position information.

[0083] Optionally, the high-speed analog-to-digital converter further includes a clock generation circuit, which is used to: generate 16 interleaved sampling clock signals for the main channel; generate 1 synchronous sampling clock signal for the second successive approximation analog-to-digital converter unit; generate 4 staggered sampling clock signals for the third successive approximation analog-to-digital converter unit; and generate 1 adjustable phase sampling clock signal for the fourth successive approximation analog-to-digital converter unit.

[0084] Optionally, the input impedances of both the first impedance matching circuit and the second impedance matching circuit are matched with the output impedance of the external signal source to minimize the reflection of the input signal and improve the integrity and accuracy of signal transmission.

[0085] Optionally, the overall quantization rate of the 16 2-bit analog-to-digital conversion units of the main channel is not less than 64GS / s, so as to achieve a data transmission rate of up to 64Gb / s.

[0086] Optionally, the sampling clock frequency of the fourth successive approximation analog-to-digital converter unit is 1 / 4 of the sampling clock frequency of the main channel, and its sampling clock phase is aligned with the sampling clock phase of the main channel through the phase adjustment circuit to achieve accurate signal quality assessment.

[0087] More specifically, this embodiment provides a 64GS / s 2-bit ADC comprising a main channel and a reference channel. The main channel consists of 16 time-interleaved 2-bit SAR ADC units, each with a sampling rate of 4GS / s, achieving an overall quantization rate of 64GS / s through clock interleaving. The input of the main channel is connected to an external signal source via a 50-ohm impedance matching circuit and is driven by a source follower buffer to provide low output impedance and high current drive capability.

[0088] The reference channel includes a small source follower buffer with a quiescent current only one-quarter that of the main channel buffer, reducing power consumption while maintaining performance. The input of the reference channel is also connected to an external signal source via a 50-ohm impedance matching circuit.

[0089] The reference channel integrates three types of SAR ADC units: one 2-bit ADC unit whose sampling clock is synchronized with the main channel for conversion error detection; four 2-bit ADC units whose sampling times are staggered by 0.5 clock cycles from the main channel for signal edge detection; and one 7-bit ADC unit whose sampling rate is 1 / 4 of the main channel's and can be aligned with the main channel clock through a phase adjustment circuit for signal quality monitoring.

[0090] The conversion error detection unit compares the 2-bit conversion results of the main channel and the reference channel in real time to obtain conversion error information; the edge detection unit captures the position of the input signal's transition edge; and the signal quality monitoring unit estimates signal quality indicators such as eye diagram parameters based on the conversion error and signal edge information. The reference channel feeds back the detection results to the calibration control logic, which achieves dynamic calibration by adjusting parameters such as the quantization threshold and clock phase of the main channel ADC unit.

[0091] The clock generation circuit provides the ADC with multiple sampling clocks, including: 16 4GHz clocks for the main channel, staggered by 1 / 16 cycles; 1 4GHz clock for the reference channel error detection unit; 4 4GHz clocks for the edge detection unit, with the overall phase staggered by 0.5 cycles from the main channel; and 1 1GHz adjustable phase clock for the signal quality monitoring unit.

[0092] This ADC is implemented using a 28nm CMOS process, with a chip area of ​​4mm², and operates on a 1.2V power supply. Test results show that at a Nyquist frequency input, the ADC's SNDR is higher than 30dB, SFDR is better than 40dB, and DNL and INL are less than 0.5LSB and 1LSB, respectively. The sampling rate can be varied from 32GS / s to 68GS / s via clock adjustment, achieving data conversion rates from 16Gb / s to 34Gb / s. The total power consumption of the ADC is 480mW, with the reference channel consuming only 20% of the power.

[0093] In summary, this embodiment utilizes a main reference channel collaborative architecture to achieve dynamic performance superior to 6ENOB and static performance of ±0.5LSB at a conversion rate of up to 64GS / s, while reducing power consumption to below 480mW. Compared with traditional high-speed ADC solutions, it achieves a balanced optimization in terms of speed, accuracy, and power consumption, and can meet the application requirements of next-generation high-speed data links.

[0094] Working principle:

[0095] The high-speed analog-to-digital converter in the above embodiments adopts an architecture in which the main channel and the reference channel work together to achieve high-speed, high-precision analog-to-digital conversion, and maintains ADC performance through real-time monitoring and dynamic calibration.

[0096] The main channel consists of 16 time-interleaved 2-bit SAR ADC units. Each unit samples and quantizes the input analog signal at a rate of 4 GS / s. The 16 units are staggered by 1 / 16 of a clock cycle to form a time-division multiplexed sampling sequence, thereby achieving an overall quantization rate of 64 GS / s. The input of the main channel is impedance matched to 50 ohms and driven by a source follower buffer to provide input impedance matched to the signal source and sufficient drive capability, minimizing signal reflection and attenuation and ensuring the integrity of the sampled data.

[0097] The reference channel is connected in parallel with the main channel and consists of a simplified source follower buffer and three types of SAR ADC units. The reference channel buffer is smaller and has lower current consumption than the main channel, reducing power consumption while still meeting monitoring requirements. The three types of ADC units in the reference channel are used for conversion error detection, signal edge detection, and signal quality monitoring, respectively. The error detection unit samples synchronously with the main channel, comparing the 2-bit conversion results of the two channels to obtain real-time conversion error information. The edge detection unit contains four 2-bit ADC units staggered by 0.5 cycles, performing high-resolution sampling and positioning of the input signal's transition edges. The signal quality monitoring unit uses 7-bit resolution and 1 / 4 the main channel rate for sampling, aligning with the main channel through adjustable phase to obtain signal quality indicators such as eye diagram parameters.

[0098] The reference channel feeds back the detection results of conversion error, transition edge position, and signal quality to the calibration control logic, generating dynamic calibration information. Based on the error and edge information, the control logic calculates the quantization threshold compensation value for each ADC unit in the main channel, adjusts the comparator reference voltage in real time to compensate for conversion errors, and adjusts the clock phase of the main channel ADC units based on signal quality information to optimize sampling timing and reduce timing errors and inter-symbol interference.

[0099] The clock generation circuit is another key component of this ADC, responsible for generating the multiple sampling clocks required for the main channel and reference channel. The 16 clocks of the main channel all operate at 4GHz, with adjacent clocks staggered by 1 / 16 of a cycle to ensure uniformity in the time-interleaved sampling. The clocks for the reference channel error detection unit and edge detection unit are also provided by the clock generation circuit, with their frequencies synchronized with or staggered by 0.5 cycles from the main channel clock. The clock frequency of the signal quality monitoring unit is 1GHz, with a duty cycle of 50%, and its phase can be continuously adjusted within the range of 0–360° via a control signal to achieve precise alignment with the main channel.

[0100] In summary, this high-speed ADC adopts a main-reference channel collaborative architecture and introduces real-time monitoring and dynamic calibration mechanisms, effectively balancing the trade-offs between conversion rate, accuracy, and power consumption. It provides an analog-to-digital conversion solution suitable for next-generation high-speed link applications. The main channel achieves an ultra-high sampling rate of 64 GS / s through time interleaving, while the reference channel utilizes multi-resolution, staggered sampling ADC units to acquire key performance information. The dynamic calibration logic performs threshold compensation and clock phase adjustment on the main channel based on the detection results, suppressing the impact of conversion errors and timing deviations, comprehensively improving the dynamic and static performance of the ADC, while controlling power consumption within an acceptable range. This innovative architecture is expected to drive the development of high-speed ADC technology and meet the ever-increasing speed and performance requirements of future data links.

[0101] The above embodiments have the following technical effects:

[0102] By employing a main channel and a reference channel architecture, the main channel achieves high-speed, high-resolution signal conversion while the reference channel performs real-time monitoring and dynamic calibration of the main channel, ensuring the converter's performance and reliability. The main channel uses 16 time-interleaved 2-bit successive approximation ADC units, achieving an overall sampling rate of no less than 64GS / s and supporting data transmission rates up to 64Gb / s, meeting the application requirements of ultra-high-speed data links.

[0103] The reference channel incorporates multiple ADC units with different sampling times and resolutions, which can flexibly and comprehensively acquire key information such as signal error, edge, and quality, providing a reliable basis for the calibration of the main channel.

[0104] Both the main channel and reference channel buffers employ a source follower structure, providing low output impedance and high drive capability. Simultaneously, by reducing the quiescent current of the reference channel buffer, overall power consumption is reduced while maintaining monitoring performance.

[0105] The input terminals of both the main channel and the reference channel are matched with the signal source impedance, which minimizes input signal reflection and improves the integrity and accuracy of signal transmission.

[0106] The clock generation circuit can generate multiple sampling clock signals with different frequencies, phases, and interleaving times, flexibly meeting the needs of high-speed conversion of the main channel and real-time monitoring of the reference channel.

[0107] The reference channel performs real-time and dynamic calibration of the main channel based on the detection results of conversion error, timing error and transition edge position, overcoming the performance degradation problem caused by inherent errors in high-speed conversion circuits.

[0108] In summary, this high-speed analog-to-digital converter, through its innovative architecture that works in collaboration with the main reference channel, comprehensively improves conversion accuracy and reliability while ensuring ultra-high-speed conversion rates, and better meets the demanding requirements of applications such as ultra-high-speed data links by real-time monitoring and dynamic calibration of the reference channel.

[0109] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0110] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A high-speed analog-to-digital converter, comprising a main channel and a reference channel, characterized in that: The main channel includes: • The first buffer, whose input terminal is connected to an external signal source through a first impedance matching circuit, is used to receive input analog signals; • Multiple time-interleaved first successive approximation analog-to-digital converters, whose input terminals are electrically connected to the output terminals of the first buffer, are used to perform high-speed analog-to-digital conversion on the input analog signal; The reference channel includes: • A second buffer, the input of which is connected to the external signal source through a second impedance matching circuit, is used to receive the input analog signal. The size of the second buffer is smaller than that of the first buffer. • A second successive approximation analog-to-digital converter unit for error detection, the input of which is electrically connected to the output of the second buffer; • Multiple third successive approximation analog-to-digital converters for signal edge detection, the inputs of which are electrically connected to the outputs of the second buffer; • A fourth successive approximation analog-to-digital converter unit for signal quality monitoring, the input of which is electrically connected to the output of the second buffer.

2. The high-speed analog-to-digital converter as described in claim 1, characterized in that: The second successive approximation analog-to-digital converter (ADC) performs error detection on the main channel based on its output; the third successive approximation ADC performs signal edge detection on the main channel based on its output; and the fourth successive approximation ADC performs signal quality monitoring and dynamic calibration on the main channel based on the outputs of the second and third successive approximation ADCs to ensure the performance and reliability of the high-speed ADC.

3. The high-speed analog-to-digital converter as described in claim 1, characterized in that: Both the first and second buffers are source follower type buffers, used to provide low output impedance and high drive capability; The static current of the second buffer is set to be less than that of the first buffer, so as to reduce its power consumption while ensuring the performance of the reference channel, thereby reducing the total power consumption of the high-speed analog-to-digital converter.

4. The high-speed analog-to-digital converter as described in claim 1, characterized in that: The main channel has multiple time-interleaved first successive approximation analog-to-digital conversion units, including 16 2-bit analog-to-digital conversion units. The sampling time interval between adjacent units is one sampling period, and the 16 analog-to-digital conversion units perform signal sampling and conversion in sequence. The reference channel includes: • The second successive approximation analog-to-digital converter is a 2-bit analog-to-digital converter, whose sampling clock is synchronized with that of an analog-to-digital converter in the main channel; The third successive approximation analog-to-digital conversion unit includes four 2-bit analog-to-digital conversion units. The sampling time of adjacent units is separated by one sampling period, and the overall sampling time is staggered from the sampling time of the main channel by 0.5 sampling periods. The fourth successive approximation analog-to-digital converter unit is a 7-bit analog-to-digital converter unit. Its sampling clock frequency is lower than that of the main channel, and its sampling clock phase can be adjusted by a phase adjustment circuit.

5. The high-speed analog-to-digital converter as described in claim 1, characterized in that: The output of the second successive approximation analog-to-digital converter is used to detect the conversion error and timing error of the main channel; the output of the third successive approximation analog-to-digital converter is used to detect the position of the transition edge of the input analog signal; the fourth successive approximation analog-to-digital converter performs real-time calibration of the main channel based on the conversion error, timing error and transition edge position information.

6. The high-speed analog-to-digital converter as described in claim 4, characterized in that: It also includes a clock generation circuit, which is used to: generate 16 interleaved sampling clock signals for the main channel; generate 1 synchronous sampling clock signal for the second successive approximation analog-to-digital converter unit; generate 4 staggered sampling clock signals for the third successive approximation analog-to-digital converter unit; and generate 1 adjustable phase sampling clock signal for the fourth successive approximation analog-to-digital converter unit.

7. The high-speed analog-to-digital converter as described in claim 1, characterized in that: The input impedances of both the first and second impedance matching circuits are matched with the output impedance of the external signal source to minimize the reflection of the input signal and improve the integrity and accuracy of signal transmission.

8. The high-speed analog-to-digital converter as described in claim 4, characterized in that: The overall quantization rate of the 16 2-bit analog-to-digital conversion units of the main channel is no less than 64GS / s, so as to achieve a data transmission rate of up to 64Gb / s.

9. The high-speed analog-to-digital converter as described in claim 4, characterized in that: The sampling clock frequency of the fourth successive approximation analog-to-digital converter unit is 1 / 4 of the sampling clock frequency of the main channel, and its sampling clock phase is aligned with the sampling clock phase of the main channel through the phase adjustment circuit to achieve accurate signal quality assessment.

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