Input / output circuit

Abstract

This input / output circuit (1) comprises: three P-type transistors (P1, P2, P3) connected in series between a first power supply and an input / output terminal (INOUT); three N-type transistors (N1, N2, N3) connected in series between the input / output terminal (INOUT) and a fourth power supply; an N-type transistor (N4) and a P-type transistor (P4) connected in series between a second power supply and a third power supply; an N-type transistor (N5) and a P-type transistor (P5) connected in series between the second power supply and the third power supply; and inverter circuits (60, 70) having a loop configuration in which the input node of one inverter circuit and the output node of the other inverter circuit are connected.

Description

Input / Output Circuit

[0001] The present disclosure relates to an input / output circuit of an IO cell that outputs a signal to the outside of a semiconductor device (LSI (Large Scale Integration)) or inputs a signal from the outside of the semiconductor device.

[0002] In conventional semiconductor devices, a transistor with a thick gate (high breakdown voltage transistor) and a transistor with a thin gate (low breakdown voltage transistor) having a lower breakdown voltage than the thick gate transistor have been prepared. Generally, a high breakdown voltage transistor has a high allowable voltage stress (breakdown voltage) and is used in an IO cell that communicates a high voltage signal with the outside of the LSI. A low breakdown voltage transistor is used in an internal cell (such as a memory cell or a standard cell) that handles a relatively low voltage signal.

[0003] In recent years, due to manufacturing reasons associated with transistor miniaturization, etc., semiconductor devices without high breakdown voltage transistors have been studied. In the future, since communication of a relatively high voltage signal (such as 1.8 V) may occur, an IO cell that handles a high voltage signal using only low breakdown voltage transistors has been studied.

[0004] For example, Patent Document 1 discloses an output circuit of an IO cell that outputs a voltage signal several times the breakdown voltage of a transistor.

[0005] U.S. Patent No. 9,214,933

[0006] However, further reduction of the transistor breakdown voltage due to the progress of miniaturization and a decrease in the operating voltage associated therewith are assumed, but there is no input / output circuit that can flexibly and easily adapt to them. Also, in an input circuit having a Schmitt trigger function, it becomes even more difficult to generate hysteresis, and the resistance to noise mixed in the input signal becomes weak.

[0007] In view of the above problems, an object of the present disclosure is to solve the above problems.

[0008] In one aspect of the present disclosure, an input / output circuit outputs an output signal that changes in accordance with a first input signal from an input / output terminal and receives a second input signal input to the input / output terminal, comprising: a first P-type transistor whose source is connected to a first power supply, whose drain is connected to a first node, and whose gate receives a signal that changes in accordance with the first input signal; a second P-type transistor whose source is connected to the first node, whose drain is connected to a second node, and whose gate is connected to a second power supply having a lower power supply voltage than the first power supply; a third P-type transistor whose source is connected to the second node, whose drain is connected to the input / output terminal, and whose gate is connected to a third node; a first N-type transistor whose drain is connected to the input / output terminal, whose source is connected to a fourth node, and whose gate is connected to the third node; a second N-type transistor whose drain is connected to the fourth node, whose source is connected to a fifth node, and whose gate is connected to a third power supply having a lower power supply voltage than the second power supply; and The inverter comprises: a third N-type transistor whose input is connected to the fifth node, whose source is connected to a fourth power supply having a lower power supply voltage than the third power supply, and whose gate receives a signal that changes according to the first input signal; a fourth N-type transistor whose drain is connected to the second power supply, whose source is connected to the third node, and whose gate is connected to the second node; a fourth P-type transistor whose source is connected to the third node, whose drain is connected to the third power supply, and whose gate is connected to the fourth node; a fifth N-type transistor whose drain is connected to the second power supply, whose source is connected to the sixth node, whose drain is connected to the third power supply, and whose gate is connected to the fourth node; a first inverter circuit whose input is connected to the sixth node and whose output is connected to the seventh node; and a second inverter circuit whose input is connected to the seventh node and whose output is connected to the sixth node.

[0009] By adopting the above configuration, an input / output circuit with a Schmitt trigger function is realized. In the above embodiment of the input / output circuit, in the input mode in which a second input signal is input, a current is generated for a predetermined period of time, flowing from the second power supply to the third power supply via the fifth P-type transistor or the fifth N-type transistor, in accordance with the rising or falling edge of the second input signal. As a result, the rising or falling edge of the voltage at the sixth node becomes gradual, and a hysteresis wider than the difference between the second power supply and the third power supply can be generated.

[0010] Furthermore, since the voltage across each terminal of each transistor is maintained below the transistor's breakdown voltage during the operation of the input / output circuit, the aging degradation of each transistor can be effectively prevented.

[0011] The input / output circuit according to this disclosure has a Schmitt trigger function and can generate a hysteresis wider than the difference between the second and third power supplies. Furthermore, since the voltage across each terminal of each transistor is maintained below the transistor's breakdown voltage during the operation of the input / output circuit, the aging degradation of each transistor can be effectively prevented.

[0012] Circuit diagram of the input / output circuit according to the first embodiment Waveform diagram showing an example of operation in the input mode of the input / output circuit of Figure 1 Waveform diagram showing an example of operation in the output mode of the input / output circuit of Figure 1 Circuit diagram of the input / output circuit according to the second embodiment Circuit diagram of the input / output circuit according to the third embodiment Circuit diagram of the input / output circuit according to the fourth embodiment Circuit diagram of the input / output circuit according to modified example 1 Circuit diagram of another input / output circuit according to modified example 1 Truth table showing the operation of the circuit in Figure 8 Circuit diagram of the input / output circuit according to modified example 2 Circuit diagram of another input / output circuit according to modified example 2

[0013] The embodiments will be described below with reference to the drawings.

[0014] In this disclosure, "connection" is a broad concept encompassing electrical connection, including not only direct connections but also indirect electrical connections via passive elements, etc. The circuit diagrams shown below are simplified illustrations focusing on the components relevant to this disclosure. Therefore, components shown as directly connected may, in actual circuit configurations, be indirectly connected due to other components being positioned between them. Furthermore, in this disclosure, "terminal" refers to an entry and exit point for current provided for the connection of an electrical circuit. For example, it is not intended to be limited to specific configurations such as semiconductor pads; wiring and vias connecting circuits and components may also qualify as terminals.

[0015] Furthermore, in the following explanation, common symbols or names may be used to describe the nodes and terminals of a circuit and the signals passing through those nodes and terminals, and common symbols may be used to describe the power supply name and the power supply voltage of that power supply. Also, regarding the voltage of terminals and nodes, only the symbol indicating the voltage may be used, and it may be written as "(terminal name or node name) = (symbol indicating voltage)". Specifically, for example, if the voltage of the input / output terminal INOUT is VDD (voltage of power supply VDD), it may be written as "INOUT = VDD".

[0016] 1. Figure 1 of the First Embodiment is a circuit diagram of an input / output circuit according to the first embodiment. Specifically, the input / output circuit 1 receives a first input signal IN1 and outputs a first output signal OUT1 (corresponding to an output signal) which changes according to the first input signal IN1 to the input / output terminal INOUT. The first input signal IN1 is, for example, a signal output from an internal circuit (not shown) of a semiconductor device (LSI). The input / output circuit 1 also receives a second input signal IN2 input to the input / output terminal INOUT and outputs a second output signal OUT2 which changes according to the second input signal IN2 to the internal output terminal C. The input / output circuit 1 is a circuit using a low-voltage transistor and is capable of inputting and outputting voltage signals approximately three times the transistor's breakdown voltage. The input / output circuit 1 is provided, for example, in the IO cell (signal input / output section) of an LSI. In this case, the input / output pad of the LSI corresponds to the input / output terminal INOUT.

[0017] The first input signal IN1 transitions between VSS and VDD, and the first output signal OUT1 transitions between VSS and 3VDD. VDD is the power supply voltage of power supply VDD (corresponding to the third power supply), 2VDD is the power supply voltage of power supply 2VDD (corresponding to the second power supply), 3VDD is the power supply voltage of power supply 3VDD (corresponding to the first power supply), and VSS is the power supply voltage of ground VSS (corresponding to the fourth power supply). The relative magnitudes of these power supply voltages are "VSS < VDD < 2VDD < 3VDD". For example, VDD is a low voltage of less than 1.0 [V], and typically decreases with the miniaturization of transistors. For example, 2VDD is twice the voltage of VDD, and 3VDD is three times the voltage of VDD.

[0018] 1-1. Configuration of the Input / Output Circuit As shown in Diagram 1, the input / output circuit 1 comprises an output circuit 2 and an input circuit 3. The output circuit 2 comprises an output driver 10, a control circuit 20, and a buffer circuit 30. The input circuit 3 comprises an input buffer circuit 40 and a step-down circuit 50. Note that each transistor described below is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, there is no intention to limit it to MOSFETs, and alternative transistors or switching elements may be used.

[0019] The input / output circuit 1 can be switched between operating in input mode, receiving a second input signal IN2 from the input / output terminal INOUT, or in output mode, outputting a first output signal OUT1 from the input / output terminal INOUT, based on the mode switching signal EN input from the mode switching terminal EN.

[0020] (1) Output Driver The output driver 10 is a circuit that outputs a first output signal OUT1 (amplitude: VSS to 3VDD), which changes in accordance with a first input signal IN1 (amplitude: VSS to VDD) input to the internal input terminal IN1, to the input / output terminal INOUT. The specific operation of the output driver 10 will be explained later. The internal input terminal IN1 is, for example, a node that connects a circuit within the LSI (not shown) to the output driver 10.

[0021] The output driver 10 includes P-type transistors P1, P2, and P3 connected in series between the power supply 3VDD and the input / output terminal INOUT, and N-type transistors N3, N2, and N1 connected in series between the input / output terminal INOUT and the ground VSS. The P-type transistors P1, P2, P3, and P4 (described later) and the N-type transistors N1, N2, N3, and N4 (described later) are so-called low-voltage transistors. In the following, when P-type transistors P1 to P4 and N-type transistors N1 to N4 are described without distinction, they may be collectively referred to simply as "low-voltage transistors." In this example, low-voltage transistors are transistors that, when viewed individually, have a voltage rating of VDD + α. α is, for example, a value approximately equal to the threshold voltage of the transistor.

[0022] The P-type transistor P1 (corresponding to the first P-type transistor) has its source connected to power supply 3VDD and its drain connected to node n1 (corresponding to the first node). The gate of the P-type transistor P1 is connected to the output 31 of the buffer circuit 30 via node n6, and receives a signal from the buffer circuit 30 that changes according to the first input signal IN1. The P-type transistor P2 (corresponding to the second P-type transistor) has its source connected to node n1, its drain connected to node n2 (corresponding to the second node), and its gate connected to power supply 2VDD. The P-type transistor P3 (corresponding to the third P-type transistor) has its source connected to node n2, its drain connected to the input / output terminal INOUT, and its gate connected to node n3 (corresponding to the third node).

[0023] N-type transistor N3 (corresponding to the first N-type transistor) has its drain connected to the input / output terminal INOUT, its source connected to node n4 (corresponding to the fourth node), and its gate connected to node n3. N-type transistor N2 (corresponding to the second N-type transistor) has its drain connected to node n4, its source connected to node n5 (corresponding to the fifth node), and its gate connected to the power supply VDD. N-type transistor N1 (corresponding to the third N-type transistor) has its drain connected to node n5 and its source connected to ground VSS. The gate of N-type transistor N1 is connected to the output 32 of buffer circuit 30 via node n7, and receives a signal from buffer circuit 30 that changes according to the first input signal IN1.

[0024] (2) Control circuit The control circuit 20 is a circuit that controls the gate voltages of the P-type transistor P3 and the N-type transistor N3, i.e., the voltage amplitude of node n3, in the range of VDD to 2VDD, according to the voltages of nodes n2 and n4.

[0025] The control circuit 20 includes an N-type transistor N4 (corresponding to a fourth N-type transistor) and a P-type transistor P4 (corresponding to a fourth P-type transistor) connected in series between the power supply 2VDD and the power supply VDD. The drain of the N-type transistor N4 is connected to the power supply 2VDD, the source is connected to node n3, and the gate is connected to node n2. The source of the P-type transistor P4 is connected to node n3, the drain is connected to the power supply VDD, and the gate is connected to node n4.

[0026] (3) Buffer Circuit The buffer circuit 30 propagates a signal that changes in response to the first input signal IN1 to nodes n6 and n7. Specifically, the buffer circuit 30 propagates a signal that changes between 3VDD and 2VDD as output 31 to node n6 in response to the change in the first input signal IN1 from VSS to VDD. In other words, the buffer circuit 30 shifts (boosts) the first input signal IN1, which changes between VSS and VDD, to a signal that changes between 3VDD and 2VDD and propagates it to node n6 (see Figure 3). The buffer circuit 30 also propagates a signal that changes between VDD and VSS as output 32 to node n7 in response to the change in the first input signal IN1 from VSS to VDD (see Figure 3).

[0027] The buffer circuit 30 is equipped with a mode switching terminal EN for switching between input and output modes. As described above, the mode switching signal EN input to the mode switching terminal EN switches between operating in input mode and operating in output mode.

[0028] Note that the buffer circuit 30 is not an essential component of the input / output circuit 1. For example, the buffer circuit 30 may be provided outside of the input / output circuit 1.

[0029] (4) Input Buffer Circuit The input buffer circuit 40 is a buffer circuit with a Schmitt trigger function. The input buffer circuit 40 propagates a signal that changes between VDD and 2VDD in response to the voltage changes at nodes n2 and n4 to node n9 (corresponding to the seventh node). In input mode, the voltage at node n2 changes between VDD + Vtp and 3VDD in response to the change of the second input signal IN2 from VSS to 3VDD. Vtp is the threshold voltage of the P-type transistor. The voltage at node n4 changes between VSS and 2VDD - Vtn in response to the change of the second input signal IN2 from VSS to 3VDD. Vtn is the threshold voltage of the N-type transistor.

[0030] The input buffer circuit 40 includes an N-type transistor N5 (corresponding to the fifth N-type transistor) and a P-type transistor P5 (corresponding to the fifth P-type transistor) connected in series between the power supply 2VDD and the power supply VDD. The drain of the N-type transistor N5 is connected to the power supply 2VDD, the source is connected to node n8 (corresponding to the sixth node), and the gate is connected to node n2. The source of the P-type transistor P5 is connected to node n8, the drain is connected to the power supply VDD, and the gate is connected to node n4.

[0031] The input buffer circuit 40 includes inverter circuits 60 and 70 that operate between power supply 2VDD and power supply VDD. Inverter circuit 60 (corresponding to the first inverter circuit) and inverter circuit 70 (corresponding to the second inverter circuit) form a loop configuration in which one input node and the other output node are connected. Specifically, inverter circuit 60 has its input connected to node n8 and its output connected to node n9. Inverter circuit 70 has its input connected to node n9 and its output connected to node n8. The specific circuit configuration of inverter circuits 60 and 70 is not particularly limited, and general inverter circuits can be used. Figure 1 shows an example in which inverter circuit 70 includes a P-type transistor P7 and an N-type transistor N7. The source of the P-type transistor P7 is connected to power supply 2VDD, its drain is connected to node n8, and its gate is connected to node n9. The drain of the N-type transistor N7 is connected to node n8, its source is connected to power supply VDD, and its gate is connected to node n9.

[0032] (5) Step-down circuit The step-down circuit 50 steps down the Low potential from VDD to VSS and the High potential from 2VDD to VDD. In other words, the step-down circuit 50 outputs a second output signal OUT2 to the internal output terminal C, which changes between VSS and VDD in response to the change from VDD to 2VDD at node n9. The specific configuration of the step-down circuit 50 is not particularly limited, and a conventionally known general step-down circuit (level shift circuit) can be used.

[0033] 1-2. Operation of the Input / Output Circuit The operation of the input / output circuit 1 according to this embodiment will be described below. In the following description, the gate-drain voltage of a transistor will be simply referred to as Vgd. Similarly, the gate-source voltage will be simply referred to as Vgs, and the drain-source voltage will be simply referred to as Vds. As mentioned above, the threshold voltage of a P-type transistor will be referred to as Vtp, and the threshold voltage of an N-type transistor will be referred to as Vtn.

[0034] (Operation Example 1) Input Mode Figure 2 shows the voltage of each node and the on / off state of each transistor in an example of operation in input mode. The mode switching signal EN is set to input mode. When the mode switching signal EN is set to input mode, n6 = 3VDD and n7 = VSS. In Figure 2, the second waveform from the bottom shows the change in |Vgd| of the P-type transistor P3 and the N-type transistor N3. The first waveform from the bottom shows the change in |Vgd| of the P-type transistor P5 with a solid line and the change in |Vgd| of the N-type transistor N5 with a dashed line.

[0035] (Operation Example 1-1) IN2 = VSS → 3VDD, OUT2 = VSS → VDD Here, we will explain the operation in which the second input signal IN2, which is input to the input / output terminal INOUT, transitions from Low to High. The left side of Figure 2 is a waveform diagram related to the operation of IN2 = VSS → 3VDD, OUT2 = VSS → VDD.

[0036] As the second input signal IN2 rises, nodes n2 and n4 rise, and in the process, the P-type transistor P5 turns off and the N-type transistor N5 turns on. As a result, the voltage at node n8 begins to rise. When IN2 = VSS, n9 = 2VDD, so the input to the inverter circuit 70 is 2VDD. In this case, the N-type transistor N7 is on, and current is generated from the power supply 2VDD to the power supply VDD via the N-type transistors N5 and N7. As a result, the rise speed of the voltage at node n8 becomes slower.

[0037] Subsequently, as the voltage at node n8 rises, that is, as the input to inverter circuit 60 rises slowly, the output of inverter circuit 60 inverts. As a result, the voltage at node n9 falls from 2VDD to VDD, and the N-type transistor N7 of inverter circuit 70 turns off. This stops the current from power supply 2VDD to power supply VDD via N-type transistors N5 and N7, causing the voltage at node n8 to rise sharply. Therefore, after the second input signal IN2 exceeds 2VDD, the voltage at node n9 falls, and the voltage at internal output terminal C changes from VSS to VDD. In other words, the threshold level at which the input circuit 3 with Schmitt trigger functionality transitions from a Low level to a High level (hereinafter referred to as "threshold VIH") exceeds 2VDD.

[0038] To summarize this example of operation, as the voltage at node n2 rises, the N-type transistor N5 turns on after its gate voltage exceeds 2VDD. When the N-type transistor N5 turns on, current flows from power supply 2VDD to power supply VDD, and the voltage at node n8 rises slowly. Subsequently, when the output of the inverter circuit 60 inverts, the voltage at node n8 rises sharply. Through this operation, a hysteresis wider than the voltage amplitude of the input buffer circuit 40 can be generated. Furthermore, since the current flowing from power supply 2VDD to power supply VDD occurs between identical transistors, N-type transistor N5 and N-type transistor N7, variations in hysteresis caused by manufacturing variations of the transistors can be suppressed.

[0039] (Operation Example 1-2) IN2 = 3VDD → VSS, OUT2 = VDD → VSS Here, we will explain the operation in which the second input signal IN2, which is input to the input / output terminal INOUT, transitions from High to Low. The right side of Figure 2 is a waveform diagram related to the operation of IN2 = 3VDD → VSS, OUT2 = VDD → VSS.

[0040] As the second input signal IN2 falls, nodes n2 and n4 fall, and in the process, the P-type transistor P5 turns on and the N-type transistor N5 turns off. As a result, the voltage at node n8 begins to fall from 2VDD. When IN2 = 3VDD, n9 = VDD, so the input to the inverter circuit 70 is VDD. In this case, the P-type transistor P7 is on, and current is generated from the power supply 2VDD to the power supply VDD via the P-type transistors P7 and P5. As a result, the falling speed of node n8 becomes slower.

[0041] Subsequently, as the voltage at node n8 gradually falls, that is, as the input to the inverter circuit 60 gradually falls, the output of the inverter circuit 60 inverts. As a result, the voltage at node n9 rises from VDD to 2VDD, and the P-type transistor P7 of the inverter circuit 70 turns off. This stops the current from power supply 2VDD to power supply VDD via P-type transistors P7 and P5, causing the voltage at node n8 to drop sharply. Therefore, after the second input signal IN2 falls below VDD, node n9 rises, and the voltage at the internal output terminal C changes from VDD to VSS. In other words, the threshold level at which the input circuit 3 with a Schmitt trigger function transitions from a High level to a Low level (hereinafter referred to as "threshold VIL") falls below VDD.

[0042] To summarize this example of operation, as the voltage at node n4 decreases, the P-type transistor P5 turns on after its gate voltage falls below VDD. When the P-type transistor P5 turns on, current flows from power supply 2VDD to power supply VDD, and the voltage at node n8 falls slowly. Subsequently, when the output of the inverter circuit 60 inverts, the voltage at node n8 drops sharply. Through this operation, a hysteresis wider than the voltage amplitude of the input buffer circuit 40 can be generated. Furthermore, since the current flowing from power supply 2VDD to power supply VDD occurs between identical transistors, P-type transistor P7 and P-type transistor P5, variations in hysteresis caused by manufacturing variations of the transistors can be suppressed.

[0043] (Operation Example 2) Output Mode Figure 3 shows the voltages of each node and the on / off states of each transistor in the operation example of the output mode. The mode switching signal EN is set to the output mode.

[0044] (Operation Example 2-1) When IN1 = VSS and OUT1 = VSS When IN1 = VSS, n7 = VDD, and N-type transistors N1 and N2 turn on, resulting in n4 = VSS. Then, P-type transistor P4 turns on, making n3 = VDD, and N-type transistor N3 turns on, causing OUT1 = VSS. Also, when IN1 = VSS, n6 = 3VDD, and P-type transistor P1 turns off. As described above, since n3 = VDD, n2 = VDD + Vtp. Given that VDD + Vtp < 2VDD, N-type transistor N4 turns off.

[0045] Here, the Vgd of P-type transistor P3 and N-type transistor N3 is the voltage between node n3 and the input / output terminal INOUT, and |Vgd| = VDD. This is below the breakdown voltage of the low-voltage transistor. Also, for P-type transistor P3, Vgs = (VDD + Vtp) - VDD = Vtp, and Vds = (VDD + Vtp) - VSS = VDD + Vtp, so both are below the breakdown voltage of the low-voltage transistor. Similarly, for N-type transistor N3, Vgs = VDD - VSS = VDD, and Vds = VSS - VSS = 0 [V], so both are below the breakdown voltage of the low-voltage transistor.

[0046] (Operation Example 2-2) When IN1 = VDD and OUT1 = 3VDD When IN1 = VDD, n6 = 2VDD, and P-type transistors P1 and P2 turn on, making n2 = 3VDD. Then, N-type transistor N4 turns on, resulting in n3 = 2VDD, and P-type transistor P3 turns on, causing OUT1 = 3VDD. When IN1 = VDD, n7 = VSS, and N-type transistor N1 turns off. As described above, since n3 = 2VDD, n4 = 2VDD - Vtn. Given that 2VDD - Vtn > VDD, P-type transistor P4 turns off.

[0047] Here, the Vgd of the P-type transistor P3 and the N-type transistor N3 is the voltage between the node n3 and the input / output terminal INOUT, and Vgd = 3VDD - 2VDD = VDD. This is below the breakdown voltage of the low breakdown voltage transistor. Also, the Vgs of the P-type transistor P3 is Vgs = 3VDD - 2VDD = VDD, and the Vds is Vds = 3VDD - 3VDD = 0 [V], so both are below the breakdown voltage of the low breakdown voltage transistor. Similarly, the Vgs of the N-type transistor N3 is Vgs = 2VDD - (2VDD - Vtn) = Vtn, and the Vds is Vds = 3VDD - (2VDD - Vtn) = VDD + Vtn, so both are below the breakdown voltage of the low breakdown voltage transistor.

[0048] (Operation Example 2-3) When IN1 = VSS → VDD and OUT1 = VSS → 3VDD The left side of FIG. 3 is an example of the operation waveform when IN1 = VSS → VDD and OUT1 = VSS → 3VDD. Here, the operation in which the first input signal IN1 transitions from Low to High and the first output signal OUT1 changes from Low to High will be described. When the first input signal IN1 transitions from Low to High, the on / off states of the transistors transition from the state of "Operation Example 2-1" described above to the state of "Operation Example 2-2". Here, the operation related to the terminal voltage of the P-type transistor P3 and the N-type transistor N3 will be mainly described.

[0049] When the first input signal IN1 transitions from Low to High, the P-type transistors P1, P2, and P3 turn on, and the voltages of the first output signal OUT1 and the node n2 rise toward 3VDD. Since the N-type transistor N4 turns on during the voltage rise process of the first output signal OUT1 and the node n2, the voltage of the node n3 rises from VDD toward 2VDD.

[0050] In this case, the start of the voltage rise at node n3 is delayed by the time T1 required for the N-type transistor N4 to turn on, which is delayed by the start of the rise of the first output signal OUT1. Therefore, the |Vgd| of the P-type transistor P3 and the N-type transistor N3 is maintained below VDD, even while the first output signal OUT1 changes from Low to High, and remains below the breakdown voltage of the low-voltage transistor. The same applies to the |Vgs| and |Vds| of the P-type transistor P3 and the N-type transistor N3; they are maintained at voltages below the breakdown voltage of the low-voltage transistor even while the first output signal OUT1 changes from Low to High.

[0051] (Operation Example 2-4) When IN1 = VDD → VSS, OUT1 = 3VDD → VSS, the right side of Figure 3 shows the waveform when IN1 = VDD → VSS, OUT1 = 3VDD → VSS, that is, when the first input signal IN1 transitions from High to Low and the first output signal OUT1 changes from High to Low.

[0052] When the first input signal IN1 transitions from High to Low, the on / off state of each transistor transitions from the state described in "Operation Example 2-2" to the state described in "Operation Example 2-1". Here, we will mainly explain the operation related to the terminal voltage of the P-type transistor P3 and the N-type transistor N3.

[0053] When the first input signal IN1 transitions from High to Low, N-type transistors N1, N2, and N3 turn on, and the voltage of the first output signal OUT1 and node n4 decreases toward VSS. As the voltage of the first output signal OUT1 and node n4 decreases, P-type transistor P4 turns on, so the voltage of node n3 decreases from 2VDD toward VDD.

[0054] In this case, the start of the falling edge of the voltage at node n3 is delayed by the time T2 required for the P-type transistor P4 to turn on, which is delayed by the start of the falling edge of the first output signal OUT1. Therefore, the |Vgd| of the P-type transistor P3 and the N-type transistor N3 are maintained below VDD, even while the first output signal OUT1 changes from High to Low, and remain below the breakdown voltage of the low-voltage transistor. The same applies to the |Vgs| and |Vds| of the P-type transistor P3 and the N-type transistor N3; even while the first output signal OUT1 changes from High to Low, their voltages are maintained below the breakdown voltage of the low-voltage transistor.

[0055] 1-3. Effects of the First Embodiment According to this embodiment, the control circuit 20 controls the gate voltages of the P-type transistors P3, P5 and the N-type transistors N3, N5 according to the characteristics of the first output signal OUT1 or the second input signal IN2, which fluctuate depending on the breakdown voltage and operating voltage of the transistors. As a result, during the operation of the input / output circuit 1, the |Vgd|, |Vgs|, and |Vds| of each transistor are maintained at a state below the breakdown voltage of the low-breakdown transistor. As a result, compared to the conventional technology, the degradation of transistors over time can be effectively prevented.

[0056] The input circuit 3 in this embodiment has a Schmitt trigger function, which generates hysteresis. In the input circuit 3, a current flows from the power supply 2VDD to VDD for a predetermined period in response to the rising or falling edge of the second input signal IN2. This makes the rising or falling edge of the voltage at node n8 gradual. At this time, the input buffer circuit 40 operates with a voltage amplitude of VDD to 2VDD, but the threshold VIH is above 2VDD and the threshold VIL is below VDD. This makes it possible to generate hysteresis with a voltage width wider than the voltage amplitude of the input buffer circuit 40.

[0057] The current flowing from the power supply 2VDD to VDD is generated between transistors of the same type, thus suppressing hysteresis variations caused by manufacturing variations in the transistors.

[0058] The output driver 10 and control circuit 20 located in the output circuit 2 control the voltage amplitude which changes in accordance with the transition of the second input signal IN2 input from outside the LSI. This eliminates the need for a dedicated control circuit equivalent to the control circuit 20 in the input circuit 3, thereby simplifying the design and reducing the circuit area. Furthermore, since the control circuit 20 in this embodiment has a very simple configuration consisting of two transistors, it also simplifies the design of the input / output circuit 1 and reduces the circuit area.

[0059] <Second Embodiment> Figure 4 is a circuit diagram of the input / output circuit 1 according to the second embodiment. In Figure 4, components corresponding to those in Figure 1 are denoted by the same reference numerals. The following description will focus on the differences from the first embodiment.

[0060] 2-1. Configuration of the Input / Output Circuit In the input / output circuit 1 of Figure 4, the internal configuration of the input buffer circuit 40 differs from that of Figure 1. In other words, in the input / output circuit 1 of Figure 4, the configuration other than the input buffer circuit 40 is the same as in Figure 1.

[0061] (1) Input Buffer Circuit The basic configuration and operation of the input buffer circuit 40 are the same as those in Figure 1. Specifically, in this embodiment as well, the input buffer circuit 40 is a buffer circuit with a Schmitt trigger function. The input buffer circuit 40 propagates a signal that changes between VDD and 2VDD in response to voltage changes at nodes n2 and n4 to node n9 (corresponding to the 7th or 9th node).

[0062] The input buffer circuit 40 further includes an N-type transistor N6 and a P-type transistor P6 in addition to the configuration shown in Figure 1. The N-type transistor N6 (corresponding to the sixth N-type transistor) is provided between the source of the N-type transistor N5 and node n8 (corresponding to the sixth or seventh node), and its gate is connected to node n2. The P-type transistor P6 is provided between the source of the P-type transistor P5 and node n8, and its gate is connected to node n4.

[0063] In other words, the input buffer circuit 40 comprises N-type transistors N5, N6 and P-type transistors P5, P6 connected in series between the power supply 2VDD and the power supply VDD. The drain of the N-type transistor N5 is connected to the power supply 2VDD, the source is connected to node n11 (corresponding to the sixth node), and the gate is connected to node n2. The drain of the N-type transistor N6 is connected to node n11, the source is connected to node n8, and the gate is connected to node n2. The source of the P-type transistor P6 (corresponding to the sixth P-type transistor or the fifth P-type transistor) is connected to node n8, the drain is connected to node n10 (corresponding to the eighth node), and the gate is connected to node n4. The source of the P-type transistor P5 (corresponding to the fifth P-type transistor or the sixth P-type transistor) is connected to node n10, the drain is connected to the power supply VDD, and the gate is connected to node n4.

[0064] The input buffer circuit 40 includes inverter circuits 60 and 70 that operate between power supply 2VDD and power supply VDD. The configuration of inverter circuit 60 can be the same as that in Figure 1. Inverter circuit 70 includes a P-type transistor P7 (corresponding to the seventh P-type transistor) and an N-type transistor N7 (corresponding to the seventh N-type transistor). The source of the P-type transistor P7 is connected to the second power supply 2VDD, the drain is connected to node n8 via P-type transistor P6, and the gate is connected to node n9. In other words, the source of the P-type transistor P7 is connected to power supply 2VDD, the drain is connected to node n10, and the gate is connected to node n9. The source of the N-type transistor N7 is connected to power supply VDD, the drain is connected to node n8 via N-type transistor N6, and the gate is connected to node n9. In other words, the source of the N-type transistor N7 is connected to power supply VDD, the drain is connected to node n11, and the gate is connected to node n9. As described above, the inverter circuit 60 and the inverter circuit 70 form a loop configuration in which one input node and the other output node are connected via an N-type transistor N6 or a P-type transistor P6.

[0065] 2-2. Operation of the Input / Output Circuit The operation of the input / output circuit 1 according to this embodiment will be described below. Here, the focus will be on the configuration added or modified from Figure 1 in Figure 4. Note that the operation of the output mode is the same as (Operation Example 2) of the first embodiment, and will not be described here.

[0066] (Operation Example 3) Input Mode (Operation Example 3-1) When IN2 = VSS → 3VDD and OUT2 = VSS → VDD, the operation of the second input signal IN2, which is input to the input / output terminal INOUT, transitioning from Low to High will be explained here.

[0067] As the second input signal IN2 rises, nodes n2 and n4 rise, and in the process, the P-type transistor P5 turns off and the N-type transistor N5 turns on. As a result, the voltage at node n11 begins to rise. When IN2 = VSS, n9 = 2VDD, so the input to the inverter circuit 70 is 2VDD. In this case, the N-type transistor N7 is on, and current is generated from the power supply 2VDD to the power supply VDD via the N-type transistors N5 and N7. As a result, the rise speed of the voltages at nodes n11 and n8 slows down. The subsequent operation is the same as in (Operation Example 1-1) described above.

[0068] To summarize this example of operation, as the voltage at node n2 rises, the N-type transistor N5 turns on after its gate voltage exceeds 2VDD. When the N-type transistor N5 turns on, current flows from power supply 2VDD to power supply VDD, and the voltages at nodes n11 and n8 rise gradually. Subsequently, when the output of the inverter circuit 60 inverts, the voltages at nodes n11 and n8 rise sharply. Through this operation, a hysteresis wider than the voltage amplitude of the input buffer circuit 40 can be generated. Furthermore, since the current flowing from power supply 2VDD to power supply VDD occurs between identical transistors, N-type transistor N5 and N-type transistor N7, variations in hysteresis caused by manufacturing variations of the transistors can be suppressed.

[0069] (Operation Example 3-2) When IN2 = 3VDD → VSS and OUT2 = VDD → VSS, this section describes the operation in which the second input signal IN2, which is input to the input / output terminal INOUT, transitions from High to Low.

[0070] As the second input signal IN2 falls, nodes n2 and n4 fall, and in the process, the P-type transistor P5 turns on and the N-type transistor N5 turns off. As a result, the voltage at node n10 begins to fall from 2VDD. When IN2 = 3VDD, n9 = VDD, so the input to the inverter circuit 70 is VDD. In this case, the P-type transistor P7 is on, and current is generated from the power supply 2VDD to the power supply VDD via the P-type transistors P7 and P5. As a result, the falling speed of nodes n10 and n8 slows down. The subsequent operation is the same as in (Operation Example 1-2) described above.

[0071] To summarize this example of operation, as the voltage at node n4 decreases, the P-type transistor P5 turns on after its gate voltage falls below VDD. When the P-type transistor P5 turns on, current flows from power supply 2VDD to power supply VDD, and the voltages at nodes n10 and n8 fall slowly. Subsequently, when the output of the inverter circuit 60 inverts, the voltages at nodes n10 and n8 fall sharply. Through this operation, a hysteresis wider than the voltage amplitude of the input buffer circuit 40 can be generated. Furthermore, since the current flowing from power supply 2VDD to power supply VDD occurs between identical transistors, P-type transistor P7 and P-type transistor P5, variations in hysteresis caused by manufacturing variations of the transistors can be suppressed.

[0072] 2-3. Effects of the Second Embodiment According to this embodiment, similar to the first embodiment, in the input circuit 3, a current flows from the power supply 2VDD to VDD for a predetermined period in accordance with the rising or falling edge of the second input signal IN2. As a result, the rising or falling edge of the voltages at nodes n11 and n8, or nodes n10 and n8, becomes gradual. At this time, the input buffer circuit 40 operates with a voltage amplitude of VDD to 2VDD, but the threshold VIH is above 2VDD and the threshold VIL is below VDD. As a result, it is possible to generate hysteresis with a voltage width wider than the voltage amplitude of the input buffer circuit 40.

[0073] Furthermore, similar to the first embodiment, the following effects can be obtained: (1) Compared to the conventional technology, the aging degradation of transistors can be accurately prevented; (2) Variations in hysteresis caused by manufacturing variations of transistors can be suppressed; or (3) The design of the input / output circuit 1 can be simplified and the circuit area can be reduced.

[0074] Furthermore, with the configuration of this embodiment, no through-current is generated between 2VDD and VDD in the inverter circuit 70 when the input buffer circuit 40 is operating. In addition, the through-current generated between power supply 2VDD and power supply VDD is reduced by connecting N-type transistors N5 and N6 in series between power supply 2VDD and node n8, and by connecting P-type transistors P6 and P5 in series between node n8 and power supply VDD. As a result, the power consumption of the input / output circuit 1 can be reduced compared to the configuration of the first embodiment.

[0075] <Third Embodiment> Figure 5 is a circuit diagram of the input / output circuit 1 according to the third embodiment. In Figure 5, components corresponding to those in Figure 1 are denoted by the same reference numerals. The following description will focus on the differences from the first embodiment.

[0076] 3-1. Configuration of Input / Output Circuits In the input / output circuit 1 of Figure 5, the internal configuration of the input buffer circuit 40 differs from that of Figure 1. In other words, in the input / output circuit 1 of Figure 5, the configuration other than the input buffer circuit 40 is the same as in Figure 1.

[0077] The input buffer circuit 40, in addition to the configuration shown in Figure 1, also includes a Schmitt trigger on / off function. Specifically, the input buffer circuit 40 differs from the first embodiment in that the inverter circuit 70 switches between a first operating state (Schmitt trigger on operation) where it functions as an inverter based on the control signal ST, and a second operating state (Schmitt trigger off operation) where the output becomes high impedance. Specifically, the inverter circuit 70 is configured to maintain a state in which it does not output a signal (e.g., a high impedance state) when the Schmitt trigger function is stopped. Figure 5 shows an example of a circuit configuration in which the Schmitt trigger function is stopped when the control signal ST input from the control terminal ST is Low. However, as described above, it is sufficient that the inverter circuit 70 maintains a state in which it does not output a signal (e.g., a high impedance state) when the Schmitt trigger function is stopped, and the specific circuit configuration is not limited to Figure 5.

[0078] In the example shown in Figure 5, the inverter circuit 70 includes P-type transistors P8, P7 and N-type transistors N7, N8 connected in series between the power supply 2VDD and the power supply VDD. The N-type transistor N7 (corresponding to the sixth N-type transistor) has its drain connected to node n8, its source connected to node n13 (corresponding to the eighth node), and its gate connected to node n9. The N-type transistor N8 (corresponding to the seventh N-type transistor) has its drain connected to node n13, its source connected to the power supply VDD, and its gate receives a control signal ST. The P-type transistor P7 (corresponding to the sixth P-type transistor) has its source connected to node n12 (corresponding to the ninth node), its drain connected to node n8, and its gate connected to node n9. The P-type transistor P8 (corresponding to the seventh P-type transistor) has its source connected to the power supply 2VDD, its drain connected to node n12, and its gate receives an inverted signal of the control signal ST.

[0079] 3-2. Operation of the Input / Output Circuit The operation of the input / output circuit 1 according to this embodiment will be described below. Here, the focus will be on the configurations added or modified from those in Figure 1, as shown in Figure 5.

[0080] (Operation Example 4) Operation related to turning the Schmitt trigger function on / off (Operation Example 4-1) When the Schmitt trigger function is turned on (when ST = High) When ST = High (2VDD), the P-type transistor P8 and the N-type transistor N8 are turned on, and the inverter circuit 70 enters a first operating state in which it functions as an inverter. That is, the Schmitt trigger function is turned on. As a result, it operates in the same manner as the first embodiment. Specifically, in input mode, it operates in the same manner as (Operation Example 1) described above, and in output mode, it operates in the same manner as (Operation Example 2) described above.

[0081] (Operation Example 4-2) When the Schmitt trigger function is turned off (when ST = Low) When ST = Low (VDD), the P-type transistor P8 and N-type transistor N8 are turned off, and the inverter circuit 70 does not output a signal regardless of the voltage of the input node n9, i.e., it enters a high-impedance state. As a result, even when the input / output circuit 1 operates in input mode and the input / output terminal INOUT transitions between VSS and 3VDD, and the input buffer circuit 40 enters an operating state, no current flows from 2VDD to VDD via the P-type transistors P5 and P7, and no current flows from 2VDD to VDD via the N-type transistors N5 and N7. As a result, hysteresis is not generated. In other words, the Schmitt trigger function is stopped.

[0082] 3-3. Effects of the Third Embodiment According to this embodiment, the Schmitt trigger function can be controlled to be turned on or off according to the specifications of the device (e.g., LSI) on which the input / output circuit 1 is mounted. This allows the Schmitt trigger function to be stopped, for example, when high-speed input / output operation is required in the input / output circuit 1.

[0083] Furthermore, when the Schmitt trigger function is turned on, the same effects as those of the first embodiment described above can be obtained. Specifically, the following effects can be obtained: (1) Compared to the conventional technology, the aging degradation of the transistor can be accurately prevented; (2) Hysteresis with a voltage width wider than the voltage amplitude of the input buffer circuit 40 can be generated; (3) Variations in hysteresis caused by manufacturing variations of the transistor can be suppressed; or (4) The design of the input / output circuit 1 can be simplified and the circuit area can be reduced.

[0084] <Fourth Embodiment> Figure 6 is a circuit diagram of the input / output circuit 1 according to the fourth embodiment. In Figure 6, components corresponding to those in Figure 4 are denoted by the same reference numerals. The following description will focus on the differences from the second embodiment.

[0085] 4-1. Configuration of the Input / Output Circuit In the input / output circuit 1 of Figure 6, the internal configuration of the input buffer circuit 40 differs from that of Figure 4. In other words, in the input / output circuit 1 of Figure 6, the configuration other than the input buffer circuit 40 is the same as in Figure 4.

[0086] The input buffer circuit 40, in addition to the configuration shown in Figure 4, also includes a Schmitt trigger on / off function. Specifically, the input buffer circuit 40 differs from the second embodiment in that the inverter circuit 70 switches between a first operating state (Schmitt trigger on operation) where it functions as an inverter based on the control signal ST, and a second operating state (Schmitt trigger off operation) where the output becomes high impedance. Specifically, the inverter circuit 70 is configured to maintain a state in which it does not output a signal (e.g., a high impedance state) when the Schmitt trigger function is stopped. Figure 6 shows an example of a circuit configuration in which the Schmitt trigger function is stopped when the control signal ST input from the control terminal ST is Low. However, as described above, it is sufficient that the inverter circuit 70 maintains a state in which it does not output a signal (e.g., a high impedance state) when the Schmitt trigger function is stopped, and the specific circuit configuration is not limited to Figure 6.

[0087] In the example shown in Figure 6, the inverter circuit 70 includes an N-type transistor N8 and a P-type transistor P8 in addition to the circuit shown in Figure 4. The N-type transistor N8 (corresponding to the eighth N-type transistor) is located between the source of the N-type transistor N7 and the power supply VDD, and receives a control signal (ST) at its gate. In other words, the N-type transistors N7 and N8 are connected in series between node n11 and the power supply VDD. The P-type transistor P8 (corresponding to the eighth P-type transistor) is located between the power supply 2VDD and the source of the P-type transistor P7, and receives an inverted signal of the control signal ST at its gate. In other words, the P-type transistors P8 and P7 are connected in series between power supply 2VDD and node n10.

[0088] 4-2. Operation of the Input / Output Circuit The operation of the input / output circuit 1 according to this embodiment will be described below. Here, the focus will be on the configurations added or modified from those in Figure 4 in Figure 6.

[0089] (Operation Example 5) Operation related to turning the Schmitt trigger function on / off (Operation Example 5-1) When the Schmitt trigger function is turned on (when ST = High) When ST = High (2VDD), the P-type transistor P8 and the N-type transistor N8 are turned on, and the inverter circuit 70 enters a first operating state in which it functions as an inverter. That is, the Schmitt trigger function is turned on. As a result, it operates in the same manner as the first embodiment. Specifically, in input mode, it operates in the same manner as (Operation Example 3) of the second embodiment, and in output mode, it operates in the same manner as the second embodiment, that is, in the same manner as (Operation Example 2) of the first embodiment.

[0090] (Operation Example 5-2) When the Schmitt trigger function is turned off (ST = Low) When ST = Low (VDD), the P-type transistor P8 and N-type transistor N8 are turned off, and the inverter circuit 70 does not output a signal regardless of the voltage of the input node n9, i.e., it enters a high-impedance state. As a result, even when the input / output circuit 1 operates in input mode and the second input signal IN2 transitions between VSS and 3VDD, and the input buffer circuit 40 enters an operating state, no current flows from 2VDD to VDD via the P-type transistors P7 and P5, and no current flows from 2VDD to VDD via the N-type transistors N5 and N7. As a result, hysteresis is not generated. In other words, the Schmitt trigger function is stopped.

[0091] 4-3. Effects of the Fourth Embodiment According to this embodiment, the Schmitt trigger function can be controlled to be turned on or off according to the specifications of the device (e.g., LSI) on which the input / output circuit 1 is mounted. This allows the Schmitt trigger function to be stopped, for example, when high-speed input / output operation is required in the input / output circuit 1.

[0092] Furthermore, when the Schmitt trigger function is turned on, the same effects as those of the second embodiment described above can be obtained. That is, according to this embodiment, the following effects can be obtained: (1) Compared to the conventional technology, the aging degradation of the transistor can be accurately prevented; (2) Hysteresis with a voltage width wider than the voltage amplitude of the input buffer circuit 40 can be generated; (3) Variations in hysteresis caused by manufacturing variations of the transistor can be suppressed; (4) The design of the input / output circuit 1 can be simplified and the area of ​​the circuit can be reduced; or (5) The power consumption of the input / output circuit 1 can be reduced.

[0093] <Other Embodiments> The technology in this disclosure is not limited to the configurations described in the embodiments above, and many modifications, such as changes, substitutions, additions, and omissions, can be made as appropriate by a person with ordinary skill in the art within the technical concept of this disclosure. Furthermore, it is possible to combine the components described in the embodiments above to create new embodiments.

[0094] For example, in each of the embodiments or modifications described above, the power supply voltage of power supply 3VDD is not limited to three times the voltage of VDD. In other words, the amplitude of the output signal voltage is not limited to three times VDD. For example, by adjusting the voltage of each node, voltages exceeding three times VDD or voltages below three times VDD can be output as the first output signal OUT1 from the input / output terminal INOUT, or input as the second input signal IN2 from the input / output terminal INOUT.

[0095] <Modification 1> In each of the first to fourth embodiments, the input circuit 3 may be provided with a function to stop the signal input operation. For example, the inverter circuit 60 may be configured to switch between a first operating state in which it functions as an inverter and a second operating state in which the output becomes a fixed signal, based on the control signal IE. This makes it possible to output a fixed signal from the internal output terminal C in both input mode and output mode.

[0096] The following describes a specific circuit configuration example related to this modified example 1, with reference to Figure 7. Figure 7 shows an example of a circuit in which the input operation stop function of the input circuit 3 is added to the input / output circuit 1 of the first embodiment. In Figure 7, components corresponding to those in Figure 1 are denoted by the same reference numerals. The following description will focus on the differences from the first embodiment.

[0097] 5-1. Configuration of Input / Output Circuits In the input / output circuit 1 of Figure 7, the configuration of the inverter circuit 60 differs from that in Figure 1. In other words, in the input / output circuit 1 of Figure 7, the configuration other than the inverter circuit 60 is the same as in Figure 1.

[0098] In Figure 7, the inverter circuit 60 includes a NAND circuit 62 that receives the control signal IE input from node n8 and control terminal IE. Note that the circuit configuration for stopping the input operation is not limited to the NAND circuit 62; for example, a NOR circuit may be used. In addition, the input buffer circuit 40 may employ other circuit configurations such that the input operation is stopped based on the control signal IE, that is, the output from the internal output terminal C is fixed.

[0099] 5-2. Operation of Input / Output Circuits When IE = Low (VDD), node n9 is fixed to 2VDD. As a result, the output of internal output terminal C is fixed to VSS. In other words, the input operation of input circuit 3 is stopped.

[0100] When IE = High (2VDD), the input operation of the input circuit 3 is turned on. At this time, the NAND circuit 62 functions as an inverter and operates in the same way as in the first embodiment. That is, the input / output circuit 1 operates in the same way as in (Operation Example 1) described above in input mode, and operates in the same way as in (Operation Example 2) described above in output mode.

[0101] 5-3. Effects of Modification 1 According to this modification, in both input mode and output mode, the input circuit 3 can be stopped and a fixed signal can be output from the internal output terminal C. That is, for example, a fixed signal can be output to the circuit connected to the internal output terminal C. This is effective in reducing power consumption because, for example, circuits that do not need to operate can be stopped.

[0102] Furthermore, when the input operation of the input circuit 3 is turned on, the same effects as in the first embodiment described above can be obtained. Specifically, the following effects can be obtained: (1) Compared to the conventional technology, the aging degradation of the transistor can be accurately prevented; (2) Hysteresis with a voltage width wider than the voltage amplitude of the input buffer circuit 40 can be generated; (3) Variations in hysteresis caused by manufacturing variations of the transistor can be suppressed; or (4) The design of the input / output circuit 1 can be simplified and the circuit area can be reduced.

[0103] Note that the inverter circuit 60 shown in Figure 7 may be applied to input / output circuits 1 other than those in Embodiment 1. For example, in Figures 4 to 6, the inverter circuit 60 may be replaced with the circuit in Figure 7, and the same effects as described above can be obtained.

[0104] Figure 8 shows an example in which the inverter circuit 60 according to Modification 1 is applied to the input / output circuit 1 of Figure 5. That is, the input / output circuit 1 of Figure 8 is equipped with the on / off function of the Schmitt trigger described in the third embodiment and the function of stopping the input operation of the input circuit 3 described in Modification 1.

[0105] Figure 9 shows a truth table relating to the operation of the input / output circuit 1 shown in Figure 8 (particularly the operation of the input circuit 3).

[0106] As shown in Figure 9, when IE = High (2VDD), the input operation of the input circuit 3 is turned on. When IE = High and ST = High, the NAND circuit 62 functions as an inverter and the Schmitt trigger function is turned on, so it operates the same as in the first embodiment. That is, the input / output circuit 1 operates the same as (operation example 1) described above in input mode and the same as (operation example 2) described above in output mode. When IE = High and ST = Low, the Schmitt trigger function is turned off, and the output of the inverter circuit 70 becomes high impedance. As a result, hysteresis is not generated.

[0107] When IE = Low, regardless of the second input signal IN2 to the input / output terminal INOUT, the second output signal OUT2 output from the internal output terminal C is fixed to Low (VSS).

[0108] <Modification 2> In each embodiment of the first to fourth embodiments or in Modification 1, a configuration may be added to reduce the effect of voltage fluctuations due to the coupling of parasitic capacitances. Figures 10 and 11 are circuit diagrams of the input / output circuit according to Modification 2 of the first embodiment. In Figures 10 and 11, components corresponding to those in Figure 1 are denoted by the same reference numerals. The following description will focus on the differences from the first embodiment.

[0109] 6-1. Configuration of the Input / Output Circuit The input / output circuit 1 in Figures 10 and 11 differs from the configuration in Figure 1 in the internal configuration of the control circuit 20. In other words, the configuration of the input / output circuit 1 in Figures 10 and 11 is the same except for the control circuit 20.

[0110] Specifically, the control circuit 20 in Figure 10, in addition to the configuration in Figure 1, includes an N-type transistor N9 (corresponding to the sixth or eighth N-type transistor) and a P-type transistor P9 (corresponding to the sixth or eighth P-type transistor) connected in series between the power supply 2VDD and the power supply VDD. The drain of the N-type transistor N9 is connected to the power supply 2VDD, and the source and gate are connected to node n3. The source and gate of the P-type transistor P9 are connected to node n3, and the drain is connected to the power supply VDD. The N-type transistor N9 and the P-type transistor P9 are the low-voltage transistors mentioned above.

[0111] The control circuit 20 in Figure 11, in addition to the configuration in Figure 1, includes a P-type transistor P9 (corresponding to the sixth or eighth P-type transistor) and an N-type transistor N9 (corresponding to the sixth or eighth N-type transistor) connected in series between the power supply 2VDD and the power supply VDD. The source and gate of the P-type transistor P9 are connected to the power supply 2VDD, and the drain is connected to node n3. The drain of the N-type transistor N9 is connected to node n3, and the source and gate are connected to the power supply VDD.

[0112] In Figures 10 and 11, the control circuit 20, similar to Figure 1, controls the gate voltages of the P-type transistor P3 and the N-type transistor N3, i.e., the voltage amplitude of node n3, within the range of VDD to 2VDD, according to the operation of the output driver 10.

[0113] Incidentally, when the first output signal OUT1 or the second input signal IN2 transitions, the voltage at node n3 may fluctuate unexpectedly due to the coupling of parasitic capacitance between the input / output terminal INOUT and node n3. For example, the voltage at node n3 may exceed 2VDD or fall below VDD. As shown in Figures 10 and 11, this voltage fluctuation can be suppressed by providing a P-type transistor P9 and an N-type transistor N9. Note that parasitic capacitance fluctuates due to factors such as the proximity of wiring within the circuit. Therefore, both the P-type transistor P9 and the N-type transistor N9 may be provided, or either the P-type transistor P9 or the N-type transistor N9 may be provided.

[0114] 6-2. Operation of the Input / Output Circuit In this modified example, the basic operation of the input / output circuit 1 as a whole is the same as in (Operation Example 1) and (Operation Example 2) described above. Here, we will mainly explain the configuration newly added in Figures 10 and 11.

[0115] In the input / output circuit 1 of Figure 10, when the voltage at node n3 rises above 2VDD, the N-type transistor N9 turns on during this process and acts to lower the voltage at node n3 to 2VDD. In the input / output circuit 1 of Figure 10, when the voltage at node n3 falls below VDD, the P-type transistor P9 turns on during this process and acts to raise the voltage at node n3 to VDD.

[0116] In the input / output circuit 1 of Figure 11, when the voltage at node n3 rises above 2VDD, the P-type transistor P9 turns on during this process and acts to lower the voltage at node n3 to 2VDD. In the input / output circuit 1 of Figure 11, when the voltage at node n3 falls below VDD, the N-type transistor N9 turns on during this process and acts to raise the voltage at node n3 to VDD.

[0117] 6-3. Effects and Benefits of Modified Example 2 According to this modified example, in addition to the effects and benefits of the embodiment described above, the following effects and benefits can be obtained.

[0118] Even when the voltage at the parasitic capacitance coupling node n3 exceeds 2VDD or falls below VDD during the operation of the input / output circuit 1, the |Vgd|, |Vgs|, and |Vds| of each P-type transistor and each N-type transistor remain below the breakdown voltage of the low-voltage transistor. This effectively prevents transistor degradation over time compared to conventional technology. Furthermore, the output driver 10 and control circuit 20 located in the output circuit 2 control the voltage amplitude which changes in accordance with the transition of the second input signal IN2 input from outside the LSI. This eliminates the need for a dedicated control circuit equivalent to the control circuit 20 in the input circuit 3, thereby simplifying the design and reducing the circuit area. Moreover, since the control circuit 20 according to this embodiment has a very simple configuration consisting of four transistors, it is possible to simplify the design of the input / output circuit 1 and reduce the circuit area.

[0119] This disclosure effectively prevents the aging degradation of transistors, making it useful as an input / output circuit for LSIs.

[0120] 1 Input / Output Circuit 60 Inverter Circuit (First Inverter Circuit) 62 NAND Circuit 70 Inverter Circuit (Second Inverter Circuit) IE Control Signal IN1 First Input Signal IN2 Second Input Signal INOUT Input / Output Terminal OUT1 First Output Signal (Output Signal) N1 N-type Transistor (Third N-type Transistor) N2 N-type Transistor (Second N-type Transistor) N3 N-type Transistor (First N-type Transistor) N4 N-type Transistor (Fourth N-type Transistor) N5 N-type Transistor (Fifth N-type Transistor) N6 N-type Transistor (Sixth N-type Transistor) N7 N-type Transistor (Sixth N-type Transistor, Seventh N-type Transistor) N8 N-type Transistor (Seventh N-type Transistor, Eighth N-type Transistor) N9 N-type Transistor (Sixth N-type Transistor, Eighth N-type Transistor) N10 N-type transistor (6th N-type transistor, 8th N-type transistor) P1 P-type transistor (1st P-type transistor) P2 P-type transistor (2nd P-type transistor) P3 P-type transistor (3rd P-type transistor) P4 P-type transistor (4th P-type transistor) P5 P-type transistor (5th P-type transistor, 6th P-type transistor) P6 P-type transistor (6th P-type transistor, 5th P-type transistor) P7 P-type transistor (6th P-type transistor, 7th P-type transistor) P8 P-type transistor (7th P-type transistor, 8th P-type transistor) P9 P-type transistor (6th P-type transistor, 8th N-type transistor) P10 P-type transistor (6th P-type transistor, 8th N-type transistor) ST Control signal VDD Power supply (3rd power supply) 2VDD Power supply (2nd power supply) 3VDD Power supply (1st power supply) VSS Ground (4th power supply) n1 node (1st node) n2 node (2nd node) n3 node (3rd node) n4 node (4th node) n5 node (5th node) n8 node (6th node, 7th node) n9 node (7th node, 9th node) n10 node (8th node) n11 node (6th node) n12 node (9th node) n13 node (8th node)

Claims

1. An input / output circuit that outputs an output signal that changes in accordance with a first input signal from an input / output terminal and receives a second input signal input to the input / output terminal, comprising: a first P-type transistor whose source is connected to a first power supply, whose drain is connected to a first node, and whose gate receives a signal that changes in accordance with the first input signal; a second P-type transistor whose source is connected to the first node, whose drain is connected to a second node, and whose gate is connected to a second power supply with a lower power supply voltage than the first power supply; a third P-type transistor whose source is connected to the second node, whose drain is connected to the input / output terminal, and whose gate is connected to a third node; a first N-type transistor whose drain is connected to the input / output terminal, whose source is connected to a fourth node, and whose gate is connected to the third node; and a second N-type transistor whose drain is connected to the fourth node, whose source is connected to a fifth node, and whose gate is connected to a third power supply with a lower power supply voltage than the second power supply. An input / output circuit comprising: a third N-type transistor whose drain is connected to the fifth node, whose source is connected to a fourth power supply having a lower power supply voltage than the third power supply, and whose gate receives a signal that changes according to the first input signal; a fourth N-type transistor whose drain is connected to the second power supply, whose source is connected to the third node, and whose gate is connected to the second node; a fourth P-type transistor whose source is connected to the third node, whose drain is connected to the third power supply, and whose gate is connected to the fourth node; a fifth N-type transistor whose drain is connected to the second power supply, whose source is connected to the sixth node, whose drain is connected to the third power supply, and whose gate is connected to the fourth node; a first inverter circuit whose input is connected to the sixth node and whose output is connected to the seventh node; and a second inverter circuit whose input is connected to the seventh node and whose output is connected to the sixth node.

2. An input / output circuit according to claim 1, wherein the second inverter circuit switches between a first operating state in which it functions as an inverter and a second operating state in which the output becomes high impedance, based on a control signal.

3. An input / output circuit according to claim 2, wherein the second inverter circuit comprises: a sixth N-type transistor whose drain is connected to the sixth node, whose source is connected to the eighth node, and whose gate is connected to the seventh node; a seventh N-type transistor whose drain is connected to the eighth node, whose source is connected to the third power supply, and whose gate receives the control signal; a sixth P-type transistor whose source is connected to the ninth node, whose drain is connected to the sixth node, and whose gate is connected to the seventh node; and a seventh P-type transistor whose source is connected to the second power supply, whose drain is connected to the ninth node, and whose gate receives an inverted signal of the control signal.

4. An input / output circuit according to claim 1, wherein the first inverter circuit switches between a first operating state in which it functions as an inverter and a second operating state in which the output becomes a fixed signal, based on a control signal.

5. An input / output circuit according to claim 1, comprising: a sixth N-type transistor whose drain is connected to the second power supply and whose source and gate are connected to the third node; and a sixth P-type transistor whose source and gate are connected to the third node and whose drain is connected to the third power supply.

6. An input / output circuit according to claim 1, comprising: a sixth P-type transistor whose source and gate are connected to the second power supply and whose drain is connected to the third node; and a sixth N-type transistor whose source and gate are connected to the third power supply and whose drain is connected to the third node.

7. An input / output circuit according to claim 1, further comprising: a sixth N-type transistor provided between the source of the fifth N-type transistor and the sixth node, with its gate connected to the second node; and a sixth P-type transistor provided between the source of the fifth P-type transistor and the sixth node, with its gate connected to the fourth node, wherein the second inverter circuit comprises: a seventh P-type transistor with its source connected to the second power supply, its drain connected to the sixth node via the sixth P-type transistor, and its gate connected to the seventh node; and a seventh N-type transistor with its source connected to the third power supply, its drain connected to the sixth node via the sixth N-type transistor, and its gate connected to the seventh node.

8. An input / output circuit according to claim 7, wherein the second inverter circuit switches between a first operating state in which it functions as an inverter and a second operating state in which the output becomes high impedance, based on a control signal.

9. An input / output circuit according to claim 8, wherein the second inverter circuit comprises an eighth N-type transistor provided between the source of the seventh N-type transistor and the third power supply, with the gate receiving the control signal, and an eighth P-type transistor provided between the second power supply and the source of the seventh P-type transistor, with the gate receiving an inverted signal of the control signal.

10. An input / output circuit according to claim 7, wherein the first inverter circuit switches between a first operating state in which it functions as an inverter and a second operating state in which the output becomes a fixed signal, based on a control signal.

11. An input / output circuit according to claim 7, comprising: an eighth N-type transistor whose drain is connected to the second power supply and whose source and gate are connected to the third node; and an eighth P-type transistor whose source and gate are connected to the third node and whose drain is connected to the third power supply.

12. An input / output circuit according to claim 7, comprising: an eighth P-type transistor whose source and gate are connected to the second power supply and whose drain is connected to the third node; and an eighth N-type transistor whose source and gate are connected to the third power supply and whose drain is connected to the third node.

13. An input / output circuit that outputs an output signal that changes in accordance with a first input signal from an input / output terminal and receives a second input signal input to the input / output terminal, comprising: a first P-type transistor whose source is connected to a first power supply, whose drain is connected to a first node, and whose gate receives a signal that changes in accordance with the first input signal; a second P-type transistor whose source is connected to the first node, whose drain is connected to a second node, and whose gate is connected to a second power supply with a lower power supply voltage than the first power supply; a third P-type transistor whose source is connected to the second node, whose drain is connected to the input / output terminal, and whose gate is connected to a third node; a first N-type transistor whose drain is connected to the input / output terminal, whose source is connected to a fourth node, and whose gate is connected to the third node; and a second N-type transistor whose drain is connected to the fourth node, whose source is connected to a fifth node, and whose gate is connected to a third power supply with a lower power supply voltage than the second power supply. A third N-type transistor whose drain is connected to the fifth node, whose source is connected to a fourth power supply having a lower power supply voltage than the third power supply, and whose gate receives a signal that changes according to the first input signal; a fourth N-type transistor whose drain is connected to the second power supply, whose source is connected to the third node, and whose gate is connected to the second node; a fourth P-type transistor whose source is connected to the third node, whose drain is connected to the third power supply, and whose gate is connected to the fourth node; a fifth N-type transistor whose drain is connected to the second power supply, whose source is connected to the sixth node, and whose gate is connected to the second node; a sixth N-type transistor whose drain is connected to the sixth node, whose source is connected to the seventh node, and whose gate is connected to the second node; a fifth P-type transistor whose source is connected to the seventh node, whose drain is connected to the eighth node, and whose gate is connected to the fourth node; a sixth P-type transistor whose source is connected to the eighth node, whose drain is connected to the third power supply, and whose gate is connected to the fourth node; A first inverter circuit whose input is connected to the seventh node and whose output is connected to the ninth node,An input / output circuit comprising: a second inverter circuit whose input is connected to the ninth node, the second inverter circuit comprising: a seventh P-type transistor whose source is connected to the second power supply, whose drain is connected to the eighth node, and whose gate is connected to the ninth node; and a seventh N-type transistor whose source is connected to the third power supply, whose drain is connected to the sixth node, and whose gate is connected to the ninth node.

14. An input / output circuit according to claim 13, wherein the second inverter circuit switches between a first operating state in which it functions as an inverter and a second operating state in which the output becomes high impedance, based on a control signal.

15. An input / output circuit according to claim 14, wherein the second inverter circuit comprises an eighth N-type transistor provided between the source of the seventh N-type transistor and the third power supply, with the gate receiving the control signal, and an eighth P-type transistor provided between the second power supply and the source of the seventh P-type transistor, with the gate receiving an inverted signal of the control signal.

16. An input / output circuit according to claim 13, wherein the first inverter circuit switches between a first operating state in which it functions as an inverter and a second operating state in which the output becomes a fixed signal, based on a control signal.

17. An input / output circuit according to claim 13, comprising: an eighth N-type transistor whose drain is connected to the second power supply and whose source and gate are connected to the third node; and an eighth P-type transistor whose source and gate are connected to the third node and whose drain is connected to the third power supply.

18. An input / output circuit according to claim 13, comprising: an eighth P-type transistor whose source and gate are connected to the second power supply and whose drain is connected to the third node; and an eighth N-type transistor whose source and gate are connected to the third power supply and whose drain is connected to the third node.

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