Display driving circuit and display device

Abstract

A display driving circuit and a display device. The display driving circuit comprises a first clock group (CZ1), a second clock group (CZ2) and gate driving circuits (100). By means of using different clock groups for node control modules (11) and first output modules (12) respectively, second gate control signals output by second output modules (14) can be individually adjusted while first gate control signals output by the first output modules (12) are kept unchanged, thus helping to improve the display effect according to requirements.

Description

Display driving circuit and display device

[0001] This application claims priority to Chinese Patent Application No. 2024119011514, filed on December 20, 2024, entitled "Display Driving Circuit and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, specifically to a display driving circuit and a display device. Background Technology

[0003] The control display panel has different refresh rates for different display areas to achieve a zoned frequency design, which can reduce power consumption.

[0004] However, the gate drive unit in the gate drive circuit that supports the display panel to realize the segmented frequency design will output multiple gate control signals. The relative positions between the multiple gate control signals are relatively fixed, which may affect the display effect in some cases. Invention Overview

[0005] This application provides a display driving circuit and a display device to alleviate the technical problem that it is difficult to adjust the second gate control signal independently while keeping the first gate control signal unchanged.

[0006] In a first aspect, this application provides a display driving circuit, which includes a first clock group, a second clock group, and a gate driving circuit. The clock signal transmitted in the first clock group is different from the clock signal transmitted in the second clock group. Each gate driving circuit includes multiple cascaded gate driving units. Each gate driving unit includes a node control module, at least one first output module, at least one first frequency divider module, and a second output module. The node control module is electrically connected to the first clock group, the first node of the gate driving unit at this level, and the second node of the gate driving unit at this level, and is configured to control the transmission of clock signals to the first clock group according to a first control signal and the clock signal in the first clock group. The signals of the first node and the second node; each first output module is electrically connected to the first node and the second node, and each first output module is configured to output a first gate control signal according to the frequency division control signal, the clock signal transmitted in the second clock group, the signal of the first node and the signal of the second node; the first frequency division module is electrically connected to the first node, the second node and the first output module, and is configured to control the signal transmission between the first node and the corresponding first output module according to the frequency division control signal and the signal of the second node; the second output module is electrically connected to the first node and is configured to output a second gate control signal according to the corresponding frequency division control signal and the signal of the first node.

[0007] Secondly, this application provides a display device, which includes a display panel and the aforementioned display driving circuit. The display panel includes a plurality of pixel groups arranged in sequence, each pixel group including two adjacent rows of sub-pixels. The second gate control signal of the X1-level gate driving unit in the first gate driving circuit drives the X2-th pixel group, and the second gate control signal of the X3-level gate driving unit in the second gate driving circuit drives the X2-th pixel group. Wherein, X2 is greater than X3 and less than X1, and X1, X2, and X3 are all integers. The difference between X1 and X3 is 2n+3, where n is an integer greater than or equal to 0. Beneficial effects

[0008] The display driving circuit and display device provided in this application are connected to the first clock group through the node control module and the first output module is connected to the second clock group. This allows the node control module and the first output module to use different clock groups. Compared with the node control module and the first output module using the same clock group, the second gate control signal output by the second output module can be adjusted separately while keeping the first gate control signal output by the first output module unchanged. This is beneficial for improving the display effect as needed. Attached Figure Description

[0009] Figure 1 is a schematic diagram of the display driving circuit provided in an embodiment of this application.

[0010] Figure 2 is a circuit schematic diagram of the gate driving unit provided in an embodiment of this application.

[0011] Figure 3 is a timing diagram of the gate drive unit shown in Figure 2.

[0012] Figure 4 is a schematic diagram of the structure of the display device provided in the embodiment of this application.

[0013] Figure 5 is a circuit schematic diagram of a sub-pixel provided in an embodiment of this application.

[0014] Figure 6 is a timing diagram of the sub-pixels shown in Figure 5. Embodiments of the present invention

[0015] To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description of this application is provided with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining this application and are not intended to limit this application.

[0016] This embodiment provides a display driving circuit. Please refer to Figures 1 to 6. As shown in Figure 1, the display driving circuit includes a first clock group CZ1, a second clock group CZ2, and a gate driving circuit 100. Each gate driving circuit 100 includes multiple cascaded gate driving units, which include odd-numbered gate driving units and even-numbered gate driving units.

[0017] Odd-numbered gate drive units include, for example, the first-stage gate drive unit, the third-stage gate drive unit, and so on. Even-numbered gate drive units include, for example, the second-stage gate drive unit, the fourth-stage gate drive unit, and so on.

[0018] The first clock group CZ1 includes a first clock line and a second clock line. The first clock line is electrically connected to one of the odd-level gate driving units and the even-level gate driving units, and the second clock line is electrically connected to the other of the odd-level gate driving units and the even-level gate driving units.

[0019] The first clock line is used to transmit the first clock signal ECK1, and the second clock line is used to transmit the second clock signal ECK2. The frequency of the first clock signal ECK1 is the same as the frequency of the second clock signal ECK2, and the phase of the first clock signal ECK1 is different from the phase of the second clock signal ECK2.

[0020] The second clock group CZ2 includes four clock lines, which transmit the third clock signal PCK1, the fourth clock signal PCK2, the fifth clock signal PCK3, and the sixth clock signal PCK4, respectively. The third clock signal PCK1, the fourth clock signal PCK2, the fifth clock signal PCK3, and the sixth clock signal PCK4 all have the same frequency but different phases.

[0021] The clock signal transmitted in the first clock group CZ1 is different from the clock signal transmitted in the second clock group CZ2. For example, the duty cycle of the clock signal transmitted in the first clock group CZ1 is different from the duty cycle of the clock signal transmitted in the second clock group CZ2. The low level of the clock signal transmitted in the first clock group CZ1 is different in timing from the low level of the clock signal transmitted in the second clock group CZ2, and / or, the falling edge of the clock signal transmitted in the first clock group CZ1 is different in timing from the falling edge of the clock signal transmitted in the second clock group CZ2. This allows the second gate control signal to be adjusted independently while keeping the first gate control signal unchanged.

[0022] The clock signals CK1 and CK2 connected to the odd-numbered gate drive units originate from the third clock signal PCK1 and the fourth clock signal PCK2, respectively, while the clock signal ECK connected to the odd-numbered gate drive units originates from the first clock signal ECK1. The clock signals CK1 and CK2 connected to the even-numbered gate drive units originate from the fifth clock signal PCK3 and the sixth clock signal PCK4, while the clock signal ECK connected to the even-numbered gate drive units originates from the second clock signal ECK2.

[0023] The first-stage gate driver unit receives the start signal STV and outputs at least one of the first gate control signals, namely Pscan[1] and Pscan[2], and the second gate control signal, namely Nscan[1]. The second-stage gate driver unit outputs at least one of the first gate control signals, namely Pscan[3] and Pscan[4], and the second gate control signal, namely Nscan[2]. The third-stage gate driver unit outputs at least one of the first gate control signals, namely Pscan[5] and Pscan[6], and the second gate control signal, namely Nscan[3]. The fourth-stage gate driver unit outputs at least one of the first gate control signals, namely Pscan[7] and Pscan[8], and the second gate control signal, namely Nscan[4]. This continues until the last-stage gate driver unit.

[0024] As shown in Figure 2, the gate driving unit, namely GA[q], includes a node control module 11. The node control module 11 is electrically connected to the first clock group CZ1, the first node K of the current gate driving unit, and the second node P[n] of the current gate driving unit. It is configured to control the signals transmitted to the first node K and the second node P[n] according to the first control signal and the clock signal in the first clock group CZ1.

[0025] Each gate drive unit, GA[q], also includes at least one first output module 12. Each first output module 12 is electrically connected to the first node K and the second node P[n]. Each first output module 12 is configured to output a first gate control signal according to the frequency division control signal FL, the clock signal transmitted in the second clock group CZ2, the signal of the first node K, and the signal of the second node P[n].

[0026] Each gate drive unit, GA[q], also includes at least one first frequency divider module 13. The first frequency divider module 13 is electrically connected to the first node K, the second node P[n], and the first output module 12, and is configured to control the signal transmission between the first node K and the corresponding first output module 12 according to the frequency divider control signal FL and the signal of the second node P[n].

[0027] Each gate drive unit, GA[q], also includes a second output module 14, which is electrically connected to the first node K and is configured to output a second gate control signal according to the corresponding frequency division control signal FL and the signal of the first node K.

[0028] It is understood that the display driving circuit provided in this embodiment is connected to the first clock group CZ1 through the node control module 11 and the second clock group CZ2 through the first output module 12, so that the node control module 11 and the first output module 12 use different clock groups. Compared with the node control module 11 and the first output module 12 using the same clock group, the second gate control signal output by the second output module 14 can be adjusted separately while keeping the first gate control signal output by the first output module 12 unchanged, which is beneficial to improve the display effect as needed.

[0029] In some embodiments, the gate drive unit further includes a second frequency divider module 15 and a first control module 16. The second frequency divider module 15 is electrically connected to the first node K, the second node P[n], and the second output module 14, and is configured to control the signal transmission between the first node K and the second output module 14 according to the frequency divider control signal FL and the signal of the second node P[n]. The first control module 16 is electrically connected to the second output module 14 and is configured to control the signal transmission between the first power supply terminal PVGH and the second output module 14 according to the clock signal in the first clock group CZ1 and the potential of the second node P[n].

[0030] It should be noted that by controlling the first control module 16 through the clock signal in the first clock group CZ1, the first gate control signal output by the first output module 12 can be kept unchanged, thus avoiding the impact of separate adjustment of the second gate control signal output by the second output module 14.

[0031] In some embodiments, the first control module 16 includes a first transistor T17 and a second transistor T18. The first terminal of the first transistor T17 is electrically connected to the second output module 14, and the gate of the first transistor T17 is connected to the clock signal in the first clock group CZ1. The first terminal of the second transistor T18 is electrically connected to the second terminal of the first transistor T17, the gate of the second transistor T18 is electrically connected to the second node P[n], and the second terminal of the second transistor T18 is electrically connected to the first power supply terminal PVGH.

[0032] In some embodiments, the gate drive unit further includes a second control module 17, which is electrically connected to the first output module 12 and is configured to control the signal transmission between the first power supply terminal PVGH and at least one first output module 12 according to the clock signal in the first clock group CZ1 and the potential of the second node P[n].

[0033] It should be noted that by controlling the second control module 17 through the clock signal in the first clock group CZ1, the first gate control signal output by the first output module 12 can be kept unchanged, thus avoiding the impact of separate adjustment of the second gate control signal output by the second output module 14.

[0034] In some embodiments, the second control module 17 includes a third transistor T21 and a fourth transistor T22. The first terminal of the third transistor T21 is electrically connected to the first output module 12, and the gate of the third transistor T21 is connected to the clock signal in the first clock group CZ1. The first terminal of the fourth transistor T22 is electrically connected to the second terminal of the third transistor T21, the gate of the fourth transistor T22 is electrically connected to the second node P[n], and the second terminal of the fourth transistor T22 is electrically connected to the first power supply terminal PVGH.

[0035] In some embodiments, the gate drive unit further includes a third control module 18, which is electrically connected to the first node K and the second node P[n] and is configured to control the signal transmission between the first power supply terminal PVGH and the first node K according to the clock signal in the first clock group CZ1 and the potential of the second node P[n].

[0036] It should be noted that by controlling the third control module 18 through the clock signal in the first clock group CZ1, the first gate control signal output by the first output module 12 can be kept unchanged, thus avoiding the impact of separate adjustment of the second gate control signal output by the second output module 14.

[0037] In some embodiments, the third control module 18 includes a fifth transistor T4 and a sixth transistor T5. The first terminal of the fifth transistor T4 is electrically connected to the first node K, and the gate of the fifth transistor T4 is connected to the clock signal in the first clock group CZ1. The first terminal of the sixth transistor T5 is electrically connected to the second terminal of the fifth transistor T4, the gate of the sixth transistor T5 is electrically connected to the second node P[n], and the second terminal of the sixth transistor T5 is electrically connected to the first power supply terminal PVGH.

[0038] In some embodiments, as shown in FIG2, the node control module 11 includes at least one of a seventh transistor T13, an eighth transistor T12, a ninth transistor T2, a tenth transistor T1, and an eleventh transistor T3.

[0039] The control terminal of the seventh transistor T13 is configured to receive the corresponding start signal STV or the signal of the second node, P[n-1], in the previous gate drive unit. The input terminal of the seventh transistor T13 is electrically connected to the third power supply terminal NVGL or the fourth power supply terminal PVGL.

[0040] The control terminal of the eighth transistor T12 is electrically connected to the control terminal of the seventh transistor T13, the input terminal of the eighth transistor T12 is electrically connected to the first power supply terminal PVGH, and the output terminal of the eighth transistor T12 is electrically connected to the output terminal of the seventh transistor T13.

[0041] The control terminal of the ninth transistor T2 is configured to receive ECK. The input terminal of the ninth transistor T2 is electrically connected to the output terminal of the seventh transistor T13, and the output terminal of the ninth transistor T2 is electrically connected to the first node K.

[0042] The control terminal of the tenth transistor T1 is electrically connected to the first node K, the input terminal of the tenth transistor T1 is electrically connected to the fourth power supply terminal PVGL, and the output terminal of the tenth transistor T1 is electrically connected to the second node P[n].

[0043] The control terminal of the eleventh transistor T3 is electrically connected to the first node K, the input terminal of the eleventh transistor T3 is electrically connected to the first power supply terminal PVGH, and the output terminal of the eleventh transistor T3 is electrically connected to the second node P[n].

[0044] In some embodiments, as shown in FIG2, the node control module 11 further includes a twelfth transistor T14, the control terminal of the twelfth transistor T14 being electrically connected to the second node P[n], the input terminal of the twelfth transistor T14 being electrically connected to the third power supply terminal NVGL, and the output terminal of the twelfth transistor T14 being electrically connected to the first node K.

[0045] The first frequency divider module 13 includes a first frequency divider transistor T20, a second frequency divider transistor T19, and a first capacitor C3.

[0046] The control terminal of the first frequency divider transistor T20 is electrically connected to the second node P[n] of the gate drive circuit of this stage, and the input terminal of the first frequency divider transistor T20 is connected to the first frequency divider control signal FL1.

[0047] The control terminal of the second frequency divider transistor T19 is electrically connected to the output terminal of the first frequency divider transistor T20. The input terminal of the second frequency divider transistor T19 is electrically connected to the first node K. The output terminal of the second frequency divider transistor T19 is electrically connected to the corresponding first output module 12 and node M.

[0048] The first terminal of the first capacitor C3 is electrically connected to the control terminal of the second frequency divider transistor T19, and the second terminal of the first capacitor C3 is electrically connected to the output terminal of the second frequency divider transistor T19.

[0049] In some embodiments, as shown in FIG2, the second frequency divider module 15 includes a third frequency divider transistor T16, a fourth frequency divider transistor T11, and a second capacitor C2.

[0050] The control terminal of the third frequency divider transistor T16 is electrically connected to the second node P[n], and the input terminal of the third frequency divider transistor T16 is connected to the second frequency divider control signal FL2.

[0051] The control terminal of the fourth frequency divider transistor T11 is electrically connected to the output terminal of the third frequency divider transistor T16, the input terminal of the fourth frequency divider transistor T11 is electrically connected to the first node K, and the output terminal of the fourth frequency divider transistor T11 is electrically connected to the corresponding second output module 14 and node W.

[0052] The first terminal of the second capacitor C2 is electrically connected to the control terminal of the fourth frequency divider transistor T11, and the second terminal of the second capacitor C2 is electrically connected to the output terminal of the fourth frequency divider transistor T11.

[0053] Please refer to Figure 2. One of the first output modules 12 includes a first switching transistor T8, a first output transistor T6, a second output transistor T7, and a third capacitor C1.

[0054] The control terminal of the first switching transistor T8 is electrically connected to the second node P[n-2] of the (n-2)th stage gate drive unit, and the input terminal of the first switching transistor T8 is electrically connected to node M.

[0055] The control terminal of the first output transistor T6 is electrically connected to the corresponding first frequency divider module 13. The input terminal of the first output transistor T6 is configured to receive the corresponding clock signal CK1, and the output terminal of the first output transistor T6 is configured to output the first gate control signal, namely Pscan[q].

[0056] The control terminal of the second output transistor T7 is electrically connected to the second node P[n], the input terminal of the second output transistor T7 is electrically connected to the first power supply terminal PVGH, and the output terminal of the second output transistor T7 is electrically connected to the output terminal of the first output transistor T6.

[0057] The first terminal of the third capacitor C1 is electrically connected to the control terminal of the first output transistor T6, and the second terminal of the third capacitor C1 is electrically connected to the output terminal of the first output transistor T6.

[0058] Please refer to Figure 2, where another first output module 12 includes a second switching transistor T23, a third output transistor T24, a fourth output transistor T25, and a fourth capacitor C4.

[0059] The control terminal of the second switching transistor T23 is electrically connected to the second node P[n-2] of the (n-2)th stage gate drive unit, and the input terminal of the second switching transistor T23 is electrically connected to node M.

[0060] The control terminal of the third output transistor T24 is electrically connected to the corresponding first frequency divider module 13. The input terminal of the third output transistor T24 is configured to receive the corresponding clock signal CK2, and the output terminal of the third output transistor T24 is configured to output the first gate control signal, namely Pscan[q+1].

[0061] The control terminal of the fourth output transistor T25 is electrically connected to the second node P[n], the input terminal of the fourth output transistor T25 is electrically connected to the first power supply terminal PVGH, and the output terminal of the fourth output transistor T25 is electrically connected to the output terminal of the third output transistor T24.

[0062] The first terminal of the fourth capacitor C4 is electrically connected to the control terminal of the third output transistor T24, and the second terminal of the fourth capacitor C4 is electrically connected to the output terminal of the third output transistor T24.

[0063] Please refer to Figure 2. The second output module 14 includes a fifth output transistor T9 and a sixth output transistor T10.

[0064] The control terminal of the fifth output transistor T9 is electrically connected to the output terminal of the fourth frequency divider transistor T11. The input terminal of the fifth output transistor T9 is electrically connected to the second power supply terminal NVGH. The output terminal of the fifth output transistor T9 is used to output the second gate control signal, namely Nscan[q].

[0065] The control terminal of the sixth output transistor T10 is electrically connected to the first node K, the input terminal of the sixth output transistor T10 is electrically connected to the third power supply terminal NVGL, and the output terminal of the sixth output transistor T10 is electrically connected to the output terminal of the fifth output transistor T9.

[0066] Please refer to Figure 2. The gate drive unit also includes a reset transistor T15. The control terminal of the reset transistor T15 is configured to receive a reset control signal Ctr. The input terminal of the reset transistor T15 is electrically connected to the first power supply terminal PVGH, and the output terminal of the reset transistor T15 is electrically connected to the first node K.

[0067] Optionally, the reset transistor T15 is configured to be enabled when the display device is powered on and / or during the blanking interval.

[0068] Optionally, each of the above-mentioned transistors can be a P-type transistor or an N-type transistor. The semiconductor of each of the above-mentioned transistors can be a silicon semiconductor or an oxide semiconductor.

[0069] Optionally, in some embodiments, the first transistor T17, the third transistor T21, the fifth transistor T4, the seventh transistor T13, the tenth transistor T1, the twelfth transistor T14, and the sixth output transistor T10 are N-type transistors, and the remaining transistors are P-type transistors.

[0070] Optionally, in some embodiments, the voltage corresponding to the fourth power supply terminal PVGL is less than the voltage corresponding to the first power supply terminal PVGH, and the voltage corresponding to the third power supply terminal NVGL is less than the voltage corresponding to the second power supply terminal NVGH.

[0071] Figure 3 is a timing diagram of the gate drive unit shown in Figure 2. As can be seen from Figure 3, as the pulse of the start signal STV changes, the pulse of the second gate control signal, Nscan[q], also changes accordingly; at the same time, the waveforms of node Q1 and node Q2 also change accordingly, but the effective pulses at node Q1 and node Q2 do not change. Therefore, the first gate control signals, Pscan[q] and Pscan[q+1], remain unchanged.

[0072] The low-level widths of node Q1 and Q2 are both 4H, and the low-level widths of Pscan[q] and Pscan[q+1] are both 2H. The low-level width of Pscan[q] coincides with the low-level width of node Q1 in timing, and the low-level width of Pscan[q+1] coincides with the low-level width of node Q2 in timing.

[0073] The low-level width of node Q1 and the low-level width of node Q2 are controlled by the clock signal ECK in the first clock group CZ1 to control the ninth transistor T2. Therefore, as the positions of the start signal STV pulse and the ECK pulse move, the positions of the low-level width of node Q1 and the low-level width of node Q2 will also move.

[0074] In other words, after the positions of the start signals STV and ECK are moved, the 4H low-level widths of nodes Q1 and Q2, which control the generation of the first gate control signal, will also be moved. The 2H widths for generating Pscan[q] and Pscan[q+1] only need to be within the 4H low-level widths of nodes Q1 and Q2. Therefore, when the start signals STV and ECK are moved, the second gate control signal can be adjusted without changing Pscan[q] and Pscan[q+1]. This is because the clock signals in the first clock group CZ1 and the clock signals in the second clock group CZ2 are different types of signals.

[0075] In other words, the first clock signal ECK1 and the second clock signal ECK2 belong to the same type of signal, as do the third clock signal PCK1, the fourth clock signal PCK2, the fifth clock signal PCK3, and the sixth clock signal PCK4. The first clock signal ECK1 and the second clock signal ECK2 belong to a different type of signal than the third clock signal PCK1, the fourth clock signal PCK2, the fifth clock signal PCK3, and the sixth clock signal PCK4.

[0076] In some embodiments, as shown in FIG4, the display driving circuit includes two gate driving circuits 100, which include a first gate driving circuit 101 and a second gate driving circuit 102. The first control signal is a start signal STV or the signal of the second node P[n-1] in the previous gate driving unit. When the first control signal is the start signal STV, the first gate driving circuit 101 is connected to the first start signal STV, and the second gate driving circuit 102 is connected to the second start signal STV. The difference between the pulse duration of the first start signal STV and the pulse duration of the second start signal STV is greater than or equal to 4H, where H is a unit time. The falling edge of the first start signal STV coincides with the falling edge of the second start signal STV in time.

[0077] It should be noted that this makes the first gate control signal of the X4th level gate driving unit in the first gate driving circuit 101 completely consistent with the first gate control signal of the X4th level gate driving unit in the second gate driving circuit 102, so that the two gate driving circuits 100 can drive the same row of sub-pixels Spi on both sides.

[0078] In some embodiments, as shown in FIG4, this embodiment provides a display device, which includes a display panel 200 and the aforementioned display driving circuit. The display panel 200 includes a plurality of pixel groups arranged in sequence, and each pixel group includes two adjacent rows of sub-pixels Spi. The second gate control signal of the X1-level gate driving unit in the first gate driving circuit 101 drives the X2-level pixel group, and the second gate control signal of the X3-level gate driving unit in the second gate driving circuit 102 drives the X2-level pixel group. Wherein, X2 is greater than X3 and less than X1, and X1, X2 and X3 are all integers. The difference between X1 and X3 is 2n+3, where n is an integer greater than or equal to 0.

[0079] It is understood that since the display device provided in this embodiment includes the above-mentioned display driving circuit, it can also be connected to the first clock group CZ1 through the node control module 11 and the second clock group CZ2 through the first output module 12, so that the node control module 11 and the first output module 12 use different clock groups. Compared with the node control module 11 and the first output module 12 using the same clock group, the second gate control signal output by the second output module 14 can be adjusted separately while keeping the first gate control signal output by the first output module 12 unchanged, which is beneficial to improve the display effect as needed.

[0080] It should be noted that X1 being greater than X3 allows the reset transistor Tr of each sub-pixel Spi in the X2 pixel group to turn on before the compensation transistor Tc of each sub-pixel Spi in the X2 pixel group.

[0081] The first four rows of sub-pixels Spi from top to bottom can be exemplarily virtual sub-pixels Spi. Nscan-Tc represents the second gate control signal of the first gate drive circuit 101 used to control the switching of the compensation transistor Tc in the sub-pixel Spi. Nscan-Tr represents the second gate control signal of the second gate drive circuit 102 used to control the switching of the reset transistor Tr in the sub-pixel Spi.

[0082] In some embodiments, the first gate control signal of the X4th level gate driving unit in the first gate driving circuit 101 drives the X2th pixel group, and the first gate control signal of the X4th level gate driving unit in the second gate driving circuit 102 drives the X2th pixel group; wherein, X4 is greater than X3 and less than X1, the difference between X4 and X3 is greater than or equal to 2, and X4 is an integer.

[0083] It should be noted that this ensures that the write transistor will only be turned on when the reset transistor Tr is off, thus avoiding interference with the writing of data signals.

[0084] In some embodiments, as shown in FIG4, the display driving circuit may further include a third gate driving circuit 103, which includes a plurality of cascaded shift registers, each shift register being used to provide a light emission control signal EM, and each light emission control signal controlling a pixel group in two paths.

[0085] In some embodiments, the first clock group CZ1 is electrically connected to the third gate drive circuit 103 to provide a corresponding clock signal to the third gate drive circuit 103.

[0086] It should be noted that the first gate drive circuit 101 and the second gate drive circuit 102 reuse the clock signal in the first clock group CZ1, which can realize the individual adjustment of the second gate control signal without adding an extra clock line or clock signal.

[0087] In some embodiments, as shown in FIG4, the display driving circuit may further include a fourth gate driving circuit 104, which includes a plurality of cascaded shift registers, each shift register being used to provide an initialization control signal, and each initialization control signal controlling a pixel group in two ways.

[0088] As shown in Figure 5, each sub-pixel Spi includes a light-emitting device Di and a pixel driving circuit that drives the light-emitting device Di to emit light. The pixel driving circuit includes a driving transistor Tdr and a writing transistor Tda.

[0089] Optionally, the light-emitting device Di can be an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode, etc.

[0090] The driving transistor Tdr is electrically connected to the light-emitting device Di between the first voltage terminal Vdd and the second voltage terminal Vss. The driving transistor Tdr is configured to generate a driving current to drive the light-emitting device Di to emit light.

[0091] Optionally, the input terminal of the driving transistor Tdr is electrically connected to the first voltage terminal Vdd, the output terminal of the driving transistor Tdr is electrically connected to the anode of the light-emitting device Di, the cathode of the light-emitting device Di is electrically connected to the second voltage terminal Vss, and the voltage supplied by the first voltage terminal Vdd is greater than the voltage supplied by the second voltage terminal Vss.

[0092] The write transistor Tda is configured to transmit a data signal to the control terminal of the drive transistor Tdr. Specifically, the input terminal of the write transistor Tda is configured to receive the corresponding data signal DS, the output terminal of the write transistor Tda is electrically connected to the input terminal of the drive transistor Tdr, and the control terminal of the write transistor Tda is connected to the first gate control signal, Pscan[q]. This allows control over the frequency at which multiple sub-pixels (Spi) refresh the display data, enabling the display panel 200 to achieve a segmented frequency display design.

[0093] The sub-pixel Spi also includes a compensation transistor Tc. The input terminal of the compensation transistor Tc is electrically connected to the output terminal of the driving transistor Tdr. The output terminal of the compensation transistor Tc is electrically connected to the control terminal of the driving transistor Tdr. The control terminal of the compensation transistor Tc is configured to receive the second gate control signal, namely Nscan[q].

[0094] The sub-pixel Spi includes a reset transistor Tr, the input of which is electrically connected to the reset line VLr, and the output of which is electrically connected to the control terminal of the drive transistor Tdr. The control terminal of the reset transistor Tr is configured to receive the second gate control signal, namely Nscan[q-3].

[0095] Optionally, the compensation transistor Tc and the reset transistor Tr are silicon transistors or oxide transistors, and are either P-type or N-type transistors. Optionally, to reduce leakage current from the control terminal of the driving transistor Tdr to its output terminal and the reset line VLr, the compensation transistor Tc and the reset transistor Tr are oxide transistors. For compatibility with existing manufacturing processes, the compensation transistor Tc and the reset transistor Tr are N-type transistors. It is understood that the active layer of the oxide transistor includes indium gallium zinc oxide, etc.

[0096] Please refer to Figure 5. The sub-pixel Spi also includes a first initial transistor Ti1, a first light-emitting control transistor Te1, a second light-emitting control transistor Te2, and a storage capacitor Cst.

[0097] The input terminal of the first initial transistor Ti1 is configured to receive the first initial signal transmitted by the first initial line VL1, the output terminal of the first initial transistor Ti1 is electrically connected to the anode of the light-emitting device Di, and the control terminal of the first initial transistor Ti1 is configured to receive Pscan2.

[0098] The input terminal of the first light-emitting control transistor Te1 is electrically connected to the first voltage terminal Vdd, and the output terminal of the first light-emitting control transistor Te1 is electrically connected to the input terminal of the driving transistor Tdr.

[0099] The input terminal of the second light-emitting control transistor Te2 is electrically connected to the output terminal of the driving transistor Tdr. The output terminal of the second light-emitting control transistor Te2 is electrically connected to the anode of the light-emitting device Di. The control terminal of the second light-emitting control transistor Te2 is electrically connected to the control terminal of the first light-emitting control transistor Te1 and is connected to the light-emitting control signal EM.

[0100] The first terminal of the storage capacitor Cst is electrically connected to the first voltage terminal Vdd, and the second terminal of the storage capacitor Cst is electrically connected to the control terminal of the driving transistor Tdr.

[0101] Optionally, the sub-pixel Spi also includes a bootstrap capacitor Cboost, the first terminal of which is electrically connected to the control terminal of the data transistor Tda, and the second terminal of which is electrically connected to the control terminal of the driving transistor Tdr.

[0102] Please refer to Figures 5 and 6. Before the improvement, the time difference between the rising edge of Nscan[q-3] and the rising edge of Nscan[q] was 4H, and the time difference between the falling edge of Nscan[q-3] and the falling edge of Nscan[q] was 4H. Pscan[q] and Pscan[q+1] both had negative pulses when Nscan[q-3] was low and Nscan[q] was high, so as to realize the writing of the data signal DS.

[0103] However, the timing configuration prior to the aforementioned improvements resulted in poor optical performance of the subpixels, specifically manifested as flickering, color shift, and low-frequency flicker during VRR (high-low frequency image switching).

[0104] The time difference between the rising edge of Nscan[q-3] and the rising edge of Nscan[q], and / or the time difference between the falling edge of Nscan[q-3] and the falling edge of Nscan[q], can also be set to 0H, but setting it to 0H will worsen the ghosting.

[0105] By improving the above-mentioned display driving circuit, the output waveform of the second gate control signal can be adjusted by approximately ±0.5H before and after the first gate control signal remains unchanged.

[0106] This means that when the first gate driving circuit 101 and the second gate driving circuit 102 on both the left and right sides output the same first gate control signal, the time difference between the rising edge of Nscan[q-3] and the rising edge of Nscan[q], and / or the time difference between the falling edge of Nscan[q-3] and the falling edge of Nscan[q], can not be an integer multiple of H. That is, the time difference between rising edges can be finely adjusted under the premise of the design value of 2H, and each second gate control signal can be finely adjusted by ±0.5H. Finally, the time difference between the rising edge and / or the time difference between the falling edge of Nscan[q-3] and Nscan[q] can be adjusted between 1H and 3H, which can fully meet the VRR's requirement for the time difference between rising edges, thereby achieving a normal display effect under VRR.

[0107] Optionally, in order to achieve the best display performance under VRR, the rising edge time difference and / or falling edge time difference between Nscan[q-3] and Nscan[q] can be adjusted to a value between 1.5H and 2H.

[0108] It is understood that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of this application, and all such substitutions or changes should fall within the protection scope of the appended claims.

Claims

1. A display drive circuit, wherein, The display driving circuit includes a first clock group, a second clock group, and a gate driving circuit. The clock signal transmitted in the first clock group is different from the clock signal transmitted in the second clock group. Each gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes: The node control module is electrically connected to the first clock group, the first node of the gate driving unit of this level, and the second node of the gate driving unit of this level, and is configured to control the signals transmitted to the first node and the second node according to the first control signal and the clock signal in the first clock group. At least one first output module, each first output module being electrically connected to the first node and the second node, each first output module being configured to output a first gate control signal according to a frequency division control signal, a clock signal transmitted in the second clock group, a signal from the first node and a signal from the second node; At least one first frequency divider module is electrically connected to the first node, the second node and the first output module, and is configured to control the signal transmission between the first node and the corresponding first output module according to the frequency divider control signal and the signal of the second node; The second output module, electrically connected to the first node, is configured to output a second gate control signal according to the corresponding frequency division control signal and the signal of the first node.

2. The display drive circuit of claim 1, wherein, The gate driving unit further includes: The second frequency division module is electrically connected to the first node, the second node and the second output module, and is configured to control the signal transmission between the first node and the second output module according to the frequency division control signal and the signal of the second node; The first control module, electrically connected to the second output module, is configured to control the signal transmission between the first power supply terminal and the second output module based on the clock signal in the first clock group and the potential of the second node.

3. The display drive circuit of claim 2, wherein, The first control module includes: The first transistor has its first terminal electrically connected to the second output module, and its gate is connected to the clock signal in the first clock group. The second transistor has its first terminal electrically connected to the second terminal of the first transistor, its gate electrically connected to the second node, and its second terminal electrically connected to the first power supply terminal.

4. The display drive circuit of claim 1, wherein, The gate driving unit further includes a second control module, which is electrically connected to the first output module and is configured to control the signal transmission between the first power supply terminal and at least one of the first output modules according to the clock signal in the first clock group and the potential of the second node.

5. The display drive circuit of claim 4, wherein, The second control module includes: The third transistor has its first terminal electrically connected to the first output module, and its gate is connected to the clock signal in the first clock group. The fourth transistor has its first terminal electrically connected to the second terminal of the third transistor, its gate electrically connected to the second node, and its second terminal electrically connected to the first power supply terminal.

6. The display drive circuit of claim 1, wherein, The gate driving unit further includes a third control module, which is electrically connected to the first node and the second node and is configured to control the signal transmission between the first power supply terminal and the first node according to the clock signal in the first clock group and the potential of the second node.

7. The display drive circuit of claim 6, wherein, The third control module includes: The fifth transistor has its first terminal electrically connected to the first node, and its gate connected to the clock signal in the first clock group. The sixth transistor has its first terminal electrically connected to the second terminal of the fifth transistor, its gate electrically connected to the second node, and its second terminal electrically connected to the first power supply terminal.

8. The display drive circuit of claim 1, wherein, The plurality of cascaded gate drive units include odd-numbered gate drive units and even-numbered gate drive units; The first clock group includes a first clock line and a second clock line. The first clock line is electrically connected to one of the odd-level gate driving units and the even-level gate driving units, and the second clock line is electrically connected to the other of the odd-level gate driving units and the even-level gate driving units.

9. The display driving circuit according to any one of claims 1-8, wherein, The display driving circuit includes two gate driving circuits, and the two gate driving circuits include a first gate driving circuit and a second gate driving circuit. The first control signal is a start signal or a signal of the second node in the gate driving unit of the previous stage; when the first control signal is the start signal, the first gate driving circuit is connected to the first start signal, and the second gate driving circuit is connected to the second start signal. The difference between the pulse duration of the first start signal and the pulse duration of the second start signal is greater than or equal to 4H, where H is a unit time; the falling edge of the first start signal coincides with the falling edge of the second start signal in time.

10. A display device, wherein, The display device includes: The display panel includes a plurality of pixel groups arranged in sequence, each pixel group including two adjacent rows of sub-pixels; The display driving circuit as described in claim 9, wherein the second gate control signal of the X1-level gate driving unit in the first gate driving circuit drives the X2-th pixel group, and the second gate control signal of the X3-level gate driving unit in the second gate driving circuit drives the X2-th pixel group; Where X2 is greater than X3 and less than X1, and X1, X2 and X3 are all integers; the difference between X1 and X3 is 2n+3, where n is an integer greater than or equal to 0.

11. The display device of claim 10, wherein, In the first gate driving circuit, the first gate control signal of the X4th stage gate driving unit drives the X2nd pixel group, and in the second gate driving circuit, the first gate control signal of the X4th stage gate driving unit drives the X2nd pixel group. Where X4 is greater than X3 and less than X1, the difference between X4 and X3 is greater than or equal to 2, and X4 is an integer.

12. The display device of claim 10, wherein, The display driving circuit includes a first clock group, a second clock group, and a gate driving circuit. The clock signal transmitted in the first clock group is different from the clock signal transmitted in the second clock group. Each gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes: The node control module is electrically connected to the first clock group, the first node of the gate driving unit of this level, and the second node of the gate driving unit of this level, and is configured to control the signals transmitted to the first node and the second node according to the first control signal and the clock signal in the first clock group. At least one first output module, each first output module being electrically connected to the first node and the second node, each first output module being configured to output a first gate control signal according to a frequency division control signal, a clock signal transmitted in the second clock group, a signal from the first node and a signal from the second node; At least one first frequency divider module is electrically connected to the first node, the second node and the first output module, and is configured to control the signal transmission between the first node and the corresponding first output module according to the frequency divider control signal and the signal of the second node; The second output module, electrically connected to the first node, is configured to output a second gate control signal according to the corresponding frequency division control signal and the signal of the first node.

13. The display device of claim 12, wherein, The duty cycle of the clock signal transmitted in the first clock group is different from the duty cycle of the clock signal transmitted in the second clock group.

14. The display device of claim 13, wherein, The gate driving unit further includes: The second frequency division module is electrically connected to the first node, the second node and the second output module, and is configured to control the signal transmission between the first node and the second output module according to the frequency division control signal and the signal of the second node; The first control module, electrically connected to the second output module, is configured to control the signal transmission between the first power supply terminal and the second output module based on the clock signal in the first clock group and the potential of the second node.

15. The display device of claim 14, wherein, The first control module includes: The first transistor has its first terminal electrically connected to the second output module, and its gate is connected to the clock signal in the first clock group. The second transistor has its first terminal electrically connected to the second terminal of the first transistor, its gate electrically connected to the second node, and its second terminal electrically connected to the first power supply terminal.

16. The display device of claim 13, wherein, The gate driving unit further includes a second control module, which is electrically connected to the first output module and is configured to control the signal transmission between the first power supply terminal and at least one of the first output modules according to the clock signal in the first clock group and the potential of the second node.

17. The display device of claim 16, wherein, The second control module includes: The third transistor has its first terminal electrically connected to the first output module, and its gate is connected to the clock signal in the first clock group. The fourth transistor has its first terminal electrically connected to the second terminal of the third transistor, its gate electrically connected to the second node, and its second terminal electrically connected to the first power supply terminal.

18. The display device of claim 13, wherein, The gate driving unit further includes a third control module, which is electrically connected to the first node and the second node and is configured to control the signal transmission between the first power supply terminal and the first node according to the clock signal in the first clock group and the potential of the second node.

19. The display device of claim 18, wherein, The third control module includes: The fifth transistor has its first terminal electrically connected to the first node, and its gate connected to the clock signal in the first clock group. The sixth transistor has its first terminal electrically connected to the second terminal of the fifth transistor, its gate electrically connected to the second node, and its second terminal electrically connected to the first power supply terminal.

20. The display device of claim 13, wherein, The plurality of cascaded gate drive units include odd-numbered gate drive units and even-numbered gate drive units; The first clock group includes a first clock line and a second clock line. The first clock line is electrically connected to one of the odd-level gate driving units and the even-level gate driving units, and the second clock line is electrically connected to the other of the odd-level gate driving units and the even-level gate driving units.

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