Semiconductor device, power module, conversion circuit, vehicle, and method for manufacturing semiconductor device
By introducing a second region and buried layer structure into the semiconductor device, a PN junction parasitic diode and transistor are formed, which solves the problem of large reverse conduction voltage drop in silicon carbide trench devices and achieves higher performance stability and safety.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- YOFC ADVANCED SEMICONDUCTOR (WUHAN) CO LTD
- Filing Date
- 2025-08-12
- Publication Date
- 2026-06-25
AI Technical Summary
The reverse conduction voltage drop of silicon carbide trench devices is too large, which affects the stability and reliability of the devices, and existing technologies are unable to solve this problem effectively.
Introducing a second region and buried layer structure into a semiconductor device forms a PN junction parasitic diode and transistor, enhancing the reverse conduction freewheeling capability. By integrating the freewheeling diode and transistor, the reverse conduction voltage drop is reduced, and the discharge speed is increased.
It effectively reduces the reverse conduction voltage drop of semiconductor devices, improves the performance stability and safety of devices, and enhances the discharge speed during reverse connection.
Smart Images
Figure CN2025113989_25062026_PF_FP_ABST
Abstract
Description
Semiconductor devices, power modules, conversion circuits, vehicles, and methods for fabricating semiconductor devices.
[0001] This application claims priority to Chinese Patent Application No. 202411885611.9, filed with the Chinese Patent Office on December 20, 2024, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, such as semiconductor devices, power modules, conversion circuits, vehicles, and methods for fabricating semiconductor devices. Background Technology
[0003] Silicon carbide trench devices have advantages such as high current density and small cell pitch, and are widely used. In trench devices, there is a parasitic PN junction diode between the source and drain, which is often used as a freewheeling diode. However, when a positive voltage is applied to the source, its reverse conduction voltage drop is too large, which affects the stability and reliability of the device. Summary of the Invention
[0004] This application provides semiconductor devices, power modules, conversion circuits, vehicles, and methods for fabricating semiconductor devices, reducing reverse conduction voltage drop of semiconductor devices, increasing the discharge speed of semiconductor devices when reverse connected, and improving the performance stability and safety of semiconductor devices.
[0005] This application provides a semiconductor device, comprising: a semiconductor body including a substrate, an epitaxial layer, a well region, a first region, and a second region; the epitaxial layer is located on one side of the substrate, the well region is disposed on the side of the epitaxial layer away from the substrate, and the first region is disposed on the side of the well region away from the substrate; the surface of the first region away from the substrate is a first surface, and the first surface is respectively provided with a gate trench and a source trench, both of which extend from the first surface into the epitaxial layer; the second region is disposed on the side of the source trench away from or close to the gate trench; the first region and the epitaxial layer are of a first doping type, and the well region and the second region are of a second doping type; a gate structure is located within the gate trench; a source structure is located within the source trench; and a drain is located on the side of the substrate away from the epitaxial layer.
[0006] In one embodiment, the second region is disposed on the side of the source trench away from the gate trench, the second region extends from the first surface into the epitaxial layer, and the orthographic projection of the second region on the bottom of the source trench at least covers a portion of the bottom of the source trench.
[0007] In one embodiment, the semiconductor body further includes: a first buried layer disposed in the epitaxial layer on the side of the source trench near the gate trench, wherein the orthographic projection of the first buried layer on the sidewall of the source trench near the gate trench does not overlap with the orthographic projections of the well region and the first region on the sidewall of the source trench near the gate trench.
[0008] In one embodiment, the second region is disposed on the side of the source trench near the gate trench, and the second region extends from the first surface into the epitaxial layer; the orthographic projection of the second region on the bottom of the source trench at least covers a portion of the bottom of the source trench.
[0009] In one embodiment, the semiconductor body further includes: a second buried layer disposed in the epitaxial layer on the side of the source trench away from the gate trench, wherein the orthographic projection of the second buried layer on the sidewall of the source trench away from the gate trench does not overlap with the orthographic projections of the well region and the first region on the sidewall of the source trench away from the gate trench.
[0010] In one embodiment, the source structure includes a first insulating layer and a trench source; the first insulating layer is disposed on the inner wall and bottom of the source trench; the trench source is disposed in the source trench on one side of the first insulating layer; wherein the length of the trench source in the extending direction of the source trench is greater than the depth of the source trench.
[0011] In one embodiment, the semiconductor device further includes: a second insulating layer disposed on the side of the first surface away from the gate structure; the orthographic projection of the second insulating layer on the first surface covers the gate structure; an ohmic contact metal layer located on the side of the second insulating layer away from the gate structure, the ohmic contact metal layer being electrically connected to the first region; the metal material of the ohmic contact metal layer including titanium.
[0012] This application also provides a power module, including a substrate and at least one of the above-described semiconductor devices, wherein the substrate is configured to support the semiconductor devices.
[0013] This application also provides a power conversion circuit, which is configured to perform one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, the semiconductor device being electrically connected to the circuit board.
[0014] This application also provides a vehicle including a load and the aforementioned power conversion circuit, wherein the power conversion circuit is configured to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.
[0015] This application also provides a method for fabricating a semiconductor device, comprising: providing a semiconductor body, the semiconductor body including a substrate, an epitaxial layer, a well region, a first region, and a second region, the epitaxial layer being located on one side of the substrate, the well region being disposed on the side of the epitaxial layer away from the substrate, and the first region being disposed on the side of the well region away from the substrate; the surface of the first region away from the substrate serving as a first surface, the first surface being respectively provided with a gate trench and a source trench, the gate trench and the source trench both extending from the first surface into the epitaxial layer; the second region being disposed on the side of the source trench away from or near the gate trench; the first region and the epitaxial layer being of a first doping type, and the well region and the second region being of a second doping type; forming a gate structure in the gate trench; forming a source structure in the source trench; and forming a drain on the side of the substrate away from the epitaxial layer.
[0016] In one embodiment, when the second region is disposed on the side of the source trench away from the gate trench, the second region extends from the first surface into the epitaxial layer, and the orthographic projection of the second region on the bottom of the source trench at least covers a portion of the bottom of the source trench.
[0017] In one embodiment, the semiconductor body further includes a first buried layer; the fabrication method further includes: forming the first buried layer in the epitaxial layer on the side of the source trench near the gate trench, wherein the orthographic projection of the first buried layer on the sidewall of the source trench near the gate trench does not overlap with the orthographic projections of the well region and the first region on the sidewall of the source trench near the gate trench.
[0018] In one embodiment, when the second region is disposed on the side of the source trench near the gate trench, the second region extends from the first surface into the epitaxial layer; the orthographic projection of the second region on the bottom of the source trench at least covers a portion of the bottom of the source trench.
[0019] In one embodiment, the semiconductor body further includes a second buried layer; the fabrication method further includes: forming the second buried layer in the epitaxial layer on the side of the source trench away from the gate trench, wherein the orthographic projection of the second buried layer on the sidewall of the source trench away from the gate trench does not overlap with the orthographic projections of the well region and the first region on the sidewall of the source trench away from the gate trench.
[0020] In one embodiment, forming a source structure within the source trench includes: forming a first insulating layer on the inner wall and bottom of the source trench; and forming a trench source within the source trench on one side of the first insulating layer, wherein the length of the trench source in the extending direction of the source trench is greater than the depth of the source trench.
[0021] In one embodiment, the semiconductor device further includes: an ohmic contact metal layer and a second insulating layer; the fabrication method further includes: forming the second insulating layer on the side of the first surface away from the gate structure; the orthographic projection of the second insulating layer on the first surface covers the gate structure; forming the ohmic contact metal layer on the side of the second insulating layer away from the gate structure, the ohmic contact metal layer being electrically connected to the first region; the metal material of the ohmic contact metal layer includes titanium. Attached Figure Description
[0022] Figure 1 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;
[0023] Figure 2 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;
[0024] Figure 3 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;
[0025] Figure 4 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;
[0026] Figure 5 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;
[0027] Figure 6 is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of this application;
[0028] Figure 7 is a schematic diagram of an intermediate structure of a preparation process provided in an embodiment of this application;
[0029] Figure 8 is a schematic diagram of the intermediate structure of another preparation process provided in the embodiments of this application;
[0030] Figure 9 is a schematic diagram of the intermediate structure of another preparation process provided in the embodiments of this application;
[0031] Figure 10 is a schematic diagram of the intermediate structure of another preparation process provided in the embodiments of this application;
[0032] Figure 11 is a schematic diagram of the intermediate structure of another preparation process provided in the embodiment of this application;
[0033] Figure 12 is a schematic diagram of the intermediate structure of another preparation process provided in the embodiment of this application;
[0034] Figure 13 is a schematic diagram of the intermediate structure of another preparation process provided in the embodiments of this application. Detailed Implementation
[0035] Figure 1 is a schematic diagram of a semiconductor device provided in an embodiment of this application. Referring to Figure 1, it includes: a semiconductor body 100, which includes a substrate 10, an epitaxial layer 20, a well region 30, a first region 40, and a second region 50. The epitaxial layer 20 is located on one side of the substrate 10, the well region 30 is disposed on the side of the epitaxial layer 20 away from the substrate 10, and the first region 40 is disposed on the side of the well region 30 away from the substrate 10. The surface of the first region 40 away from the substrate 10 is designated as a first surface. The first surface is provided with a gate trench 70 and a source trench 60, both of which extend from the first surface into the epitaxial layer 20; the second region 50 is disposed on the side of the source trench 60 away from or close to the gate trench 70; the first region 40 and the epitaxial layer 20 are of the first doping type, and the well region 30 and the second region 50 are of the second doping type; the gate structure is located in the gate trench 70; the source structure is located in the source trench 60; and the drain 110 is located on the side of the substrate 10 away from the epitaxial layer 20.
[0036] The material of the substrate 10 and the epitaxial layer 20 may be the same or different. For example, the materials of the substrate 10 and the epitaxial layer 20 may include silicon or silicon carbide. The semiconductor device in this embodiment may be a silicon carbide trench metal-oxide-semiconductor field-effect transistor (MOSFET). The first doping type in this embodiment may be N-type doping, and the second doping type may be P-type doping, or the first doping type may be P-type doping, and the second doping type may be N-type doping. In the accompanying drawings, P+ and N+ indicate high ion doping concentration in the region, and P- and N- indicate low ion doping concentration in the region. Among them, the N-type doping ion may be phosphorus (P) or nitrogen (N) ions, and the P-type doping ion may be aluminum (Al) ions or boron (B) ions. For example, in this embodiment of the application, the first doping type is N-type doping and the second doping type is P-type doping. When the semiconductor device is an N-type device, the substrate 10 is N+ type doped, for example, it can be an N+ silicon carbide substrate 10; the epitaxial layer 20 is N- type doped, for example, it can be an N- silicon carbide epitaxial layer 20; when the semiconductor device is a P-type device, the substrate 10 is P+ type doped and the epitaxial layer 20 is P- type doped.
[0037] An epitaxial layer 20 is formed on one side of the substrate 10. A well region 30 is formed on the side of the epitaxial layer 20 away from the substrate 10, and a first region 40 is formed on the side of the well region 30 away from the substrate 10. The well region 30 is of a second doping type, and the first region 40 is of a first doping type. The well region 30 and the first region 40 are configured to form a conductive channel for a semiconductor device. The well region 30 and the first region 40 can be formed by methods such as epitaxial growth, ion implantation, or vapor deposition.
[0038] A gate trench 70 and a source trench 60 are formed on the first surface through an etching process. The gate trench 70 and the source trench 60 can be formed simultaneously in the same fabrication process. In other embodiments, the gate trench 70 and the source trench 60 are set to different depths, so they need to be etched stepwise in different fabrication processes. For example, the depth of the source trench 60 can be 1.2-2.5 μm, and the depth of the gate trench 70 can be 0.7-1.2 μm. By selecting appropriate depths for the source trench 60 and the gate trench 70, the on-resistance and breakdown voltage of the semiconductor device can be optimized while ensuring device performance, enabling the device to operate stably at higher voltages. The gate trench 70 and the source trench 60 pass through the first region 40 and the well region 30, extending from the first surface to the epitaxial layer 20. The source trench 60 is located on one side of the gate trench 70 and can be an annular trench, configured to surround the gate trench 70. The source trench 60 can also be an independent trench, and multiple source trenches 60 are distributed on both sides of the gate trench 70. For example, in Figure 1, source trenches 60 are arranged on both sides of the gate trench 70, and the two source trenches 60 can be arranged symmetrically or asymmetrically. A second region 50 is formed on the side of the source trench 60 away from the gate trench 70 by ion implantation.
[0039] A gate structure is disposed within a gate trench 70, and a source structure is disposed within a source trench 60. For example, the gate structure may include a first insulating layer 71 and a trench gate 72. The first insulating layer 71 is disposed on the inner wall and bottom of the gate trench 70. The first insulating layer 71 may be a gate oxide layer, which may be a high dielectric constant (K) material. The trench gate 72 may be a polysilicon layer. The gate structure is disposed within the gate trench 70, and the well regions 30 on both sides of the gate structure can form vertical conductive channels, which can eliminate the junction field-effect transistor (JFET) region, resulting in lower on-resistance of the semiconductor device.
[0040] The source structure may include a first insulating layer 71 and a trench source 62. The first insulating layer 71 is disposed on the inner wall and bottom of the source trench 60. The trench source 62 may be a polysilicon layer. The first insulating layer 71 in the source structure may be the same as the first insulating layer 71 in the gate structure. Therefore, during fabrication, the first insulating layer 71 in the source structure and the first insulating layer 71 in the gate structure may be formed simultaneously. The source structure is disposed within the source trench 60. The second region 50 is disposed on the side of the source trench 60 away from the gate trench 70. That is, the second region 50 is disposed on the side of the source structure away from the gate structure. The doping type of the second region 50 is the same as the doping type of the well region 30. Therefore, a depletion region can be formed between the second region 50 and the epitaxial layer 20, which can shield the electric field of the gate structure, thereby improving the problem of gate oxide breakdown and ensuring the reliability of device operation. Furthermore, since the second region 50 and the epitaxial layer 20 have different doping types, a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20, serving as a freewheeling diode 102. Because the second region 50 is not provided on the side of the source trench 60 near the gate trench 70, a PNP or NPN transistor is formed between the epitaxial layer 20, the well region 30, and the first region 40 on the side of the source trench 60 near the gate trench 70, serving as a freewheeling transistor 101. Therefore, a freewheeling diode 102 and a freewheeling transistor 101 are integrated on both sides of the source trench, respectively. The source metal layer 120 is electrically connected to the source structure. The source metal layer 120 serves as the source of the semiconductor device. When a positive voltage is applied to the source, the freewheeling diode 102 can conduct. When a positive voltage is applied to the source, the source structure acts as the control electrode of the freewheeling transistor 101, and the freewheeling transistor 101 can also conduct. By integrating the freewheeling diode 102 and the freewheeling transistor 101, the reverse connection freewheeling path of the semiconductor device is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the discharge speed of the semiconductor device during reverse connection is increased, and the performance stability and safety of the semiconductor device are improved.
[0041] In some embodiments, the second region 50 may also be disposed on the side of the source trench 60 near the gate trench 70. Figure 2 is a schematic diagram of another semiconductor device provided in an embodiment of this application. Referring to Figure 2, the doping type of the second region 50 is the same as that of the well region 30. Similarly, the second region 50 can also serve to shield the electric field of the gate structure. On the side of the source trench 60 near the gate trench 70, a freewheeling diode 102 is formed between the second region 50 and the epitaxial layer 20. On the side of the source trench 60 away from the gate trench 70, a PNP or NPN freewheeling transistor 101 is formed between the epitaxial layer 20, the well region 30, and the first region 40. This can also increase the reverse connection freewheeling path of the semiconductor device, reduce the reverse conduction voltage drop of the semiconductor device, and increase the discharge speed of the semiconductor device when reverse connected.
[0042] The semiconductor device provided in the embodiments of this application includes: a semiconductor body 100, which includes a substrate 10, an epitaxial layer 20, a well region 30, a first region 40, and a second region 50. The epitaxial layer 20 is located on one side of the substrate 10, the well region 30 is disposed on the side of the epitaxial layer 20 away from the substrate 10, and the first region 40 is disposed on the side of the well region 30 away from the substrate 10. The surface of the first region 40 away from the substrate 10 is used as a first surface, and a gate trench 70 and a source trench 60 are respectively disposed on the first surface. Both the gate trench 70 and the source trench 60 extend from the first surface into the epitaxial layer 20. The second region 50 is disposed on the side of the source trench 60 away from or close to the gate trench 70. The gate structure is located in the gate trench 70. The source structure is located in the source trench 60. The drain 110 is located on the side of the substrate 10 away from the epitaxial layer 20. The first region 40 and the epitaxial layer 20 are of the first doping type, while the well region 30 and the second region 50 are of the second doping type. Because the second region 50 and the epitaxial layer 20 have different doping types, a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20, serving as a freewheeling diode 102. Since the second region 50 is not provided on the side of the source trench 60 near or far from the gate trench 70, a PNP or NPN transistor is formed between the epitaxial layer 20, the well region 30, and the first region 40, serving as a freewheeling transistor 101. Therefore, when a positive voltage is applied to the source, the freewheeling diode 102 can conduct, and the source structure acts as the control electrode of the freewheeling transistor 101, allowing the freewheeling transistor 101 to also conduct. By integrating the freewheeling diode 102 and the freewheeling transistor 101, the reverse connection freewheeling path of the semiconductor device is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the leakage speed of the semiconductor device during reverse connection is improved, and the performance stability and safety of the semiconductor device are enhanced.
[0043] In some embodiments, the second region 50 is disposed on the side of the source trench 60 away from the gate trench 70, the second region 50 extends from the first surface into the epitaxial layer 20, and the orthographic projection of the second region 50 on the bottom of the source trench 60 at least covers a portion of the bottom of the source trench 60.
[0044] Referring again to Figure 1, the second region 50 can be formed on one side of the source trench 60 by ion implantation, so that the second region 50 is distributed on the side of the source trench 60 away from the gate trench 70. In this embodiment, the second region 50 is distributed on the side of the source trench 60 away from the gate trench 70. A PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20, which is used as a freewheeling diode 102. The orthogonal projection of the second region 50 on the bottom of the source trench 60 at least covers part of the bottom of the source trench 60. That is, the second region 50 can at least partially cover the bottom of the source trench 60, or completely cover the bottom of the source trench 60, thereby increasing the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and further improving the electric field of the shielded gate structure.
[0045] Figure 3 is a schematic diagram of the structure of another semiconductor device provided in the embodiment of this application. Referring to Figure 3, the semiconductor body 100 further includes: a first buried layer 80 disposed in the epitaxial layer 20 on the side of the source trench 60 near the gate trench 70. The orthographic projection of the first buried layer 80 on the sidewall of the source trench 60 near the gate trench 70 does not overlap with the orthographic projections of the well region 30 and the first region 40 on the sidewall of the source trench 60 near the gate trench 70.
[0046] The difference from the semiconductor device shown in Figure 1 is that a first buried layer 80 is disposed in the epitaxial layer 20 on the side of the source trench 60 near the gate trench 70. The first buried layer 80 can be formed by ion implantation, and the doping type of the first buried layer 80 is the same as that of the second region 50. For example, when forming the epitaxial layer 20, the first buried layer 80 can be formed by ion implantation, and the source trench 60 is formed according to the position of the first buried layer 80, so that the first buried layer 80 is distributed on the side of the source trench 60 near the gate trench 70. The first buried layer 80 can also cover the bottom of the source trench 60, so that it is adjacent to the second region 50 at the bottom of the source trench 60, further improving the effect of shielding the electric field of the gate structure. The first buried layer 80 can extend along the sidewall of the source trench 60 in the direction pointing to the first region 40, but the first buried layer 80 does not contact the first region 40 and the well region 30 to avoid blocking the channel of the freewheeling transistor 101.
[0047] In some embodiments, the second region 50 is disposed on the side of the source trench 60 near the gate trench 70, and the second region 50 extends from the first surface into the epitaxial layer 20; the orthographic projection of the second region 50 on the bottom of the source trench 60 at least covers a portion of the bottom of the source trench 60.
[0048] Referring again to Figure 2, the second region 50 can be formed on one side of the source trench 60 by ion implantation, so that the second region 50 is distributed on the side of the source trench 60 near the gate trench 70. In this embodiment, the second region 50 is distributed on the side of the source trench 60 near the gate trench 70, and a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20, which is used as a freewheeling diode 102. The orthogonal projection of the second region 50 on the bottom of the source trench 60 at least covers part of the bottom of the source trench 60. That is, the second region 50 can at least partially cover the bottom of the source trench 60, or completely cover the bottom of the source trench 60, thereby increasing the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and the side of the second region 50 near the gate trench 70 can further improve the electric field of the shielded gate structure.
[0049] Figure 4 is a schematic diagram of another semiconductor device provided in an embodiment of this application. Referring to Figure 4, the difference from the semiconductor device shown in Figure 2 is that a second buried layer 90 is provided in the epitaxial layer 20 on the side of the source trench 60 away from the gate trench 70. The second buried layer 90 can be formed by ion implantation, and the doping type of the second buried layer 90 is the same as that of the second region 50. For example, when forming the epitaxial layer 20, the second buried layer 90 can be formed by ion implantation, and the source trench 60 is formed according to the position of the second buried layer 90, so that the second buried layer 90 is distributed on the side of the source trench 60 close to the gate trench 70. The second buried layer 90 can also cover the bottom of the source trench 60, so that it is adjacent to the second region 50 at the bottom of the source trench 60, further improving the effect of shielding the electric field of the gate structure. The second buried layer 90 can extend along the sidewall of the source trench 60 in the direction pointing to the first region 40, but the second buried layer 90 does not contact the first region 40 and the well region 30 to avoid blocking the channel of the freewheeling transistor 101.
[0050] Based on the above embodiments, the source structure includes a first insulating layer 71 and a trench source 62; the first insulating layer 71 is disposed on the inner wall and bottom of the source trench 60; the trench source 62 is disposed in the source trench 60 on one side of the first insulating layer 71; wherein, the length of the trench source 62 in the extending direction of the source trench 60 is greater than the depth of the source trench 60.
[0051] The first insulating layer 71 is disposed on the inner wall and bottom of the source trench 60. The trench source 62 can be a polysilicon layer. The first insulating layer 71 in the source structure is the same as the first insulating layer 71 in the gate structure. Therefore, during fabrication, the first insulating layer 71 in the source structure and the first insulating layer 71 in the gate structure can be formed simultaneously. Then, a polysilicon layer is deposited, and the entire polysilicon layer is etched back, leaving 200-500 nm of polysilicon layer remaining on the first surface. Then, photoresist is used to protect the polysilicon layer in the source trench 60, and etching back continues until the gate trench 70 is filled with a polysilicon layer. The deposition height of the polysilicon layer in the source trench 60 is greater than the depth of the source trench 60. In other words, the polysilicon layer protrudes beyond the plane of the first surface, thus, when the source metal layer 120 is formed on the first surface, the protrusion will be inside the source metal layer 120, thereby increasing the contact area between the polysilicon layer and the source metal layer 120. This is beneficial for improving the voltage sensitivity of the control electrode of the freewheeling transistor 101 and for controlling the conduction process of the freewheeling transistor 101. For example, the protrusion can be cylindrical, trapezoidal, conical, or other regular or irregular shapes, as long as it can increase the contact area between the polysilicon layer and the source metal layer 120.
[0052] Referring to Figures 1-4, the semiconductor device further includes: a second insulating layer 130 disposed on the side of the first surface away from the gate structure; the orthographic projection of the second insulating layer 130 on the first surface covers the gate structure; an ohmic contact metal layer 140 located on the side of the second insulating layer 130 away from the gate structure, the ohmic contact metal layer 140 being electrically connected to the first region 40; the metal material of the ohmic contact metal layer 140 includes titanium.
[0053] A second insulating layer 130 is formed on the surface of the first region 40 away from the substrate 10. The second insulating layer 130 can be an interlayer dielectric (ILD) and can cover the surface of the gate structure. An ohmic contact metal layer 140 is disposed on the side of the second insulating layer 130 away from the gate structure. A source metal layer 120 is formed on the surface of the ohmic contact metal layer 140 away from the substrate 10. The second insulating layer 130 isolates the gate structure and the source metal layer 120. The ohmic contact metal layer 140 is electrically connected to the trench source 62. When the ohmic contact metal layer 140 contacts the trench source 62, the resistance of the contact surface is very small, making the current-voltage relationship linear and not generating significant additional impedance. A good ohmic contact can reduce the contact resistance between the source and the trench source 62, thereby improving the conductivity of the device. The ohmic contact metal of the ohmic contact metal layer 140 can be nickel (Ni), but Ni is prone to reacting with the polysilicon layer, which reduces the reliability of the device. Therefore, the ohmic contact metal can be titanium (Ti). For example, if Ti is used as the ohmic contact metal, the ohmic contact metal layer 140 will not react with the polysilicon layer, and the ohmic contact metal layer 140 has a contact connection with the first region 40. When the first region 40 is N+ doped, titanium and the first region 40 can achieve a lower contact resistance, which can reduce the reverse conduction voltage drop of the freewheeling transistor 101.
[0054] This application provides a power module based on the above embodiments, including a substrate and a semiconductor device according to any embodiment of this application, wherein the substrate is configured to carry the semiconductor device.
[0055] The power module provided by the technical solution of this application has the same beneficial effects as the semiconductor device in any embodiment of this application.
[0056] Based on the above embodiments, this application provides a power conversion circuit. The power conversion circuit is configured to perform one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application. The semiconductor device is electrically connected to the circuit board.
[0057] The power conversion circuit provided in the embodiments of this application has the same beneficial effects as the semiconductor device in any embodiment of this application.
[0058] Based on the above embodiments, this application provides a vehicle including a load and a power conversion circuit as described in any embodiment of this application. The power conversion circuit is configured to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.
[0059] This application provides a method for fabricating a semiconductor device based on the above embodiments. Figure 5 is a flowchart of a method for fabricating a semiconductor device provided in this application. Referring to Figure 5, the fabrication method includes:
[0060] S110. A semiconductor body 100 is provided. The semiconductor body 100 includes a substrate 10, an epitaxial layer 20, a well region 30, a first region 40, and a second region 50. The epitaxial layer 20 is located on one side of the substrate 10. The well region 30 is disposed on the side of the epitaxial layer 20 away from the substrate 10. The first region 40 is disposed on the side of the well region 30 away from the substrate 10. The surface of the first region 40 away from the substrate 10 is a first surface. A gate trench 70 and a source trench 60 are respectively disposed on the first surface. Both the gate trench 70 and the source trench 60 extend from the first surface into the epitaxial layer 20. The second region 50 is disposed on the side of the source trench 60 away from or close to the gate trench 70. The first region 40 and the epitaxial layer 20 are of a first doping type, and the well region 30 and the second region 50 are of a second doping type.
[0061] The material of the substrate 10 and the epitaxial layer 20 may be the same or different. For example, the materials of the substrate 10 and the epitaxial layer 20 may include silicon or silicon carbide. The semiconductor device in this embodiment may be a silicon carbide trench MOSFET. The first doping type in this embodiment may be N-type doping, and the second doping type may be P-type doping, or the first doping type may be P-type doping, and the second doping type may be N-type doping. In the accompanying drawings, P+ and N+ indicate that the ion doping concentration in the region is high, and P- and N- indicate that the ion doping concentration in the region is low. Among them, the N-type doped ion may be P or N ion, and the P-type doped ion may be Al ion or B ion. For example, in this embodiment of the application, the first doping type is N-type doping and the second doping type is P-type doping. When the semiconductor device is an N-type device, the substrate 10 is N+ type doped, for example, it can be an N+ silicon carbide substrate 10; the epitaxial layer 20 is N- type doped, for example, it can be an N- silicon carbide epitaxial layer 20; when the semiconductor device is a P-type device, the substrate 10 is P+ type doped and the epitaxial layer 20 is P- type doped.
[0062] An epitaxial layer 20 is formed on one side of the substrate 10. A well region 30 is formed on the side of the epitaxial layer 20 away from the substrate 10, and a first region 40 is formed on the side of the well region 30 away from the substrate 10. The well region 30 is of a second doping type, and the first region 40 is of a first doping type. The well region 30 and the first region 40 are configured to form a conductive channel for a semiconductor device. The well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation, or vapor deposition. The surface of the first region 40 away from the substrate 10 serves as a first surface. A gate trench 70 and a source trench 60 are formed on the first surface by an etching process. The gate trench 70 and the source trench 60 can be formed simultaneously in the same fabrication process. For example, in some embodiments, the gate trench 70 and the source trench 60 have different depths, so the gate trench 70 and the source trench 60 are etched stepwise in different fabrication processes. For example, the depth of the source trench 60 can be 1.2-2.5 μm, and the depth of the gate trench 70 can be 0.7-1.2 μm. By selecting appropriate depths for the source trench 60 and the gate trench 70, the on-resistance and breakdown voltage of the semiconductor device can be optimized while ensuring device performance, enabling the device to operate stably at higher voltages. The gate trench 70 and the source trench 60 pass through the first region 40 and the well region 30, extending from the first surface to the epitaxial layer 20. The source trench 60 is located on one side of the gate trench 70, and the source trench 60 can be an annular trench, configured to surround the gate trench 70. The source trench 60 can also be an independent trench, and multiple source trenches 60 are distributed on both sides of the gate trench 70. For example, in the figure, source trenches 60 are arranged on both sides of the gate trench 70, and the two source trenches 60 can be arranged symmetrically or asymmetrically. A second region 50 is formed on the side of the source trench 60 away from the gate trench 70 by ion implantation.
[0063] Referring to Figure 1, when the second region 50 is disposed on the side of the source trench 60 away from the gate trench 70, the second region 50 extends from the first surface into the epitaxial layer 20, and the orthographic projection of the second region 50 onto the bottom of the source trench 60 at least partially covers the bottom of the source trench 60. That is, the second region 50 can at least partially cover the bottom of the source trench 60, or completely cover the bottom of the source trench 60, thereby increasing the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and further enhancing the electric field of the shielded gate structure.
[0064] Referring to Figure 2, the second region 50 can also be disposed on the side of the source trench 60 near the gate trench 70. When the second region 50 is disposed on the side of the source trench 60 near the gate trench 70, the second region 50 extends from the first surface into the epitaxial layer 20; the orthographic projection of the second region 50 onto the bottom of the source trench 60 at least partially covers the bottom of the source trench 60. That is, the second region 50 can at least partially cover the bottom of the source trench 60, or completely cover the bottom of the source trench 60, thereby increasing the contact area between the second region 50 and the epitaxial layer 20, thereby increasing the depletion region between the second region 50 and the epitaxial layer 20, and the side of the second region 50 near the gate trench 70 can further enhance the electric field of the shielded gate structure.
[0065] S120. A gate structure is formed in the gate trench.
[0066] A gate structure is disposed within a gate trench 70, and a source structure is disposed within a source trench 60. For example, the gate structure may include a first insulating layer 71 and a trench gate 72. The first insulating layer 71 is disposed on the inner wall and bottom of the gate trench 70. The first insulating layer 71 may be a gate oxide layer, which may be a high dielectric constant (K) material. The trench gate 72 may be a polysilicon layer. The gate structure is disposed within the gate trench 70, and the well regions 30 on both sides of the gate structure can form vertical conductive channels, which can eliminate the JFET region and reduce the on-resistance of the semiconductor device.
[0067] S130, a source structure is formed in the source trench.
[0068] The source structure may include a first insulating layer 71 and a trench source 62. The first insulating layer 71 is disposed on the inner wall and bottom of the source trench 60. The trench source 62 may be a polysilicon layer. The source structure is disposed within the source trench 60. A second region 50 is disposed on the side of the source trench 60 away from the gate trench 70. That is, the second region 50 is disposed on the side of the source structure away from the gate structure. The doping type of the second region 50 is the same as that of the well region 30. Therefore, a depletion region can be formed between the second region 50 and the epitaxial layer 20, which can shield the electric field of the gate structure, thereby improving the problem of gate oxide breakdown and ensuring the reliability of device operation. Furthermore, since the second region 50 and the epitaxial layer 20 have different doping types, a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20, which is used as a freewheeling diode 102. Since the second region 50 is not provided on the side of the source trench 60 near the gate trench 70, a PNP or NPN transistor is formed between the epitaxial layer 20, the well region 30, and the first region 40 on the side of the source trench 60 near the gate trench 70, serving as a freewheeling transistor 101. Therefore, a freewheeling diode and a freewheeling transistor 101 are integrated on both sides of the source trench, respectively. A source metal layer 120 covers the first surface, wherein the source metal layer 120 is electrically connected to the source structure. When a positive voltage is applied to the source, the freewheeling diode 102 can conduct. When a positive voltage is applied to the source, the source structure acts as the control electrode of the freewheeling transistor 101, and the freewheeling transistor 101 can also conduct. By integrating the freewheeling diode 102 and the freewheeling transistor 101, the reverse connection freewheeling path of the semiconductor device is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the leakage speed of the semiconductor device during reverse connection is improved, and the performance stability and safety of the semiconductor device are enhanced.
[0069] Referring to Figure 2, the second region 50 can also be disposed on the side of the source trench 60 near the gate trench 70. The doping type of the second region 50 is the same as that of the well region 30. Similarly, the second region 50 can also serve to shield the electric field of the gate structure. On the side of the source trench 60 near the gate trench 70, a freewheeling diode 102 is formed between the second region 50 and the epitaxial layer 20. On the side of the source trench 60 away from the gate trench 70, a PNP or NPN freewheeling transistor 101 is formed between the epitaxial layer 20, the well region 30, and the first region 40. This can also increase the reverse connection freewheeling path of the semiconductor device, reduce the reverse conduction voltage drop of the semiconductor device, and increase the discharge speed of the semiconductor device during reverse connection.
[0070] S140, A drain electrode is formed on the side of the substrate away from the epitaxial layer.
[0071] The drain 110 can be formed on the side of the substrate 10 away from the epitaxial layer 20 by means of sputtering or other methods. In this process, the surface of the substrate 10 away from the epitaxial layer 20 is first thinned, and then the drain 110 is formed by sputtering or other methods. The drain 110 is a metal conductive layer. For example, the metal conductive layer can be Ti, Ni, or silver (Ag).
[0072] The method for fabricating a semiconductor device provided in the embodiments of this application includes: providing a semiconductor body 100, the semiconductor body 100 including a substrate 10, an epitaxial layer 20, a well region 30, a first region 40 and a second region 50, the epitaxial layer 20 being located on one side of the substrate 10, the well region 30 being disposed on the side of the epitaxial layer 20 away from the substrate 10, and the first region 40 being disposed on the side of the well region 30 away from the substrate 10; the surface of the first region 40 away from the substrate 10 serving as a first surface, the first surface being provided with a gate trench 70 and a source trench 60, both the gate trench 70 and the source trench 60 extending from the first surface into the epitaxial layer 20; the second region 50 being disposed on the side of the source trench 60 away from or close to the gate trench 70; a gate structure being formed in the gate trench 70; a source structure being formed in the source trench 60; and a drain 110 being formed on the side of the substrate 10 away from the epitaxial layer 20. The first region 40 and the epitaxial layer 20 are of the first doping type, while the well region 30 and the second region 50 are of the second doping type. Because the second region 50 and the epitaxial layer 20 have different doping types, a PN junction parasitic diode can be formed between the second region 50 and the epitaxial layer 20, serving as a freewheeling diode 102. Since the second region 50 is not provided on the side of the source trench 60 or away from the side closest to the gate trench 70, a PNP or NPN transistor is formed between the epitaxial layer 20, the well region 30, and the first region 40, serving as a freewheeling transistor 101. Therefore, when a positive voltage is applied to the source, the freewheeling diode 102 can conduct, and the source structure acts as the control electrode of the freewheeling transistor 101, allowing the freewheeling transistor 101 to also conduct. By integrating the freewheeling diode 102 and the freewheeling transistor 101, the reverse connection freewheeling path of the semiconductor device is increased, the reverse conduction voltage drop of the semiconductor device is reduced, the leakage speed of the semiconductor device during reverse connection is improved, and the performance stability and safety of the semiconductor device are enhanced.
[0073] The semiconductor body 100 also includes a first buried layer 80; the fabrication method further includes: forming the first buried layer 80 in the epitaxial layer 20 on the side of the source trench 60 near the gate trench 70, wherein the orthographic projection of the first buried layer 80 on the sidewall of the source trench 60 near the gate trench 70 does not overlap with the orthographic projections of the well region 30 and the first region 40 on the sidewall of the source trench 60 near the gate trench 70.
[0074] Referring to Figure 3, the first buried layer 80 can be formed by ion implantation, and the first buried layer 80 has the same doping type as the second region 50. For example, when forming the epitaxial layer 20, the first buried layer 80 can be formed by ion implantation, and a source trench 60 is formed according to the position of the first buried layer 80, so that the first buried layer 80 is distributed on the side of the source trench 60 near the gate trench 70. The first buried layer 80 can also cover the bottom of the source trench 60, achieving an adjacent arrangement with the second region 50 at the bottom of the source trench 60, further enhancing the effect of shielding the gate structure electric field. The first buried layer 80 can extend along the sidewall of the source trench 60 in the direction pointing towards the first region 40, but the first buried layer 80 does not contact the first region 40 and the well region 30, avoiding blocking the channel of the freewheeling transistor 101.
[0075] The semiconductor body 100 further includes a second buried layer 90; the fabrication method further includes: forming a second buried layer 90 in an epitaxial layer 20 on the side of the source trench 60 away from the gate trench 70, wherein the orthographic projection of the second buried layer 90 on the sidewall of the source trench 60 away from the gate trench 70 does not overlap with the orthographic projections of the well region 30 and the first region 40 on the sidewall of the source trench 60 away from the gate trench 70.
[0076] Referring to Figure 4, the second buried layer 90 can be formed by ion implantation, and the doping type of the second buried layer 90 is the same as that of the second region 50. For example, when forming the epitaxial layer 20, the second buried layer 90 can be formed by ion implantation, and a source trench 60 is formed according to the position of the second buried layer 90, so that the second buried layer 90 is distributed on the side of the source trench 60 near the gate trench 70. The second buried layer 90 can also cover the bottom of the source trench 60, achieving an adjacent arrangement with the second region 50 at the bottom of the source trench 60, further enhancing the effect of shielding the electric field of the gate structure. The second buried layer 90 can extend along the sidewall of the source trench 60 in the direction pointing towards the first region 40, but the second buried layer 90 does not contact the first region 40 and the well region 30, avoiding blocking the channel of the freewheeling transistor 101.
[0077] Forming a source structure within a source trench 60 includes: forming a first insulating layer 71 on the inner wall and bottom of the source trench 60; and forming a trench source 62 within the source trench 60 on one side of the first insulating layer 71, wherein the length of the trench source 62 in the extending direction of the source trench 60 is greater than the depth of the source trench 60.
[0078] The first insulating layer 71 is disposed on the inner wall and bottom of the source trench 60. The trench source 62 can be a polysilicon layer, and the first insulating layer 71 in the source structure can be the same as the first insulating layer 71 in the gate structure. Therefore, during fabrication, the first insulating layer 71 in the source structure and the first insulating layer 71 in the gate structure can be formed simultaneously. Then, a polysilicon layer is deposited, and the entire polysilicon layer is etched back to leave 200-500 nm of polysilicon layer remaining on the first surface. Then, photoresist is used to protect the polysilicon layer in the source trench 60, and etching back continues to fill the gate trench 70 with a polysilicon layer. The deposition height of the polysilicon layer in the source trench 60 is greater than the depth of the source trench 60. In other words, the polysilicon layer protrudes beyond the plane of the first surface, thus, when the source metal layer 120 is formed on the first surface, the protrusion will be inside the source metal layer 120, thereby increasing the contact area between the polysilicon layer and the source metal layer 120. This is beneficial for improving the voltage sensitivity of the control electrode of the freewheeling transistor 101 and for controlling the conduction process of the freewheeling transistor 101. For example, the protrusion can be cylindrical, trapezoidal, conical, or other regular or irregular shapes, as long as it can increase the contact area between the polysilicon layer and the source metal layer 120.
[0079] The semiconductor device further includes: an ohmic contact metal layer 140 and a second insulating layer 130; the fabrication method further includes: forming the second insulating layer 130 on the side of the first surface away from the gate structure; the orthographic projection of the second insulating layer 130 on the first surface covers the gate structure; forming the ohmic contact metal layer 140 on the side of the second insulating layer 130 away from the gate structure, the ohmic contact metal layer 140 being electrically connected to the first region 40; the metal material of the ohmic contact metal layer 140 includes titanium.
[0080] A second insulating layer 130 is formed on the surface of the first region 40 away from the substrate 10. The second insulating layer 130 can be an ILD (Integrated Water Layer) and can cover the surface of the gate structure. An ohmic contact metal layer 140 is disposed on the side of the second insulating layer 130 away from the gate structure. A source electrode is formed on the surface of the ohmic contact metal layer 140 away from the substrate 10. The second insulating layer 130 isolates the gate structure and the source electrode. The ohmic contact metal layer 140 is electrically connected to the trench source electrode 62. When the ohmic contact metal layer 140 contacts the trench source electrode 62, the resistance of the contact surface is very small, making the current-voltage relationship linear and not generating significant additional impedance. A good ohmic contact can reduce the contact resistance between the source electrode and the trench source electrode 62, thereby improving the conductivity efficiency of the device. The ohmic contact metal of the ohmic contact metal layer 140 can be Ni, but Ni is prone to reacting with the polysilicon layer, which reduces the reliability of the device. Therefore, the ohmic contact metal can be Ti. For example, if Ti is used as the ohmic contact metal, the ohmic contact metal layer 140 will not react with the polysilicon layer, and the ohmic contact metal layer 140 has a contact connection with the first region 40. When the first region 40 is N+ doped, the contact between titanium and the first region 40 can achieve a lower contact resistance, thereby reducing the reverse conduction voltage drop of the freewheeling transistor 101.
[0081] This application uses the semiconductor device structure shown in Figure 3 as an example to introduce a method for fabricating a semiconductor device. Figure 6 is a flowchart of another method for fabricating a semiconductor device provided in this application. Figure 7 is a schematic diagram of an intermediate structure of a fabrication process provided in this application. Figure 8 is a schematic diagram of an intermediate structure of a fabrication process provided in this application. Figure 9 is a schematic diagram of an intermediate structure of a fabrication process provided in this application. Figure 10 is a schematic diagram of an intermediate structure of a fabrication process provided in this application. Figure 11 is a schematic diagram of an intermediate structure of a fabrication process provided in this application. Figure 12 is a schematic diagram of an intermediate structure of a fabrication process provided in this application. Figure 13 is a schematic diagram of an intermediate structure of a fabrication process provided in this application. The fabrication method includes:
[0082] S210, A first portion of an epitaxial layer 20 is formed on one side of the substrate 10, and a first buried layer 80 is formed in the first portion of the epitaxial layer 20.
[0083] The substrate 10 can be an N+ doped silicon carbide substrate. By growing a first epitaxial layer 20 on the substrate 10 and then performing ion implantation at a certain position, a first buried layer 80 of P+ doped type is formed, and its structure is shown in Figure 7.
[0084] S220, a second epitaxial layer 20 is formed on the side of the first epitaxial layer 20 away from the substrate 10, as shown in FIG8.
[0085] S230, a well region 30 is formed on the side of the epitaxial layer 20 in the second part away from the substrate 10; a first region 40 is formed on the side of the well region 30 away from the substrate 10.
[0086] The well region 30 and the first region 40 are configured to form a conductive channel for a semiconductor device. The well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation or vapor deposition, and their structure is shown in Figure 9.
[0087] S240, the surface of the first region 40 away from the substrate 10 is used as the first surface, and a gate trench 70 and a source trench 60 are formed on the first surface, so that the first buried layer 80 is located on the side of the source trench 60 close to the gate trench 70; the gate trench 70 and the source trench 60 both extend from the first surface into the epitaxial layer 20.
[0088] The gate trench 70 and source trench 60 are set to different depths, so they need to be etched stepwise in different fabrication processes. For example, the depth of the source trench 60 can be 1.2-2.5 μm, and the depth of the gate trench 70 can be 0.7-1.2 μm. By selecting appropriate depths for the source trench 60 and the gate trench 70, the on-resistance and breakdown voltage of the semiconductor device can be optimized while ensuring device performance, enabling the device to operate stably at higher voltages. The gate trench 70 and source trench 60 pass through the first region 40 and the well region 30, extending from the first surface to the epitaxial layer 20. Their structure is shown in Figure 10.
[0089] S250, a second region 50 is formed on the side of the source trench 60 away from the gate trench 70.
[0090] A second region 50 is formed on the side of the source trench 60 away from the gate trench 70 by ion implantation. The first region 40 is of the first doping type, and the well region 30 and the second region 50 are of the second doping type; its structure is shown in Figure 11.
[0091] S260, A gate structure is formed in the gate trench 70, and a source structure is formed in the source trench 60.
[0092] A gate structure is disposed within a gate trench 70, and a source structure is disposed within a source trench 60. The gate structure may include a first insulating layer 71 and a trench gate 72. The first insulating layer 71 is disposed on the inner wall and bottom of the gate trench 70. The source structure may include a first insulating layer 71 and a trench source 62. The first insulating layer 71 is disposed on the inner wall and bottom of the source trench 60. During fabrication, the first insulating layer 71 in the source structure and the first insulating layer 71 in the gate structure can be formed simultaneously by a thermal oxidation process. The first insulating layer 71 at the bottom of the gate trench 70 is thicker, while the first insulating layer 71 on the sidewall of the gate trench 70 is thinner. Then, a polysilicon layer is deposited, and the entire polysilicon layer is etched back, leaving 200-500nm of polysilicon layer remaining on the first surface. The polysilicon layer within the source trench 60 is then protected using photoresist, and etching back continues until the gate trench 70 is filled with a polysilicon layer, forming the trench gate 72. The deposition height of the polysilicon layer within the source trench 60 is greater than the depth of the source trench 60. In other words, the polysilicon layer protrudes beyond the plane of the first surface, forming a protrusion. Therefore, when the source metal layer 120 is subsequently formed on the first surface, the protrusion will be inside the source metal layer 120, thereby increasing the contact area between the polysilicon layer and the source metal layer 120. This is beneficial for improving the voltage sensitivity of the control electrode of the freewheeling transistor 101 and for controlling the conduction process of the freewheeling transistor 101. For example, the protrusion can be cylindrical, trapezoidal, conical, or other regular or irregular shapes, as long as it increases the contact area between the polysilicon layer and the source metal layer 120. Its structure is shown in Figure 12.
[0093] S270, a second insulating layer 130 is formed on the side of the first surface away from the gate structure; the orthogonal projection of the second insulating layer 130 on the first surface covers the gate structure; an ohmic contact metal layer 140 is formed on the side of the second insulating layer 130 away from the gate structure.
[0094] A second insulating layer 130 is fabricated, covering the surface of the gate structure and exposing the ohmic contact region, which includes a portion of the first region. An ohmic contact metal layer 140 is then fabricated. The ohmic contact metal layer 140 is electrically connected to the first region 40; the metal material of the ohmic contact metal layer 140 includes titanium. Its structure is shown in Figure 13.
[0095] S280 forms a source metal layer 120, a passivation layer 150, and a drain 110 on the other side of the substrate 10. Its structure is shown in Figure 3.
Claims
1. A semiconductor device, comprising: A semiconductor body (100) includes a substrate (10), an epitaxial layer (20), a well region (30), a first region (40), and a second region (50). The epitaxial layer (20) is located on one side of the substrate (10), the well region (30) is disposed on the side of the epitaxial layer (20) away from the substrate (10), and the first region (40) is disposed on the side of the well region (30) away from the substrate (10). The surface of the first region (40) away from the substrate (10) serves as the first region (50). A first surface is provided with a gate trench (70) and a source trench (60), both of which extend from the first surface into the epitaxial layer (20); a second region (50) is disposed on the side of the source trench (60) away from or close to the gate trench (70); the first region (40) and the epitaxial layer (20) are of a first doping type, and the well region (30) and the second region (50) are of a second doping type; The gate structure is located within the gate trench (70); The source structure is located within the source trench (60); The drain (110) is located on the side of the substrate (10) away from the epitaxial layer (20).
2. The semiconductor device of claim 1, wherein, The second region (50) is disposed on the side of the source trench (60) away from the gate trench (70), the second region (50) extends from the first surface into the epitaxial layer (20), and the orthographic projection of the second region (50) on the bottom of the source trench (60) at least covers a portion of the bottom of the source trench (60).
3. The semiconductor device of claim 2, wherein, The semiconductor body (100) also includes: A first buried layer (80) is disposed in the epitaxial layer (20) on the side of the source trench (60) near the gate trench (70), wherein the orthographic projection of the first buried layer (80) on the sidewall of the source trench (60) near the gate trench (70) does not overlap with the orthographic projections of the well region (30) and the first region (40) on the sidewall of the source trench (60) near the gate trench (70).
4. The semiconductor device of claim 1, wherein, The second region (50) is disposed on the side of the source trench (60) near the gate trench (70), and the second region (50) extends from the first surface into the epitaxial layer (20); The orthographic projection of the second region (50) onto the bottom of the source trench (60) at least partially covers the bottom of the source trench (60).
5. The semiconductor device of claim 4, wherein, The semiconductor body (100) also includes: The second buried layer is disposed in the epitaxial layer (20) on the side of the source trench (60) away from the gate trench (70), wherein the orthographic projection of the second buried layer on the sidewall of the source trench (60) away from the gate trench (70) does not overlap with the orthographic projections of the well region (30) and the first region (40) on the sidewall of the source trench (60) away from the gate trench (70).
6. The semiconductor device according to any one of claims 1-5, wherein, The source structure includes a first insulating layer (71) and a trench source (62); The first insulating layer (71) is disposed on the inner wall and bottom of the source trench (60); The trench source electrode (62) is disposed in the source trench (60) on one side of the first insulating layer (71); wherein the length of the trench source electrode (62) in the extension direction of the source trench (60) is greater than the depth of the source trench (60).
7. The semiconductor device of claim 6, wherein, The semiconductor device further includes: A second insulating layer (130) is disposed on the side of the first surface away from the gate structure; the orthographic projection of the second insulating layer (130) on the first surface covers the gate structure; An ohmic contact metal layer (140) is located on the side of the second insulating layer (130) away from the gate structure, and the ohmic contact metal layer (130) is electrically connected to the first region (40); the metal material of the ohmic contact metal layer (130) includes titanium.
8. A power module comprising a substrate and at least one semiconductor device as claimed in any one of claims 1-7, wherein the substrate is configured to support the semiconductor device.
9. A power conversion circuit, the power conversion circuit being configured to perform at least one of the following: current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-7, wherein the semiconductor device is electrically connected to the circuit board.
10. A vehicle, comprising a load and a power conversion circuit as claimed in claim 9, the power conversion circuit being configured to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the power to the load.
11. A method for fabricating a semiconductor device, comprising: A semiconductor body is provided, the semiconductor body including a substrate, an epitaxial layer, a well region, a first region and a second region, the epitaxial layer being located on one side of the substrate, the well region being disposed on the side of the epitaxial layer away from the substrate, and the first region being disposed on the side of the well region away from the substrate; the surface of the first region away from the substrate is designated as a first surface, and the first surface is respectively provided with a gate trench and a source trench, both of which extend from the first surface into the epitaxial layer; The second region is disposed on the side of the source trench that is away from or close to the gate trench; the first region and the epitaxial layer are of the first doping type, and the well region and the second region are of the second doping type; A gate structure is formed within the gate trench; A source structure is formed within the source trench; A drain electrode is formed on the side of the substrate away from the epitaxial layer.
12. The method of producing a semiconductor device according to Claim 11, wherein When the second region is disposed on the side of the source trench away from the gate trench, the second region extends from the first surface into the epitaxial layer, and the orthographic projection of the second region on the bottom of the source trench at least covers a portion of the bottom of the source trench.
13. The method of producing a semiconductor device according to Claim 12, wherein The semiconductor body also includes a first buried layer; The preparation method further includes: A first buried layer is formed in the epitaxial layer on the side of the source trench near the gate trench, wherein the orthographic projection of the first buried layer on the sidewall of the source trench near the gate trench does not overlap with the orthographic projections of the well region and the first region on the sidewall of the source trench near the gate trench.
14. The method of producing a semiconductor device according to Claim 11, wherein When the second region is disposed on the side of the source trench close to the gate trench, the second region extends from the first surface into the epitaxial layer; The orthographic projection of the second region onto the bottom of the source trench at least partially covers the bottom of the source trench.
15. The method of producing a semiconductor device according to Claim 14, wherein The semiconductor body also includes a second buried layer; The preparation method further includes: A second buried layer is formed in the epitaxial layer on the side of the source trench away from the gate trench, wherein the orthographic projection of the second buried layer on the sidewall of the source trench away from the gate trench does not overlap with the orthographic projections of the well region and the first region on the sidewall of the source trench away from the gate trench.
16. The method of fabricating a semiconductor device according to any one of claims 11-15, wherein, The source structure is formed within the source trench, including: A first insulating layer is formed on the inner wall and bottom of the source trench; A trench source is formed in the source trench on one side of the first insulating layer, wherein the length of the trench source in the extending direction of the source trench is greater than the depth of the source trench.
17. The method of producing a semiconductor device according to Claim 16, wherein The semiconductor device further includes: an ohmic contact metal layer and a second insulating layer; The preparation method further includes: A second insulating layer is formed on the side of the first surface away from the gate structure; the orthographic projection of the second insulating layer on the first surface covers the gate structure; The ohmic contact metal layer is formed on the side of the second insulating layer away from the gate structure, and the ohmic contact metal layer is electrically connected to the first region; the metal material of the ohmic contact metal layer includes titanium.