Gate driving system and gate driving method
The gate drive system addresses the need for reliable real-time and protective monitoring in high-voltage devices by using dual feedback signals to manage semiconductor element states and anomalies, ensuring efficient operation and reduced complexity.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HITACHI LTD
- Filing Date
- 2025-07-15
- Publication Date
- 2026-06-25
AI Technical Summary
Existing power conversion devices in high-voltage applications like railway vehicles lack a reliable mechanism to notify both real-time state monitoring and protective operation monitoring of semiconductor elements using a feedback signal without increasing space or cost, and existing solutions may cause compatibility issues.
A gate drive system with a feedback signal generation unit that outputs a first feedback signal based on the semiconductor element's state and a second feedback signal with a predetermined period in response to anomaly detection, allowing the controller to stop the semiconductor element's operation when a mismatch occurs, with the second feedback signal's period set to be longer than the predetermined time for anomaly analysis.
Enables real-time state and protective operation monitoring without additional communication interfaces, allowing identification and analysis of abnormalities in power semiconductor devices, thus enhancing reliability and reducing potential device damage.
Smart Images
Figure JP2025025224_25062026_PF_FP_ABST
Abstract
Description
Gate drive system and gate drive method
[0001] The present invention relates to a gate drive system and a gate drive method.
[0002] Currently, in power conversion devices that drive motors of railway vehicles and large construction machines, insulated gate bipolar transistors (IGBTs) are often used as power semiconductor devices. This power conversion device controls the current flowing through the motor that is the load by turning on / off the IGBT, and drives the motor. The conversion circuit part includes an IGBT, a gate driver that controls the gate voltage of the IGBT to turn on / off the IGBT, a controller that sends control commands to the gate driver, a smoothing capacitor that suppresses fluctuations in the power supply voltage generated by large current switching, and a bus bar that connects the IGBT to the smoothing capacitor and the power supply, etc.
[0003] Since such power conversion devices control high voltage and current, if the power semiconductor device is miscontrolled and a power supply short circuit or the like occurs, the device itself may be destroyed, and a technology for detecting abnormalities in the power semiconductor device is required.
[0004] For example, Patent Document 1 discloses a technology for shortening the delay time of the abnormal detection output of a power semiconductor device in a power conversion device using an IGBT.
[0005] Japanese Patent No. 5049817
[0006] On the other hand, in power conversion devices used in electric vehicles, home appliances, or general industrial equipment, etc., conventionally, a protection circuit is installed in the gate driver, and when an excessive current flows through the IGBT or an excessive voltage is applied, it detects this and turns off the gate voltage from the gate driver, and notifies this to the controller as a feedback signal.
[0007] However, in power conversion devices that perform such relatively low-voltage current control, the feedback signal is generally used to notify abnormal detection as described above, and the function of the feedback signal is different from that of power conversion devices that require high voltage and high reliability such as railway vehicles.
[0008] Referring to Figure 7, the feedback function of a conventional power conversion circuit for high-voltage current control will be explained.
[0009] Figure 7 shows an example of a timing chart for a conventional power converter for high-voltage current control. Figure 7 shows the timing relationship between the command signal output from the controller, the drive circuit output of the gate driver corresponding to the gate voltage of the IGBT, and the feedback signal from the gate driver to the controller.
[0010] When the command signal from the controller inverts from off to on at time t1, the gate driver's drive circuit output is inverted to on at time t2 with a slight delay. The gate driver monitors the drive circuit output, and when it determines that the IGBT has been turned on at time t2, it inverts the feedback signal to on at time t3 and outputs it to the controller.
[0011] Note that there is a delay Tdon between time t1 when the command signal is turned on and time t3 when the feedback signal is turned on. This delay Tdon is due to the processing time of the circuit inside the gate driver. Similarly, there is a delay Tdoff between time t4 when the command signal is turned off and time t6 when the feedback signal is turned off. While delays Tdon and Tdoff are generally designed to be the same time, they may be designed to be different times depending on the actual delay.
[0012] The controller compares the feedback signal with the command signal, and if there is a mismatch, it determines that there is an abnormality and stops the gate drive system.
[0013] For example, if some abnormality occurs in the IGBT at time t7 and the drive circuit output drops to the off level, the gate driver immediately detects this and inverts the feedback signal to the off level. The controller determines that the mismatch between the command signal and the feedback signal is abnormal at time t8, when it has continued for a predetermined time Tdet from time t7, and inverts the command signal to the off level to stop the gate drive system.
[0014] The reason why a mismatch is determined when the mismatch state persists for a predetermined time Tdet is that electromagnetic field noise is emitted near high-voltage devices, and there is a possibility that this noise may be superimposed on the feedback signal, causing a momentary erroneous inversion. This measure is used to eliminate that effect. Generally, the predetermined time Tdet for mismatch determination is set to several hundred nanoseconds to several microseconds.
[0015] Furthermore, mismatches between command signals and feedback signals inevitably occur when the on / off states are reversed at time t1 or time t4. While there is no problem if the delays Tdon and Tdoff are shorter than the predetermined time Tdet, in the case of power converters for high-voltage current control in railway vehicles and other applications, the devices are large and take time to operate, so delays Tdon and Tdoff may be longer than the predetermined time Tdet. For this reason, it is common practice to disable the mismatch detection function for a certain period from time t1 or time t4. This period is called the "detection mask period".
[0016] As explained above, in power converters for high-voltage current control, the gate driver's feedback signal can notify the state of the power semiconductor element, but it is used to verify consistency with the command signal in real time. Therefore, even if protection circuits such as overcurrent protection circuits and overvoltage protection circuits are installed, the feedback signal cannot notify that a protection operation has been performed.
[0017] For this reason, it might be possible to add a separate communication line for protection operation notifications, but this raises concerns about increased space and cost, and would also necessitate adding an interface for protection operation monitoring to the controller, potentially causing compatibility issues with existing gate drive systems.
[0018] Therefore, the present invention aims to provide a technology that notifies both the results of real-time state monitoring and the results of protective operation monitoring of a semiconductor element using a feedback signal from a gate driver in a gate drive system.
[0019] To solve the above problems, a typical gate drive system of the present invention includes a feedback signal generation unit that outputs a first feedback signal generated according to the on / off state of a semiconductor element and a second feedback signal with a predetermined period T generated in response to an anomaly detection unit to a controller as feedback signals. The controller stops the on / off state of the semiconductor element when the on / off state of the command signal and the on / off state of the feedback signal become mismatched over a predetermined time Tdet, and uses the second feedback signal to analyze the nature of the anomaly, with the predetermined period T satisfying T / 2 > Tdet.
[0020] According to the present invention, the feedback signal of the gate driver of the gate drive system can notify both the results of real-time state monitoring and the results of protective operation monitoring of the semiconductor element. Problems, configurations, and effects other than those described above will be revealed by the description of embodiments below.
[0021] Figure 1 shows an example of the configuration of the gate drive system of Example 1. Figure 2 shows an example of the timing chart of the gate drive system of Example 1. Figure 3 shows an example of the configuration of the gate drive system of Example 2. Figure 4 shows an example of the configuration of the gate drive system of Example 3. Figure 5 shows an example of the configuration of the gate drive system of Example 4. Figure 6 shows an example of the timing chart of the gate drive system of Example 4. Figure 7 shows an example of the timing chart of a conventional power converter for high-voltage current control.
[0022] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to these embodiments. Furthermore, in the drawings, identical parts are denoted by the same reference numerals.
[0023] (Configuration of Example 1) The configuration of the gate drive system of Example 1 will be described with reference to Figure 1. Figure 1 is a diagram showing an example of the configuration of the gate drive system of Example 1. As shown in Figure 1, the gate drive system includes a controller 100 and a gate driver 109 to drive the power semiconductor device 101.
[0024] The gate driver 109 comprises a first isolated communication means 102, a drive circuit 103, an abnormality detection circuit 104, an output state monitoring circuit 105, a feedback signal generation circuit 106, a second isolated communication means 107, and an oscillation pattern generation circuit 108 as its components.
[0025] Next, the components of the gate drive system in this embodiment will be described. The controller 100 is a control logic unit that includes the function of generating command signals to switch the power semiconductor device 101 on or off.
[0026] The first isolated communication means 102 includes a function to output command signals from the controller 100 to the drive circuit 103.
[0027] The drive circuit 103 is a drive signal generation unit that receives a command signal from the controller 100 via the first isolated communication means 102, generates a drive signal (drive circuit output) for turning the power semiconductor device 101 on / off, and outputs this to the power semiconductor device 101.
[0028] The abnormality detection circuit 104 is an abnormality detection unit (protection circuit) that includes the function of detecting abnormalities in the power semiconductor device 101 and protecting it, by outputting the detection result to the drive circuit 103 and the oscillation pattern generation circuit 108. Examples of abnormalities that the abnormality detection circuit 104 can detect include overcurrent according to Example 2, circuit short circuit according to Example 3, and other cases such as overtemperature of the element device.
[0029] The output status monitoring circuit 105 includes the function of monitoring the drive signal (drive circuit output) of the drive circuit 103 and outputting the monitoring result to the feedback signal generation circuit 106.
[0030] The feedback signal generation circuit 106 includes the function of generating a first feedback signal upon receiving input from the output state monitoring circuit 105, and generating a second feedback signal upon receiving an oscillation pattern input from the oscillation pattern generation circuit 108.
[0031] The second isolated communication means 107 includes a function to output a feedback signal from the feedback signal generation circuit 106 to the controller 100.
[0032] The oscillation pattern generation circuit 108 includes the function of generating an oscillation pattern in response to the input from the abnormality detection circuit 104 and outputting it to the feedback signal generation circuit 106.
[0033] (Operation of Example 1) Next, the operation of the gate drive system of Example 1 will be described with reference to Figure 2. Figure 2 is a diagram showing an example of the timing chart of the gate drive system of Example 1. The delay Tdon, delay Tdoff, predetermined time Tdet, and mask detection period in Figure 2 are the same as those described earlier, so they will not be repeated in the description of the timing chart of this example.
[0034] (Normal operation of Example 1) First, the operation of the gate drive system under normal conditions will be explained with reference to the timing chart before time t7 in Figure 2(a).
[0035] When the controller 100 outputs an ON command as a command signal at time t1, the ON command is notified to the drive circuit 103 via the first isolated communication means 102. Based on the ON command, the drive circuit 103 raises the gate voltage Vg of the power semiconductor device 101 to the ON level at time t2. In Figure 2(a), this is shown as the ON inversion of the drive circuit output at time t2.
[0036] Regarding the drive circuit output, for example, in the case of a typical IGBT, the gate voltage Vg is set to -15V or 0V when off, and is raised to 15V when on.
[0037] The output state monitoring circuit 105 detects that the drive circuit output has been inverted to ON and notifies the feedback signal generation circuit 106 to generate a first feedback signal.
[0038] Upon receiving this notification, the feedback signal generation circuit 106 generates a first feedback signal (on-invert) at time t3 and provides feedback to the controller 100 via the second isolation communication means 107 that the gate voltage Vg has turned on (that the power semiconductor device 101 has turned on).
[0039] Next, when the controller 100 outputs an off command as a command signal at time t4, the off command is notified to the drive circuit 103, just as in the case of an on command. Based on this off command, the drive circuit 103 lowers the gate voltage Vg of the power semiconductor device 101 to the off level at time t5. In Figure 2(a), this is shown as the off inversion of the drive circuit output at time t5.
[0040] The output state monitoring circuit 105 detects that the drive circuit output has been turned off and notifies the feedback signal generation circuit 106 to stop the first feedback signal. Upon receiving this notification, the feedback signal generation circuit 106 stops (turns off) the first feedback signal at time t6 and feeds back to the controller 100 via the second isolation communication means 107 that the gate voltage Vg has reached the off level (that the power semiconductor device 101 has been turned off).
[0041] As mentioned above, in this embodiment as well, the controller 100 does not perform matching between the command signal and the feedback signal during the detection mask period. That is, when an ON command is output as a command signal, matching is performed in real time from time t2 after the end of the detection mask period, and when an OFF command is output as a command signal, matching is performed in real time from time t5 after the end of the detection mask period.
[0042] (Abnormal operation in Example 1) Next, referring to the timing chart from time t7 onwards in Figure 2(a), the operation of the gate drive system when an abnormality occurs while the command signal is ON will be explained.
[0043] When an abnormality occurs at time t7 when the command signal is in the ON state, the abnormality detection circuit 104 detects this abnormality and notifies the drive circuit 103. As a result, the drive circuit output is inverted to OFF, and the power semiconductor device 101 is turned off. At the same time, the output state monitoring circuit 105 receives the OFF inversion of the drive circuit output and notifies the feedback signal generation circuit 106 to stop the first feedback signal.
[0044] Further, the abnormality detection circuit 104 also notifies this abnormality to the oscillation pattern generation circuit 108. As a result, the oscillation pattern generation circuit 108 outputs an oscillation pattern generated with an oscillation period Toc to the feedback signal generation circuit 106 from time t7.
[0045] As a result, at time t7, the feedback signal generation circuit 106 stops (inverts to OFF) the first feedback signal and outputs an oscillation pattern signal with an oscillation period Toc from the oscillation pattern generation circuit 108 to the controller 100 as the second feedback signal.
[0046] Here, for the second feedback signal, it is necessary to set the half period of the oscillation period Toc to be longer than a predetermined time Tdet for determining the mismatch between the first feedback signal and the command signal. This is because if Tdet≧1 / 2×Toc is set, the feedback signal will invert again before the mismatch is determined and the mismatch state will be resolved, making it impossible for the controller 100 to detect the abnormality.
[0047] Regarding the oscillation period Toc, when the Duty is 50%, it may be set as 1 / 2×Toc>Tdet. However, as shown in Fig. 2(a), the OFF period Toc1 and the ON period Toc2 of the oscillation may be set to be of unequal length, for example, Toc1>Toc2. However, in that case as well, it is necessary to set the shorter period to be longer than the predetermined time Tdet.
[0048] When the first feedback signal stops (inverts off), if the mismatch between the first feedback signal (inverted off) and the command signal (on command) continues for a predetermined time Tdet from time t7, the controller 100 turns off the command signal at time t8 to stop the on / off operation of the power semiconductor device 101. However, even after stopping the on / off operation of the power semiconductor device 101, the oscillation by the oscillation pattern generation circuit 108 for generating the second feedback signal continues for a predetermined period. Thereby, by using the existing function of recording the log of the feedback signal, it becomes possible to analyze the content of the abnormality at a later time.
[0049] (Operation 2 at the time of abnormality in Example 1) Next, referring to the timing chart after time t7 in FIG. 2(b), the operation of the gate drive system when an abnormality occurs with the command signal in the off state will be described. Note that the operation of the gate drive system before time t7 in FIG. 2(b) is the same as that before time t7 in FIG. 2(a), so the description thereof will be omitted.
[0050] When an abnormality occurs at time t7 when the command signal is in the off state, the abnormality detection circuit 104 detects this abnormality and notifies the drive circuit 103. However, since the drive circuit 103 is in the off state, the drive circuit output remains off.
[0051] When the abnormality detection circuit 104 detects an abnormality, it also notifies this abnormality to the oscillation pattern generation circuit 108. As a result, the oscillation pattern generation circuit 108 outputs an oscillation pattern with an oscillation period Toc to the feedback signal generation circuit 106 from time t7. As a result, the feedback signal generation circuit 106 outputs an oscillation pattern with an oscillation period Toc to the controller 100 as the second feedback signal from time t7 (the first feedback signal remains in the off state).
[0052] If the controller 100 detects that the mismatch between the second feedback signal (on-inversion) and the command signal (off-command) persists from time t8, when the second feedback signal oscillates and then inverts to ON, until a predetermined time Tdet, it will keep the command signal as an OFF command even after time t9, thereby stopping the ON / OFF switching of the power semiconductor device 101. However, similar to Figure 2(a), even after stopping the ON / OFF switching of the power semiconductor device 101, the oscillation by the oscillation pattern generation circuit 108 for generating the second feedback signal continues for a predetermined period. This makes it possible to analyze the abnormality later using the existing function of recording feedback signal logs.
[0053] According to the configuration of this embodiment, both the results of real-time status monitoring and the results of protective operation monitoring can be notified as feedback signals to the controller 100. Therefore, in existing gate drive systems, there is no need to add or modify the communication interface between the controller 100 and the gate driver 109, or the software installed on the controller 100. Furthermore, it becomes possible not only to identify the gate driver where the abnormality occurred, but also to confirm the nature of the abnormality.
[0054] (Configuration of Example 2) Referring to Figure 3, the configuration of the gate drive system of Example 2 will be described. Compared to Example 1, Example 2 includes an overcurrent detection circuit 302 as a specific example of the abnormality detection circuit 104 used as a protection circuit.
[0055] Figure 3 shows an example of the configuration of the gate drive system of Embodiment 2. The same reference numerals are used for components that are the same as those in Embodiment 1, and their descriptions are omitted.
[0056] The power semiconductor device in this embodiment is an IGBT module 301 composed of an IGBT element and a reverse diode, and includes parasitic inductance 303 present inside the module and in the wiring.
[0057] The overcurrent detection circuit 302 includes a function to monitor the voltage of the parasitic inductance 303 of the IGBT module 301 and notifies the drive circuit 103 and the oscillation pattern generation circuit 108 of the detection result.
[0058] (Operation in Case of Abnormality in Example 2) The operation when an abnormality occurs in the gate drive system of Example 2 will be described below.
[0059] When a sudden overcurrent flows through the IGBT module 301, a voltage is generated across the parasitic inductance 303. The overcurrent detection circuit 302 monitors this voltage and, if it exceeds a predetermined value, determines that an overcurrent has occurred. It then inverts the drive signal from the drive circuit 103 and notifies the oscillation pattern generation circuit 108 of the overcurrent.
[0060] The subsequent operation is the same as in Embodiment 1. The oscillation pattern generation circuit 108 outputs the oscillation pattern generated with oscillation period Toc to the feedback signal generation circuit 106. The feedback signal generation circuit 106 receives an off-inversion of the drive signal from the output state monitoring circuit 105 and stops (turns off) the first feedback signal, and also outputs the oscillation pattern with oscillation period Toc from the oscillation pattern generation circuit 108 to the controller 100 as the second feedback signal. When the controller 100 determines that there is a mismatch between the first feedback signal or the second feedback signal and the command signal, it stops the on / off switching of the power semiconductor device 101. In Embodiment 2 as well, even after stopping the on / off switching of the power semiconductor device 101, the oscillation by the oscillation pattern generation circuit 108 for generating the second feedback signal continues for a predetermined period.
[0061] The overcurrent detection circuit 302 can use any method to detect overcurrent, such as monitoring the voltage generated across the parasitic inductance 303 with a comparator and making a determination if it exceeds a specified value, or integrating the voltage from the parasitic inductance 303 and determining that an overcurrent has flowed if this integrated value exceeds a certain value.
[0062] This allows the same effects as in Example 1 to be achieved even when an overcurrent occurs in the IGBT module.
[0063] (Configuration of Example 3) Referring to Figure 4, the configuration of the gate drive system of Example 3 will be described. Compared to Example 1, Example 3 includes a collector voltage detection circuit 401 as another specific example of the abnormality detection circuit 104 used as a protection circuit.
[0064] Figure 4 shows an example of the configuration of the gate drive system of Embodiment 3. Components identical to those in Embodiments 1 and 2 are denoted by the same reference numerals, and their descriptions are omitted.
[0065] The power semiconductor device in this embodiment includes an IGBT module 301.
[0066] The collector voltage detection circuit 401 is a collector voltage detection type short-circuit protection circuit (DSAT type) and includes a function to monitor both the collector voltage and gate voltage of the IGBT module 301, and notifies the oscillation pattern generation circuit 108 of the detection results obtained from this monitoring.
[0067] (Operation in Case of Abnormality in Example 3) The operation when an abnormality occurs in the gate drive system of Example 3 will be described below.
[0068] When the collector voltage of the IGBT module 301 is ON and rises, which should normally drop to a few volts, the collector voltage detection circuit 401 detects this as an overcurrent (short circuit) and inverts the drive signal from the drive circuit 103, while also notifying the oscillation pattern generation circuit 108 of the overcurrent (short circuit).
[0069] The subsequent operation is the same as in Embodiment 1. The oscillation pattern generation circuit 108 outputs the oscillation pattern generated with oscillation period Toc to the feedback signal generation circuit 106. The feedback signal generation circuit 106 receives an off-inversion of the drive signal from the output state monitoring circuit 105 and stops (turns off) the first feedback signal, and also outputs the oscillation pattern signal with oscillation period Toc from the oscillation pattern generation circuit 108 as a second feedback signal to the controller 100. When the controller 100 determines that there is a mismatch between the first feedback signal or the second feedback signal and the command signal, it stops the on / off switching of the power semiconductor device 101. In Embodiment 3 as well, even after stopping the on / off switching of the power semiconductor device 101, the oscillation by the oscillation pattern generation circuit 108 for generating the second feedback signal continues for a predetermined period.
[0070] This allows the same effects as in Example 1 to be achieved even when a short circuit occurs in the IGBT module.
[0071] (Configuration of Example 4) Referring to Figure 5, the configuration of the gate drive system of Example 4 will be described. Compared to Example 1, Example 4 includes both the overcurrent detection circuit 302 of Example 2 and the collector voltage detection circuit 401 of Example 3 as another specific example of the abnormality detection circuit 104 used as a protection circuit.
[0072] Figure 5 shows an example of the configuration of the gate drive system of Embodiment 4. The same reference numerals are used for components that are the same as those in Embodiments 1 to 3, and their descriptions are omitted.
[0073] The power semiconductor device in this embodiment is an IGBT module 301 composed of an IGBT element and a reverse diode, similar to the one in Embodiment 2, and includes parasitic inductance 303 present inside the module and in the wiring.
[0074] The multiple oscillation pattern generation circuit 501 receives the detection results from the overcurrent detection circuit 302 and the collector voltage detection circuit 401, generates oscillation patterns with different oscillation periods corresponding to each detection result, and notifies the feedback signal generation circuit 106 of these patterns.
[0075] (Operation in abnormal conditions of Example 4) Figure 6 shows an example of a timing chart for the gate drive system of Example 4. The feedback signal from time t7 onwards in Figure 6(a) shows the second feedback signal when the overcurrent detection circuit 302 is activated, and the feedback signal from time t7 onwards in Figure 6(b) shows the second feedback signal when the collector voltage detection circuit 401 is activated.
[0076] The operation of the gate drive system in Example 4 is the same as when an abnormality occurs in the gate drive system of Example 2 if the overcurrent detection circuit 302 detects an overcurrent in the IGBT module 301, and the operation is the same as when an abnormality occurs in the gate drive system of Example 3 if the collector voltage detection circuit 401 detects a short circuit in the IGBT module 301.
[0077] However, the multiple oscillation pattern generation circuit 501 notifies the feedback signal generation circuit 106 of oscillation patterns with different oscillation periods based on the abnormality detection by the overcurrent detection circuit 302 and the abnormality detection by the collector voltage detection circuit 401. In this embodiment, the oscillation period Toc3 of the second feedback signal shown in Figure 6(a) and the oscillation period Toc4 of the second feedback signal shown in Figure 6(b) are set to different periods (Toc4 > Toc3) so that the two second feedback signals can be distinguished. In this way, the nature of the abnormality (type of abnormality) can be determined by the different oscillation periods of the second feedback signals.
[0078] In this embodiment, an example is shown in which the gate drive system has two protection circuits, but it is not limited to this, and it may have three or more protection circuits, and oscillation patterns with different oscillation periods may be set according to the number of protection circuits.
[0079] (Modifications) Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of the present invention.
[0080] For example, in the embodiment of the present invention, the target of the gate drive system is a power semiconductor device, but it is not limited to this, and any semiconductor element may be used as the target of the drive system. Furthermore, the gate drive system according to the present invention can also be applied to each of the multiple semiconductor elements constituting a power conversion device.
[0081] Furthermore, although the protection circuit is located inside the gate driver in this embodiment of the present invention, it is not limited to this and may be located outside the gate driver.
[0082] 100: Controller, 101: Power semiconductor device (semiconductor element), 102: First isolated communication means, 103: Drive circuit (drive signal generation unit), 104: Anomaly detection circuit (anomaly detection unit), 105: Output state monitoring circuit, 106: Feedback signal generation circuit, 107: Second isolated communication means, 108: Oscillation pattern generation circuit, 109: Gate driver, 301: IGBT module, 302: Overcurrent detection circuit (anomaly detection unit), 303: Parasitic inductance, 401: Collector voltage detection circuit (anomaly detection unit), 501: Multiple oscillation pattern generation circuit
Claims
1. A gate drive system comprising a controller that outputs a command signal to switch a semiconductor element on or off, and a gate driver that switches the semiconductor element on or off based on the command signal, wherein the gate driver comprises: an abnormality detection unit that detects an abnormality in the semiconductor element; a drive signal generation unit that generates a drive signal for switching the semiconductor element on or off based on the command signal input from the controller, and inverts the drive signal for turning on to off in response to the abnormality detection unit's detection of an abnormality; and a feedback signal generation unit that outputs a first feedback signal generated according to the on / off state of the semiconductor element and a second feedback signal with a predetermined period T generated in response to the abnormality detection unit's detection of an abnormality as feedback signals to the controller, wherein the controller stops switching the semiconductor element on or off when the on / off state of the command signal and the on / off state of the feedback signal are inconsistent for a predetermined time Tdet, and uses the second feedback signal to analyze the content of the abnormality detection, and the predetermined period T satisfies T / 2 > Tdet.
2. The gate drive system according to claim 1, characterized in that the abnormality detection unit detects an overcurrent flowing through the semiconductor element.
3. The gate drive system according to claim 1, characterized in that the abnormality detection unit detects an overvoltage applied to the semiconductor element.
4. The gate drive system according to claim 1, wherein the anomaly detection unit comprises at least two means for detecting different types of anomalies in the semiconductor element, and the predetermined period T is different depending on the type of anomaly.
5. A power conversion device comprising semiconductor elements driven using the gate drive system described in any one of claims 1 to 4.
6. A gate driving method for driving a semiconductor element, comprising: generating a drive signal for turning the semiconductor element on / off based on a command signal input from a controller; generating a first feedback signal according to the on / off state of the semiconductor element, and generating a second feedback signal with a predetermined period T generated in response to an abnormality detection of the semiconductor element; outputting the first feedback signal and the second feedback signal as feedback signals to the controller; stopping the on / off state of the semiconductor element when the on / off state of the command signal and the on / off state of the feedback signal are inconsistent for a predetermined time Tdet, and simultaneously analyzing the content of the abnormality detection from the second feedback signal; and the predetermined period T satisfying T / 2 > Tdet.
7. The gate driving method according to claim 6, characterized in that the detection of an abnormality in the semiconductor element is the detection of an overcurrent flowing through the semiconductor element.
8. The gate driving method according to claim 6, characterized in that the detection of an abnormality in the semiconductor element is the detection of an overvoltage applied to the semiconductor element.
9. The gate driving method according to claim 6, characterized in that the detection of anomalies in the semiconductor element includes different types of anomaly detection, and the predetermined period T is different depending on the type of anomaly detection.