Display device and driving method therefor

Abstract

The present application provides a display device and a driving method therefor. The display device comprises a display panel and a driving system electrically connected to the display panel. The driving system comprises a clock module used for generating a clock signal, a determination module used for generating a reset signal on the basis of the relationship between clock information in the clock signal and preset information, and a processing module used for acquiring, on the basis of reset information in the reset signal, a display signal used for controlling the display panel to display an image. The processing module is further used for processing the display signal.

Description

Display device and its driving method

[0001] This application claims priority to Chinese patent application No. 202411867481.6, filed on December 17, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more specifically to display devices and their driving methods. Background Technology

[0003] As the integration of timing controllers in display modules becomes increasingly sophisticated, the technology of integrating timing controllers and data drivers into a single "timing controller embedded data driver" chip has been gradually applied to display products. However, current "timing controller embedded data driver" chips need to meet strict timing requirements during display device power-on, and how to meet these timing requirements to avoid black screen phenomena during power-on has become a current challenge. Invention Overview

[0004] The purpose of this application is to provide a display device and its driving method to improve the black screen phenomenon when the display device is powered on.

[0005] In a first aspect, this application provides a display device, including a display panel and a driving system electrically connected to the display panel, the driving system comprising:

[0006] The clock module is used to generate clock signals;

[0007] The judgment module is used to generate a reset signal based on the relationship between the clock information in the clock signal and preset information;

[0008] The processing module is used to obtain a display signal for controlling the display screen of the display panel based on the reset information in the reset signal, and to process the display signal.

[0009] Wherein, the clock signal includes multiple clock pulses, the clock information includes the number of clock pulses, the preset information includes a preset value, and the judgment module includes:

[0010] A counting unit is used to generate a first control signal according to the clock signal. The first control signal is an effective first control potential when the number of clock pulses is greater than or equal to the preset value. The effective first control potential is used to control the reset information to be a first sub-reset signal.

[0011] The processing module is used to obtain the display signal based on the first sub-reset signal.

[0012] The driving system includes a driving chip, which includes a clock module, a judgment module, a processing module, and a data driving module.

[0013] The processing module is used to generate an image signal based on the clock signal and the display signal;

[0014] The data driving module is used to control the display panel to display images based on the image signals.

[0015] Secondly, this application provides a display device, including a display panel and a driving system electrically connected to the display panel, the driving system comprising:

[0016] The clock module is used to generate clock signals;

[0017] The judgment module is used to generate a reset signal based on the relationship between the clock information in the clock signal and preset information;

[0018] The processing module is used to obtain a display signal for controlling the display screen of the display panel based on the reset information in the reset signal, and to process the display signal.

[0019] In some embodiments, the clock signal includes multiple clock pulses, the clock information includes the number of clock pulses, the preset information includes a preset value, and the judgment module includes:

[0020] A counting unit is used to generate a first control signal according to the clock signal. The first control signal is an effective first control potential when the number of clock pulses is greater than or equal to the preset value. The effective first control potential is used to control the reset information to be a first sub-reset signal.

[0021] The processing module is used to obtain the display signal based on the first sub-reset signal.

[0022] Thirdly, this application also provides a driving method for a display device, the display device including a display panel and a driving system electrically connected to the display panel, the driving system including a clock module, a judgment module, and a processing module, the method including:

[0023] The clock module generates a clock signal;

[0024] The judgment module generates a reset signal based on the relationship between the clock information in the clock signal and preset information.

[0025] The processing module obtains the display signal for controlling the display panel's display screen based on the reset information in the reset signal, and processes the display signal.

[0026] Beneficial effects: This application provides a display device and its driving method. The display device includes a display panel and a driving system electrically connected to the display panel. The driving system includes a clock module for generating a clock signal, a judgment module for generating a reset signal based on the clock signal, and a processing module for obtaining a display signal for controlling the display screen of the display panel based on the reset information in the reset signal. By setting the judgment module to generate a reset signal based on the relationship between the clock information in the clock signal and preset information, the driving system can determine the time to obtain the display signal based on the clock signal. The reset signal has an effective potential only when the clock signal is stable, so as to control the driving system to obtain the display signal and perform effective parsing. This avoids parsing errors caused by obtaining the display signal when the clock signal is unstable, and improves the black screen phenomenon when the display device is powered on. Attached Figure Description

[0027] The present application will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for explaining some embodiments of the present application. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0028] Figures 1 and 2 are architectural diagrams of the display device provided in the embodiments of this application.

[0029] Figures 3, 5, and 6 are waveform diagrams of some signals of the display device provided in the embodiments of this application.

[0030] Figure 4 is a circuit diagram of the counting unit provided in an embodiment of this application.

[0031] Figure 7 is a flowchart of the driving method of the display device provided in the embodiment of this application. Implementation methods of this application

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] In the description of this application, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. Furthermore, it should be noted that the accompanying drawings only provide structures closely related to this application, omitting some details less relevant to the application. The purpose is to simplify the drawings and make the application points clear at a glance, not to indicate that the actual device is exactly the same as the drawings, and is not intended to limit the actual device.

[0034] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase at various points in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0035] This application provides a display device, which may include, but is not limited to, the following embodiments and combinations thereof.

[0036] In some embodiments, as shown in Figures 1 and 2, the display device 100 includes a display panel 10 and a driving system 20 electrically connected to the display panel 10. The driving system 20 includes: a clock module 201 for generating a clock signal CLK; a judgment module 202 for generating a reset signal Reset based on the relationship between clock information in the clock signal CLK and preset information; and a processing module 203 for obtaining a display signal for controlling the display screen of the display panel 10 based on reset information in the reset signal Reset. The processing module 203 is also used to process the display signal.

[0037] The display device 100 can be, but is not limited to, an organic self-emissive display device, an inorganic self-emissive display device, or a liquid crystal display device. The display device 100 may also include a gate driver 50, which can be a gate driving circuit located on the substrate of the display panel 10 or a chip disposed independently of the display panel 10 (Figure 1 only illustrates the former as an example). For ease of description, Figure 1 only illustrates the arrangement of multiple sub-pixel P arrays in the display panel 10 as an example, for example, they can be arranged in n rows and m columns (n ​​and m are both positive integers).

[0038] Specifically, the display panel 10 may also include multiple gate lines (GL1 to GLn) electrically connected to the gate driver 50 and multiple data lines (DL1 to DLm) electrically connected to the source driver. Gate driver 50 generates multiple gate signals corresponding to multiple rows of sub-pixels P. Each gate line (one of GL1 to GLn) is electrically connected to the corresponding row of sub-pixels P to transmit the corresponding gate signal to the corresponding row of sub-pixels P. Each gate signal includes a gate active pulse for controlling the corresponding pixel group to turn on. The multiple gate active pulses are arranged sequentially on the time axis so that the corresponding multiple pixel groups are turned on sequentially. Each data line (one of DL1 to DLm) is electrically connected to the corresponding column of sub-pixels P to transmit a corresponding data signal data generated by the source driver (e.g., the data driving module 205 in Figures 1 and 2). Each data signal data includes multiple data voltages corresponding to the multiple sub-pixels P in that column. The multiple data signals data corresponding to the multiple columns of sub-pixels P are matched so that when each pixel group is turned on, the multiple data voltages corresponding to the multiple sub-pixels P in the pixel group can be transmitted to the corresponding multiple sub-pixels P through the multiple data lines (DL1 to DLm).

[0039] As shown in Figures 1 and 2, the data driving module 205 and the timing control module 204 can be integrated into the same driving system 20, i.e., the driving system 20 can be a "timing controller embedded data driver" chip. The timing control module 204 may include a clock module 201, a judgment module 202, and a processing module 203. The processing module 203 is used to generate an image signal based on the clock signal CLK and the display signal. The data driving module 205 is used to control the display panel 10 to display the image based on the image signal.

[0040] Of course, unlike what is shown in Figures 1 and 2, the data driving module 205 and the timing control module 204 can also be set independently. In this case, the data driving module 205 can be considered as the source driving chip and the timing control module 204 as the timing control chip. The timing control chip can be electrically connected to the display panel 10, and the source driving chip can be electrically connected between the display panel 10 and the timing control chip. The timing control chip includes the aforementioned clock module 201, judgment module 202 and processing module 203. The source driving chip is used to control the display panel 10 to display the screen according to the image signal (generated by the processing module 203).

[0041] Regardless of whether the data driving module 205 and the timing control module 204 are set independently (this application only illustrates the example of the two being integrated in the same driving system 20), the display device 100 also includes a power manager 30. The power manager 30 is used to supply power to the gate driver 50, the data driving module 205 and the timing control module 204. The timing control module 204 generates timing signals and transmits them to the gate driver 50 and the data driving module 205, and generates image signals and transmits them to the data driving module 205. Then, the gate driver 50 generates the above-mentioned multiple gate signals, and the data driving module 205 generates the above-mentioned multiple data signals, thereby driving multiple sub-pixels P to emit light.

[0042] Specifically, as shown in Figure 2, the clock module 201 (e.g., a crystal oscillator) in the driving system 20 (timing control module 204) generates a clock signal CLK. The processing module 203 in the driving system 20 (timing control module 204) needs to parse the display signal obtained from the storage module according to the clock signal CLK, thereby obtaining system signals (information required for the operation of the driving system 20), image signals, control signals, and the aforementioned timing signals. The aforementioned timing signals can be used as the working timing of the gate driver 50 and the data driver module 205. Furthermore, the data driver module 205 can process the image signal according to the control signal and the aforementioned timing signals to generate the aforementioned multiple data signals data, and the gate driver 50 can generate the aforementioned multiple gate signals gate according to the control signal and the aforementioned timing signals.

[0043] As discussed above, since the clock signal CLK is needed to parse and display signals to generate the timing signals for the control gate driver 50, the data driver module 205, and the aforementioned system signals, image signals, and control signals, if the driver system 20 (timing control module 204) acquires the display signal before the clock signal CLK is stable, it will cause the parsing of the display signal to be disordered, resulting in the generation of incorrect timing signals, system signals, image signals, and control signals, ultimately leading to a black screen phenomenon upon power-on.

[0044] Understandably, in this embodiment, the processing module 203 controls the driving system 20 to acquire the display signal based on the reset signal Reset. By setting a judgment module 202 to generate the reset signal Reset based on the clock signal CLK, the time when the driving system 20 acquires the display signal can be determined at least based on the clock signal CLK. The reset signal Reset can only have an effective potential when the clock signal CLK is stable, so as to control the driving system 20 to acquire the display signal and perform effective parsing. This avoids parsing errors caused by acquiring the display signal when the clock signal CLK is not stable, and improves the black screen phenomenon of the display device 100 when it is powered on.

[0045] In some embodiments, the clock signal CLK shown in Figures 2 and 3 includes multiple clock pulses p, the clock information includes the number of clock pulses p, the preset information includes a preset value, and the judgment module 202 includes: a counting unit 2021, used to control the reset information to a first sub-reset signal (i.e., the amplitude of the reset signal Reset is the amplitude of the first sub-reset signal) when the number of clock pulses p is greater than or equal to the preset value, and the processing module 203 is used to obtain the display signal based on the first sub-reset signal. Here, "control" can be understood as direct control or indirect control; the specific meaning will be understood in conjunction with the discussion below.

[0046] As discussed above, in this embodiment, considering that the clock signal CLK generated by the clock module 201 is not very stable in the initial period (for example, at least one of the period or peak-to-peak value of the clock signal CLK is unstable), the processing module 203 cannot accurately parse the display signal at this time. Therefore, the counting unit 2021 is set to count the number of clock pulses p in the clock signal CLK, and the reset signal Reset is controlled to be the first sub-reset signal only when the number of clock pulses p is greater than or equal to a preset value. The processing module 203 is used to obtain the display signal according to the first sub-reset signal in the Reset reset signal, and does not obtain the display signal when the second sub-reset signal before the Reset reset signal becomes the first sub-reset signal.

[0047] The preset value can be set according to the number of pulses required for the clock signal CLK to reach stability. It can be assumed that when the number of clock pulses p is greater than or equal to the preset value, the period and peak-to-peak value of the clock signal CLK will reach stability.

[0048] Therefore, by setting the counting unit 2021 to count the number of clock pulses p in the clock signal CLK, the processing module 203 can obtain the display signal only when the number of clock pulses p is greater than or equal to a preset value, thereby performing effective analysis and avoiding analysis errors caused by obtaining the display signal before the clock signal CLK is stable.

[0049] In some embodiments, as shown in Figures 2 to 4, the counting unit 2021 includes: a plurality of triggers 01, used to generate a plurality of corresponding trigger signals Qi (i is an integer greater than or equal to 0) according to the clock signal CLK; and a signal processor 02, used to control the reset signal Reset to be the first sub-reset signal when the plurality of trigger signals Qi are respectively a plurality of corresponding sub-preset values.

[0050] The counting function can be implemented by using a corresponding number of triggers 01 according to the value of the preset value and the type of trigger 01. Each trigger 01 can generate a corresponding trigger signal Qi according to the clock signal CLK. When the number of clock pulses p is greater than or equal to the preset value, that is, when the values ​​of multiple trigger signals Qi are respectively the corresponding sub-preset values, the signal processor 02 controls the reset signal Reset to the first sub-reset signal mentioned above.

[0051] Considering that the trigger signal Qi generated by each flip-flop 01 can be either 0 or 1, n flip-flops 01 can output 2. n Therefore, to achieve the counting function, the number n of trigger 01 and the preset value N can satisfy "2 n The equation ≥ N, which means the number of results output by n flip-flops (0 and 1), is 2. n The value must be no less than the preset value N in order to achieve the maximum count of 2. n The preset value is not less than the preset value N. Further, multiple sub-preset values ​​are set based on the preset value N to ensure that when multiple trigger signals Qi are respectively their corresponding sub-preset values, they also correspond to the decimal preset value N. In this embodiment, a preset value N of 31 is used as an example. Considering 2... 5 ≥31≥2 4 Therefore, five triggers 01 need to be set.

[0052] Specifically, as shown in Figure 4, taking the JK flip-flop 01 as an example, the J and K terminals of the JK flip-flop are electrically connected to the first voltage line used to transmit a logic high potential (e.g., corresponding to the first voltage signal VCC). The clock terminal CP of the first-stage JK flip-flop is electrically connected to the clock module to obtain the clock signal CLK. The clock terminal CP of each of the second to last stage JK flip-flops is electrically connected to the output terminal of the previous stage JK flip-flop to obtain the trigger signal of the previous stage.

[0053] Based on the control principle of the JK flip-flop, when the rising or falling edge of the clock signal CP arrives, the output state of the JK flip-flop will be updated according to the inputs of J and K. This includes the toggle mode, that is, when both the J and K terminals are logic high level "1", the trigger signal Qi output by the output terminal Q will toggle. That is, if Qi was previously logic low level "0", it will toggle to logic high level "1", and vice versa.

[0054] As shown in Figure 4, in this embodiment, the clock signal CLK is transmitted to the clock terminal CP of each flip-flop 01, and the J terminal and K terminal are electrically connected to the first voltage line used to transmit the logic high potential "1" (for example, corresponding to the first voltage signal VCC). That is, the first voltage signal VCC is a constant voltage signal with an amplitude of logic high potential "1", and the clock terminal CP of the first stage JK flip-flop is loaded with the clock signal CLK. The clock terminal CP of each subsequent stage JK flip-flop is loaded with the trigger signal of the previous stage.

[0055] Referring to Figures 3, 4, and 5, this embodiment takes n=5 and the falling edge of the clock signal CP as an example. At the beginning of the first clock pulse p0 of the clock signal CLK, the signal processor 02 resets the reset terminal R of each JK flip-flop (for example, sets it to "0") so that the five trigger signals (i.e., Q0 to Q4) of the five JK flip-flops are all set to "0" during the first clock pulse p0. Thereafter, the trigger signal Q0 of the first-stage JK flip-flop is flipped once on each falling edge of the clock signal CLK, that is, the period of the trigger signal Q0 is twice that of the clock signal CLK. The trigger signal Q1 of the second-stage JK flip-flop is flipped once on each falling edge of the trigger signal Q0, that is, the period of the trigger signal Q1 is twice that of the trigger signal Q0, and so on. The period of the trigger signal Qj is twice that of the trigger signal Qj-1, where j is a positive integer in [1, 4].

[0056] Among them, "Q4Q3Q2Q1Q0" starts counting from "00000" (decimal 0) to "11111" (decimal 31), which means that the clock signal CLK has 32 pulses (the first clock pulse p0 to the thirty-second clock pulse p31). The signal processor 02 can be set to control the reset signal Reset as the first sub-reset signal when "Q4Q3Q2Q1Q0" is "11111". That is, the reset signal Reset is controlled as the first sub-reset signal only after the clock signal CLK has 32 pulses. This controls the processing module 203 to obtain the display signal and effectively parse the display signal through the stable clock signal CLK at this time, avoiding parsing errors caused by obtaining the display signal when the clock signal CLK is not stable.

[0057] Of course, since N=31, signal processor 02 can also be set to control the reset signal Reset as the first sub-reset signal when "Q4Q3Q2Q1Q0" is "11110" (30 in decimal). This is because it is equivalent to controlling the reset signal Reset as the first sub-reset signal after 31 pulses of the clock signal CLK, which also meets the above requirements.

[0058] It should be noted that when “Q4Q3Q2Q1Q0” counts to the above-required “11111” or “11110”, multiple flip-flops 01 can be prevented from continuing to count by, for example, controlling the reset terminal R, so that “Q4Q3Q2Q1Q0” remains at the above-required “11111” or “11110”.

[0059] In some embodiments, as shown in Figures 4 and 5, the signal processor 02 is configured to control the reset signal Reset to be the first sub-reset signal when each of the plurality of trigger signals Qi is a first sub-trigger signal (e.g., "1"). That is, this embodiment fully utilizes the upper limit of the count of the plurality of triggers 01, controlling the reset signal Reset to be the first sub-reset signal only when the maximum count value is reached. With a fixed number of triggers 01 (i.e., the same storage resources), the occurrence of the first sub-reset signal can be sufficiently delayed. The display signal is acquired and effectively parsed only after the clock signal CLK is sufficiently stable, minimizing the risk of parsing errors caused by acquiring the display signal before the clock signal CLK is stable.

[0060] Of course, the appropriate number of trigger 01s can also be selected based on the preset value N, and the upper limit of the count of multiple trigger 01s can be fully utilized, so that the preset value N is closer to 2. k Instead of 2 k+1 When (k is a positive integer greater than 0), n can be set to k instead of k+1 to avoid wasting storage resources by selecting too many trigger 0s and 1s.

[0061] In some embodiments, as shown in Figures 1, 2, and 6, the display device 100 further includes a power manager 30 electrically connected to the driving system 20. The power manager 30 is used to generate a second voltage signal. The counting unit 2021 is used to generate a first control signal Con1 based on the clock signal CLK. The judgment module 202 includes an AND gate unit 2022 electrically connected to the counting unit 2021 and the power manager 30, used to control the reset signal Reset to the first sub-reset signal based on the second voltage signal and the first control signal Con1. It can be understood that the counting unit 2021 indirectly controls the reset signal Reset to the first sub-reset signal by generating the first control signal Con1 based on the clock signal CLK. Of course, the counting unit 2021 can also directly control the reset signal Reset to the first sub-reset signal based on the clock signal CLK.

[0062] Specifically, the second voltage signal may include, but is not limited to, the first sub-voltage signal PAVDD, the second sub-voltage signal VCore, and the third sub-voltage signal VDDIO. The first sub-voltage signal PAVDD can be applied to the data driving module 205, which generates multiple gamma reference voltages based on the first sub-voltage signal PAVDD, and generates the data signal data based on the multiple gamma reference voltages and the aforementioned image signal. The second sub-voltage signal VCore can be applied to the timing control module 204 as its core voltage. The third sub-voltage signal VDDIO can be applied to the timing control module 204 to power its internal I / O modules, and can also be applied to the data driving module 205 to power its internal logic modules.

[0063] As can be understood, in conjunction with Figures 3 and 6, the counting unit 2021 in this embodiment is used to generate a first control signal Con1 based on the clock signal CLK, and to generate a reset signal Reset based on the first control signal Con1 and the second voltage signal by setting the AND gate unit 2022. That is, the reset signal Reset is not only related to whether the clock signal CLK has reached stability, but also to the amplitude of the second voltage signal. It can be understood that when the first sub-voltage signal PAVDD, the second sub-voltage signal VCore, the third sub-voltage signal VDDIO and the clock signal CLK have all reached stability, the AND gate unit 2022 controls the reset signal Reset to be the first sub-reset signal, thereby controlling the processing module 203 to obtain the display signal. At this time, not only is the risk of display signal parsing errors reduced, but the second voltage signal also reaches a stable state, and the timing control module 204 and the data driving module 205 also have the corresponding operating voltage, further improving the reliability of the drive system 20.

[0064] In some embodiments, as shown in FIG1, the display device 100 further includes a reset circuit 40 electrically connected to the driving system 20, the reset circuit 40 being used to generate an initial reset signal Reset0; wherein, the AND gate unit 2022 is used to generate a second control signal Con2 based on the second voltage signal and the first control signal Con1, the second control signal Con2 being used to adjust the initial reset signal Reset0 to the reset signal Reset.

[0065] Specifically, referring to Figures 1 and 2, it can be considered that the three sub-voltage signals in the second voltage signal reach stability after the first time period T1. Since the initial reset signal Reset0 generated by the reset circuit 40 is not controlled by the second control signal Con2 generated by the judgment module 202, it can be considered that the initial reset signal Reset0 reaches stability after the second time period T2 after the first time period T1. At this time, it can be considered that the clock signal CLK has not reached stability. If the judgment module 202 in this application is not set, the initial reset signal Reset0 will directly act on the processing module 203, causing it to acquire and parse the display signal before the clock signal CLK has reached stability, resulting in the risk of a black screen on startup.

[0066] Understandably, in this embodiment, by setting a counting unit 2021 to generate a first control signal Con1 based on the clock signal CLK, and a gate unit 2022 to generate a second control signal Con2 based on the second voltage signal and the first control signal Con1, it can be considered that the moment when the clock signal CLK reaches a stable state is the start time of the effective potential of the first control signal Con1, and the moment when the first control signal Con1 reaches an effective potential and the second voltage signal both reach a stable state is the start time of the effective potential of the second control signal Con2, which is also the start time of the first sub-reset signal in the reset signal Reset. Thus, the processing module 203 only acquires and parses the display signal when both the clock signal CLK and the second voltage signal reach a stable state, reducing the risk of a black screen upon startup.

[0067] In other words, compared to the second time period T2, in this application, due to the setting of the judgment module 202, the first control signal Con1 is only valid when the clock signal CLK reaches a stable state after the first time period T1 (for example, the end time of the third time period T3), and then the second control signal Con2 is only valid. That is, the reset signal Reset is only the first sub-reset signal after the third time period T3, which is longer than the second time period T2.

[0068] As shown in Figure 2, the reset circuit 40 may include a first resistor R1 and a first capacitor C1 connected in series. One end of the first resistor R1 is loaded with a constant voltage signal, such as the first voltage signal VCC mentioned above. One end of the first capacitor C1 may be grounded. The connection point of the first resistor R1 and the first capacitor C1 may be electrically connected to the AND gate unit 2022.

[0069] In some embodiments, as shown in Figures 1 and 2, the power manager 30 is further configured to generate a third voltage signal STB, and the clock module 201 is configured to generate the clock signal CLK based on the third voltage signal STB. That is, it can be considered that the clock module 201 generates the clock signal CLK to produce multiple clock pulses p only when the third voltage signal STB reaches the corresponding effective potential (e.g., a high potential), and the effective potential of the third voltage signal STB can be considered as the trigger signal for the clock module 201 to generate the clock signal CLK.

[0070] Specifically, when the power manager 30 is powered on, the third voltage signal STB can reach the corresponding effective potential, so that the level conversion circuit in the drive system 20 (which may also be included in the processing module 203) can generate a sub-timing signal acting on the gate driver 50 according to the timing signal, thereby controlling the gate driver 50 to generate multiple gate signals; and when the power manager 30 is powered off, the third voltage signal STB can become the corresponding ineffective potential, so that the gate driver 50 is no longer acted on by the sub-timing signal but is an ineffective potential, causing the gate driver 50 to discharge and reducing the risk of power-off ghosting on the display panel 10.

[0071] As shown in Figure 2, the power manager 30 can be electrically connected to the clock module 201 through a circuit consisting of the second resistor R2 and the second capacitor C2. One end of the second resistor R2 is loaded with a constant voltage signal, for example, the first voltage signal VCC mentioned above. One end of the second capacitor C2 can be grounded. The terminal in the power manager 30 used to output the third voltage signal STB can be connected to the connection point of the second resistor R2 and the second capacitor C2.

[0072] To better illustrate the above-described display device, this application also provides a driving method for the display device, which may include, but is not limited to, the following embodiments and combinations thereof.

[0073] In some embodiments, as shown in FIG7, the driving method of the display device may include, but is not limited to, the following steps and a combination of the following steps.

[0074] S1, the clock module generates a clock signal;

[0075] S2, the judgment module generates a reset signal based on the relationship between the clock information in the clock signal and preset information;

[0076] S3, the processing module controls the driving system to obtain a display signal for controlling the display panel to display an image based on the reset information in the reset signal, and processes the display signal.

[0077] The clock module, judgment module, processing module, clock signal, reset signal, and display signal can be referred to in the relevant descriptions above.

[0078] Understandably, in the driving method of this display device, the processing module 203 controls the driving system 20 to acquire the display signal based on the reset signal Reset, and the control judgment module 202 is used to generate the reset signal Reset based on the clock signal CLK, so that the time when the driving system 20 acquires the display signal can be determined at least based on the clock signal CLK. The reset signal Reset can only have an effective potential when the clock signal CLK is stable, so as to control the driving system 20 to acquire the display signal and then perform effective parsing, avoiding parsing errors caused by acquiring the display signal when the clock signal CLK is not stable, and improving the black screen phenomenon of the display device 100 when powered on.

[0079] Specifically, the clock information includes the number of clock pulses p, the preset information includes preset values, and step S2 may include, but is not limited to, the following steps:

[0080] S201, the counting unit generates a first control signal according to the clock signal. The first control signal is a corresponding valid first control potential when the number of clock pulses is greater than or equal to the preset value. The valid first control potential is used to control the reset information to be a first sub-reset signal.

[0081] The preset values ​​can be found in the description above.

[0082] Correspondingly, step S3 may include, but is not limited to, the following steps:

[0083] S301, the processing module acquires the display signal when the reset information is the first sub-reset signal.

[0084] Understandably, by counting the number of clock pulses p in the clock signal CLK through the counting unit 2021, the processing module 203 can obtain the display signal only when the number of clock pulses p is greater than or equal to a preset value, thereby performing effective analysis and avoiding analysis errors caused by obtaining the display signal before the clock signal CLK is stable.

[0085] Step S3 may include, but is not limited to, the following steps:

[0086] S302, the processing module generates an image signal based on the clock signal and the display signal;

[0087] Furthermore, when the drive system 20 includes a drive chip, and the drive chip includes a clock module 201, a judgment module 202, a processing module 203, and a data drive module 205, that is, when the drive system 20 (drive chip 0 is a timing controller embedded data driver) is a timing controller, the steps after step S302 may include, but are not limited to, the following steps:

[0088] S3021, the data driving module is used to control the display panel to display the image according to the image signal.

[0089] Alternatively, when the driving system 20 includes a timing control chip electrically connected to the display panel 10 and a source driver chip electrically connected between the display panel 10 and the timing control chip, and the timing control chip includes a clock module 201, a judgment module 202, and a processing module 203, that is, when the driving system 20 is a discrete architecture, the steps after step S302 may include, but are not limited to, the following steps:

[0090] S3022, the source driver chip is used to control the display panel to display the image according to the image signal.

[0091] For details of steps S3021 and S3022, please refer to the relevant description in the above description of the display device 100.

[0092] It should be noted that the driving system 20, display panel 10, clock module 201, processing module 203, gate driver 50, data driving module 205, etc. mentioned in this application can be substantially composed of at least one transistor device, and may also include at least one of capacitors and resistors, as well as wires electrically connected between different components. For specific configuration details, please refer to the above discussion.

[0093] The display device and its driving method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display device, wherein, Includes a display panel and a driving system electrically connected to the display panel, the driving system comprising: The clock module is used to generate clock signals; The judgment module is used to generate a reset signal based on the relationship between the clock information in the clock signal and preset information; The processing module is configured to obtain a display signal for controlling the display panel to display an image based on the reset information in the reset signal, and to process the display signal. Wherein, the clock signal includes multiple clock pulses, the clock information includes the number of clock pulses, the preset information includes a preset value, and the judgment module includes: A counting unit is used to generate a first control signal according to the clock signal. The first control signal is an effective first control potential when the number of clock pulses is greater than or equal to the preset value. The effective first control potential is used to control the reset information to be a first sub-reset signal. The processing module is used to obtain the display signal based on the first sub-reset signal; The driving system includes a driving chip, which includes a clock module, a judgment module, a processing module, and a data driving module. The processing module is used to generate an image signal based on the clock signal and the display signal; The data driving module is used to control the display panel to display images based on the image signals.

2. The display device as claimed in claim 1, wherein, The counting unit includes: Multiple triggers are used to generate corresponding trigger signals based on the clock signal; A signal processor is configured to generate the first control signal based on a plurality of the trigger signals.

3. The display device as claimed in claim 2, wherein, The first and second terminals of the flip-flop are electrically connected to a first voltage line for transmitting a first voltage signal. The clock terminal of the first-stage flip-flop is electrically connected to the clock module. The clock terminal of each of the second to last-stage flip-flops is electrically connected to the output terminal of the previous-stage flip-flop.

4. The display device as claimed in claim 2 or 3, wherein, The signal processor is configured to control the first control signal to the corresponding effective first control potential when each of the plurality of trigger signals is a first sub-trigger signal.

5. The display device according to any one of claims 1 to 3, wherein, It also includes a power manager electrically connected to the drive system, the power manager being used to generate a second voltage signal, and the determination module further includes: An AND gate unit, electrically connected to the counting unit and the power manager, is used to control the reset signal to be the first sub-reset signal according to the effective first control potential corresponding to the second voltage signal and the first control signal.

6. The display device as claimed in claim 5, wherein, It also includes a reset circuit electrically connected to the drive system, the reset circuit being used to generate an initial reset signal; The AND gate unit is used to generate a second control signal based on the second voltage signal and the first control signal, and the second control signal is used to adjust the initial reset signal to the reset signal.

7. The display device as claimed in claim 5, wherein, The power manager is also used to generate a third voltage signal, and the clock module is used to generate the clock signal based on the third voltage signal.

8. A display device, wherein, Includes a display panel and a driving system electrically connected to the display panel, the driving system comprising: The clock module is used to generate clock signals; The judgment module is used to generate a reset signal based on the relationship between the clock information in the clock signal and preset information; The processing module is used to obtain a display signal for controlling the display screen of the display panel based on the reset information in the reset signal, and to process the display signal.

9. The display device as claimed in claim 8, wherein, The clock signal includes multiple clock pulses, the clock information includes the number of clock pulses, the preset information includes a preset value, and the judgment module includes: A counting unit is used to generate a first control signal according to the clock signal. The first control signal is an effective first control potential when the number of clock pulses is greater than or equal to the preset value. The effective first control potential is used to control the reset information to be a first sub-reset signal. The processing module is used to obtain the display signal based on the first sub-reset signal.

10. The display device as claimed in claim 9, wherein, The counting unit includes: Multiple triggers are used to generate corresponding trigger signals based on the clock signal; A signal processor is configured to generate the first control signal based on a plurality of the trigger signals.

11. The display device as claimed in claim 10, wherein, The first and second terminals of the flip-flop are electrically connected to a first voltage line for transmitting a first voltage signal. The clock terminal of the first-stage flip-flop is electrically connected to the clock module. The clock terminal of each of the second to last-stage flip-flops is electrically connected to the output terminal of the previous-stage flip-flop.

12. The display device as claimed in claim 10 or 11, wherein, The signal processor is configured to control the first control signal to the corresponding effective first control potential when each of the plurality of trigger signals is a first sub-trigger signal.

13. The display device according to any one of claims 9 to 11, wherein, It also includes a power manager electrically connected to the drive system, the power manager being used to generate a second voltage signal, and the determination module further includes: An AND gate unit, electrically connected to the counting unit and the power manager, is used to control the reset signal to be the first sub-reset signal according to the effective first control potential corresponding to the second voltage signal and the first control signal.

14. The display device as claimed in claim 13, wherein, It also includes a reset circuit electrically connected to the drive system, the reset circuit being used to generate an initial reset signal; The AND gate unit is used to generate a second control signal based on the second voltage signal and the first control signal, and the second control signal is used to adjust the initial reset signal to the reset signal.

15. The display device as claimed in claim 13, wherein, The power manager is also used to generate a third voltage signal, and the clock module is used to generate the clock signal based on the third voltage signal.

16. The display device according to any one of claims 8 to 11, 14 to 15, wherein, The driving system includes a driving chip, which includes a clock module, a judgment module, a processing module, and a data driving module. The processing module is used to generate an image signal based on the clock signal and the display signal; The data driving module is used to control the display panel to display images based on the image signals.

17. The display device according to any one of claims 8 to 11, 14 to 15, wherein, The driving system includes a timing control chip electrically connected to the display panel and a source driver chip electrically connected between the display panel and the timing control chip. The timing control chip includes a clock module, a judgment module and a processing module. The processing module is used to generate an image signal based on the clock signal and the display signal; The source driver chip is used to control the display panel to display images based on the image signals.

18. A driving method for a display device, wherein, The display device includes a display panel and a driving system electrically connected to the display panel. The driving system includes a clock module, a judgment module, and a processing module. The method includes: The clock module generates a clock signal; The judgment module generates a reset signal based on the relationship between the clock information in the clock signal and preset information. The processing module obtains the display signal for controlling the display panel's display screen based on the reset information in the reset signal, and processes the display signal.

19. The driving method for the display device as claimed in claim 18, wherein, The clock signal includes multiple clock pulses, the clock information includes the number of clock pulses, the preset information includes a preset value, the judgment module includes a counting unit, and the step of the judgment module generating a reset signal based on the relationship between the clock information in the clock signal and the preset information includes: The counting unit generates a first control signal according to the clock signal. The first control signal is a corresponding valid first control potential when the number of clock pulses is greater than or equal to the preset value. The valid first control potential is used to control the reset information to be a first sub-reset signal. The step of the processing module obtaining a display signal for controlling the display panel based on the reset information in the reset signal includes: The processing module acquires the display signal when the reset information is the first sub-reset signal.

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