Beamformer integrated circuit and phased array antenna module

Abstract

This beamformer integrated circuit comprises a plurality of first input / output ports, a second input / output port, and a connecting circuit. The plurality of first input / output ports are electrically connected to a plurality of antenna elements. RF signals are inputted into and outputted from the second input / output port. The connecting circuit connects the plurality of first input / output ports with the second input / output port and transfers RF signals between the plurality of first input / output ports and the second input / output port. The connecting circuit has a plurality of front-end circuits, at least one amplifier, and at least one temperature compensation circuit. The plurality of front-end circuits each include a phase shifter that changes the phase of the RF signal, and are connected to the plurality of first input / output ports. The amplifier amplifies the RF signal. In the temperature compensation circuit, the higher the temperature, the smaller the pass loss generated in the RF signal.

Description

Beamformer integrated circuits and phased array antenna modules

[0001] The present invention relates to a beamformer integrated circuit and a phased array antenna module. This application claims priority under Japanese Patent Application No. 2024-219745, filed in Japan on December 16, 2024, the contents of which are incorporated herein by reference.

[0002] Conventionally, phased array antenna modules, such as those disclosed in Non-Patent Document 1, are known. This phased array antenna module comprises a plurality of antenna elements and a beamformer integrated circuit connected to these antenna elements. This beamformer integrated circuit includes an amplifier and a plurality of phase shifters.

[0003] The amplifier amplifies the transmit signal (RF signal) supplied to each antenna element with a desired gain, and also amplifies the received signal (RF signal) received by each antenna with a desired gain. Multiple phase shifters are provided in a one-to-one correspondence with multiple antenna elements. Each phase shifter sets the phase of the signal transmitted and received by the corresponding antenna element to a desired value. By independently adjusting the phase of the signal transmitted and received by each antenna element using multiple phase shifters, the direction of the beam transmitted and received by the phased array antenna module is adjusted.

[0004] B. Sadhu et al., “A 24-to-30GHz 256-element dual-polarized 5G phased array with fast beamswitching support for >30,000 beams”, 2022 IEEE Int'Solid-State Circuits Conf. (ISSCC), pp 436-437, Feb. 2022

[0005] For example, in conventional beamformer integrated circuits, such as those disclosed in Non-Patent Document 1, a problem has been the large variation in gain due to temperature fluctuations. Specifically, in conventional beamformer integrated circuits, the gain is higher at lower temperatures and lower at higher temperatures. It is desirable that the gain of a beamformer integrated circuit be constant with respect to temperature fluctuations.

[0006] In conventional beamformer integrated circuits, methods such as optimizing the gain setting of the amplifier included in the beamformer integrated circuit for temperature fluctuations were employed to keep the beamformer integrated circuit's gain constant. However, this method had problems such as performance degradation and increased costs of the beamformer integrated circuit due to the complexity of the settings and the addition of temperature control functions.

[0007] This invention has been made in consideration of these circumstances and aims to provide a beamformer integrated circuit and a phased array antenna module that can easily suppress gain fluctuations due to temperature fluctuations.

[0008] To solve the above problems, a beamformer integrated circuit according to embodiment 1 of the present invention comprises: a plurality of first input / output ports electrically connected to a plurality of antenna elements so as to correspond one-to-one with the plurality of antenna elements; a second input / output port to which an RF signal is input and output; a connection circuit that connects the plurality of first input / output ports and the second input / output port and transmits the RF signal between the plurality of first input / output ports and the second input / output port, wherein the connection circuit each includes a phase shifter for changing the phase of the RF signal; a plurality of front-end circuits connected to the plurality of first input / output ports so as to correspond one-to-one with the plurality of first input / output ports; at least one amplifier for amplifying the RF signal; and at least one temperature compensation circuit that reduces the pass loss caused to the RF signal as the temperature increases.

[0009] According to embodiment 1 of the present invention, a beamformer integrated circuit can be provided that can easily suppress gain fluctuations in response to temperature fluctuations.

[0010] Furthermore, in embodiment 2 of the present invention, in the beamformer integrated circuit of embodiment 1, each of the plurality of front-end circuits includes a first temperature compensation circuit which is one of the temperature compensation circuits.

[0011] Furthermore, in embodiment 3 of the present invention, in the beamformer integrated circuit of embodiment 2, each of the plurality of front-end circuits includes a front-end amplifier which is one of the amplifiers, each of the plurality of front-end circuits has a first connection port which is electrically connected to the second input / output port, and in each of the plurality of front-end circuits, the first temperature compensation circuit is arranged between the front-end amplifier and the first connection port.

[0012] Furthermore, aspect 4 of the present invention is a beamformer integrated circuit according to aspect 3, wherein each of the plurality of front-end circuits includes a first switch circuit located between the front-end amplifier and the first connection port for switching the path through which the RF signal is transmitted in the front-end circuit, and in each of the plurality of front-end circuits, the first temperature compensation circuit is located between the first switch circuit and the first connection port and is located adjacent to the first switch circuit.

[0013] Furthermore, aspect 5 of the present invention is a beamformer integrated circuit in any one of aspects 1 to 4, wherein the connection circuit includes a group amplifier which is one of the amplifiers, and has an amplification circuit which is electrically connected to two or more of the plurality of front-end circuits, and the amplification circuit includes a second temperature compensation circuit which is one of the temperature compensation circuits.

[0014] Furthermore, in embodiment 6 of the present invention, in the beamformer integrated circuit of embodiment 5, the amplification circuit has a second connection port that is electrically connected to the second input / output port, and in the amplification circuit, the second temperature compensation circuit is arranged between the group amplifier and the second connection port.

[0015] Further, in the beamformer integrated circuit of Aspect 6 of the present invention, the amplification circuit includes a second switch circuit disposed between the batch amplifier and the second connection port that switches a path through which the RF signal is transmitted in the amplification circuit. In the amplification circuit, the second temperature compensation circuit is disposed between the second switch circuit and the second connection port and is disposed adjacent to the second switch circuit.

[0016] Further, in the beamformer integrated circuit according to any one of Aspects 1 to 7 of the present invention, the plurality of front-end circuits include a plurality of first front-end circuits corresponding to the antenna elements that transmit and receive a first polarization wave, and a plurality of second front-end circuits corresponding to the antenna elements that transmit and receive a second polarization wave orthogonal to the first polarization wave. The plurality of first front-end circuits and the plurality of second front-end circuits are alternately arranged.

[0017] Further, in the beamformer integrated circuit according to any one of Aspects 1 to 7 of the present invention, the plurality of front-end circuits include a plurality of first front-end circuits corresponding to the antenna elements that transmit and receive a first polarization wave, and a plurality of second front-end circuits corresponding to the antenna elements that transmit and receive a second polarization wave orthogonal to the first polarization wave. The plurality of first front-end circuits are arranged adjacent to each other, and the plurality of second front-end circuits are arranged adjacent to each other.

[0018] Further, the phased array antenna module according to Aspect 10 of the present invention includes the beamformer integrated circuit according to any one of Aspects 1 to 9, and the plurality of antenna elements connected to the plurality of first input / output ports so as to correspond one-to-one with the plurality of first input / output ports.

[0019] According to the above aspects of the present invention, it is possible to provide a beamformer integrated circuit and a phased array antenna module that can easily suppress gain fluctuations with respect to temperature fluctuations.

[0020] It is a plan view showing a phased array antenna module according to the first embodiment of the present invention. It is a circuit diagram showing a beamformer integrated circuit according to the first embodiment of the present invention. It is a circuit diagram showing a front-end circuit according to the first embodiment of the present invention. It is a circuit diagram showing an amplifier circuit according to the first embodiment of the present invention. It is a circuit diagram showing a temperature compensation circuit according to the first embodiment of the present invention. It is a circuit diagram showing a variable attenuator and a switching attenuator according to the first embodiment of the present invention. It is a circuit diagram showing a current mirror circuit for temperature compensation according to the first embodiment of the present invention. It is a graph showing an example of the temperature characteristics of the temperature compensation circuit according to the first embodiment of the present invention. It is another graph showing an example of the temperature characteristics of the temperature compensation circuit according to the first embodiment of the present invention. It is a circuit diagram showing a beamformer integrated circuit according to the second embodiment of the present invention.

[0021] (First Embodiment) Hereinafter, the beamformer integrated circuit 1 and the phased array antenna module 100 according to the first embodiment of the present invention will be described based on the drawings.

[0022] <Phased Array Antenna Module> FIG. 1 is a plan view showing a phased array antenna module 100 according to the first embodiment of the present invention.

[0023] As shown in FIG. 1, the phased array antenna module 100 according to the present embodiment includes a plurality (eight in the illustrated example) of beamformer integrated circuits 1, a plurality of antenna elements 2, and a substrate 3. The phased array antenna module 100 is provided, for example, in a wireless communication device that uses an RF signal in a millimeter wave band or the like. The wireless communication device is configured to be capable of beamforming that can freely change the beam pattern, for example.

[0024] The substrate 3 is, for example, a printed substrate or the like. However, the type of the substrate 3 is not particularly limited. A known substrate can be appropriately adopted as the substrate 3. The substrate 3 has a first surface 3a and a second surface 3b located on the side opposite to the first surface 3a.

[0025] Multiple antenna elements 2 are mounted on the first surface 3a of the substrate 3. The multiple antenna elements 2 are arranged in two dimensions on the first surface 3a, forming an antenna array. As will be described in detail later, the multiple antenna elements 2 are connected to multiple first input / output ports 1a (described later) of multiple beamformer integrated circuits 1 in a one-to-one correspondence.

[0026] The phased array antenna module 100 transmits and receives electromagnetic waves using multiple antenna elements 2. Hereinafter, the mode in which the phased array antenna module 100 transmits electromagnetic waves will be referred to as the "transmission mode," and the mode in which the phased array antenna module 100 receives electromagnetic waves will be referred to as the "receiving mode."

[0027] Although detailed illustrations are omitted, the multiple antenna elements 2 include antenna elements 2 that transmit and receive a first polarization (antenna elements 2 for the first polarization) and antenna elements 2 that transmit and receive a second polarization orthogonal to the first polarization (antenna elements 2 for the second polarization). The number of antenna elements 2 for the first polarization and the number of antenna elements 2 for the second polarization included in the multiple antenna elements 2 may be equal to each other.

[0028] For example, at each of the 64 antenna elements 2 shown in Figure 1, both a first polarization antenna element 2 and a second polarization antenna element 2 are provided. For example, the first polarization antenna element 2 is provided so as to be exposed on the first surface 3a. On the other hand, the second polarization antenna element 2 is provided so as to overlap the first polarization antenna element 2 in a plan view (i.e., viewed from a direction perpendicular to the first surface 3a). That is, the second polarization antenna element 2 is provided on a different layer of the substrate 3 from the layer on which the first polarization antenna element 2 is provided. In this case, the phased array antenna module 100 has a total of 128 antenna elements 2, consisting of 64 first polarization antenna elements 2 and 64 second polarization antenna elements 2.

[0029] In this specification, the first polarization is horizontal polarization (H polarization), and the second polarization is vertical polarization (V polarization). However, the first polarization may be vertical polarization and the second polarization may be horizontal polarization. That is, one of the first and second polarizations may be horizontal polarization and the other may be vertical polarization.

[0030] The beamformer integrated circuit 1 is mounted on the second surface 3b of the substrate 3. The beamformer integrated circuit 1 is an integrated circuit that controls the beam patterns of a plurality of antenna elements 2 (antenna arrays). In this embodiment, sixteen antenna elements 2 are connected to each beamformer integrated circuit 1 (detailed illustration is omitted). The electrical connection structure between the beamformer integrated circuit 1 and the antenna elements 2 is not particularly limited. Known connection structures can be appropriately adopted as the electrical connection structure between the beamformer integrated circuit 1 and the antenna elements 2.

[0031] <Beamformer Integrated Circuit> Figure 2 is a circuit diagram showing a beamformer integrated circuit 1 according to the first embodiment of the present invention.

[0032] As shown in Figure 2, in this specification, a first direction X and a second direction Y are defined in the beamformer integrated circuit 1, and the positional relationships of the configuration of the beamformer integrated circuit 1 are described based on these directions X and Y. The first direction X is a direction along the surface on which the beamformer integrated circuit 1 is mounted (i.e., the second surface 3b of the substrate 3). The second direction Y is a direction along the surface on which the beamformer integrated circuit 1 is mounted (i.e., the second surface 3b of the substrate 3) and intersects (for example, is orthogonal to) the first direction X. One direction in the first direction X is referred to as the right and is represented by the direction +X in the figure. The direction opposite to the right is referred to as the left and is represented by the direction -X in the figure. One direction in the second direction Y is referred to as the upward and is represented by the direction +Y in the figure. The direction opposite to the upward is referred to as the downward and is represented by the direction -Y in the figure.

[0033] As shown in Figure 2, the beamformer integrated circuit 1 according to this embodiment includes a plurality of (sixteen in the illustrated example) first input / output ports 1a, at least one (two in the illustrated example) second input / output ports 1b, a connection circuit 4, a control circuit 40, and a pair of analog / digital conversion circuits 50 (a first analog / digital conversion circuit 51 and a second analog / digital conversion circuit 52).

[0034] The first input / output port (first input / output terminal) 1a is a port (terminal) for the beamformer integrated circuit 1 to exchange RF signals with the antenna element 2.

[0035] In transmission mode, the first input / output port 1a functions as an output port (output terminal) that outputs an RF signal toward the antenna element 2. In reception mode, the first input / output port 1a functions as an input port (input terminal) that receives an RF signal from the antenna element 2.

[0036] Multiple first input / output ports 1a are connected to multiple antenna elements 2 in a one-to-one correspondence with each antenna element 2. That is, in this embodiment, the multiple first input / output ports 1a include sixteen ports 1a-1 to 1a-16. The sixteen ports 1a-1 to 1a-16 correspond one-to-one with sixteen antenna elements 2, and each port 1a-1 to 1a-16 is electrically connected to the corresponding antenna element 2. Specifically, ports 1a-1 to 1a-16 and the antenna elements 2 may be connected via wiring provided on the substrate 3. Alternatively, ports 1a-1 to 1a-16 and the antenna elements 2 may be connected by electromagnetic interaction due to electromagnetic waves.

[0037] Ports 1a-1, 1a-2, 1a-3, 1a-4, 1a-9, 1a-10, 1a-11, and 1a-12 are arranged in this order from left to right on the upper edge of the beamformer integrated circuit 1. Ports 1a-5, 1a-6, 1a-7, 1a-8, 1a-13, 1a-14, 1a-15, and 1a-16 are arranged in this order from left to right on the lower edge of the beamformer integrated circuit 1.

[0038] Hereinafter, the first input / output port 1a connected to the antenna element 2 for the first polarization will be referred to as the first input / output port 1aA for the first polarization, and the first input / output port 1a connected to the antenna element 2 for the second polarization will be referred to as the first input / output port 1aB for the second polarization. That is, the first input / output port 1aA for the first polarization is a port for inputting and outputting the first polarization, and the first input / output port 1aB for the second polarization is a port for inputting and outputting the second polarization.

[0039] In this embodiment, ports 1a-1, 1a-3, 1a-5, 1a-7, 1a-9, 1a-11, 1a-13, and 1a-15 function as first polarization input / output ports 1aA, and ports 1a-2, 1a-4, 1a-6, 1a-8, 1a-10, 1a-12, 1a-14, and 1a-16 function as second polarization input / output ports 1aB. In other words, at the upper and lower edges of the beamformer integrated circuit 1, a plurality of (four in the illustrated example) first polarization input / output ports 1aA and a plurality of (four in the illustrated example) second polarization input / output ports 1aB are alternately arranged in the first direction X.

[0040] The second input / output port (second input / output terminal) 1b is a port (terminal) to which RF signals are input and output. As will be described later, the second input / output port 1b (ports 1b-1, 1b-2) is connected to the first input / output port 1a (ports 1a-1 to 1a-16) via the connection circuit 4. An input / output device (not shown) that performs input and output of RF signals is connected to the second input / output port 1b. In other words, the second input / output port 1b is a port for the beamformer integrated circuit 1 to exchange RF signals with the input / output device. The input / output device connected to the second input / output port 1b may be, for example, an RFIC (Radio Frequency Integrated Circuit).

[0041] In transmission mode, the second input / output port 1b functions as an input port (input terminal) to which an RF signal is input from an input / output device. In reception mode, the second input / output port 1b functions as an output port (output terminal) to which an RF signal is output towards the input / output device.

[0042] In this embodiment, two ports, 1b-1 and 1b-2, are provided as the second input / output port 1b. Port 1b-1 is located on the left edge of the beamformer integrated circuit 1. Port 1b-2 is located on the right edge of the beamformer integrated circuit 1.

[0043] Hereinafter, the second input / output port 1b connected to the first input / output port 1aA for the first polarization via the connection circuit 4 will be referred to as the second input / output port 1bA for the first polarization, and the second input / output port 1b connected to the first input / output port 1aB for the second polarization via the connection circuit 4 will be referred to as the second input / output port 1bB for the second polarization. In other words, the second input / output port 1bA for the first polarization is a port for inputting and outputting the first polarization, and the second input / output port 1bB for the second polarization is a port for inputting and outputting the second polarization.

[0044] In this embodiment, port 1b-1 functions as a second input / output port 1bA for the first polarization, and port 1b-2 functions as a second input / output port 1bB for the second polarization.

[0045] The connection circuit 4 is a circuit that connects a plurality of first input / output ports 1a (ports 1a-1 to 1a-16) and at least one second input / output port 1b (ports 1b-1, 1b-2). The connection circuit 4 transmits RF signals between the plurality of first input / output ports 1a and at least one second input / output port 1b. The connection circuit 4 according to this embodiment has a plurality of (sixteen in the illustrated example) front-end circuits 10, at least one (two in the illustrated example) distributor / combiner 20, and at least one (two in the illustrated example) amplifier circuits 30.

[0046] Multiple front-end circuits 10 are connected to multiple first input / output ports 1a in a one-to-one correspondence with each of the multiple first input / output ports 1a. That is, in this embodiment, the multiple front-end circuits 10 include sixteen front-end circuits 10-1 to 10-16. The sixteen front-end circuits 10-1 to 10-16 correspond one-to-one with sixteen ports 1a-1 to 1a-16, and each front-end circuit 10-1 to 10-16 is connected to the corresponding port 1a-1 to 1a-16.

[0047] In other words, the sixteen front-end circuits 10-1 to 10-16 correspond one-to-one with the sixteen antenna elements 2, and each front-end circuit 10-1 to 10-16 is electrically connected to the corresponding antenna element 2 via the first input / output port 1a.

[0048] Each front-end circuit 10-1 to 10-16 is positioned at the upper or lower edge of the beamformer integrated circuit 1 so as to face the corresponding port 1a-1 to 1a-16 in the second direction Y.

[0049] Front-end circuits 10-1, 10-2, 10-3, 10-4, 10-9, 10-10, 10-11, and 10-12 are arranged in this order from left to right on the upper edge of the beamformer integrated circuit 1. Front-end circuits 10-5, 10-6, 10-7, 10-8, 10-13, 10-14, 10-15, and 10-16 are arranged in this order from left to right on the lower edge of the beamformer integrated circuit 1.

[0050] Hereinafter, the front-end circuit 10 connected to the first input / output port 1aA for the first polarization will be referred to as the first front-end circuit 10A, and the front-end circuit 10 connected to the first input / output port 1aB for the second polarization will be referred to as the first input / output port 1aB for the second polarization. In other words, the first front-end circuit 10A corresponds to the antenna element 2 for the first polarization, and the second front-end circuit 10B corresponds to the antenna element 2 for the second polarization.

[0051] In this embodiment, front-end circuits 10-1, 10-3, 10-5, 10-7, 10-9, 10-11, 10-13, and 10-15 function as first front-end circuits 10A, and front-end circuits 10-2, 10-4, 10-6, 10-8, 10-10, 10-12, 10-14, and 10-16 function as second front-end circuits 10B. In other words, at the upper and lower edges of the beamformer integrated circuit 1, a plurality of (four in the illustrated example) first front-end circuits 10A and a plurality of (four in the illustrated example) second front-end circuits 10B are alternately arranged in the first direction X.

[0052] Each front-end circuit 10 has a port 10a and a port 10b. Port 10a is a port (terminal) connected to the first input / output port 1a. Port 10b is a port (terminal) connected to the distributor / combiner 20 (port 20a, described later). Port 10b is electrically connected to the second input / output port 1b via the distributor / combiner 20 and the amplification circuit 30. Port 10b is also referred to as the first connection port.

[0053] In transmission mode, the front-end circuit 10 amplifies the RF signal input to port 10b with a desired gain and phase shift by a desired amount, and outputs it to the corresponding antenna element 2 through port 10a and the first input / output port 1a. In reception mode, the front-end circuit 10 amplifies the RF signal input to port 10a through the first input / output port 1a by the corresponding antenna element 2 with a desired gain and phase shift by a desired amount, and outputs it from port 10b. Details of the front-end circuit 10 will be described later.

[0054] The amplification circuit 30 is connected to the second input / output port 1b. The amplification circuit 30 is also referred to as a BIDI (BiDirectional) circuit 30. In this embodiment, two amplification circuits 30A and 30B are provided as the amplification circuit 30.

[0055] Hereinafter, the amplification circuit 30 connected to the second input / output port 1bA for the first polarization will be referred to as the first amplification circuit 30A, and the amplification circuit 30 connected to the second input / output port 1bB for the second polarization will be referred to as the second amplification circuit 30B. In other words, the first amplification circuit 30A corresponds to the antenna element 2 for the first polarization, and the second amplification circuit 30B corresponds to the antenna element 2 for the second polarization.

[0056] The first amplifier circuit 30A is positioned on the left edge of the beamformer integrated circuit 1 so as to face the first polarization second input / output port 1bA in the first direction X. The second amplifier circuit 30B is positioned on the right edge of the beamformer integrated circuit 1 so as to face the second polarization second input / output port 1bB in the first direction X.

[0057] The two amplification circuits 30 are electrically connected to a plurality of front-end circuits 10. Specifically, the two amplification circuits 30 are connected to the plurality of front-end circuits 10 via two distributors / combiners 20, which will be described later. More specifically, the first amplification circuit 30A is connected to two or more (eight in the illustrated example) first front-end circuits 10A via the first distributor / combiner 20A (described later), and the second amplification circuit 30B is connected to two or more (eight in the illustrated example) second front-end circuits 10B via the second distributor / combiner 20B (described later).

[0058] Each amplification circuit 30 has ports 30a and 30b. Port 30a is a port (terminal) connected to the distributor / combiner 20 (port 20b, described later). Port 30b is a port (terminal) connected to the second input / output port 1b. Port 30b is electrically connected to the second input / output port 1b. Port 30b is also referred to as the second connection port.

[0059] In transmission mode, the amplification circuit 30 amplifies the RF signal input to port 30b with a desired gain and outputs it to the corresponding multiple front-end circuits 10 via port 30a and the distributor / combiner 20. In reception mode, the amplification circuit 30 amplifies the RF signal input to port 30a via the distributor / combiner 20 by the corresponding multiple front-end circuits 10 with a desired gain and outputs it from port 30b. Details of the amplification circuit 30 will be described later.

[0060] The distributor / combiner 20 connects the amplification circuit 30 and the multiple front-end circuits 10. In this embodiment, two distributors / combiners 20A and 20B (first distributor / combiner 20A and second distributor / combiner 20B) are provided as the distributor / combiner 20.

[0061] The first distributor / combiner 20A connects the first amplifier circuit 30A and multiple first front-end circuits 10A. The second distributor / combiner 20B connects the second amplifier circuit 30B and multiple second front-end circuits 10B. In other words, the first distributor / combiner 20A corresponds to the antenna element 2 for the first polarization, and the second distributor / combiner 20B corresponds to the antenna element 2 for the second polarization.

[0062] Each distributor / combiner 20 has multiple ports 20a (eight in the illustrated example) connected to multiple front-end circuits 10, and a port 20b connected to an amplification circuit 30. Each distributor / combiner 20 distributes the RF signal input from the amplification circuit 30 to port 20b to the multiple front-end circuits 10 through the multiple ports 20a. In addition, each distributor / combiner 20 combines the RF signals input from the multiple front-end circuits 10 to the multiple ports 20a and outputs them to the amplification circuit 30 through port 20b.

[0063] The two distributors / combiners 20A and 20B are positioned in the second direction Y between front-end circuits 10-1, 10-2, 10-3, 10-4, 10-9, 10-10, 10-11, and 10-12 and front-end circuits 10-5, 10-6, 10-7, 10-8, 10-13, 10-14, 10-15, and 10-16. The first distributor / combiner 20A is positioned above the second distributor / combiner 20B. Each distributor / combiner 20A and 20B extends in the first direction X from the location of front-end circuits 10-1 and 10-5 to the location of front-end circuits 10-12 and 10-16.

[0064] The control circuit 40 controls the operation of the front-end circuit 10 and the amplification circuit 30. The control circuit 40 controls, for example, the operation of the phase shifter 11, temperature compensation circuits 12 and 31, switch circuits 13, 16, 32 and 34, and variable gain amplifiers 14T and 14R, which will be described later. The control circuit 40 may include, for example, SRAM (Static Random Access Memory).

[0065] The control circuit 40 is located in the central part of the beamformer integrated circuit 1. In the first direction X, the control circuit 40 is located between the front-end circuits 10-4, 10-8 and the front-end circuits 10-9, 10-13.

[0066] The analog-to-digital conversion circuit 50 acquires, for example, the intensity of electromagnetic waves transmitted and received by each antenna element 2. The analog-to-digital conversion circuit 50 may also acquire temperature and power supply voltage. Note that the beamformer integrated circuit 1 does not necessarily have to include the analog-to-digital conversion circuit 50.

[0067] In this embodiment, the analog-to-digital conversion circuit 50 includes a first analog-to-digital conversion circuit 51 and a second analog-to-digital conversion circuit 52. The first analog-to-digital conversion circuit 51 acquires the intensity of electromagnetic waves transmitted and received by the antenna elements 2 connected to the front-end circuits 10-1, 10-2, 10-3, 10-4, 10-9, 10-10, 10-11, and 10-12. The second analog-to-digital conversion circuit 52 acquires the intensity of electromagnetic waves transmitted and received by 10-5, 10-6, 10-7, 10-8, 10-13, 10-14, 10-15, and 10-16.

[0068] The two analog-to-digital conversion circuits 51 and 52 are arranged in the second direction Y such that the control circuit 40 is sandwiched between them. The first analog-to-digital conversion circuit 51 is located at the upper edge of the beamformer integrated circuit 1. The second analog-to-digital conversion circuit 52 is located at the lower edge of the beamformer integrated circuit 1.

[0069] The details of the front-end circuit 10 and the amplification circuit 30 will be described below. As described below, the connection circuit 4 has at least one (or more in this embodiment) amplifiers and at least one (or more in this embodiment) temperature compensation circuits. Each amplifier amplifies the RF signal. Each amplifier may have a temperature characteristic in which the gain increases as the temperature decreases and decreases as the temperature increases. Each temperature compensation circuit has a temperature characteristic in which the pass loss caused to the RF signal increases as the temperature decreases and decreases as the temperature increases.

[0070] <Front-end circuit> Figure 3 is a circuit diagram showing a front-end circuit 10 according to the first embodiment of the present invention.

[0071] As shown in Figure 3, the front-end circuit 10 according to this embodiment includes a phase shifter 11, a first temperature compensation circuit 12, a first switch circuit 13, a variable gain amplifier 14T, a variable gain amplifier 14R, a power amplifier 15T, a low-noise amplifier 15R, and a third switch circuit 16.

[0072] Each of the variable gain amplifiers 14T, 14R, 15T, and 15R is one of the amplifiers (described above) in the connection circuit 4. Each of the variable gain amplifiers 14T, 14R, 15T, and 15R is also called a front-end amplifier. The first temperature compensation circuit 12 is one of the temperature compensation circuits (described above) in the connection circuit 4.

[0073] The variable gain amplifier 14T and the power amplifier 15T are located on the transmission path 10T, while the variable gain amplifier 14R and the low-noise amplifier 15R are located on the reception path 10R. The transmission path 10T is the path through which RF signals are transmitted in transmission mode. The reception path 10R is the path through which RF signals are transmitted in reception mode.

[0074] Switch circuits 13 and 16 switch the path through which the RF signal is transmitted in the front-end circuit 10 between the transmission path 10T and the reception path 10R. Switch circuits 13 and 16 switch paths 10T and 10R, for example, in response to control by the control circuit 40. Switch circuits 13 and 16 may switch paths 10T and 10R at a predetermined time interval.

[0075] The first switch circuit 13 is located on the port 10b side (i.e., on the second input / output port 1b side (see Figure 2)) of the variable gain amplifier 14T, variable gain amplifier 14R, power amplifier 15T, and low noise amplifier 15R. In other words, the first switch circuit 13 is located between the variable gain amplifier 14T, variable gain amplifier 14R, power amplifier 15T, and low noise amplifier 15R and port 10b. Hereinafter, the variable gain amplifier 14T, variable gain amplifier 14R, power amplifier 15T, and low noise amplifier 15R may be collectively referred to as the "first amplifier group." The first switch circuit 13 is located between the first amplifier group and port 10b. Note that the phrase "the first switch circuit 13 is located between the first amplifier group and port 10b" includes not only the case where the first switch circuit 13 is adjacent to the first amplifier group and / or port 10b, but also the case where other objects exist between the first switch circuit 13 and the first amplifier group and / or port 10b. This applies to all instances of the phrase “placed between” in this specification. The third switch circuit 16 is located on the port 10a side (i.e., on the first input / output port 1a side (see Figure 2)) of the first amplifier group (variable gain amplifier 14T, variable gain amplifier 14R, power amplifier 15T, and low noise amplifier 15R). In other words, the third switch circuit 16 is located between the first amplifier group (variable gain amplifier 14T, variable gain amplifier 14R, power amplifier 15T, and low noise amplifier 15R) and port 10a.

[0076] The phase shifter 11 changes the phase of the RF signal passing through the transmission path 10T or the RF signal passing through the reception path 10R in accordance with the control circuit 40. In other words, the phase shifter 11 is provided in common to both the transmission path 10T and the reception path 10R. Alternatively, a separate phase shifter may be provided for the transmission path 10T and the reception path 10R. In this case, the phase shifter 11 may be omitted.

[0077] The first temperature compensation circuit 12 causes a predetermined pass-through loss according to the temperature for RF signals passing through the transmission path 10T or RF signals passing through the reception path 10R. Specifically, the first temperature compensation circuit 12 has a temperature characteristic in which the pass-through loss is greater at lower temperatures and smaller at higher temperatures. The temperature characteristics may be the same or different among the multiple first temperature compensation circuits 12 that are present in multiple front-end circuits 10. The internal configuration of the first temperature compensation circuit 12 will be described later.

[0078] The first temperature compensation circuit 12 is provided in common to the transmission path 10T and the reception path 10R. Specifically, the first temperature compensation circuit 12 in this embodiment is located on the port 10b side (i.e., on the second input / output port 1b side (see Figure 2)) of the power amplifier 15T, the variable gain amplifier 14T, and the first switch circuit 13. In other words, the first temperature compensation circuit 12 is located between the power amplifier 15T, the variable gain amplifier 14T, the first switch circuit 13, and port 10b. The first temperature compensation circuit 12 is located between the first amplifier group and the first switch circuit 13 and port 10b. Furthermore, the first temperature compensation circuit 12 is located adjacent to the first switch circuit 13. In other words, the first temperature compensation circuit 12 is directly connected to the first switch circuit 13.

[0079] In addition, temperature compensation circuits may be provided separately for the transmission path 10T and the reception path 10R. In this case, the first temperature compensation circuit 12 may be omitted.

[0080] The variable gain amplifier 14T amplifies the RF signal passing through the transmission path 10T with a predetermined gain according to the control circuit 40. The variable gain amplifier 14T may also have the function of a phase inverter that inverts the phase of the RF signal passing through the transmission path 10T. The power amplifier 15T amplifies the RF signal passing through the transmission path 10T with a predetermined gain.

[0081] The low-noise amplifier 15R amplifies the RF signal passing through the receiving path 10R with a predetermined gain. The low-noise amplifier 15R may also have a function as a phase inverter that inverts the phase of the RF signal passing through the receiving path 10R. By incorporating the phase inverter function into the low-noise amplifier 15R instead of the variable-gain amplifier 14R, the circuit size of the front-end circuit 10 can be reduced. The variable-gain amplifier 14R amplifies the RF signal passing through the receiving path 10R with a predetermined gain according to the control by the control circuit 40.

[0082] The control circuit 40 described above adjusts the phase amount and gain of the RF signal in each of the multiple front-end circuits 10. This makes it possible to change the beam pattern (beam direction and shape, etc.) of the electromagnetic waves transmitted and received by the beamformer integrated circuit 1.

[0083] <Amplifier Circuit> Figure 4 is a circuit diagram showing an amplifier circuit 30 according to the first embodiment of the present invention.

[0084] As shown in Figure 4, the amplification circuit 30 according to this embodiment includes a second temperature compensation circuit 31, a second switch circuit 32, a power amplifier 33T, a low-noise amplifier 33R, and a fourth switch circuit 34.

[0085] Each of the power amplifier 33T and the low-noise amplifier 33R is one of the amplifiers (described above) in the connection circuit 4. Each of the power amplifier 33T and the low-noise amplifier 33R is also called a combined amplifier. The second temperature compensation circuit 31 is one of the temperature compensation circuits (described above) in the connection circuit 4.

[0086] The power amplifier 33T is located on the transmission path 30T, and the low-noise amplifier 33R is located on the reception path 30R. The transmission path 30T is the path through which RF signals are transmitted in transmission mode. The reception path 30R is the path through which RF signals are transmitted in reception mode.

[0087] Switch circuits 32 and 34 switch the path through which the RF signal is transmitted in the amplification circuit 30 between the transmission path 30T and the reception path 30R. Switch circuits 32 and 34 switch paths 30T and 30R, for example, in response to control by the control circuit 40. Switch circuits 32 and 34 may switch paths 30T and 30R at a predetermined time interval.

[0088] The second switch circuit 32 is located on the port 30b side, i.e., on the second input / output port 1b side (see Figure 2), compared to the power amplifier 33T and the low-noise amplifier 33R. In other words, the second switch circuit 32 is located between the power amplifier 33T and the low-noise amplifier 33R and port 30b. Hereinafter, the power amplifier 33T and the low-noise amplifier 33R may be collectively referred to as the "second amplifier group." The second switch circuit 32 is located between the second amplifier group and port 30b. The fourth switch circuit 34 is located on the port 30a side, i.e., on the first input / output port 1a side (see Figure 2), compared to the second amplifier group (power amplifier 33T and low-noise amplifier 33R). In other words, the fourth switch circuit 34 is located between the second amplifier group (power amplifier 33T and low-noise amplifier 33R) and port 30a.

[0089] The second temperature compensation circuit 31 imparts a predetermined pass loss according to the temperature to the RF signal passing through the transmission path 30T or the RF signal passing through the reception path 30R. Specifically, the second temperature compensation circuit 31 has a temperature characteristic in which the pass loss is greater at lower temperatures and smaller at higher temperatures. The temperature characteristics of the two second temperature compensation circuits 31 in the two amplification circuits 30 may be the same or different. Furthermore, the temperature characteristics of the second temperature compensation circuit 31 may be the same or different from the temperature characteristics of the first temperature compensation circuit 12. The internal configuration of the second temperature compensation circuit 31 will be described later.

[0090] The second temperature compensation circuit 31 is provided in common to both the transmission path 30T and the reception path 30R. Specifically, in this embodiment, the second temperature compensation circuit 31 is located on the port 30b side (i.e., on the second input / output port 1b side (see Figure 2)) of the power amplifier 33T, the low-noise amplifier 33R, and the second switch circuit 32. In other words, the second temperature compensation circuit 31 is located between the power amplifier 33T, the low-noise amplifier 33R, the second switch circuit 32, and port 30b. The second temperature compensation circuit 31 is located between the second amplifier group, the second switch circuit 32, and port 30b. Furthermore, the second temperature compensation circuit 31 is located adjacent to the second switch circuit 32. In other words, the second temperature compensation circuit 31 is directly connected to the second switch circuit 32.

[0091] The power amplifier 33T amplifies the RF signal passing through the transmission path 30T with a predetermined gain. The low-noise amplifier 33R amplifies the RF signal passing through the reception path 30R with a predetermined gain. With this amplification circuit 30, the RF signals passing through the multiple front-end circuits 10 (i.e., transmitted and received by the multiple antenna elements 2) are amplified collectively with a predetermined gain.

[0092] <Temperature Compensation Circuit> In this embodiment, the first temperature compensation circuit 12 and the second temperature compensation circuit 31 have the same circuit configuration. Therefore, in the following description, the first temperature compensation circuit 12 and the second temperature compensation circuit 31 will be collectively referred to as the "temperature compensation circuit 60," and the description of the temperature compensation circuit 60 will be replaced by the descriptions of the first temperature compensation circuit 12 and the second temperature compensation circuit 31. The temperature compensation circuit 60 having the circuit configuration shown below makes it easier to miniaturize the front-end circuit 10 and the amplification circuit 30. Furthermore, the configuration of the temperature compensation circuit 60 described below is merely an example. The configuration of the temperature compensation circuit 60 can be changed as appropriate, as long as it is possible to achieve a temperature characteristic in which the pass loss caused in the RF signal decreases as the temperature increases.

[0093] Figure 5 is a circuit diagram showing a temperature compensation circuit 60 according to the first embodiment of the present invention.

[0094] As shown in Figure 5, the temperature compensation circuit 60 according to this embodiment includes two terminals 61 and 62, a transmission line 63 (transmission path), two variable attenuators 64A and 64B, four switching attenuators 65A to 65D, a variable control unit 66, and a switching control unit 67. The variable control unit 66 includes a temperature compensation current mirror circuit 66a and a control voltage generation unit 66b. The temperature compensation circuit 60 is also referred to as a composite attenuator 60. The temperature compensation current mirror circuit 66a is also simply referred to as a current mirror circuit 66a.

[0095] Each terminal 61 and 62 is a connection terminal for receiving or transmitting a high-frequency signal So (RF signal) of a predetermined frequency (predetermined wavelength) from an external source. In the temperature compensation circuit 60 (i.e., the first temperature compensation circuit 12) of the front-end circuit 10, one of the two terminals 61 and 62 is connected to the phase shifter 11, and the other is connected to the first switch circuit 13 (see also Figure 3). In the temperature compensation circuit 60 (i.e., the second temperature compensation circuit 31) of the amplification circuit 30, one of the two terminals 61 and 62 is connected to the port 30b, and the other is connected to the second switch circuit 32 (see also Figure 4).

[0096] The transmission line 63 is provided to connect terminals 61 and 62, and transmits a high-frequency signal So between terminals 61 and 62.

[0097] The two variable attenuators 64A and 64B and the four switching attenuators 65A to 65D are connected in series in the transmission line 63. In the direction from terminal 61 to terminal 62, the first variable attenuator 64A, the first switching attenuator 65A, the second switching attenuator 65B, the second variable attenuator 64B, the third switching attenuator 65C, and the fourth switching attenuator 65D are connected in this order.

[0098] The first variable attenuator 64A is a high-frequency attenuation circuit in which the attenuation amount can change continuously. The first variable attenuator 64A is equipped with a control terminal. The control terminal of the first variable attenuator 64A is connected to the output terminal of the control voltage generation unit 66b and the control terminal of the second variable attenuator 64B.

[0099] This first variable attenuator 64A applies a first variable attenuation amount to the high-frequency signal So based on the control voltage Vm input from the control voltage generation unit 66b. The first variable attenuation amount is an attenuation amount that can take on a continuous value.

[0100] The first switching attenuator 65A is a high-frequency attenuation circuit that switches between having attenuation or not. The first switching attenuator 65A is equipped with a control terminal. The control terminal of the first switching attenuator 65A is connected to the first output terminal of the switching control unit 67, the control terminal of the third switching attenuator 65C, and the first correction terminal of the control voltage generation unit 66b.

[0101] In this first switching attenuator 65A, the presence or absence of an attenuation amount (first switching attenuation amount) applied to the high-frequency signal So is set based on a first switching signal Vc1 input from the switching control unit 67. That is, the first switching attenuator 65A switches based on the first switching signal Vc1 between a state in which the first switching attenuation amount is applied to the high-frequency signal So and output, and a state in which the first switching attenuation amount is not applied to the high-frequency signal So and output.

[0102] The second switching attenuator 65B is a high-frequency attenuation circuit that switches between having attenuation or not. The second switching attenuator 65B is equipped with a control terminal. The control terminal of the second switching attenuator 65B is connected to the second output terminal of the switching control unit 67, the control terminal of the fourth switching attenuator 65D, and the second correction terminal of the control voltage generation unit 66b.

[0103] In this second switching attenuator 65B, the presence or absence of an attenuation amount (second switching attenuation amount) applied to the high-frequency signal So is set based on a second switching signal Vc2 input from the switching control unit 67. That is, the second switching attenuator 65B switches based on the second switching signal Vc2 between a state in which the second switching attenuation amount is applied to the high-frequency signal So and a state in which the second switching attenuation amount is not applied to the high-frequency signal So and a state in which it is not applied to the high-frequency signal So.

[0104] The second variable attenuator 64B, like the first variable attenuator 64A, is a high-frequency attenuation circuit in which the attenuation amount can be continuously changed. The second variable attenuator 64B is equipped with control terminals. The control terminals of the second variable attenuator 64B are connected to the output terminals of the control voltage generation unit 66b and the control terminals of the first variable attenuator 64A.

[0105] This second variable attenuator 64B applies a second variable attenuation to the high-frequency signal So based on the control voltage Vm input from the control voltage generation unit 66b and outputs the result. The second variable attenuation, like the first variable attenuation, is an attenuation that can take on a continuous value.

[0106] The third switching attenuator 65C is a high-frequency attenuation circuit that switches between having attenuation or not. The third switching attenuator 65C is equipped with a control terminal. The control terminal of the third switching attenuator 65C is connected to the first output terminal of the switching control unit 67, the control terminal of the first switching attenuator 65A, and the first correction terminal of the control voltage generation unit 66b.

[0107] In this third switching attenuator 65C, the presence or absence of an attenuation amount (third switching attenuation amount) applied to the high-frequency signal So is set based on the first switching signal Vc1 input from the switching control unit 67. That is, the third switching attenuator 65C switches based on the first switching signal Vc1 between a state in which the third switching attenuation amount is applied to the high-frequency signal So and output, and a state in which the third switching attenuation amount is not applied to the high-frequency signal So and output.

[0108] The fourth switching attenuator 65D is a high-frequency attenuation circuit that switches between having attenuation or not. The fourth switching attenuator 65D is equipped with a control terminal. The control terminal of the fourth switching attenuator 65D is connected to the second output terminal of the switching control unit 67, the control terminal of the second switching attenuator 65B, and the second correction terminal of the control voltage generation unit 66b.

[0109] In this fourth switching attenuator 65D, the presence or absence of an attenuation amount (fourth switching attenuation amount) applied to the high-frequency signal So is set based on the second switching signal Vc2 input from the switching control unit 67. That is, the fourth switching attenuator 65D switches based on the second switching signal Vc2 between a state in which the fourth switching attenuation amount is applied to the high-frequency signal So and a state in which the fourth switching attenuation amount is not applied to the high-frequency signal So and a state in which it is not applied to the high-frequency signal So.

[0110] In this embodiment, the variable attenuators 64A, 64B and the switching attenuators 65A to 65D differ in whether the attenuation amount is changed continuously or discretely (with or without), so either the same circuit configuration or different circuit configurations may be adopted.

[0111] Figure 6 shows the control signal V ｃｔｒｌ The diagram shows an example of a circuit configuration for variable attenuators 64A, 64B and switching attenuators 65A to 65D that adjust the attenuation amount continuously or discretely (with or without) based on the given parameters. Specifically, Figure 6 is a circuit diagram showing variable attenuators 64A, 64B and switching attenuators 65A to 65D according to the first embodiment of the present invention. However, the configuration of the variable attenuators 64A, 64B and switching attenuators 65A to 65D is not limited to the configuration shown in Figure 6 and can be changed as appropriate.

[0112] The variable attenuators 64A, 64B and the switching attenuators 65A to 65D shown in Figure 6 are located at terminal RF １ and terminal RF ２ The system comprises a transmission line g1 provided between the transmission line g1 and the ground potential (GND). This transistor g2 is provided between the transmission line g1 and the ground potential (GND).

[0113] In other words, this transistor g2 has a drain terminal connected to the transmission line g1, a source terminal connected to ground potential (GND), and a control signal V ｃｔｒｌ It has a gate terminal to which the signal V is input. In such variable attenuators 64A, 64B and switching attenuators 65A to 65D, the control signal V ｃｔｒｌ The variable attenuation or switching attenuation is set by adjusting the resistance value (DS resistance value) between the drain terminal and source terminal of transistor g2.

[0114] As shown in Figure 5, the variable control unit 66 includes a temperature compensation current mirror circuit 66a and a control voltage generation unit 66b, as described above. The variable control unit 66 is a first control signal generation unit that generates a control voltage Vm as a first control signal. The control voltage Vm sets the variable attenuation amount of the variable attenuators 64A and 64B. This variable control unit 66 corrects the variable attenuation amount of the variable attenuators 64A and 64B based on the switching signals Vc1 and Vc2 input to the correction terminal from the switching control unit 67. That is, by correcting the control voltage Vm based on the switching signals Vc1 and Vc2, this variable control unit 66 applies a desired variable attenuation amount to the high-frequency signal So regardless of the operating state of the switching attenuators 65A to 65D.

[0115] The temperature-compensating current mirror circuit 66a is a current generation circuit equipped with a pair of output terminals (a first output terminal and a second output terminal). The first output terminal of this temperature-compensating current mirror circuit 66a is connected to the first input terminal of the control voltage generation unit 66b, and the second output terminal is connected to the second input terminal of the control voltage generation unit 66b.

[0116] The temperature compensation current mirror circuit 66a generates a first temperature compensation current I1 and a second temperature compensation current I2 as output currents. The first temperature compensation current I1 and the second temperature compensation current I2 suppress fluctuations in the variable attenuation amount of the variable attenuators 64A and 64B based on fluctuations in ambient temperature T. That is, the temperature compensation current mirror circuit 66a generates a first temperature compensation current I1 whose current value decreases as the ambient temperature T rises, and a second temperature compensation current I2 whose current value remains constant even when the ambient temperature T fluctuates. The temperature compensation current mirror circuit 66a outputs the generated first temperature compensation current I1 and second temperature compensation current I2 to the control voltage generation unit 66b.

[0117] In other words, the first temperature compensation current I1 is a current with a negative slope (negative gradient) with respect to changes in ambient temperature T. In contrast, the second temperature compensation current I2 has the characteristic that its current value does not change even when the ambient temperature T changes. The second temperature compensation current I2 may, if necessary, be a current with a positive slope (positive gradient) with respect to changes in ambient temperature T.

[0118] Such a temperature-compensating current mirror circuit 66a has a circuit configuration as shown in Figure 7, for example. That is, Figure 7 is a circuit diagram showing a temperature-compensating current mirror circuit 66a. However, the configuration of the temperature-compensating current mirror circuit 66a is not limited to the configuration in Figure 7 and can be changed as appropriate.

[0119] Figure 7 shows a circuit configuration in which a first temperature compensation current I1 or a second temperature compensation current I2 is output to the control voltage generation unit 66b. Although a detailed explanation is omitted, the temperature compensation current mirror circuit 66a may have a circuit configuration that allows the first temperature compensation current I1 or the second temperature compensation current I2 to flow in from the control voltage generation unit 66b.

[0120] The temperature compensation current mirror circuit 66a includes a pair of current mirror circuits 68 and 69 corresponding to a first temperature compensation current I1 and a second temperature compensation current I2. The pair of current mirror circuits 68 and 69 have, for example, the circuit configuration shown in Figure 7. In the case of the circuit configuration shown in Figure 7, the first current mirror circuit 68 generates the first temperature compensation current I1 and outputs it to the first input terminal of the control voltage generation unit 66b. The second current mirror circuit 69 generates the second temperature compensation current I2 and outputs it to the second input terminal of the control voltage generation unit 66b.

[0121] The first current mirror circuit 68 comprises a first reference terminal 68a, a pair of transistors 68b and 68c, a pair of resistors 68d and 68e, and a first output terminal 68f. The first current mirror circuit 68 also has a first mirror ratio set by the pair of resistors 68d and 68e.

[0122] Here, in Figure 7, the first reference current I ｒｅｆ１ The first reference current source that outputs the current is omitted for convenience. That is, the first current mirror circuit 68 includes the first reference terminal 68a, a pair of transistors 68b and 68c, a pair of resistors 68d and 68e, and the first output terminal 68f shown in Figure 7, in addition to the first reference current source.

[0123] The first reference terminal 68a is connected to the drain and gate terminals of the first transistor 68b and the gate terminal of the second transistor 68c, as well as to a first reference current source (not shown). The first reference terminal 68a receives a first reference current I from the first reference current source. ｒｅｆ１ The following is entered.

[0124] The first transistor 68b is a P-channel MOS field-effect transistor, as shown in the figure. The drain terminal of the first transistor 68b is connected to its own gate terminal, the gate terminal of the second transistor 68c, and the first reference terminal 68a. The source terminal of the first transistor 68b is connected to one end of the first resistor 68d.

[0125] Furthermore, the gate terminal of the first transistor 68b is connected to its own drain terminal, the gate terminal of the second transistor 68c, and the first reference terminal 68a. That is, the first transistor 68b is provided in a diode-connected state in which its own drain terminal and gate terminal are mutually connected. Such a first transistor 68b operates in the active region by the first reference current I ｒｅｆ１ and the source current is set to a current value substantially equal to the first reference current I ｒｅｆ１ .

[0126] The drain terminal of the second transistor 68c is connected to the first output terminal 68f. The source terminal of the second transistor 68c is connected to one end of the second resistor 68e. Also, the gate terminal of the second transistor 68c is connected to the first reference current source via the gate terminal and drain terminal of the first transistor 68b and the first reference terminal 68a. Such a second transistor 68c operates in the active region by the first reference current I ｒｅｆ１ and the source current is set to a current value substantially equal to the first reference current I ｒｅｆ１ .

[0127] The first resistor 68d is a two-terminal element having a first resistance value R1(T) that depends on the ambient temperature T. This first resistance value R1 has a temperature characteristic in which the resistance value decreases as the ambient temperature T rises, that is, a negative slope (negative gradient). One end of the first resistor 68d is connected to the source terminal of the first transistor 68b, and the other end of the first resistor 68d is connected to the DC power supply Vcc. When the first transistor 68b operates in the active region based on the first reference current I ｒｅｆ１ , a first voltage drop corresponding to the first reference current I ｒｅｆ１ occurs in the first resistor 68d.

[0128] The second resistor 68e is a two-terminal element having a second resistance value R2(T) that depends on the ambient temperature T. This second resistance value R2 has a temperature characteristic in which the resistance value increases with increasing ambient temperature T, i.e., a positive slope (positive gradient). One end of the second resistor 68e is connected to the source terminal of the second transistor 68c, and the other end of the second resistor 68e is connected to the DC power supply Vcc. In other words, the first current mirror circuit 68 is a circuit in which the first resistor 68d and the second resistor 68e, which have different temperature characteristic slopes, are connected to the input and output sides.

[0129] 1st reference current I ｒｅｆ１ Based on this, the second transistor 68c operates in the active region, and the second resistor 68e receives the first reference current I ｒｅｆ１ A first Miller current (i.e., a first temperature compensation current I1) corresponding to the first Miller ratio is then supplied. In addition, a first voltage drop corresponding to the first Miller current (first temperature compensation current I1) is generated across the second resistor 68e.

[0130] The first output terminal 68f is the first output terminal of the first current mirror circuit 68. As shown in the figure, the first output terminal 68f is connected to the drain terminal of the second transistor 68c inside the first current mirror circuit 68 and is connected to the first input terminal of the control voltage generation unit 66b outside the first current mirror circuit 68.

[0131] Here, the drain current of the second transistor 68c is the first reference current I ｒｅｆ１ and the first mirror current, which is set according to the first mirror ratio. That is, the first output terminal 68f outputs the first mirror current to the control voltage generation unit 66b as the first temperature compensation current I1 of the first current mirror circuit 68.

[0132] In such a first current mirror circuit 68, the gate-source voltage V of the first transistor 68b ｇｓ１ (I ｒｅｆ１ ) and the gate-source voltage V of the second transistor 68c ｇｓ２ Using (I1), the following equation (1) holds: V ｇｓ１ (I ｒｅｆ１ ) + Iｒｅｆ１ R1(T) = V ｇｓ２ (I1)+I1・R2(T)…(1)

[0133] Also, the gate-source voltage V of the first transistor 68b ｇｓ１ (I ｒｅｆ１ ) and the gate-source voltage V of the second transistor 68c ｇｓ２ Assuming that (I1) is equal to (I1), the following equation (2) holds: I1 / I ｒｅｆ１ =R1(T) / R2(T)...(2)

[0134] The second resistance value R2(T) has a positive slope with respect to the ambient temperature T. The first resistance value R1(T) has a negative slope with respect to the ambient temperature T. Furthermore, the first reference current I ｒｅｆ１ The current does not have a gradient with respect to the ambient temperature T. Due to these facts, the first temperature compensation current I1 becomes smaller as the ambient temperature T increases. In other words, the first temperature compensation current I1 has a negative gradient with respect to the change in ambient temperature T.

[0135] Furthermore, in the case of the circuit configuration shown in Figure 7, the second current mirror circuit 69 includes a second reference terminal 69a, a pair of transistors 69b and 69c, a pair of resistors 69d and 69e, and a second output terminal 69f. The second current mirror circuit 69 also has a second mirror ratio set by the pair of resistors 69d and 69e.

[0136] Note that in Figure 7, the second reference current I ｒｅｆ２ The second reference current source that outputs the current is omitted for convenience. That is, the second current mirror circuit 69 includes a second reference terminal 69a, a pair of transistors 69b and 69c, a pair of resistors 69d and 69e, and a second output terminal 69f as shown in Figure 7, in addition to a second reference current source.

[0137] The second reference terminal 69a is connected to the drain and gate terminals of the third transistor 69b and the gate terminal of the fourth transistor 69c, as well as to a second reference current source (not shown). The second reference current I is supplied to the second reference terminal 69a from the second reference current source. ｒｅｆ２ The following is entered.

[0138] The third transistor 69b is a P-channel MOS field-effect transistor, as shown in the figure. The drain terminal of the third transistor 69b is connected to its own gate terminal, the gate terminal of the fourth transistor 69c, and the second reference terminal 69a. The source terminal of the third transistor 69b is connected to one end of the third resistor 69d.

[0139] Furthermore, the gate terminal of the third transistor 69b is connected to its own drain terminal, the gate terminal of the fourth transistor 69c, and the second reference terminal 69a. In other words, the third transistor 69b is provided in a diode connection state in which its own drain terminal and gate terminal are interconnected. This third transistor 69b is connected to the second reference current I ｒｅｆ２ It operates in the active region, and the source current is the second reference current I ｒｅｆ２ The current value is set to approximately equal to [the specified value].

[0140] The drain terminal of the fourth transistor 69c is connected to the second output terminal 69f. The source terminal of the fourth transistor 69c is connected to one end of the fourth resistor 69e. The gate terminal of the fourth transistor 69c is connected to the second reference current source via the gate and drain terminals of the third transistor 69b and the second reference terminal 69a. This fourth transistor 69c is connected to the second reference current I ｒｅｆ２ It operates in the active region, and the source current is the second reference current I ｒｅｆ２ The current value is set to approximately equal to [the specified value].

[0141] The third resistor 69d is a two-terminal element having a third resistance value R3 that is independent of the ambient temperature T. This third resistance value R3 has a temperature characteristic in which its resistance value does not change with increasing ambient temperature T. One end of the third resistor 69d is connected to the source terminal of the third transistor 69b, and the other end of the third resistor 69d is connected to the DC power supply Vcc. Second reference current I ｒｅｆ２ Based on this, the third transistor 69b operates in the active region, and the third resistor 69d receives the second reference current I ｒｅｆ２ A third voltage drop occurs accordingly.

[0142] The fourth resistor 69e is a two-terminal element having a fourth resistance value R4 that is independent of the ambient temperature T. This fourth resistance value R4 has a temperature characteristic in which its resistance value does not change with increasing ambient temperature T. One end of the fourth resistor 69e is connected to the source terminal of the fourth transistor 69c, and the other end of the fourth resistor 69e is connected to the DC power supply Vcc.

[0143] Second reference current I ｒｅｆ２ Based on this, the fourth transistor 69c operates in the active region, and the fourth resistor 69e receives the second reference current I ｒｅｆ２ A second Miller current (i.e., a second temperature compensation current I2) corresponding to the second Miller ratio is also supplied. Furthermore, a fourth voltage drop corresponding to the second Miller current (second temperature compensation current I2) is generated across the fourth resistor 69e.

[0144] The second output terminal 69f is the second output terminal of the second current mirror circuit 69. As shown in the figure, the second output terminal 69f is connected to the drain terminal of the fourth transistor 69c inside the second current mirror circuit 69 and is connected to the second input terminal of the control voltage generation unit 66b outside the second current mirror circuit 69.

[0145] Here, the drain current of the fourth transistor 69c is the second reference current I ｒｅｆ２ and the second mirror current, which is set according to the second mirror ratio. That is, the second output terminal 69f outputs the second mirror current to the control voltage generation unit 66b as the second temperature compensation current I2 of the second current mirror circuit 69.

[0146] In this second current mirror circuit 69, the gate-source voltage V of the third transistor 69b ｇｓ３ (I ｒｅｆ２ ) and the gate-source voltage V of the fourth transistor 69c ｇｓ４ Using (I2), the following equation (3) holds: V ｇｓ３ (I ｒｅｆ２ ) + I ｒｅｆ２ R3(T) = V ｇｓ４ (I2)+I2・R4(T)…(3)

[0147] Also, the gate-source voltage V of the third transistor 69b ｇｓ３ (I ｒｅｆ２ ) and the gate-source voltage V of the fourth transistor 69c ｇｓ４ Assuming that (I2) is equal to (I2), the following equation (4) holds: I2 / I ｒｅｆ２ =R3(T) / R4(T)...(4)

[0148] The third resistance value R3(T) and the fourth resistance value R4(T) do not have a gradient with respect to the ambient temperature T. Also, the second reference current I ｒｅｆ２ The current does not have a gradient with respect to the ambient temperature T. Due to these facts, the second temperature compensation current I2 remains constant even when the ambient temperature T changes. In other words, the second temperature compensation current I2 does not have a gradient with respect to changes in ambient temperature T.

[0149] The control voltage generation unit 66b generates a control voltage Vm based on the first temperature compensation current I1 and the second temperature compensation current I2 input from the temperature compensation current mirror circuit 66a, and the switching signals Vc1 and Vc2 input from the switching control unit 67.

[0150] In addition to the first input terminal, second input terminal, and output terminal, the control voltage generation unit 66b is equipped with a first correction terminal and a second correction terminal.

[0151] In the control voltage generation unit 66b, the first input terminal is connected to the first output terminal of the temperature compensation current mirror circuit 66a, and the second input terminal is connected to the second output terminal of the temperature compensation current mirror circuit 66a. Furthermore, the output terminals of the control voltage generation unit 66b are connected to the control terminals of the first variable attenuator 64A and the control terminals of the second variable attenuator 64B.

[0152] The first correction terminal in the control voltage generation unit 66b is connected to the first output terminal and the control terminal of the first switching attenuator 65A and the control terminal of the third switching attenuator 65C in the switching control unit 67. Furthermore, the second correction terminal in the control voltage generation unit 66b is connected to the second output terminal and the control terminal of the second switching attenuator 65B and the control terminal of the fourth switching attenuator 65D in the switching control unit 67.

[0153] The control voltage generation unit 66b generates a control voltage Vm based on the first temperature compensation current I1 and the second temperature compensation current I2 input from the temperature compensation current mirror circuit 66a, and the first switching signal Vc1 and the second switching signal Vc2 input from the switching control unit 67.

[0154] This control voltage generation unit 66b converts the first temperature compensation current I1 input from the temperature compensation current mirror circuit 66a into a first temperature compensation voltage V1 using a first current-voltage conversion circuit (not shown) and inputs it to the positive-phase input terminal of the instrumentation amplifier (not shown). The control voltage generation unit 66b also converts the second temperature compensation current I2 input from the temperature compensation current mirror circuit 66a into a second temperature compensation voltage V2 using a second current-voltage conversion circuit (not shown) and inputs it to the negative-phase input terminal of the instrumentation amplifier.

[0155] The control voltage generation unit 66b generates a control voltage Vm by differentially amplifying the first temperature compensation voltage V1 and the second temperature compensation voltage V2 using an instrumentation amplifier. In generating this control voltage Vm, the instrumentation amplifier adjusts the ratio of the first temperature compensation voltage V1 and the second temperature compensation voltage V2 based on switching signals Vc1 and Vc2, and also receives a reference voltage V from a reference voltage generation circuit (not shown). ｒｅｆ The offset voltage is adjusted by this. The reference voltage generation circuit generates a reference voltage V corresponding to the switching signals Vc1 and Vc2 input to the correction terminal. ｒｅｆ It generates a signal and outputs it to the reference voltage terminal of the instrumentation amplifier.

[0156] The control voltage generation unit 66b references not only the switching signals Vc1 and Vc2 input from the switching control unit 67, but also the first temperature compensation current I1 and the second temperature compensation current I2 input from the temperature compensation current mirror circuit 66a. As a result, the control voltage generation unit 66b generates a control voltage Vm that suppresses fluctuations in the variable attenuation amount of the variable attenuators 64A and 64B based on the operating state of the switching attenuators 65A to 65D, and also suppresses fluctuations in the variable attenuation amount of the variable attenuators 64A and 64B based on temperature fluctuations.

[0157] In other words, the control voltage generation unit 66b refers to the switching signals Vc1 and Vc2 when generating the control voltage Vm. As a result, the control voltage generation unit 66b generates a control voltage Vm that applies a desired variable attenuation amount to the high-frequency signal So, regardless of the operating state of the switching attenuators 65A to 65D, when the variable attenuators 64A and 64B are operating.

[0158] Furthermore, the control voltage generation unit 66b refers to the first temperature compensation current I1 and the second temperature compensation current I2 when generating the control voltage Vm. As a result, the control voltage generation unit 66b generates the control voltage Vm in a manner that suppresses fluctuations in the variable attenuation amount of the variable attenuators 64A and 64B based on temperature fluctuations.

[0159] The switching control unit 67 is equipped with a first output terminal and a second output terminal. In the switching control unit 67, the first output terminal is connected to the control terminal of the first switching attenuator 65A, the control terminal of the third switching attenuator 65C, and the first correction terminal in the control voltage generation unit 66b. In addition, in the switching control unit 67, the second output terminal is connected to the control terminal of the second switching attenuator 65B, the control terminal of the fourth switching attenuator 65D, and the second correction terminal in the control voltage generation unit 66b. The switching control unit 67 is a second control signal generation unit that generates switching signals Vc1 and Vc2 as second control signals to set the switching attenuation amounts of the switching attenuators 65A to 65D.

[0160] The switching control unit 67 generates a first switching signal Vc1 and outputs it to the first switching attenuator 65A, the third switching attenuator 65C, and the control voltage generation unit 66b. The switching control unit 67 also generates a second switching signal Vc2 and outputs it to the second switching attenuator 65B, the fourth switching attenuator 65D, and the control voltage generation unit 66b. The switching control unit 67 may be controlled by the control circuit 40. Alternatively, the control circuit 40 may function as the switching control unit 67.

[0161] The first switching signal Vc1 is a binary signal that switches between the presence or absence of the first switching attenuation amount in the first switching attenuator 65A and the presence or absence of the third switching attenuation amount in the third switching attenuator 65C. The second switching signal Vc2 is a binary signal that switches between the presence or absence of the second switching attenuation amount in the second switching attenuator 65B and the presence or absence of the fourth switching attenuation amount in the fourth switching attenuator 65D.

[0162] In this temperature compensation circuit 60, the operating state of the first switching attenuator 65A and the third switching attenuator 65C (i.e., the presence or absence of the first switching attenuation amount and the third switching attenuation amount (ON / OFF)) is switched by a first switching signal Vc1 generated by the switching control unit 67. In addition, in this temperature compensation circuit 60, the operating state of the second switching attenuator 65B and the fourth switching attenuator 65D (i.e., the presence or absence of the second switching attenuation amount and the fourth switching attenuation amount (ON / OFF)) is switched by a second switching signal Vc2 generated by the switching control unit 67.

[0163] The control voltage generation unit 66b of the variable control unit 66 takes in the first switching signal Vc1 and the second switching signal Vc2 and applies correction processing to the control voltage Vm according to the operating state of the first to fourth switching attenuators 65A to 65D. As a result, the control voltage Vm applies a desired amount of attenuation to the high-frequency signal, regardless of the operating state of the first to fourth switching attenuators 65A to 65D.

[0164] Figures 8A and 8B are characteristic diagrams showing the operation of the temperature compensation circuit 60 according to the first embodiment. That is, Figures 8A and 8B are graphs showing an example of the temperature characteristics of the temperature compensation circuit 60 according to the first embodiment of the present invention.

[0165] Figure 8A shows the temperature characteristics of the control voltage Vm in response to the ON / OFF states of the first switching signal Vc1 and the second switching signal Vc2. Figure 8B shows the attenuation of the temperature compensation circuit 60 (i.e., the transmission loss caused in the RF signal) in response to the ON / OFF states of the first switching signal Vc1 and the second switching signal Vc2. It is shown that the attenuation of the temperature compensation circuit 60 is greater at lower temperatures, and that the offset of the attenuation can be adjusted by switching control of the first to fourth switching attenuators 65A to 65D.

[0166] <Function> Next, the operation of the beamformer integrated circuit 1 and the phased array antenna module 100 configured as described above will be explained.

[0167] Conventionally, phased array antenna modules and beamformer integrated circuits, such as those disclosed in Non-Patent Document 1, are known. For example, in conventional beamformer integrated circuits, such as those disclosed in Non-Patent Document 1, a problem has been the large variation in gain due to temperature fluctuations. Specifically, in conventional beamformer integrated circuits, the gain is higher at lower temperatures and lower at higher temperatures.

[0168] In conventional beamformer integrated circuits, methods such as optimizing the gain setting of the amplifier included in the beamformer integrated circuit were employed to keep the beamformer integrated circuit's gain constant with respect to temperature fluctuations. However, this method had problems such as performance degradation and increased costs of the beamformer integrated circuit due to the complexity of the settings and the addition of temperature control functions.

[0169] To solve this problem, the beamformer integrated circuit 1 and phased array antenna module 100 according to this embodiment are provided with temperature compensation circuits 12 and 31 in the connection circuit 4 connecting the first input / output port 1a and the second input / output port 1b, which reduce the transmission loss in the RF signal as the temperature increases. The temperature characteristics of the temperature compensation circuits 12 and 31, which have high transmission loss at low temperatures and low transmission loss at high temperatures, act to cancel out the temperature characteristics of conventional beamformer integrated circuits, which have high gain at low temperatures and low gain at high temperatures. Therefore, by providing temperature compensation circuits 12 and 31 in the connection circuit 4, it is possible to realize a beamformer integrated circuit 1 and phased array antenna module 100 that can easily suppress gain fluctuations in response to temperature fluctuations.

[0170] <Summary> As described above, the beamformer integrated circuit 1 according to this embodiment includes a plurality of first input / output ports 1a electrically connected to a plurality of antenna elements 2 so as to correspond one-to-one with a plurality of antenna elements 2, a second input / output port 1b to which RF signals are input and output, and a connection circuit 4 that connects the plurality of first input / output ports 1a and the second input / output port 1b and transmits RF signals between the plurality of first input / output ports 1a and the second input / output port 1b. The connection circuit 4 includes a phase shifter 11 that changes the phase of the RF signal, a plurality of front-end circuits 10 connected to the plurality of first input / output ports 1a so as to correspond one-to-one with a plurality of first input / output ports 1a, at least one amplifier (variable gain amplifier 14T, variable gain amplifier 14R, power amplifier 15T, low noise amplifier 15R, power amplifier 33T and low noise amplifier 33R) that amplifies the RF signal, and at least one temperature compensation circuit (first temperature compensation circuit 12 and second temperature compensation circuit 31) which reduces the transmission loss caused to the RF signal as the temperature increases. This configuration provides a beamformer integrated circuit 1 that can easily suppress gain fluctuations in response to temperature fluctuations.

[0171] Furthermore, each of the multiple front-end circuits 10 includes a first temperature compensation circuit 12, which is one of the temperature compensation circuits described above. With this configuration, gain fluctuations in response to temperature fluctuations can be easily suppressed in the front-end circuit 10.

[0172] Furthermore, each of the multiple front-end circuits 10 includes a front-end amplifier (variable gain amplifier 14T, variable gain amplifier 14R, power amplifier 15T, and low-noise amplifier 15R), which is one of the above-mentioned amplifiers. Each of the multiple front-end circuits 10 has a first connection port (port 10b) that is electrically connected to the second input / output port 1b. In each of the multiple front-end circuits 10, the first temperature compensation circuit 12 is positioned between the front-end amplifier and the first connection port. This configuration makes it easier to input and output RF signals with the desired intensity to the antenna element 2.

[0173] Furthermore, each of the multiple front-end circuits 10 includes a first switch circuit 13 positioned between the front-end amplifier and the first connection port, which switches the path through which the RF signal is transmitted in the front-end circuit 10. In each of the multiple front-end circuits 10, the first temperature compensation circuit 12 is positioned between the first switch circuit 13 and the first connection port, and is also positioned adjacent to the first switch circuit 13. As a result of diligent research by the inventors of the present invention, it was found that by arranging the first temperature compensation circuit 12 and the first switch circuit 13 in this positional relationship, the front-end circuit 10 can be miniaturized. In other words, by adopting this positional relationship, the miniaturization of the front-end circuit 10 can be achieved.

[0174] Furthermore, the connection circuit 4 includes a combined amplifier (power amplifier 33T and low-noise amplifier 33R), which is one of the above-mentioned amplifiers, and has an amplification circuit 30 that is electrically connected to two or more of the multiple front-end circuits 10, and the amplification circuit 30 includes a second temperature compensation circuit 31, which is one of the above-mentioned temperature compensation circuits. With this configuration, gain fluctuations due to temperature fluctuations can be easily suppressed in the amplification circuit 30.

[0175] Furthermore, the amplification circuit 30 has a second connection port (port 30b) that is electrically connected to the second input / output port 1b, and in the amplification circuit 30, the second temperature compensation circuit 31 is positioned between the group amplifier and the second connection port. This configuration makes it easier to input and output RF signals with the desired strength to the front-end circuit 10 and the antenna element 2.

[0176] Furthermore, the amplification circuit 30 includes a second switch circuit 32 positioned between the combined amplifier (power amplifier 33T and low-noise amplifier 33R) and the second connection port, which switches the path through which the RF signal is transmitted in the amplification circuit 30. In the amplification circuit 30, the second temperature compensation circuit 31 is positioned between the second switch circuit 32 and the second connection port, and is also positioned adjacent to the second switch circuit 32. As a result of diligent research by the inventors of the present invention, it was found that by arranging the second temperature compensation circuit 31 and the second switch circuit 32 in this positional relationship, the amplification circuit 30 can be miniaturized. In other words, by adopting this positional relationship, the amplification circuit 30 can be miniaturized.

[0177] Furthermore, the multiple front-end circuits 10 include multiple first front-end circuits 10A corresponding to antenna elements 2 that transmit and receive a first polarization (e.g., horizontal polarization), and multiple second front-end circuits 10B corresponding to antenna elements 2 that transmit and receive a second polarization (e.g., vertical polarization) orthogonal to the first polarization, with the multiple first front-end circuits 10A and the multiple second front-end circuits 10B arranged alternately. This configuration may allow the beamformer integrated circuit 1 to be suitably mounted on the phased array antenna module 100.

[0178] Furthermore, the phased array antenna module 100 according to this embodiment comprises the beamformer integrated circuit 1 described above, and a plurality of antenna elements 2 connected to a plurality of first input / output ports 1a so as to correspond one-to-one with a plurality of first input / output ports 1a. This configuration makes it possible to provide a phased array antenna module 100 that can easily suppress gain fluctuations due to temperature fluctuations.

[0179] (Second Embodiment) Next, a second embodiment will be described, but the basic configuration is the same as that of the first embodiment. For this reason, the same reference numerals are used for similar components, and their descriptions are omitted; only the differences will be described.

[0180] Figure 9 is a circuit diagram showing a beamformer integrated circuit 1' according to a second embodiment of the present invention.

[0181] The beamformer integrated circuit 1' according to this embodiment differs from the beamformer integrated circuit 1 according to the first embodiment (see Figure 2) in the arrangement of the first input / output port 1aA for first polarization and the first input / output port 1aB for second polarization, the arrangement of the first front-end circuit 10A and the second front-end circuit 10B, and the shape of the distributor / combiner 20.

[0182] In this embodiment, ports 1a-1 to 1a-8 function as first polarization input / output ports 1aA, and ports 1a-9 to 1a-16 function as second polarization first input / output ports 1aB. In other words, at the upper and lower edges of the beamformer integrated circuit 1, a plurality of (four in the illustrated example) first polarization first input / output ports 1aA are arranged adjacent to each other in the first direction X, and a plurality of (four in the illustrated example) second polarization first input / output ports 1aB are arranged adjacent to each other in the first direction X.

[0183] Similarly, in this embodiment, front-end circuits 10-1 to 10-8 function as first front-end circuits 10A, and front-end circuits 10-9 to 10-16 function as second front-end circuits 10B. In other words, at the upper and lower edges of the beamformer integrated circuit 1, a plurality of (four in the illustrated example) first front-end circuits 10A are arranged adjacent to each other in the first direction X, and a plurality of (four in the illustrated example) second front-end circuits 10B are arranged adjacent to each other in the first direction X.

[0184] Furthermore, the first distributor / combiner 20A extends in the first direction X from the location where front-end circuits 10-1 and 10-5 are located to the location where front-end circuits 10-4 and 10-8 are located. The second distributor / combiner 20B extends in the first direction X from the location where front-end circuits 10-9 and 10-13 are located to the location where front-end circuits 10-12 and 10-16 are located.

[0185] Furthermore, all first front-end circuits 10A are positioned to the left of the control circuit 40, and all second front-end circuits 10B are positioned to the right of the control circuit 40. As a result, the first distributor / combiner 20A is positioned to the left of the control circuit 40, and the second distributor / combiner 20B is positioned to the right of the control circuit 40. In other words, each distributor / combiner 20A and 20B is positioned so as not to cross the control circuit 40 in the first direction X.

[0186] In the beamformer integrated circuit 1' according to this embodiment, as in the first embodiment, temperature compensation circuits 12 and 31 are provided in circuits 10 and 30, which reduce the transmission loss in the RF signal as the temperature increases (see Figures 3 and 4). This configuration makes it possible to realize a beamformer integrated circuit 1' that can easily suppress gain fluctuations in response to temperature fluctuations.

[0187] Furthermore, in this embodiment, the multiple first front-end circuits 10A are arranged adjacent to each other, and the multiple second front-end circuits 10B are arranged adjacent to each other. This configuration makes it easier to simplify and compact the circuit configuration of the connection circuit 4.

[0188] (Variations) The technical scope of the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the present invention.

[0189] For example, in the above embodiment, the case in which the beamformer integrated circuits 1 and 1' are provided with eight (eight channels) first front-end circuits 10A and eight second front-end circuits 10B is described, but the number of first front-end circuits 10A and eight second front-end circuits 10B (number of channels) can be changed as appropriate. In accordance with the change in the number of first front-end circuits 10A and eight second front-end circuits 10B, the number of first polarization first input / output ports 1aA and eight second polarization first input / output ports 1aB, the number of ports 20a in each distributor / combiner 20A and 20B, and the number of antenna elements 2 connected to the beamformer integrated circuits 1 and 1' can also be changed. For example, the beamformer integrated circuits 1 and 1' may be provided with four (four channels) first front-end circuits 10A and eight second front-end circuits 10B. Also, the number of beamformer integrated circuits 1 and the number of antenna elements 2 provided in the phased array antenna module 100 can be changed as appropriate.

[0190] Furthermore, without departing from the spirit of the present invention, the components in the above-described embodiments may be replaced with well-known components as appropriate, and the above-described embodiments and modifications may be combined as appropriate.

[0191] 100...Phased array antenna module 1, 1'...Beamformer integrated circuit 1a...First input / output port 1b...Second input / output port 2...Antenna element 4...Connection circuit 10...Front-end circuit 10A...First front-end circuit 10B...Second front-end circuit 10b...Port (first connection port) 11...Phase shifter 12...First temperature compensation circuit 13...First switch circuit 14T...Variable gain amplifier (amplifier, front-end amplifier) ​​14R...Variable gain amplifier (amplifier, front-end amplifier) ​​15T...Power amplifier (amplifier, front-end amplifier) ​​15R...Low-noise amplifier (amplifier, front-end amplifier) ​​30...Amplification circuit 30b...Port (second connection port) 31...Second temperature compensation circuit (temperature compensation circuit) 32...Second switch circuit 33T...Power amplifier (amplifier, group amplifier) ​​33R...Low-noise amplifier (amplifier, group amplifier) ​​60...Temperature compensation circuit

Claims

1. A beamformer integrated circuit comprising: a plurality of first input / output ports electrically connected to a plurality of antenna elements in a one-to-one correspondence with the plurality of antenna elements; a second input / output port to which RF signals are input and output; a connection circuit connecting the plurality of first input / output ports and the second input / output port, and transmitting the RF signals between the plurality of first input / output ports and the second input / output port, wherein the connection circuit includes a plurality of front-end circuits each including a phase shifter for changing the phase of the RF signals and connected to the plurality of first input / output ports in a one-to-one correspondence with the plurality of first input / output ports; at least one amplifier for amplifying the RF signals; and at least one temperature compensation circuit that reduces the transmission loss caused to the RF signals as the temperature increases.

2. The beamformer integrated circuit according to claim 1, wherein each of the plurality of front-end circuits includes a first temperature compensation circuit which is one of the temperature compensation circuits.

3. The beamformer integrated circuit according to claim 2, wherein each of the plurality of front-end circuits includes a front-end amplifier which is one of the amplifiers, each of the plurality of front-end circuits has a first connection port which is electrically connected to the second input / output port, and in each of the plurality of front-end circuits, the first temperature compensation circuit is disposed between the front-end amplifier and the first connection port.

4. The beamformer integrated circuit according to claim 3, wherein each of the plurality of front-end circuits includes a first switch circuit located between the front-end amplifier and the first connection port for switching the path through which the RF signal is transmitted in the front-end circuit, and in each of the plurality of front-end circuits, the first temperature compensation circuit is located between the first switch circuit and the first connection port and adjacent to the first switch circuit.

5. The beamformer integrated circuit according to any one of claims 1 to 4, wherein the connection circuit includes a group amplifier which is one of the amplifiers and has an amplification circuit which is electrically connected to two or more of the plurality of front-end circuits, and the amplification circuit includes a second temperature compensation circuit which is one of the temperature compensation circuits.

6. The beamformer integrated circuit according to claim 5, wherein the amplification circuit has a second connection port electrically connected to the second input / output port, and in the amplification circuit, the second temperature compensation circuit is arranged between the group amplifier and the second connection port.

7. The beamformer integrated circuit according to claim 6, wherein the amplification circuit includes a second switch circuit located between the collective amplifier and the second connection port for switching the path through which the RF signal is transmitted in the amplification circuit, and in the amplification circuit, the second temperature compensation circuit is located between the second switch circuit and the second connection port and adjacent to the second switch circuit.

8. The beamformer integrated circuit according to any one of claims 1 to 7, wherein the plurality of front-end circuits include a plurality of first front-end circuits corresponding to the antenna elements that transmit and receive a first polarization, and a plurality of second front-end circuits corresponding to the antenna elements that transmit and receive a second polarization orthogonal to the first polarization, and the plurality of first front-end circuits and the plurality of second front-end circuits are arranged alternately.

9. The beamformer integrated circuit according to any one of claims 1 to 7, wherein the plurality of front-end circuits include a plurality of first front-end circuits corresponding to the antenna elements that transmit and receive a first polarization, and a plurality of second front-end circuits corresponding to the antenna elements that transmit and receive a second polarization orthogonal to the first polarization, wherein the plurality of first front-end circuits are arranged adjacent to each other, and the plurality of second front-end circuits are arranged adjacent to each other.

10. A phased array antenna module comprising: a beamformer integrated circuit according to any one of claims 1 to 9; and a plurality of antenna elements connected to the plurality of first input / output ports so as to correspond one-to-one with the plurality of first input / output ports.

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