Multi-dimensionally encodable neuron device based on two-dimensional materials

Abstract

A sensing device suitable for use in a neural network is disclosed. The sensing device includes a source terminal and a drain terminal, with a channel disposed therebetween. The channel is constructed from a two dimensional material. Two different voltages are applied to the channel. The choice of voltages determines the gain of the sensing device. The drain terminals of the various sensing devices may be connected such that the current output from the various sensing devices may be aggregated. Additionally, the sensing device includes a charge trap layer to capture current generated by the device. This charge trap layer delays the current from the channel, allowing the stimulus to be sampled multiple times during a sampling period.

Description

[0001] MULT I -DIMENSIONALLY ENCODABLE NEURON DEVICE BASED ON TWO- DIMENSIONAL MATERIALS

[0002] This application claims priority of U. S. Provisional Patent Application Serial No. 63 / 735, 227, filed December 17, 2024, the disclosure of which is incorporated herein by reference in its entirety.

[0003] Field

[0004] This disclosure describes circuits and systems with optically-controlled sensing devices incorporating two-dimensional materials, including integrated circuits incorporating these devices configured to perform pre-processing of sensor outputs.

[0005] Background

[0006] Traditional sensor processing systems, such as that shown in FIG. 1A, include a sensor array including a plurality of sensing devices that produce electrical signals indicative of a stimulus applied to the sensing devices. The resulting electrical signals are typically analog signals that may be digitized using analog-to-digital conversion. The digitalized signals may then be saved in a memory. These saved digitized signals may then be processed using a processing unit to analyze the stimulus that was applied to the sensor array. The processing unit may be any suitable processor, including a rack-mounted computer, a desktop computer, a laptop computer, a mobile device, or a dedicated or special purpose processor. Examples of existing sensing devices include light sensing devices, sound sensing devices, gas sensing devices, and pressure sensing devices.

[0007] More recently, a concept referred to as in-sensor computing has emerged. In in-sensor computing, some of the processing is performed by the sensor array, as shown in FIG. IB. For example, the outputs from each of the different sensing devices, which may be a voltage or a current, may be processed using analog circuitry to offload some of the processing that is typically performed by the processing unit. This analog processing typically involves summations, where a plurality of voltages or currents are added together to create a pre-processed signal. Typically, there is a temporal aspect to this analog processing. For example, the pre-processed signals are sampled and the sampled values are used by the processing unit to perform further computations.

[0008] However, as neural networks grow larger, there is a need to offload more processing from the processing unit. Therefore, a device and system that allowed pre-processing of sensor outputs would be beneficial.

[0009] Summary

[0010] A sensing device suitable for use in a neural network is disclosed. The sensing device includes a source terminal and a drain terminal, with a channel disposed therebetween. The channel is constructed from a two dimensional material. Two different voltages are applied to the channel. The choice of voltages determines the gain of the sensing device. The drain terminals of the various sensing devices may be connected such that the current output from the various sensing devices may be aggregated. Additionally, the sensing device includes a charge trap layer to capture current generated by the device. This charge trap layer delays the current from the channel, allowing the stimulus to be sampled multiple times during a sampling period.

[0011] According to one embodiment, a sensor array is disclosed. The sensor array comprises a plurality of sensing devices configured to produce electrical signals in response to a stimulus, each of the plurality of sensing devices comprising a channel comprising a semiconductor material configured to form a p-n junction in response to application of opposite polarity voltages thereto; source and drain terminals coupled to respective ends of the channel; and a plurality of gate terminals configured to bias the semiconductor material with opposite polarity voltages, wherein a first sensing device of the plurality of sensing devices and a second sensing device of the plurality of sensing devices have differently electrostatically doped channels.

[0012] In certain embodiments, the semiconductor material is a two-dimensional semiconductor material. In certain embodiments, the first sensing device and the second sensing device are configured to produce electrical signals having different amplitudes in response to a same stimulus. In certain embodiments, the drain terminal of the first sensing device is coupled to the drain terminal of the second sensing device to aggregate the electrical signals produced by the first sensing device and the second sensing device into an aggregated electrical signal for processing. In certain embodiments, the sensor array comprises a plurality of subarrays; wherein each of the plurality of subarrays comprises a subset of the plurality of sensing devices; wherein each subset of the plurality of sensing devices is configured to receive a respective portion of the stimulus; and wherein differences in electrostatic doping of channels between the subsets are configured to multiply the respective portions of the stimulus by different respective gain values to perform multiplication of the stimulus. In certain embodiments, each of the plurality of sensing devices further comprises a charge trap layer coupled to the semiconductor material and configured to delay transfer of current, generated in response to the stimulus, out of the semiconductor material. In some embodiments, any of the above embodiments recited above may be combined with one or more of the other embodiments.

[0013] According to another embodiment, an in-sensor computing system is disclosed. The computing system comprises any of the sensor arrays described above; and a control circuit configured to apply a series of sampling pulses of the opposite polarity voltages to the plurality of gate terminals to modulate the stimulus into an integrated electrical signal.

[0014] According to another embodiment, a method of operating a sensor array is disclosed, wherein the sensor array comprises a plurality of sensing devices, each comprising a channel comprising a semiconductor material, source and drain terminals coupled to respective ends of the channel, and a plurality of gate terminals. The method comprises applying a stimulus to the plurality of sensing devices such that the plurality of sensing devices generates electrical signals in response to the stimulus; and while applying the stimulus, using the plurality of gate terminals of each of the plurality of sensing devices to bias the semiconductor material with opposite polarity voltages such that a p-n junction is formed in each of the plurality of sensing devices, wherein a first sensing device of the plurality of sensing devices and a second sensing device of the plurality of sensing devices comprise differently doped channels.

[0015] In certain embodiments, the semiconductor material is a two-dimensional semiconductor material. In certain embodiments, the first sensing device and the second sensing device are configured to produce electrical signals having different amplitudes in response to a same stimulus. In certain embodiments, a drain terminal of the first sensing device is coupled to a drain terminal of the second sensing device, and the method further comprises aggregating electrical signals produced by the first sensing device and by the second sensing device into an aggregated electrical signal for processing. In certain embodiments, the sensor array comprises a plurality of subarrays; wherein each of the plurality of subarrays comprises a subset of the plurality of sensing devices; wherein each subset of the plurality of sensing devices receives a respective portion of the stimulus; and wherein differences in electrostatic doping of channels between the subsets multiply the respective portions of the stimulus by different respective gain values to perform multiplication of the stimulus. In certain embodiments, each of the plurality of sensing devices further comprises a charge trap layer coupled to the semiconductor material and the method further comprises, by the charge trap layer, delaying transfer of current, generated in response to the stimulus, out of the semiconductor material. Any of the above embodiments recited above may be combined with one or more of the other embodiments. In certain embodiments, using the plurality of gate terminals to bias the semiconductor material comprises applying a plurality of pulses of the opposite polarity voltages to modulate the stimulus into an integrated electrical signal. In certain embodiments, the method further comprises sampling the stimulus a plurality of times during a sampling period, wherein the stimulus is sampled by biasing the semiconductor material with opposite polarity voltages during a sampling pulse; and wherein a final value of the stimulus is determined based on a current present at an end of the sampling period.

[0016] According to another embodiment, a method of manuf cturing a sensor array is disclosed. The method comprises forming a plurality of sensing devices of the sensor array, the forming comprising, for each of the plurality of sensing devices: using a semiconductor material to form a channel that is configured to form a p-n junction in response to application of opposite polarity voltages thereto; coupling source and drain terminals to respective ends of the channel; coupling a plurality of gate terminals to the channel; and forming a charge trap layer coupled to the semiconductor material to delay transfer of charges out of the semiconductor material.

[0017] In some embodiments, the semiconductor material is a two-dimensional semiconductor material. In some embodiments, the method further comprises forming a gate insulator between the gate terminals and the channel. In certain embodiments, the charge trap layer is formed between the gate insulator and the channel. In certain embodiments, the charge trap layer is disposed on a top surface of the semiconductor material. For any of the above embodiments, the method may further comprise coupling a drain terminal of a first sensing device to a drain terminal of a second sensing device such that electrical signals generated by the first sensing device and by the second sensing device are aggregated to form an aggregated electrical signal.

[0018] Brief Description of the Drawings

[0019] For a better understanding of the present disclosure, reference is made to the accompanying drawings, in which like elements are referenced with like numerals, and in which:

[0020] FIGs. 1A-1B show different sensor processing systems according to the prior art;

[0021] FIGs. 2A-2C show an in-sensor computing system according to one embodiment;

[0022] FIG. 3 shows the p-n junction formed in the 2D material by application of different gate voltages;

[0023] FIG. 4 is a timing diagram showing the current output of the sensing device based on the gate voltages and the applied stimulus;

[0024] FIG. 5 is a timing diagram showing the current output of the sensing device in response to a sampling pulse;

[0025] FIGs. 6A-6B show two embodiments of a sensing device that includes a charge trap layer;

[0026] FIG. 7 is a timing diagram showing the current output of the sensing device having a charge trap layer based on the gate voltages and the applied stimulus;

[0027] FIG. 8 is a timing diagram showing the current output of the sensing device having a charge trap layer in response to a plurality of sampling pulses;

[0028] FIG. 9A-9D show the sensor array used to encode information from three pixels; FIGs. 10A-10C show a process to fabricate the sensing device according to one embodiment; and

[0029] FIGs. 11A-11C show a process to fabricate the sensing device according to a second embodiment.

[0030] Detailed Description

[0031] This disclosure describes an in-sensor computing system that offloads the processing required by the processing unit. A sensor array made up of sensing devices created from two-dimensional (2D) materials is used to receive the stimulus and generate an weighted output for summation with other sensing devices.

[0032] A variation of this in-sensor computing is referred to as multidimensional in-sensor computing, and is shown in FIG. 2C. In this system, in addition to performing summations of the outputs from a plurality of sensing devices, each sensing device may be provided with a weight. The weight is a measure of the responsiveness of the sensing device to the applied stimulus, also referred to as gain. In other words, the gain serves as a multiplicative factor that is applied to the sensing device.

[0033] FIG. 2A shows a representative sensor array comprising three sensing devices that implement multidimensional in-sensor computing, as shown in FIG. 2C. Each sensing device includes a source terminal 110, a drain terminal 120, a gate insulator 130, and two gate terminals 140, 150. A layer of 2D material 160 is disposed above the two gate terminals 140, 150 and between an associated source terminal 110 and drain terminal 120. This layer of 2D material 160 forms a channel.

[0034] The source terminal 110, drain terminal 120 and the two gate terminals 140, 150 may be any metal or electrically conductive material, such as gold, chromium, titanium, graphene, conductive polymers or any other suitable material. The gate insulator 130 may be any insulating dielectric such as silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hexagonal boron nitride (h-BN) and others. In some embodiments, the thickness of the gate insulator 130 may be between 1 and 300 nm, although other thicknesses are also possible. The 2D material 160 may be any semiconducting two-dimensional material that has ambipolar properties, such as graphene, phosphorene (black phosphorus), silicene, germanane, tellurene, certain diselenides (such as WSe2, MoSe2, ReSe2, PtSe2, PbSe2), certain disulf ides ( such as MoS2, WS2, ReS2, SnS2) certain ditellurides (such as MoTe2, WTe2), Mo (Sei-xTex)2, W (Sei-xTex)2, SnSe, SnS, InSe, Cr2S3, Nb2SiTe4, and (BixSbi-x) Te3. In some embodiments, the thickness of the 2D material 160 may be between 0. 8nm and 20 nm, although other ranges are possible.

[0035] The two gate terminals 140, 150 allow two different voltages to be applied to the channel, referred to as Vgland Vg2, respectively. These two different voltages affect the operation of the sensing device 100. Specifically, as shown in FIG. 3, when Vglis positive and Vg2is negative, the 2D material 160 develops an N-type region and a P-type region separated by a p-n junction. This is referred to as electrostatic doping. As shown in FIG. 4, when the 2D material 160 is exposed to a stimulus, a current is produced at the drain terminal 120. In some embodiments, this stimulus is light, and more specifically, may be light with a wavelength of between 500 and 6000 nm. This current may be in the range from a few nA to tens of pA. Note that this drain current is only produced when Vg2is a positive voltage, Vg2is a negative voltage and the 2D material is exposed to light. Note as shown in FIG. 4, when the two gate terminal 140, 150 are configured such that Vgiis a negative voltage and Vg2is a positive voltage, no current is produced, regardless of the light exposure. Further, the choice of voltages for the first gate terminal 140 and the second gate terminal 150 affect the gain of the sensing device. Specifically, a larger difference between Vgland Vg2produces a larger current produced for a given amount of light. Thus, manipulation of Vgland Vg2enables different electrostatic doping of the 2D material 160.

[0036] Returning to FIG. 2A, the output from the three drain terminals 120 may be electrically connected, which serves to add the outputs from these three sensing devices together. An array of 9 sensing devices, arranged as three rows and three columns is shown in FIG. 2B. In some embodiments, the source terminals 110 are all grounded, while the drain terminals 120 are biased to a non-zero voltage, such as between -10V and +10V. If Vgifor each sensing device is positive and Vg2for each sensing device is negative, each sensing device will produce a drain current, which may be added together. Thus, a sampling pulse may be generated during which the Vglof each sensing device is positive and the Vg2of each sensing device is negative. It is only during these sampling pulses that current is produced. This is shown in FIG. 5. Thus, by using sampling pulses, coupled with a common Vgl / Vg2voltage combination for each sensing device, an in-sensor computing system, like that shown in FIG. IB may be produced. The system shown in FIG. 2A may be enhanced by applying different Vgl / Vg2combinations to each sensing device. This results in sensing devices of different electrostatic doping, and thus different weights. This would result in the multi-dimensional insensor computing system shown in FIG. 2C.

[0037] The system described above may be further enhanced through the inclusion of a charge trap layer 170, as shown in FIGs. 6A-6B. The charge trap layer 170 may be disposed on top of the 2D material 160, as shown in FIG. 6A. To do this, in some embodiments, a high energy plasma treatment may be performed on the top surface of the 2D material 160. This may be an oxygen plasma treatment in some embodiments. Alternatively, an ultrathin material may be deposited on the 2D material 160. This ultrathin material may be an evaporated / sputtered / spin-coated oxide, which contains a large number of defects that function as charge traps.

[0038] In another embodiment, the charge trap layer 170 may be disposed between the 2D material 160 and the gate insulator 130, as shown in FIG. 6B. This may be achieved in various ways. In one embodiment, the ultrathin material described above may be deposited on the gate insulator 130, prior to deposition of the 2D material 160. Alternatively, the surface morphology of the gate insulator 130 may be modified to create the charge traps. This may be achieved using a high energy plasma treatment.

[0039] This charge trap layer 170 serves to store charge for short periods of time. In this way, rather than generating a pulse of current during a sampling pulse is applied, an exponentially decaying current waveform is created, as shown in FIG. 7. In other words, the passage of current from the drain terminal 120 is delayed due to the charge trapping. In this embodiment, there is a control circuit that generates a plurality of sampling pulses for each sample period. In some instances, the duration of each sampling pulse may be between 10 ns and 10 ms. The duration of a sample period may be between 100 ns and 100 ms. Further, there may be between 10 and 1000 sampling pulses during each sample period. In this way, the current output at the end of the sample period is proportional to the amount of stimulus present during the sample period. FIG. 8 shows this phenomenon. Note that the amount of current injected during each sampling pulse is added to the already present decaying current. In this way, if multiple sampling pulses are generated during each sample period, the amount of the stimulus present during the sample period may be determined based on the current that is available at the end of the sample period. Note that the number of charge trapping defects in the charge trap layer 170 may determine the decay time and therefore the final current at the end of the sample period. Thus, by varying the thickness or number of defects in the charge trap layer 170, another method of modifying the gain of the sensing device may be achieved.

[0040] FIGs. 9A-9D show a configuration that performs matrix multiplication. FIG. 9A-9B show a set of three vertically aligned pixels and the stimulus each received.

[0041] FIG. 9C shows the sensor array that corresponds to this set of pixels. There are three sensing devices associated with each pixel (arranged as horizontal rows). Further, there are three rows which are associated with different pixels. Each of these sensing devices has a differently configured Vgl / Vg2 combination, resulting in different gains for each sensing device. In this array, the weights in the first row (Wi,2; W2f 2; Wi,3) are defined as 0.5, 0 and 0, respectively although any value may be used. The weights in the second row (W2,i; W2f 2; W2,3) are defined as 0, 1, and 0, while the weights in the third row (W3,2; W3,2; W3,3) are 0, 0, and 0.5. The drain terminals of all of the sensing devices in a column are aggregated. Thus, current Cn = S =i in* St,nr for n=l, 2, 3, wherein S2,nrepresents the stimulus received by the sensing device in the ithrow, nthcolumn. Further, the sensor array includes a bit line (BL) driver which is used to activate one of the rows. This may be done by applying a pulse to the source terminal 110.

[0042] The sensor array also includes a sample line (SL) driver, which is a control circuit used to provide the sampling pulses to the two gate terminals.

[0043] FIG. 9D shows the output from each of the current outputs. Since the middle pixel received continuous light, the sensing devices in the second row produce a current for each sampling pulse. In contrast, since the top and bottom pixel received noise, the sensing devices in those rows produce fewer current pulses. Consequently, at the end of the sample period, Cl and 03 indicate a value of 0, while 02 represents a positive value.

[0044] FIGs. 10A-10C show the fabrication process of a sensing device according to one embodiment. As shown in FIG. 10A, gate terminals 140, 150 are applied to the bottom surface of a gate insulator 130, using methods known in the art. Next, a 2D material 160 is laid on top of the gate insulator 130. The thickness of this 2D material 160 may be between 0. 8nm and 20 nm. As shown in FIG. 10B, the source terminal 110 and drain terminal 120 are then applied on top of the 2D material 160. The 2D material 160 is then subjected to a high energy plasma treatment, such as an oxygen plasma treatment. This treatment creates the charge trap layer 170, as shown in FIG. 10C.

[0045] FIGs. 11A-11C show the fabrication process of a sensing device according to a second embodiment. As shown in FIG. 11A, gate terminals 140, 150 are applied to the bottom surface of a gate insulator 130, using methods known in the art. Next, high energy treatment, such as an oxygen plasma treatment or a defective insulator deposition is performed on the top surface of the gate insulator 130. This forms the charge trap layer 170, as shown in FIG. 11B. Then, as shown in FIG. 11C, the 2D material 160 is applied on top of the charge trap layer 170. The thickness of this 2D material 160 may be between 0. 8nm and 20 nm. The source terminal 110 and drain terminal 120 are then applied on top of the 2D material 160.

[0046] The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.

Claims

What is claimed is:

1. A sensor array, comprising:a plurality of sensing devices configured to produce electrical signals in response to a stimulus, each of the plurality of sensing devices comprising:a channel comprising a semiconductor material configured to form a p-n junction in response to application of opposite polarity voltages thereto;source and drain terminals coupled to respective ends of the channel; anda plurality of gate terminals configured to bias the semiconductor material with opposite polarity voltages, wherein a first sensing device of the plurality of sensing devices and a second sensing device of the plurality of sensing devices have differently electrostatically doped channels.

2. The sensor array of claim 1, wherein the semiconductor material is a two-dimensional semiconductor material.

3. The sensor array of claim 1, wherein the first sensing device and the second sensing device are configured to produce electrical signals having different amplitudes in response to a same stimulus.

4. The sensor array of claim 1, wherein the drain terminal of the first sensing device is coupled to the drain terminal of the second sensing device to aggregate the electrical signalsproduced by the first sensing device and the second sensing device into an aggregated electrical signal for processing.

5. The sensor array of claim 1, wherein the sensor array comprises a plurality of subarrays;wherein each of the plurality of subarrays comprises a subset of the plurality of sensing devices;wherein each subset of the plurality of sensing devices is configured to receive a respective portion of the stimulus; andwherein differences in electrostatic doping of channels between the subsets are configured to multiply the respective portions of the stimulus by different respective gain values to perform multiplication of the stimulus.

6. The sensor array of any one of claims 1 to 5, wherein each of the plurality of sensing devices further comprises a charge trap layer coupled to the semiconductor material and configured to delay transfer of current, generated in response to the stimulus, out of the semiconductor material.

7. An in-sensor computing system, comprising:the sensor array of claim 6; anda control circuit configured to apply a series of sampling pulses of the opposite polarity voltages to the plurality of gate terminals to modulate the stimulus into an integrated electrical signal.

8. A method of operating a sensor array, the sensor array comprising a plurality of sensing devices each comprising achannel comprising a semiconductor material, source and drain terminals coupled to respective ends of the channel, and a plurality of gate terminals, the method comprising:applying a stimulus to the plurality of sensing devices such that the plurality of sensing devices generates electrical signals in response to the stimulus; andwhile applying the stimulus, using the plurality of gate terminals of each of the plurality of sensing devices to bias the semiconductor material with opposite polarity voltages such that a p-n junction is formed in each of the plurality of sensing devices,wherein a first sensing device of the plurality of sensing devices and a second sensing device of the plurality of sensing devices comprise differently doped channels.

9. The method of claim 8, wherein the semiconductor material is a two-dimensional semiconductor material.

10. The method of claim 8, wherein the first sensing device and the second sensing device produce electrical signals having different amplitudes in response to a same stimulus.

11. The method of claim 8, wherein a drain terminal of the first sensing device is coupled to a drain terminal of the second sensing device, and the method further comprises aggregating electrical signals produced by the first sensing device and by the second sensing device into an aggregated electrical signal for processing.

12. The method of claim 8, wherein the sensor array comprises a plurality of subarrays;wherein each of the plurality of subarrays comprises a subset of the plurality of sensing devices;wherein each subset of the plurality of sensing devices receives a respective portion of the stimulus; and wherein differences in electrostatic doping of channels between the subsets multiply the respective portions of the stimulus by different respective gain values to perform multiplication of the stimulus.

13. The method of any one of claims 8 to 12, wherein each of the plurality of sensing devices further comprises a charge trap layer coupled to the semiconductor material and the method further comprises, by the charge trap layer, delaying transfer of current, generated in response to the stimulus, out of the semiconductor material.

14. The method of claim 13, wherein using the plurality of gate terminals to bias the semiconductor material comprises applying a plurality of pulses of the opposite polarity voltages to modulate the stimulus into an integrated electrical signal.

15. The method of claim 13, further comprising:sampling the stimulus a plurality of times during a sampling period, wherein the stimulus is sampled by biasing the semiconductor material with opposite polarity voltages during a sampling pulse; andwherein a final value of the stimulus is determined based on a current present at an end of the sampling period.

16. A method of manufacturing a sensor array, the method comprising:forming a plurality of sensing devices of the sensor array, the forming comprising, for each of the plurality of sensing devices:using a semiconductor material to form a channel that is configured to form a p-n junction in response to application of opposite polarity voltages thereto; coupling source and drain terminals to respective ends of the channel;coupling a plurality of gate terminals to the channel; andforming a charge trap layer coupled to the semiconductor material to delay transfer of charges out of the semiconductor material.

17. The method of claim 16, wherein the semiconductor material is a two-dimensional semiconductor material.

18. The method of claim 16, further comprising forming a gate insulator between the gate terminals and the channel.

19. The method of claim 18, wherein the charge trap layer is formed between the gate insulator and the channel.

20. The method of claim 16, wherein the charge trap layer is disposed on a top surface of the semiconductor material.

21. The method of any one of claims 16 to 20, further comprising coupling a drain terminal of a first sensing device to a drain terminal of a second sensing device such that electrical signals generated by the first sensing device and by the second sensing device are aggregated to form an aggregated electrical signal.

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