Systems and methods for identifying wafer voltage from inflection points

Abstract

Systems and methods for identifying wafer voltage from inflection points are described. One of the methods includes receiving a voltage waveform measured at an output of the nonsinusoidal bias power supply coupled to a plasma chamber in which a substrate is processed. The method includes determining a plurality of inflection points from the voltage waveform. At each of the plurality of inflection points, a change in plasma impedance occurs. The method includes identifying, from the plurality of inflection points, that a wafer voltage at the substrate becomes positive from negative and becomes negative from positive and controlling the nonsinusoidal bias supply based on the wafer voltage.

Description

SYSTEMS AND METHODS FOR IDENTIFYING WAFER VOLTAGE FROM INFLECTION POINTSField

[0001] The present embodiments relate to systems and methods for identifying wafer voltage from inflection points.Background

[0002] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] In a plasma processing system, a radio frequency (RF) generator is coupled via an impedance matching network to a plasma chamber. A semiconductor wafer is placed within the plasma chamber for being processed. The RF generator generates an RF signal and supplies the RF signal to the impedance matching network. The impedance matching network matches an impedance of a load coupled to the impedance matching network with an impedance of a source coupled to the impedance matching network to output a modified RF signal based on the RF signal received from the RF generator. The modified RF signal is used to process the semiconductor wafer. However, the semiconductor wafer is not processed in a desirable manner.Summary

[0004] Embodiments of the disclosure provide systems, apparatus, methods and computer programs for identifying wafer voltage from inflection points. It should be appreciated that the present embodiments can be implemented in numerous ways, e.g., a process, an apparatus, a system, a device, or a method on a computer readable medium. Several embodiments are described below.

[0005] Systems and methods for estimating wafer voltage based on non-sinusoidal bias (NSB) power supply output are described. As a wafer is processed inside a plasma chamber, voltage sensing inside the plasma chamber becomes challenging and can cause defects during wafer processing. Therefore, direct measurement of wafer voltage is limited to experiments. However, the measurement of wafer voltage is highly desirable as it can provide actual voltages that ions of plasma are energized with. Additionally, this can also aid in estimating many other process parameters, such as ion flux and direct current (DC) bias. All this information is useful to characterize a process condition and to calibrate the NSB power supply. When a bias powersupply resonantly charges a plasma load, such as the plasma chamber, an NSB voltage waveform generated by the NSB power supply has unique inflection points caused by a cathode of the plasma chamber and a ground sheath capacitance within the plasma chamber. Once these inflection points are identified, the wafer voltage at the wafer is estimated based on the NSB voltage waveform. These inflection points directly correspond to the wafer voltage irrespective of the process condition. Therefore, the methods based on these inflection points are reliable and immune to changes in a bias load.

[0006] In an embodiment, one invasive method to measure the wafer voltage inside the plasma chamber is to place a wire inside the plasma chamber and attach it to the wafer. This has significant limitations and complexity due to its invasive nature and can cause process defects. Therefore, this kind of invasive method is used mostly to map out the wafer voltage for power supply outputs for different plasma process conditions. This approach uses comprehensive and complex non-linear mapping, which may not be a reliable solution given the highly uncertain and dynamic nature of plasma loads. Various machine learning methods can also be employed to further improve this kind of mapping. However, these kinds of models are usually trained with a vast amount of data.

[0007] In one embodiment, the methods, described herein, offer a physics-based solution for estimating the wafer voltage. The methods identify characteristic nodes, such as the inflection points, in the NSB voltage waveform, and the inflection points are caused by an intrinsic nature of the plasma load. For example, a resonant charging slope changes when the wafer voltage shifts from negative to positive. This is due to the ground sheath capacitance typically being larger than a cathode sheath capacitance at the cathode. A point at which a voltage slope changes at each of the inflection points indicates a time at the wafer voltage crosses a zero potential.

[0008] In an embodiment, the methods, described herein, apply a physics-based approach, which is immune to changes in operating conditions of the plasma load and use a bias power supply output measurement. The methods, described herein, can be integrated with machine learning models, resulting in a Physics Informed Neural Network model (PINN), which can provide more accurate results with smaller training datasets.

[0009] In an embodiment, a method to detect wafer voltage based on inflection points in a main NSB power supply and a tunable edge sheath (TES) NSB power supply is described. Both wafer and edge ring voltages can be detected based on the inflection points of the main and TES NSB voltage waveforms. A closed-loop control system is implemented with a difference between wafer and edge ring voltages as a controller input and / or a phase shift between the main and TES NSB voltage waveforms as the controller output. This activefeedback closed-loop controller enables the systems, described herein, to operate with aligned wafer and edge ring voltages under various conditions, such as multi-level-pulsing and low and high plasma densities.

[0010] In an embodiment, a method for identifying wafer voltage from inflection points is described. The method includes receiving a voltage waveform measured at an output of the nonsinusoidal bias power supply coupled to a plasma chamber in which a substrate is processed. The method includes determining a plurality of inflection points from the voltage waveform. At each of the plurality of inflection points, a change in plasma impedance occurs. The method includes identifying, from the plurality of inflection points, that a wafer voltage at the substrate becomes positive from negative and becomes negative from positive and controlling the nonsinusoidal bias supply based on the wafer voltage.

[0011] In one embodiment, a controller for controlling a nonsinusoidal bias supply is described. The controller includes a processor and a memory device coupled to the processor. The processor receives a voltage waveform measured at an output of the nonsinusoidal bias power supply coupled to a plasma chamber in which a substrate is processed. The processor determines a plurality of inflection points from the voltage waveform. At each of the plurality of inflection points, a change in plasma impedance occurs. The processor identifies, from the plurality of inflection points, that a wafer voltage at the substrate becomes positive from negative and becomes negative from positive. The processor controls the nonsinusoidal bias supply based on the wafer voltage.

[0012] In an embodiment, a system for controlling a nonsinusoidal bias supply is described. The system includes the nonsinusoidal bias supply and a plasma chamber having an electrode coupled to the nonsinusoidal bias supply. The plasma chamber is used to process a substrate. The system includes a controller coupled to the nonsinusoidal bias supply. The controller receives a voltage waveform measured at an output of the nonsinusoidal bias power supply and determines a plurality of inflection points from the voltage waveform. The controller identifies, from the plurality of inflection points, that a wafer voltage at the substrate becomes positive from negative and becomes negative from positive. The controller controls the nonsinusoidal bias supply based on the wafer voltage.

[0013] Some advantages of the herein described systems and methods include determining the wafer voltage based on the NSB waveform output from the NSB power supply. The wafer voltage is used to control the NSB power supply to process the wafer in a desirable manner, such as to achieve high aspect ratio (HAR) etching of the wafer. Further advantages of the herein described systems and methods include determining whether under compensation, overcompensation, or critical compensation of an ion energy distribution function (IEDF) isachieved based on the wafer voltage. There is no need to measure a slope during an ion flux compensation phase of the NSB waveform to determine whether the IEDF is undercompensated, overcompensated, or a critically compensated. Additional advantages of the herein described systems and methods include determining a wafer direct current (DC) bias based on the NSB waveform and an estimated wafer voltage waveform and controlling the wafer DC bias.

[0014] Other aspects will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The embodiments may best be understood by reference to the following description taken in conjunction with the accompanying drawings.

[0016] Figure 1 is a diagram of an embodiment of a system to illustrate use of voltage and current (V&I) sensors for determining a voltage at a substrate.

[0017] Figure 2A is an embodiment of a graph to illustrate a non-sinusoidal bias (NSB) waveform.

[0018] Figure 2B is an embodiment of a graph to illustrate a voltage at the substrate.

[0019] Figure 2C is an embodiment of a graph to illustrate a current passing through a blocking capacitor.

[0020] Figure 3A is an embodiment of a graph to illustrate an NSB waveform during a no wafer discharge (NWD) mode.

[0021] Figure 3B an embodiment of a graph to illustrate an NSB waveform during a zero wafer discharge (ZWD) mode.

[0022] Figure 4A is an embodiment of a graph to illustrate an NSB waveform.

[0023] Figure 4B is an embodiment of a graph to illustrate a first derivative with respect to time of the NSB waveform of Figure 4 A.

[0024] Figure 4C is an embodiment of a graph to illustrate a second derivative with respect to the time of the NSB waveform of Figure 4 A.

[0025] Figure 4D is an embodiment of a graph to illustrate a filtered second derivative with respect to the time of the NSB waveform.

[0026] Figure 5A is an embodiment of the graph of Figure 3A to illustrate that a processor determines whether a first magnitude difference is greater than, equal to, or less than a second magnitude difference to determine whether overcompensation, critical compensation, or undercompensation of an ion energy distribution function (IEDF) is achieved.

[0027] Figure 5B is an embodiment of a graph to illustrate that the processor determines whether a third magnitude difference is greater than, equal to, or less than a fourthmagnitude difference to determine whether overcompensation, critical compensation, or undercompensation of an IEDF is achieved.

[0028] Figure 6 is a diagram of an embodiment of a system to illustrate a control of an NSB supply to achieve an overcompensation, a critical compensation, or an undercompensation of an IEDF.

[0029] Figure 7 is an embodiment of a graph to illustrate a determination of a direct current (DC) bias of a substrate support based on differences between voltage values of an NSB waveform and voltage values of an estimated voltage at the substrate.

[0030] Figure 8 is a diagram of an embodiment of a system to illustrate use of an NSB supply.DETAILED DESCRIPTION

[0031] The following embodiments describe systems and methods for identifying wafer voltage from inflection points. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0032] Figure 1 is a diagram of an embodiment of a system 100 to illustrate use of voltage and current (V&I) sensors 102 and 104 for determining a voltage at a substrate S. The system 100 includes a host computer 106, a controller system 108, a plasma chamber 110, a direct current (DC) voltage source (Vdc) 112, a main converter and nonsinusoidal bias (NSB) modulator 116, and a tunable edge sheath (TES) converter and NSB modulator 118. The plasma chamber 110 is an example of a plasma load. An example of the plasma chamber 110 is a capacitively coupled plasma (CCP) chamber. The plasma chamber 110 lacks, such as excludes, a voltage sensor. For example, a probe, such as a wire, for measuring a voltage at the substrate S within the plasma chamber 110 is not coupled via a wall of the plasma chamber 110 to the substrate support 128. The main converter and NSB modulator 116 is sometimes referred to herein as a main CM 116 and the TES converter and NSB modulator 118 is sometimes referred to herein as a TES CM 118. Examples of a computer, such as the host computer 106, include a controller, a desktop computer, a laptop computer, and a smart phone.

[0033] The host computer 106 includes a processor 120 and a memory device 122. Examples of a processor, as used herein, include a central processing unit (CPU), a microcontroller, an application specific integrated circuit (ASIC), and a programmable logic device (PLD). As an example, a memory device includes a read-only memory (ROM) or a random access memory (RAM) or a combination thereof. To illustrate, the memory device is a flash memory.

[0034] The controller system 108 includes an ion energy controller 124 and a TES controller 126. As an example, a controller includes a processor and a memory device and the processor is coupled to the memory device. Examples of the controller include an ASIC and a PLD. The plasma chamber 110 includes a substrate support 128, an upper electrode 130, and an edge ring 132. An example of the substrate support 128 includes an electrostatic chuck (ESC). As an example, the substrate support 128 includes a dielectric plate. The dielectric plate has an electrostatic electrode embedded therein for applying a DC bias to the substrate S. The substrate support 128 includes a lower electrode fabricated from a conductive material, such as, as aluminum, tungsten, stainless steel, copper, or a combination thereof. As an example, the edge ring 132 is fabricated from an electrically conductive material, such as boron-doped single crystalline silicon. Also, as an example, the upper electrode 130 is fabricated from a conductive material, such as, as aluminum, tungsten, graphite, stainless steel, copper, or a combination thereof.

[0035] The DC voltage source 112 includes a radiofrequency (RF) oscillator 134 and an alternating current (AC) to direct current (DC) (AC -DC) rectifier 136. As an example, a converter and NSB modulator, such as the main CM 116 or the TES CM 118, includes a DC to high voltage (HV) DC (HVDC) converter (DC-HVDC converter) and an NSB modulator. As an example, the DC-HVDC converter includes an HV charger. To illustrate, the HV charger includes a combination of power supplies, such as DC power supplies or voltage power supplies, that convert, such as increase or decrease, a DC voltage from one amount to another amount to output the HVDC. The power supplies have inputs that are coupled in parallel and have outputs that are coupled in series. Each of the power supplies has a respective enable input that is controlled by the processor 120 to enable or disable the power supply to increase or decrease a number of the power supplies of the combination that convert the DC voltage. With an increase in the number of power supplies, there is an increase in the HVDC and with a decrease in the number, there is a decrease in the HVDC. As an example, the NSB modulator includes a resonant inductor. As another example, the NSB modulator includes a charging diode and the resonant inductor. To illustrate, the main CM 116 includes a main charging diode and the TES CM 118 includes a TES charging diode. The system 100 includes a storage capacitor 138.

[0036] The processor 120 is coupled to the DC voltage source 112. For example, the processor 120 is coupled to the RF oscillator 134 or the AC -DC rectifier 136 or to both the RF oscillator 134 and the AC -DC rectifier 136. The processor 120 is also coupled to the controllers 124 and 126. The ion energy controller 124 is coupled to the main CM 116 and the TES controller 126 is coupled to the TES CM 118.

[0037] The RF oscillator 134 is coupled to the AC -DC rectifier 136, which is coupled to the storage capacitor 138. Also, the AC -DC rectifier 136 is coupled to the main CM 116 and to the TES CM 118. For example, the AC -DC rectifier 136 is coupled to a main HV charger of the main converter and NSB modulator 116 and to a TES HV charger of the TES CM 118.

[0038] The main CM 116 is coupled via an output 101 and an RF connection 140 to the lower electrode of the substrate support 128. For example, the main HV charger of the main CM 116 is coupled in series to a main resonant inductor of the main CM 116 and the main resonant inductor is coupled in series via the output 101 of the main CM 116 to the RF connection 140. Also, in the example, the main resonant inductor is coupled via a main energy recovery diode of the main CM 116 to a main energy recovery (ER), such as a magnetic energy recovery (MER), circuit of the main CM 116. The main ER circuit is coupled to the storage capacitor 138. The main ER circuit is coupled to a main ion flux compensation (IFC) circuit of the main CM 116 via a main IFC diode of the main CM 116. As an example, an IFC circuit, such as the main IFC circuit or the TES IFC circuit, includes a pulser, such as a nanopulser, and a resistor-inductor-diode (RLD) circuit. To illustrate, a resistor is coupled in series with an inductor to form a series RL circuit and the series RL circuit is coupled in parallel with a diode to form the RLD circuit. The pulser is coupled in series with the RLD circuit and is coupled to the processor 120. The nanopulser, under control, of the processor 120 generates a nonsinusoidal voltage. The processor 120 is coupled to the main ER circuit and the main IFC circuit.

[0039] Similarly, the TES CM 118 is coupled via an output 103 and an RF connection 142 to the edge ring 132. For example, a TES HV charger of the TES CM 118 is coupled in series to a TES resonant inductor of the TES CM 118 and the TES resonant inductor is coupled in series via the output 103 of the TES CM 118 to the RF connection 142. Also, in the example, the TES resonant inductor is coupled via a TES energy recovery diode of the TES CM 118 to a TES ER circuit, such as a TES MER circuit, of the TES CM 118. The TES ER circuit is coupled to the storage capacitor 138. The TES ER circuit is coupled to a TES IFC circuit of the TES CM 118 via a TES IFC diode of the TES CM 118. The processor 120 is coupled to the TES ER circuit and the TES IFC circuit.

[0040] An example of an RF connection, such as the RF connection 140 or 142, is an RF transmission line. To illustrate, the RF transmission line is a coaxial structure or a coaxial cable or one or more RF straps or a combination thereof.

[0041] The V&I sensor 102 is coupled at a point 144 on the RF connection 140 V&I sensor 104 is coupled at a point 146 on the RF connection 142. An example of a point, as used herein, is a connector.

[0042] The edge ring 132 surrounds the substrate support 128. For example, the edge ring 132 is located in the plasma chamber 110 to surround a circumference of the substrate support 128. The upper electrode 130 faces the substrate support 128 and the edge ring 132. Also, the upper electrode 130 is coupled to a ground connection at a ground potential, such as a zero potential. The substrate S, such as a semiconductor wafer, is placed on a top surface of the substrate support 128 and an edge of the substrate S extends horizontally over the edge ring 132 from the circumference of the substrate support 128.

[0043] It should be noted that the DC voltage source 112, the storage capacitor 138, and the main CM 116 are components of a main NSB supply 148, which is illustrated by dashed lines. Also, the DC voltage source 112, the storage capacitor 138, and the TES CM 118 are components of a TES NSB supply 150, which is illustrated by dotted lines.

[0044] During a charging phase in which the plasma chamber 110 is charged, the RF oscillator 134 generates an RF signal 152, such as a sinusoidal signal or an alternating current (AC) signal, and sends the RF signal 152 to the AC -DC rectifier 136. The AC -DC rectifier 136 rectifies, such as converts or modifies, the RF signal 152 to a DC voltage waveform 154. For example, the processor 120 generates and sends a control signal 156. In the example, in response to receiving the control signal 156, the RF oscillator 134 oscillates to generate the RF signal 152 or in response to receiving the control signal 156, the AC -DC rectifier 136 rectifies the RF signal 152 to output the DC voltage waveform 154.

[0045] Continuing with the charging phase, the DC voltage waveform 154 is supplied from the AC -DC rectifier 136 to the main CM 116 and to the TES CM 118. The processor 120 sends a charging control signal 158 of a control signal set 157 to the ion energy controller 124 and sends a charging control signal 160 of the control signal set 157 to the TES controller 126. In response to receiving the charging control signal 158, the ion energy controller 124 generates and sends a control signal 162 to the main HV charger of the main CM 116. An example of the control signal 162 is the charging control signal 158. The control signal 162 indicates an amount of change, such as an increase, in voltage from DC voltage of the DC voltage waveform 154 to HVDC of a main HVDC voltage waveform (not shown) to be output from the main HV charger. The main HV charger outputs the main HVDC voltage waveform to the main resonant inductor. The main resonant inductor converts the main HVDC voltage waveform to output, such as generate, a main NSB waveform 164 that is provided, at an output 101 from the main CM 116. An example of the output 101 of the main CM 116 is a connector. The output 101 of the main CM 116 is the output 101 of the main NSB supply 148.

[0046] Similarly, during the charging phase, in response to receiving the control signal 160, the TES controller 126 generates and sends a control signal 166 to the TES HVcharger of the TES CM 118. An example of the control signal 166 is the charging control signal 160. The control signal 166 indicates an amount of change, such as an increase, in voltage from DC voltage of the DC voltage waveform 154 to HVDC of a TES HVDC voltage waveform (not shown) to be output from the TES HV charger. The TES HV charger outputs the TES HVDC voltage waveform to the TES resonant inductor. The TES resonant inductor converts the TES HVDC voltage waveform to output, such as generate, a TES NSB waveform 168 that is provided, at an output 103, from the TES CM 118. An example of the output 103 of the TES CM 118 is a connector. The output 103 of the TES CM 118 is the output 103 of the TES NSB supply 150.

[0047] It should be noted that an NSB waveform, such as the main NSB waveform 164 or the TES NSB waveform 168, is a nonsinusoidal waveform. For example, no portion of the NSB waveform is a sinusoid or a sine wave having a radio frequency.

[0048] It should further be noted that both the main NSB waveform 164 and the TES NSB waveform 168 has the same frequency. For example, the main NSB supply 148 and the TES NSB supply 150 have the same operating frequency, such as a radio frequency. To further illustrate, a cycle n of the NSB waveform 164 occurs during a time interval that is equal to a time interval during which a cycle n of the NSB waveform 168 occurs, where n is a positive integer.

[0049] The charging phase occurs for a predetermined amount of dwell time during each cycle of the main NSB waveform 164 and for the predetermined amount of dwell time during each cycle of the TES NSB waveform 168. After the predetermined amount of dwell time, a discharging phase in which the plasma chamber 110 is discharged starts. For example, after the predetermined amount of dwell time from a time at which processor 120 sends the control signal set 157 to the controllers 124 and 126, the main and TES charging diodes becomes reverse biased and the main and TES ER diodes become forward biased and the discharging phase starts. During the discharging phase, the processor 124 sends discharging control signals to the main and TES ER circuits and in response to receiving the discharging control signals, the main and TES ER circuits transfer RF power recovered from the plasma chamber 110 to the storage capacitor 138 for storage in the storage capacitor 138.

[0050] At an end of the discharging phase, when the plasma chamber 110 is discharged, the main and TES ER diodes becomes reversed biased after being forward biased, and an IFC phase begins for each cycle of the NSB waveforms 164 and 168. At a beginning of the IFC phase, the processor 120 sends IFC control signals to the main and TES IFC circuits to achieve IFC, such as overcompensation, critical compensation, or undercompensation.

[0051] The IFC phase continues during each cycle of the NSB waveforms 164 and 168 until a next occurrence of charging of the plasma chamber 110. For example, at an end of the IFC phase of a first cycle of the NSB waveforms 164 and 168, the processor 112 sends the control signal set 157 again, at the radio frequency, to initiate a second cycle of the NSB waveforms 164 and 168. The first cycle precedes the second cycle. In this manner, multiple cycles of the charging phase, the discharging phase, and the IFC phase of the NSB waveforms 164 and 168 repeat periodically.

[0052] In the charging, discharging, and IFC phases of each cycle of the NSB waveforms 164 and 168, the main NSB waveform 164 is supplied from the main CM 116 via the RF connection 140 to the lower electrode of the substrate support 128 and the TES NSB waveform 168 is supplied from the TES CM 118 via the RF connection 142 to the edge ring 132. As an example, an NSB waveform is not a sinusoidal waveform.

[0053] In addition, one or more process gases, such as an oxygen containing gas or a nitrogen containing gas or a combination thereof, are supplied to the plasma chamber 110. When the one or more process gases are supplied in addition to the NSB waveforms 164 and 168, plasma is generated within the plasma chamber 110 to process the substrate S. For example, one or more materials are deposited on the substrate S, or the substrate S is etched, or the substrate S is cleaned to process the substrate S.

[0054] During each cycle of the main NSB waveform 164, the V&I sensor 102 measures a complex voltage and current at the point 144 to generate a measurement signal 172 and sends the measurement signal 172 to the ion energy controller 124. The measurement signal 172 provides voltage values of the NSB waveform 164 with respect to time, which includes time values at which the voltage values of the NSB waveform 164 are measured by the V&I sensor 102. Similarly, during each cycle of the TES NSB waveform 168, the V&I sensor 104 measures a complex voltage and current at the point 146 to generate a measurement signal 174 and sends the measurement signal 174 to the TES controller 126. The measurement signal 174 provides voltage values of the NSB waveform 168 with respect to time, which includes time values at which the voltage values of the NSB waveform 168 are measured by the V&I sensor 104. The ion energy controller 124 sends the measurement signal 172 to the processor 120 and the TES controller 126 sends the measurement signal 174 to the processor 120.

[0055] In one embodiment, the functions described herein as being performed by one or more controllers, such as the ion energy controller 124 or the TES controller 126 or a combination thereof, are performed by the processor 120. For example, the controller system 108 is integrated within the host computer 106 and the VI sensors 102 and 104 are coupled to the processor 120 without being coupled to the controller system 108.

[0056] In an embodiment, the functions described herein as being performed by the processor 120 are performed by one or more controllers, such as the ion energy controller 124 or the TES controller 126 or a combination thereof, of the controller system 108. For example, the host computer 106 is integrated within the controller system 108.

[0057] In an embodiment, a first blocking capacitor is coupled between the main CM 116 and the substrate support 128 and a second blocking capacitor is coupled between the TES CM 118 and the edge ring 132. To illustrate, the first blocking capacitor is coupled to the RF connection 140 at one end and to the lower electrode of the substrate support 128 via another end. The second blocking capacitor is coupled to the RF connection 142 at one end and to the edge ring 132 via another end.

[0058] In an embodiment, instead of being coupled to the ground connection, the upper electrode 130 is coupled to a radio frequency generator, such as an RF generator operating at a frequency of 60 megahertz (MHz).

[0059] In an embodiment, instead of the CCP chamber, an inductively coupled plasma (ICP) chamber is used. In the ICP chamber, a top coil is used instead of the upper electrode 130.

[0060] In one embodiment, instead of the DC voltage source 112, multiple DC voltage sources are used and instead of the storage capacitor 138, multiple storage capacitors are used. For example, a main DC voltage source is coupled to the processor 120 and to a main storage capacitor, which is coupled to the main CM 116. Also, in the example, a TES DC voltage source is coupled to the processor 120 and to a TES storage capacitor, which is coupled to the TES CM 118. The main storage capacitor is coupled to the main DC voltage source in the same manner with the storage capacitor 138 is coupled to the DC voltage source 112 and the TES storage capacitor is coupled to the TES DC voltage source in the same manner with the storage capacitor 138 is coupled to the DC voltage source 112.

[0061] Figure 2A is an embodiment of a graph 200 to illustrate an NSB waveform 202, such as the main NSB waveform 164 or the TES NSB waveform 168 (Figure 1). The graph 200 plots a voltage of the NSB waveform 202 on a y-axis and time t on an x-axis. The time t includes values tO, tl, t2, t3, t4, t5, t6, and t7 which increase in a progressive manner as the voltage of the NSB waveform 202 is measured by a V&I sensor, such as the V&I sensor 102 or 104 (Figure 1). For example, the time tl occurs after the time tO, the time t2 occurs after the time tl, the time t3 occurs after the time t2, the time t4 occurs after the time t3, the time t5 occurs after the time t4, and the time t6 occurs after the time t5. At the time tl, a charging phase 204 of the cycle n of the NSB waveform 202 starts. During the charging phase 204, the voltage of the NSB waveform 202 increases from a negative value to a positive value during thepredetermined amount of dwell time. The cycle n occurs from the time tl to the time t7 and a cycle (n+1) of the NSB waveform 202 starts at the time t7. A time interval of each cycle is the same. For example, a time interval of the cycle (n+1) is equal to a time interval, between the times tl and t7, of the cycle n. Also, after the charging phase 204 of the cycle n, a discharging phase 206 of the cycle n occurs and after the discharging phase 206, and IFC phase 208 occurs. The discharging phase 206 of the cycle n starts at the time t4 and ends at the time t6. A discharging phase includes an energy recovery phase. Also, after the discharging phase 206 of the cycle n, an IFC phase 208 of the cycle n occurs and after the IFC phase 208, a charging phase of the NSB waveform 202 repeats for the cycle (n+1). The IFC phase 208 of the cycle n starts at the time t6 and ends at the time t7. In this manner, the charging phase 204, the discharging phase 206, and the IFC phase 208 repeat during the cycle (n+1) of the NSB waveform 202.

[0062] During the charging phase 204 of the cycle n, the processor 120 (Figure 1) determines an inflection point 210, which occurs at the time t2. Also, during the discharging phase 206 of the cycle n, the processor 120 determines an inflection point 212, which occurs at the time t5. Each inflection point 210 and 212 occurs as a result of a change in impedance of plasma formed within the plasma chamber 110 (Figure 1).

[0063] In one embodiment, the inflection point 212 occurs at a time of transition from the charging phase 204 to the discharging phase 206.

[0064] In an embodiment, the discharging phase 206 is a portion of a charging phase of the NSB waveform 202 and the charging phase extends from the time tl to the time t6. For example, the inflection point 212 occurs during the charging phase.

[0065] Figure 2B is an embodiment of a graph 220 to illustrate a voltage at the substrate S (Figure 1). The graph 220 includes a voltage waveform 222 having values of the voltage at the substrate S. The graph 220 plots the voltage at the substrate S on a y-axis and the time t on an x-axis. The x-axis of the graph 220 is the same as the x-axis of the graph 200 (Figure 2A).

[0066] The processor 120 determines, such as identifies or infers or estimates, that at the time t2 of occurrence of the inflection point 210, the voltage at the substrate S is zero during a transition from being negative to positive, such as having a negative voltage value to having a positive voltage value. Also, the processor 120 determines, such as identifies or infers or estimates, that at the time t5 of occurrence of the inflection point 212, the voltage at the substrate S is zero again during a transition from being positive to negative, such as having a positive voltage value to having a negative voltage value.

[0067] At the inflection point 210, there is an asymmetry during a rise time of the NSB waveform 202. The rise time occurs from the time tl to the time t3. At the inflection point 212, there is an asymmetry during a fall time of the NSB waveform 202. The fall time occurs from the time t4 to the time t6. As an example, the rise time of the NSB waveform 202 is greater than the fall time of the NSB waveform 202. For the voltage waveform 222, a rise time occurs from the time tl to a time t2 and a fall time occurs from the time t4 to the time t6. At a time t2.8, which occurs between the times t2 and t3, the voltage at the substrate S is maximum during the cycle n. During the rise time of the voltage waveform 222, the voltage at the substrate S increases from a negative value, such as -7000 volts, to zero volts. During the fall time of the voltage waveform 222, the voltage at the substrate S decreases from zero volts to a negative value, such as -8000 volts. The rise time of the voltage waveform 222 is less than the fall time of the voltage waveform 222.

[0068] It should be noted that the processor 120 controls the main CM 116 or the TES CM 118 (Figure 1) or a combination thereof until a voltage at a central region, such as a center region, of the substrate S is within a predetermined range from a voltage at the edge, such as an edge region, of the substrate S. For example, the processor 120 determines the voltage at the central region based on inflection points of the main NSB waveform 164 and determines the voltage at the edge region based on inflection points of the TES NSB waveform 168. To illustrate, the processor 120 determines that the voltage at the central region is positive at the time t2 and the voltage at the edge region is negative at the time t2. The processor 120 controls the main CM 116 to modify the voltage of the main NSB waveform 164 until the voltage at the central region becomes negative at the time t2 or controls the TES CM 118 to modify the voltage of the TES NSB waveform 168 until the voltage at the edge region becomes positive at the time t2. For example, the central region has a circumference extending radially from the center of the substrate S until a circumference of the central region is reached. The edge region starts at the circumference of the central region and further extends radially from the circumference until an outer circumference of the edge region is reached. The circumference of the central region also forms an inner circumference of the edge region.

[0069] Figure 2C is an embodiment of a graph 230 to illustrate a current passing through a blocking capacitor, such as the first blocking capacitor and the second blocking capacitor. The graph 230 plots a current waveform 232 of the current on a y-axis and the time t on an x-axis. The x-axis of the graph 230 is the same as the x-axis of the graph 200 (Figure 2A).

[0070] Figure 3A is an embodiment of a graph 300 to illustrate an NSB waveform 302 during a no wafer discharge (NWD) mode. The NSB waveform 302 is an example of the main NSB waveform 164 (Figure 1) or the TES NSB waveform 168 (Figure 1). The graph 300plots a voltage of the NSB waveform 302 on a y-axis and the time t on an x-axis. For example, the voltage of NSB waveform 302 include voltage values -Vb, -Va, 0 volts, VI, V2, V3, and V4 in a progressively increasing order, wherein Vb, Va, and VI through V4 are positive real numbers. To illustrate, the voltage value -Va is greater than the voltage value -Vb, the value of 0 volts is greater than the voltage value -Va, the voltage value VI is greater than the value of 0 volts and so on until the voltage value V4 is greater than the voltage value V3. As an example, the time t represents time values of a time interval in which the NSB waveform 302 is measured by a V&I sensor, such as the V&I sensor 102 are 104 (Figure 1). In the example, a measurement signal, such as the measurement signal 172 or 174 (Figure 1) includes the time values and the voltage values of the NSB waveform 302. The x-axis of the graph 300 is the same as the x-axis of the graph 200 (Figure 2A).

[0071] The NSB waveform 302 has an inflection point 304, which is an example of inflection point 210 (Figure 2). Also, the NSB waveform 302 has another inflection point 306, which is an example of the inflection point 212 (Figure 2). During the NWD mode, voltage at the substrate S is discharged at a slow rate. At the inflection point 304, there is an asymmetry during a rise time of the NSB waveform 302. The rise time occurs from the time tl to the time t3. At the inflection point 306, there is an asymmetry during a fall time of the NSB waveform 302. The fall time occurs from the time t4 to the time t6. As an example, the rise time is greater for the NSB waveform 302 than the fall time.

[0072] The NSB waveform 302 has six sections, illustrated from 1, 2, 3, 4, 5, and 6. The section 1 starts at the time tl, which is the time of start of the charging phase. The section 1, during the charging phase, of the NSB waveform 302 occurs from the time tl (Figure 2A) to the time t2 at which the inflection point 304 occurs. For example, the processor 120 determines, such as identifies, that a voltage value, such as the voltage value VI, at the inflection point 304 and the time t2 of occurrence of the inflection point 304 are received from a V&I sensor, such as the V&I sensor 102 or 104 (Figure 1). Also, the section 1 has voltage values that increase from the voltage value -Vb at the time tl to the voltage value VI at the time t2. The section 2, during the charging phase, occurs from the time t2 to the time t3 and the section 3, during the charging phase, occurs from the time t3 to the time t4. Also, the section 2 has voltage values that increase from the voltage value VI at the time t2 to the voltage value V4 at the time t3. The section 3 has voltage values that decrease from the voltage value V4 at the time t3 to the voltage value V3 at the time t4.

[0073] At the time t4, the charging phase ends and the discharging phase starts. The section 4 of the NSB waveform 302 occurs from the time t4 to the time t5 at which the inflection point 306 occurs. For example, the processor 120 determines, such as identifies, that a voltagevalue, such as the voltage value V2, at the inflection point 306 and the time t5 of occurrence of the inflection point 306 are received from a V&I sensor, such as the V&I sensor 102 or 104 (Figure 1). The section 4 has voltage values that decrease from the voltage value V3 at the time t4 to the voltage value V2 at the time t5. The section 5 of the NSB waveform 302 occurs from the time t5 to the time t6 at which the discharging phase ends and the IFC phase begins. The section 5 has voltage values that decrease from the voltage value V2 at the time t5 to the voltage value -Va at the time t6.

[0074] The section 6 of the NSB waveform 302 occurs from the time t6 to the time t7. The IFC phase of the NSB waveform 302 occurs from the time t6 to the time t7 at which the IFC phase ends and the charging phase of a cycle (n+1) of the NSB waveform 302 begins. The section 6 has voltage values that decrease from the voltage value -Va at the time t6 to the voltage value -Vb at the time t7.

[0075] Figure 3B an embodiment of a graph 310 to illustrate an NSB waveform 312 during a zero wafer discharge (ZWD) mode. The NSB waveform 312 is an example of the main NSB waveform 164 (Figure 1) or the TES NSB waveform 168 (Figure 1). The graph 310 plots a voltage of the NSB waveform 312 on a y-axis and the time t on an x-axis. The x-axis of the graph 310 is the same as the x-axis of the graph 200 (Figure 2A). The NSB waveform 312 has the inflection point 304. Also, the NSB waveform 312 has another inflection point 314. During the ZWD mode, voltage at the substrate S is discharged at a fast rate, which is greater than the slow rate. When dwell time of the NSB waveform 312 is made large enough compared to a dwell time of the NSB waveform 302 (Figure 3 A), the substrate S discharges to the ground potential and the ZWD mode is achieved. Positive current compensation can be employed for faster discharge of wafer voltage to achieve the ZWD mode.

[0076] The NSB waveform 312 has six sections, illustrated as 1, 2, 3, 4, 5, and 6. The sections 1 and 2 of the NSB waveform 312 are the same as the sections 1 and 2 of the NSB waveform 302 (Figure 3 A). The section 3, during the charging phase, of the NSB waveform 312 occurs from the time t3 to a time t4a, which occurs between the times t3 and t4.

[0077] At the time t4a, the discharging phase starts. The section 4 of the NSB waveform 312 occurs from the time t4a to a time t5a at which the inflection point 314 occurs. As an example, the section 4 of the NSB waveform is horizontally oriented, such as has a zero slope. The section 5 occurs from the time t5a to a time t6a at which the discharging phase ends and the IFC phase begins. The IFC phase occurs from the time t6a to the time t7 at which the IFC phase ends and the charging phase of the cycle (n+1) of the NSB waveform 312 begins.

[0078] Figure 4A is an embodiment of a graph 400 to illustrate an NSB waveform 402. The NSB waveform 402 is an example of the main NSB waveform 164 (Figure 1) or theTES NSB waveform 168 (Figure 1). To illustrate, the NSB waveform 402 is an example of the NSB waveform 302 (Figure 3A). As another illustration, voltage values of the NSB waveform 402 with respect to time t, illustrated in the graph 400, are provided as the measurement signal 172 (Figure 1) from the V&I sensor 102 via the ion energy controller 124 to the processor 120. As yet another illustration, voltage values of the NSB waveform 402 with respect to time t, illustrated in the graph 400, are provided as the measurement signal 174 (Figure 1) from the V&I sensor 104 via the TES controller 126 to the processor 120.

[0079] The graph 400 plots the time t on an x-axis and voltage of the NSB waveform 402 on a y-axis. As an example, the voltage of the NSB waveform 402 ranges from -7500 volts to 8000 volts. The time t of the x-axis of the graph 400 has time values tO, tla, tlb, tic, tie, and tlf during the cycle n of the NSB waveform 402. The times tO through tlf increase progressively. For example, the time tla occurs after the time tO, the time tlb occurs after the time tla and so on until the time tlf occurs after the time tie.

[0080] The NSB waveform 402 includes sections 404, 406, 408, 410, and 412 during the cycle n of the NSB waveform 402. The cycle n of the NSB waveform 402 occurs from the time tO to the time tlf. The section 404 is an example of the section 1 of the NSB waveform 302, the section 406 is an example of the section 2 of the NSB waveform 302, the section 408 is an example of the section 3 of the NSB waveform 302, the section 410 is an example of the section 4 of the NSB waveform 302, and the section 412 is an example of the section 6 of the NSB waveform 302. The section 404 has voltage values increasing from -7500 to 2500 that occurs from the time tla to the time tlb. Also, the section 406 has voltage values increasing from 2500 to 8000 from the time tlb to the time tic. The section 408 has voltage values decreasing from 8000 to 4500 from the time tic to the time tld. The section 410 has voltage values decreasing from 4500 to -6000 from the time tld to the time tie, and the section 412 has voltage values decreasing from -6000 to -7500 from the time tie to the time tlf.

[0081] Between the sections 404 and 406, there is an inflection point 416. Also, between the sections 410 and 412 there is another inflection point 418. The inflection point 416 is an example of the inflection point 210 (Figure 2A) or 304 (Figure 3A) and the inflection point 418 is an example of the inflection point 212 (Figure 2B) or 306 (Figure 3A).

[0082] Figure 4B is an embodiment of a graph 420 to illustrate a first derivative 422 with respect to the time t of the NSB waveform 402 (Figure 4A). As an example, the time t represents time values of a time interval in which the voltage values of the NSB waveform 402 are measured by a V&I sensor, such as the V&I sensor 102 are 104 (Figure 1), and the time values are received within the measurement signal 172 or 174 (Figure 1) by the processor 120. For example, the voltage values and the time values of the NSB waveform 402 are received bythe processor 120 via the ion energy controller 124 from the V&I sensor 102 when the V&I sensor 102 sends the measurement signal 172 via the ion energy controller 124 to the processor 120. As another example, the voltage values and the time values of the NSB waveform 402 are received by the processor 120 via the TES controller 126 from the V&I sensor 104 when the V&I sensor 104 sends the measurement signal 174 via the TES controller 126 to the processor 120. The graph 420 plots a voltage of the first derivative 422 on a y-axis and the time t on an x- axis. The x-axis of the graph 420 is the same as the x-axis of the graph 400 (Figure 4A). The processor 120 (Figure 1) receives from a V&I sensor, such as the V&I sensor 102 or 104, the voltage values and the time t of the NSB waveform 402 measured by the V&I sensor and determines, such as generates or computes, the first derivative 422 of the NSB waveform 402 with respect to the time t.

[0083] Figure 4C is an embodiment of a graph 430 to illustrate a second derivative 432 with respect to the time t of the NSB waveform 402 (Figure 4A). The graph 430 plots a voltage of the second derivative 432 on a y-axis and the time t on an x-axis. The x-axis of the graph 430 is the same as the x-axis of the graph 400 (Figure 4A). The processor 120 (Figure 1) determines, such as generates or computes, the second derivative 432 of the NSB waveform 402 with respect to the time t from the first derivative 422 (Figure 4B). For example, the processor 120 computes a derivative with respect to the time t of the first derivative 422 to obtain the second derivative 432.

[0084] Figure 4D is an embodiment of a graph 440 to illustrate a filtered second derivative 442 with respect to the time t of the NSB waveform 402 (Figure 4A). The graph 440 plots a voltage of the filtered second derivative 442 on a y-axis and the time t on an x-axis. The x-axis of the graph 440 is the same as the x-axis of the graph 400 (Figure 4A). The processor 120 (Figure 1) filters the second derivative 432 to obtain the filtered second derivative 442. For example, the processor 120 converts negative values of the second derivative 432 to determine positive voltage values of the filtered second derivative 442. To illustrate, a negative value having a real number, such as two, at the time tla is converted to a positive value having the same real number, such as two. Also, in the example, processor 120 maintains values of the second derivative 432 to determine maintain voltage values of the filtered second derivative 442. To illustrate, a positive value, such as 0.75, of the second derivative 432 is maintained to be the same positive value, such as 0.75.

[0085] It should be noted that the filtered second derivative 442 identifies the time tla of occurrence of the inflection point 416 (Figure 4A). For example, the processor 120 determines that at the time tla, a value, such as two, of the filtered second derivative 442 is outside, such as greater than, a predetermined threshold 444 at the time tla to determine that theinflection point 416 occurs at the time tla. The predetermined threshold 444 is a voltage value on the y-axis of the filtered second derivative 442 and is stored in the memory device 122 (Figure 1A) for access by the processor 120. At the time tla, there is a change, such as an increase or a decrease, in impedance of plasma within the plasma chamber 110. The change in the plasma impedance at the time tla is greater than a preset threshold.

[0086] Similarly, the filtered second derivative 442 identifies the time tie of occurrence of the inflection point 418 (Figure 4A). For example, the processor 120 determines that at the time tie, a value, such as 0.75, of the filtered second derivative 442 is outside, such as greater than, the predetermined threshold 444 at the time tie to determine that the inflection point 418 occurs at the time tie. At the time tie, there is a change, such as an increase or a decrease, in impedance of plasma within the plasma chamber 110. The change in the plasma impedance at the time tie is greater than the preset threshold.

[0087] The processor 120 further determines that during a time interval between the times tO and tla, a value of the filtered second derivative 442 is within, such as less than, the predetermined threshold 444 to determine that an inflection point of the NSB waveform 402 does not occur between the times tO and tla. Also, the processor 120 further determines that during a time interval between the times tla and tie, a value of the filtered second derivative 442 is within, such as less than, the predetermined threshold 444 to determine that an inflection point of the NSB waveform 402 does not occur between the times tla and tie. Moreover, the processor 120 further determines that during a time interval between the times tie and tlf, a value of the filtered second derivative 442 is within, such as less than, the predetermined threshold 444 to determine that an inflection point of the NSB waveform 402 does not occur between the times tie and tlf. In this manner, the processor 120 identifies inflection points of the NSB waveform 402 during each cycle of the NSB waveform 402.

[0088] Figure 5A is an embodiment of the graph 300 to illustrate that the processor 120 (Figure 1) determines whether a first magnitude difference is greater than, equal to, or less than a second magnitude difference to determine whether overcompensation, critical compensation, or undercompensation of an ion energy distribution function (IEDF) is achieved. An IEDF is sometimes referred to here as an ion energy distribution. The IEDF plots ion energy of ions of plasma formed within the plasma chamber 110 versus ion flux of the ions. For example, the ion energy is plotted on a y-axis and the ion flux is plotted on an x-axis. The graph 300 plots the NSB waveform 302. It should be noted that although the NSB waveform 302 has a negative slope during an IFC phase, for the purposes of Figure 5A, the NSB waveform 302 is treated as if the NSB waveform 302 has a positive slope, or a zero slope, or a negative slope during the IFC phase.

[0089] In the graph 300, a section N1 represents the section 1 of the NSB waveform 302 illustrated in Figure 3A, a section N2 represents the section 2 of the NSB waveform 302 illustrated in Figure 3A, a section N3 represents the section 4 of the NSB waveform 302 illustrated in Figure 3A, and a section N4 represents the section 5 of the NSB waveform 302 illustrated in Figure 3A. As an example, the processor 120 determines the first magnitude difference as a difference between magnitudes of the sections N1 and N2 and the second magnitude difference as a difference between magnitudes of the sections N3 and N4.

[0090] The section N1 occurs from the time tl to the time t2. The time tl is a time at which a charging phase of charging of the plasma chamber 110 starts during the cycle n and the time t2 is a time of occurrence of the inflection point 304. Also, the section N2 occurs from the time t2 to the time t3. The time t3 is a time at which a peak voltage, such as the maximum voltage amplitude of V4, of the NSB waveform 302 occurs during the charging phase. The section N3 occurs from the time t4 to the time t5. At the time t4, a discharging phase of the plasma chamber 110 starts and at the time t5, the inflection point 306 occurs. The section N4 occurs from the time t5 to the time t6. At the time t6, an IFC phase of modifying a compensation of the IEDF associated with ions of plasma formed within the plasma chamber 110 starts.

[0091] The processor 120 determines the section N1 as a difference between the voltage values VI and -Vb, determines the section N2 as a difference between the voltage values V4 and VI, determines the section N3 as a difference between the voltage values V2 and V3, and determines the section N4 as a difference between the voltage values -Va and V2. In response to determining that the first magnitude difference is greater than the second magnitude difference, the processor 120 determines that a slope of the IFC phase of the NSB waveform 302 is negative and overcompensation of the IEDF generated, by the processor 120, based on the NSB waveform 302 is achieved. On the other hand, in response to determining that the first magnitude difference is less than the second magnitude difference, the processor 120 determines that a slope of the IFC phase of the NSB waveform 302 is positive and undercompensation of the IEDF generated based on the NSB waveform 302 is achieved. Also, in response to determining that the first magnitude difference is equal to the second magnitude difference, the processor 120 determines that a slope of the IFC phase of the NSB waveform 302 is substantially zero, such as zero or horizontal, and critical compensation of the IEDF generated based on the NSB waveform 302 is achieved.

[0092] There is no need to measure or estimate an ion flux current or a slope of the NSB waveform 302 to determine whether the ion energy distribution is overcompensated, undercompensated, or critically compensated. The determination of the overcompensation,undercompensation or critical compensation and is made based on inflection points, described herein, of the NSB waveform 302.

[0093] Figure 5B is an embodiment of a graph 510 to illustrate that the processor 120 (Figure 1) determines whether a third magnitude difference is greater than, equal to, or less than a fourth magnitude difference to determine whether overcompensation, critical compensation, or undercompensation of an IEDF is achieved. The graph 510 plots voltage values of an NSB waveform 512 on a y-axis and the time t on an x-axis. The x-axis of the graph 510 is the same as the x-axis of the graph 300 (Figure 5A) and the y-axis of the graph 510 is the same as the y-axis of the graph 300. The NSB waveform 512 is an example of the main NSB waveform 164 or the TES NSB waveform 168 (Figure 1).

[0094] The graph 510 includes sections 514, 516, 518, and 520. As an example, the processor 120 determines the third magnitude difference as a difference between magnitudes of the sections 514 and 516 and the fourth magnitude difference as a difference between magnitudes of the sections 518 and 520. The processor 120 determines the section 514 as a difference between the voltage values 0 and -Vb, determines the section 516 as a difference between the voltage values V4 and 0, determines the section 518 as a difference between the voltage values V3 and 0, and determines the section 520 as a difference between the voltage values -Vb and 0. In response to determining that the third magnitude difference is equal to the fourth magnitude difference, the processor 120 determines that a slope of an IFC phase of the NSB waveform 512 is substantially zero, such as zero or horizontal, and critical compensation of an IEDF generated based on the NSB waveform 512 is achieved.

[0095] It should be noted that a charging phase during which the plasma chamber 110 (Figure 1) is charged by voltage of the NSB waveform 512 occurs between the times tl and t4. During a time interval between the times t4 and t6, a discharging phase during which the plasma chamber 110 is discharged by voltage of the NSB waveform 512 occurs. Also, during a time interval between the times t6 and t7, the IFC phase of the NSB waveform 512 occurs. The charging phase, the discharging phase, and the ion flux compensation phase occur once during the cycle n of the NSB waveform 512. Also, the charging phase, the discharging phase, and the ion flux compensation phase occur once again during a cycle (n+1) of the NSB waveform 512.

[0096] Figure 6 is a diagram of an embodiment of a system 600 to illustrate a control of an NSB supply 602 to achieve an overcompensation, a critical compensation, or an undercompensation of an IEDF. The NSB supply 602 is an example of the main NSB supply 148 (Figure 1) or of the TES NSB supply 150 (Figure 1). The system 602 includes the processor 120, the memory device 122, a controller 601, and the NSB supply 602. The controller 601 is an example of the ion energy controller 124 (Figure 1) or of the TES controller 126 (Figure 1).

[0097] The processor 120 includes a comparator 604, an average determinator 606, and a difference calculator 608. The comparator 604 is coupled to the memory device 122 and to the average determinator 606. The average determinator 606 is coupled to the difference calculator 608. The difference calculator 608 is coupled to a V&I sensor, such as the VI sensor 102 or 104 (Figure 1).

[0098] It should be noted that although the NSB waveform 302 has a negative slope during an IFC phase, for the purposes of Figure 6, the NSB waveform 302 is treated as if the NSB waveform 302 has a positive slope, or a zero slope, or the negative slope during the IFC phase.

[0099] The difference calculator 608 receives a measurement signal 610, such as the measurement signal 172 from the V&I sensor 102 or the measurement signal 174 from the V&I sensor 104 (Figure 1), for multiple predetermined time intervals, such as a time period of the cycle n of the NSB waveform 302 and a time period of the cycle (n+1) of the NSB waveform 302, and determines the first and second magnitude differences from the voltage values of the NSB waveform 302 received for each of the predetermined time intervals. For example, the difference calculator 608 determines the sections N1 and N2 from voltage values of the NSB waveform 302 received during the cycle n of the NSB waveform 302 and further determines a first instance of the first magnitude difference as a magnitude of a difference between the sections N1 and N2. Also, the difference calculator 608 determines the sections N3 and N4 from voltage values of the NSB waveform 302 received during the cycle n of the NSB waveform 302 and further determines a first instance of the second magnitude difference as a magnitude of a difference between the sections N3 and N4. The difference calculator 608 determines a first difference, such as mdiff(t), between the first instance of the first magnitude difference and the first instance of the second magnitude difference.

[0100] Continuing with the example, the difference calculator 608 further determines sections N1 and N2 from voltage values of the NSB waveform 302 received during the cycle (n+1) of the NSB waveform 302 and further determines a second instance of the first magnitude difference as a magnitude of a difference between the sections N1 and N2. Also, the difference calculator 608 determines sections N3 and N4 from voltage values of the NSB waveform 302 received during the cycle (n+1) of the NSB waveform 302 and further determines a second instance of the second magnitude difference as a magnitude of a difference between the sections N3 and N4. The difference calculator 608 determines a second difference between the second instance of the first magnitude difference and the second instance of the second magnitude difference.

[0101] The difference calculator 608 provides the first and second differences as a difference signal 612 to the average determinator 606. The average determinator 606 calculates an average of the first and second differences to output an average result 614 and provides the average result 614 to the comparator 604. As an example, the each of the first and second differences is greater than zero to indicate an overcompensation of the IEDF generated based on the NSB waveform 302. As another example, each of the first and second differences is equal than zero to indicate a critical compensation of the IEDF based on the NSB waveform 302 output from the NSB power supply 602. As yet another example, each of the first and second differences is less than zero to indicate an undercompensation of the IEDF based on the NSB waveform 302.

[0102] The comparator 604 accesses a predetermined difference 616, such as main, from the memory device 122 and compares the average result 614 with the predetermined difference 616 to determine a difference 618 between the predetermined difference 616 and the average result 614. As an example, the predetermined difference 616 is greater than zero to indicate that overcompensation of an IEDF is to be achieved. As another example, the predetermined difference 616 is equal than zero to indicate that critical compensation of the IEDF is to be achieved. As yet another example, the predetermined difference 616 is less than zero to indicate that undercompensation of the IEDF is to be achieved. The comparator 604 provides the difference 618 to the controller 601 to control the NSB supply 602 via the controller 601.

[0103] The controller 601 controls the NSB supply 602 based on the difference 618. For example, the controller 601 controls the NSB supply 602 to increase a negative voltage output from the nanopulser of the IFC circuit of the NSB supply 602 to achieve overcompensation of an IEDF from critical compensation or from undercompensation of the IEDF. To illustrate, a peak of ion flux of ions of plasma within the plasma chamber 110 (Figure 1) moves from the left of a center ion energy to the right of the center ion energy to achieve the overcompensation from the undercompensation. As another illustration, a first peak of ion flux of ions within the plasma chamber 110 on the left of the center ion energy decreases and a second peak is formed to the right of the center ion energy until both the first and second peaks have an ion flux value within a predetermined range to achieve the critical compensation from the undercompensation.

[0104] As another example, the controller 601 controls the NSB supply 602 to decrease a negative voltage output from the nanopulser of the IFC circuit of the NSB supply 602 to achieve undercompensation of an IEDF from critical compensation or from overcompensation of the IEDF. To illustrate, a peak of ion flux of ions within the plasma chamber 110 moves fromthe right of the center ion energy to the left of the center ion energy to achieve the undercompensation from the overcompensation. As another illustration, a first peak of ion flux of ions within the plasma chamber 110 on the right of the center ion energy decreases and a second peak is formed to the left of the center ion energy until both the first and second peaks have an ion flux value within the predetermined range to achieve the critical compensation from the overcompensation.

[0105] By determining the first and second magnitude differences, there is no need to determine a slope of the NSB waveform 302 during the IFC phase. Based on the first and second magnitude differences, the processor 120 determines whether an IEDF is critically compensated, overcompensated, or undercompensated to control the controller 604. The controller 604 is controlled to achieve a predetermined result, such as the predetermined difference 616, of critical compensation, overcompensation, or undercompensation of an IEDF to process the substrate S in a desirable manner, such as to achieve high aspect ratio (HAR) etching of the substrate S. For example, the substrate S is processed in a uniform manner across a radius of the substrate S when critical compensation is achieved.

[0106] In one embodiment, each of the comparator 604, the average determinator 606, and the difference calculator 608 is a separate integrated circuit, such as a PLD or an ASIC.

[0107] In an embodiment, the controller 601 is integrated within the host computer 106 (Figure 1). For example, the functions described herein as being performed by the controller 601 are performed by the processor 120.

[0108] In an embodiment, instead of the average determinator 606, another statistical determinator, such as a median value determinator, is used. The median value determinator calculates a median of the first and second differences.

[0109] In one embodiment, instead of the first and second differences, any other number of differences, such as three, four and five differences is used and each of the differences of the other number is associated with a different cycle of the NSB waveform 302.

[0110] Figure 7 is an embodiment of a graph 700 to illustrate a determination of a DC bias of the substrate support 128 (Figure 1) based on differences between voltage values of an NSB waveform 702 and estimated voltage values of a voltage waveform 704 at the substrate S. The graph 700 plots voltage on a y-axis and time t on an x-axis. The NSB waveform 702 is an example of the main NSB waveform 164 or the TES NSB waveform 168 (Figure 1).

[0111] The time t of the x-axis of the graph 700 has values t2a, t2b, t2c, t2d, t2e, t2f, t2g, t2h, t2i, t2j, t2k, and t21 in a progressively increasing manner during a cycle n of the NSB waveform 702. For example, the time value t2b occurs after the time value t2a and so on until the time value t21 occurs after the time value t2k.

[0112] For example, the processor 120 determines an inflection point 706 of the NSB waveform 702 and another inflection 708 of the NSB waveform 702 in the same manner in which the inflection points 210 and 212 (Figure 2A) from the NSB waveform 202 (Figure 2A) or the inflection points 304 and 306 (Figure 3A) are determined from the NSB waveform 302 (Figure 3 A). The processor 120 identifies that the inflection point 706 occurs at the time t2b and the inflection point 708 occurs at the time t2d. For example, the processor 120 determines, such as identifies, that a voltage value at the inflection point 706 is measured by a V&I sensor, such as the V&I sensor 102 or 104 (Figure 1), at the time t2b and a voltage value at the inflection point 708 is measured by the V&I sensor at the time t2d. The processor 120 further determines that at the time t2b of occurrence of the inflection point 706 during the cycle n of the NSB waveform 702, a voltage of the voltage waveform 704 transitions from being negative to positive and at the time t2d of occurrence of the inflection point 708 during the cycle n of the NSB waveform 702, a voltage of the voltage waveform 704 transitions from being positive to negative.

[0113] The processor 120 estimates negative voltage values of the voltage waveform 704 between the times t2a and t2b, estimates positive voltage values of the voltage waveform 704 between the times t2b and t2d, and estimates negative values of the voltage waveform 704 between the times t2d and t21. For example, the processor 120 estimates the negative voltage values of the voltage waveform 704 to be within a first predetermined range from voltage values of the NSB waveform 702 between the times t2a and t2b. In the example, the processor 120 estimates the positive voltage values of the voltage waveform 704 to be within a second predetermined range from voltage values of the NSB waveform 702 between the times t2b and t2d. The processor 120 estimates the negative voltage values of the voltage waveform 704 to be within a third predetermined range from voltage values of the NSB waveform 702 between the times t2d and t21. To illustrate, the third predetermined range is smaller than the second predetermined range and the first predetermined range is smaller than the third predetermined range. The processor 120 generates the voltage waveform 704 having the estimated voltage values from the time t2a to the time t2k.

[0114] The processor 120 further determines a statistical value, such as an average or a median, of the estimated voltage values of the voltage waveform 704 from the time t2a to the time t21. The processor 120 further determines a statistical value, such as an average or a median, of the voltage values of the NSB waveform 702 from the time t2a to the time t21. The processor 120 determines a difference between the statistical value of the voltage values of the NSB waveform 702 and the statistical value of the estimated voltage values of the voltage waveform 704 during the cycle n to determine the DC bias of the substrate support 128. Theprocessor 120 compares the DC bias with a predetermined DC bias to control processing of the substrate S in a uniform manner. For example, upon determining that the DC bias is outside a preset range from the predetermined DC bias, the processor 120 controls a DC bias voltage source (not shown) that is coupled to the substrate support 128 to apply the DC bias to the substrate support 128. The DC bias is applied to increase the DC bias to securely hold the substrate S on the top surface of the substrate support 128.

[0115] It should be noted that a charging phase during which the plasma chamber 110 (Figure 1) is charged by voltage of the NSB waveform 702 occurs between the times t2a and t2d. During a time interval between the times t2d4 and t2e, a discharging phase during which the plasma chamber 110 is discharged by voltage of the NSB waveform 702 occurs. Also, during a time interval between the times t2e and t21, an ion flux compensation phase of the NSB waveform 702 occurs. The charging phase, the discharging phase, and the ion flux compensation phase occur once during the cycle n of the NSB waveform 702. Also, the charging phase, the discharging phase, and the ion flux compensation phase occur once again during the cycle (n+1) of the NSB waveform 702.

[0116] Figure 8 is a diagram of an embodiment of a system 800 to illustrate use of an NSB supply 804 for generating an NSB waveform 806. The NSB waveform 806 is an example of the main NSB waveform 164 or the TES NSB waveform 168 (Figure 1). The NSB supply 804 is an example of the main NSB supply 148 (Figure 1) or the TES NSB supply 150 (Figure 1). The system 800 is also used to illustrate a cycle of occurrence of charging of the plasma chamber 110 followed by an occurrence of discharging including an energy recovery, such as a magnetic energy recovery, which is followed by an occurrence of IFC during each cycle of the NSB waveform 806. The cycle of occurrence of the charging of the plasma chamber 110, the occurrence of the discharging, and the occurrence of IFC repeats for multiple times.

[0117] The system 800 includes a direct current (DC) voltage source Vdc, the processor 120, an IFC circuit 808, a high-voltage (HV) charger 810, an ER circuit 812, the plasma chamber 110, and a voltage and current (V&I) sensor system 814. The DC voltage source Vdc is an example of the DC voltage source 112 or the main DC voltage source or the TES DC voltage source.

[0118] The HV charger 810 is sometimes referred to herein as a charger circuit. The system 800 further includes a diode 816, a capacitor 820, an ER diode 822, a charging diode 824, a resonant inductor 826, and an IFC diode 828. A combination of the HV charger 810, the charging diode 824, the resonant inductor 826, the ER diode 822, the ER circuit 812, the IFC diode 828, and the IFC circuit 808 is an example of the main CM 116 or the TES CM 118. The capacitor 820 is an example of the storage capacitor 138 (Figure 1) or the main storage capacitoror the TES storage capacitor. The capacitor 820 is sometimes referred to herein as an energy storage circuit or a storage cell, such as a battery. An example of the V&I sensor 814 includes a voltage and current sensor. The V&I sensor 814 is an example of the V&I sensor 102 or 104 (Figure 1).

[0119] The processor 120 is coupled to the DC voltage source Vdc. Also, the processor 120 is coupled to the IFC circuit 808, the HV charger 810, the ER circuit 812, and the V&I sensor 814. The DC voltage source Vdc is coupled in series with the diode 816 to form a series circuit. The series circuit of the DC voltage source Vdc and the diode 816 is coupled in parallel to the capacitor 820. The capacitor 820 is coupled in parallel to the HV charger 810. The capacitor 820 is also coupled to an output 828 of the ER circuit 812. The HV charger 810 has an output 830 that is coupled in series to the charging diode 824, which is coupled to the IFC diode 828 at a point 832. The IFC diode 828 is coupled to the IFC circuit 808.

[0120] Also, the point 832 is coupled to the resonant inductor 826, which is coupled to a point 834. The point 834 is coupled via an RF connection 836 to the lower electrode of the plasma chamber 110. The RF connection 836 is an example of the main RF connection 140 or the TES RF connection 142 (Figure 1). The point 834 is coupled to the ER diode 822 and to the V&I sensor 814. The ER diode 822 is coupled to an input 838 of the ER circuit 812 via a high voltage line 840.

[0121] To initiate an occurrence of a charging phase for charging the plasma load, the processor 120 generates and sends a charging control signal 842 for a first time to the HV charger 810 to control the HV charger 810. The charging control signal 842 is an example of a charging control signal, such as the charging control signal 158 or 160 (Figure 1). The charging control signal 842 indicates a primary amount of voltage, such as a positive voltage, to be output from the HV charger 810. The DC voltage source Vdc generates a voltage signal 844 that is applied via the diode 816, which is forward biased, to the HV charger 810. Upon receiving the voltage signal 844 and the charging control signal 842, the HV charger 810 modifies, such as increases or decreases, a voltage of the voltage signal 844 to output another voltage signal 846 having the primary amount of voltage indicated in the charging control signal 842. The voltage signal 844 is an example of the DC voltage waveform 154 (Figure 1). The voltage signal 846 is sent via the charging diode 824, which is forward biased, and the point 832 to the resonant inductor 826. The resonant inductor 826 modifies an impedance of the voltage signal 846 to output the NSB waveform 806 having RF power and provides the NSB waveform 806 to the lower electrode of the plasma chamber 110 via the RF connection 836.

[0122] The NSB waveform 806 having the RF power is provided to the lower electrode of the plasma chamber 110 to charge the plasma load. For example, when the one ormore process gases, such as fluorine containing gas or an oxygen containing gas or a combination thereof, are supplied to the plasma chamber 110 in addition to the NSB waveform 806, plasma is generated or stricken within the plasma chamber 110 to process the substrate S placed within the plasma chamber 110.

[0123] It should be noted that a charging time of the charging phase is fixed. For example, the plasma load is charged for a fixed amount of dwell time during each occurrence of charging. To illustrate, upon receiving the charging control signal 842 indicating the primary amount of voltage, the HV charger 810 outputs the voltage signal 846 having the primary amount of voltage for the fixed amount of dwell time. When the voltage signal 846 having the primary amount of voltage is generated for the fixed amount of dwell time, the plasma load is charged by the NSB waveform 806 for the fixed amount of dwell time during the occurrence of charging. It should be noted that until the plasma load is charged, the ER diode 822 is reversed biased and the point 834 is electrically decoupled from the ER circuit 812. For example, the ER diode 822, when reverse biased, creates an open circuit between the ER circuit 812 and the point 834. Also, during the fixed amount of dwell time, the IFC diode 828 is reverse biased and there is no ion flux compensation by the IFC circuit 808.

[0124] When the fixed amount of dwell time has passed, the ER diode 822 becomes forward biased, the charging diode 824 becomes reverse biased, and the IFC diode 828 is reverse biased. For example, after the plasma load is charged in the fixed amount of dwell time, a voltage at the point 832 is greater than a voltage at the output 830 of the HV charger 810. To illustrate, after the fixed amount of dwell time has passed, the processor 120 generates a charging control signal 850 indicating a secondary amount of voltage, such as a negative voltage, to be output from the HV charger 810, and sends the charging control signal 850 to the HV charger 810. As an example, the charging control signal 850 is a signal of the control signal set 157 (Figure 1). Upon receiving the charging control signal 850, the HV charger 810 modifies the voltage signal 846 to have the secondary amount of voltage from the primary amount of voltage. When the voltage signal 846 is modified to have the secondary amount of voltage, the charging diode 824 becomes reverse biased from being forward biased. When the charging diode 824 becomes reverse biased, the plasma load is no longer being charged based on the primary voltage of the voltage signal 846. Also, when the ER diode 822 becomes forward biased, recovery of RF energy stored in the plasma chamber 110 as a result of the charging initiates.

[0125] The processor 120 determines based on a clock that counts whether the fixed amount of dwell time has passed after the charging control signal 842 is generated. The charging control signal 842 is generated to control the HV charger 810 to charge the plasma load. The fixed amount of dwell time is sometimes referred to herein as a predetermined charging time. Inresponse to determining that the fixed amount of dwell time has passed, to initiate an occurrence of the energy recovery, the processor 120 sends a discharging control signal 852 for a first time to the ER circuit 812 to control the ER circuit 812. The discharging control signal 852 is an example of a discharging control signal of the control signal set 157 (Figure 1). The ER circuit 812 is controlled to initiate recovery of the RF energy from the plasma chamber 110 via the high voltage line 840. For example, upon receiving the discharging control signal 852, the input 838 of the ER circuit 812 receives RF energy stored within the plasma chamber 110, via the point 834, the high voltage line 840, and the ER diode 822, which is forward biased. When the ER diode 822 becomes forward biased after the fixed amount of dwell time has passed, the RF energy stored in the plasma chamber 110 is recovered by the ER circuit 812 via the point 834, the high voltage line 840, and the ER diode 822. The processor 120 controls one or more switches of the ER circuit 812 to store the RF energy in one or more inductors of the ER circuit 812. The processor 120 further controls the one or more switches of the ER circuit 812 to transfer the RF energy stored in the one or more inductors via the output 828 to the capacitor 820. The RF energy is transferred to the capacitor 820 for storage of the RF energy within the capacitor 820. The RF energy is stored in the capacitor 820 during the occurrence of the energy recovery.

[0126] When the RF energy is recovered, the capacitor 820 is charged and the ER diode 822 becomes reversed biased after being forward biased. The V&I sensor 814 measures a voltage at the point 834 to output a measurement signal 854 and sends the measurement signal 854 to the processor 120. The processor 120 determines, based on the measurement signal 854, whether the voltage at the point 834 is less than a predetermined threshold. For example, the processor 120 compares the voltage indicated by the measurement signal 854 with the predetermined threshold to determine whether the voltage is lower than the predetermined threshold. Upon determining that the voltage at the point 834 is less than the predetermined threshold, the processor 120 determines that the ER diode 822 is reversed biased. When it is determined that the ER diode 822 is reversed biased, the processor 120 determines to initiate an occurrence of the IFC. The occurrence of the IFC is initiated to control the ion flux of plasma within the plasma chamber 110. Also, after the RF energy is recovered, the charging diode 824 is still reverse biased and the IFC diode 828 becomes forward biased.

[0127] To initiate the occurrence of the IFC phase, the processor 120 sends an IFC control signal 856 for a first time to the IFC circuit 808 to control an amount of voltage that is output from the IFC circuit 808. In response to receiving the ion flux compensation control signal 856, the IFC circuit 808 achieves the amount of voltage indicated within the ion flux compensation control signal 856 to generate a current signal 858. The current signal 858 is sentfrom the IFC circuit 808 via the diode 828, which is forward biased, the point 832, the resonant inductor 826, the point 834, and the RF connection 836 to the lower electrode of the plasma chamber 110. When the current signal 858 is generated, IFC is achieved. For example, ion flux of plasma within the plasma chamber 110 is tuned, such as modified, with a change in an amount of current of the current signal 858.

[0128] The IFC occurs until a next occurrence of charging of the plasma load. For example, the IFC occurs until the processor 120 sends the charging control signal 842 to the DC voltage source Vdc for a second time and until the processor 120 sends another control signal 858 to the IFC circuit 808. After sending the charging control signal 842 for the second time to charge the plasma load, the processor 120 sends the discharging control signal 852 to the ER circuit 812 for a second time to recover RF energy from the plasma chamber 110 for the second time. It should be noted that the RF energy stored in the capacitor 820 during the first time of occurrence of the RF energy recovery is used to charge the plasma load for the second time. For example, the charge stored in the capacitor 820 based on the RF energy recovered from the plasma chamber 110 during the first time of occurrence of the RF energy recovery creates a voltage at the point 803. The voltage at the point 803 generates a voltage signal that is supplied to the HV charger 810. The HV charger 810 modifies, such as increases or decrease, the voltage at the point 803 to output a voltage signal for the second time. The voltage signal is provided via the diode 824 and the resonant inductor 826 in the same manner in which the voltage signal 846 is supplied for the first time to process the substrate S in the plasma chamber 110. Also, after sending the discharging control signal 852 for the second time, the processor 120 sends IFC control signal 856 for a second time to achieve IFC for the second time. In this manner, multiple occurrences, such as instances, of the charging of the plasma chamber 110, the magnetic energy recovery, and the ion flux compensation take place.

[0129] In an embodiment, the resonant inductor 826 is a portion of the NSB supply 804 and is included within the NSB supply 804.

[0130] It should be noted that the methods, described herein, of estimating wafer voltage are not limited to be applied using the system 800. The methods, described herein, are applied to other resonant topologies or systems in which power is delivered to a plasma chamber, such as the plasma chamber 110, through an inductor-capacitor (LC) resonant circuit. The NSB supply 804 illustrated in Figure 8 is one example of a power supply.

[0131] Embodiments described herein may be practiced with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments can also be practiced in distributed computingenvironments where tasks are performed by remote processing hardware units that are linked through a network.

[0132] In some embodiments, a controller, described herein, is a part of a system, which may be part of the above-described examples. Such systems include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems are integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and / or the type of system, is programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks coupled to or interfaced with a system.

[0133] Broadly speaking, in a variety of embodiments, the controller is defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), defining the parameters, the factors, the variables, etc., for carrying out a particular process on or for a semiconductor wafer or to a system. The program instructions are, in some embodiments, a part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0134] The controller, in some embodiments, is a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller is in a “cloud” or all or a part of a fab host computer, which allows for remote access of the wafer processing. The computer enables remote access to the system to monitor current progress of fabrication operations, examines a history of past fabrication operations, examines trends or performance metrics from a plurality offabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.

[0135] In some embodiments, a remote computer (e.g. a server) provides process recipes to a system over a network, which includes a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify the parameters, factors, and / or variables for each of the processing steps to be performed during one or more operations. It should be understood that the parameters, factors, and / or variables are specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the controller is distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0136] Without limitation, in various embodiments, example systems to which the methods are applied include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that is associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0137] It is further noted that in some embodiments, the above-described operations apply to several types of plasma reactor chambers, e.g., a plasma chamber including an inductively coupled plasma (ICP) reactor, a capacitively coupled plasma (CCP) reactor, a transformer coupled plasma reactor, conductor tools, dielectric tools, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, one or more RF generators are coupled to an inductor within the ICP reactor. Examples of a shape of the inductor include a solenoid, a dome-shaped coil, a flat-shaped coil, etc.

[0138] As noted above, depending on the process step or steps to be performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, toolslocated throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0139] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are those physically manipulating physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations.

[0140] Some of the embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.

[0141] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained over the computer network. When data is obtained over the computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0142] One or more embodiments can also be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit, e.g., a memory device, etc., that stores data, which is thereafter be read by a computer system. Examples of the non-transitory computer-readable medium include hard drives, network attached storage (NAS), read-only memory (ROM), random access memory (RAM), compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes a computer-readable tangible medium distributed over a network-coupled computer system so that the computer- readable code is stored and executed in a distributed fashion.

[0143] Although the method operations above were described in a specific order, it should be understood that in various embodiments, other housekeeping operations are performed in between operations, or the method operations are adjusted so that they occur at slightly different times, or are distributed in a system which allows the occurrence of the method operations at various intervals, or are performed in a different order than that described above.

[0144] It should further be noted that in an embodiment, one or more features from any embodiment described above are combined with one or more features of any otherembodiment without departing from a scope described in various embodiments described in the present disclosure.

[0145] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

IN THE CLAIMS1. A method for controlling a nonsinusoidal bias supply, comprising: receiving a voltage waveform measured at an output of the nonsinusoidal bias power supply coupled to a plasma chamber in which a substrate is processed; determining a plurality of inflection points from the voltage waveform; identifying, from the plurality of inflection points, that a wafer voltage at the substrate becomes positive from negative and becomes negative from positive; and controlling the nonsinusoidal bias supply based on the wafer voltage.

2. The method of claim 1, wherein the plasma chamber lacks a voltage sensor for obtaining the wafer voltage at the substrate.

3. The method of claim 1, wherein the plurality of inflection points include a first inflection point and a second inflection point, wherein said determining the plurality of inflection points includes: computing a derivative of the voltage waveform to output a first derivative waveform; computing a derivative of the first derivative waveform to output a second derivative waveform; and filtering the second derivative waveform to output a filtered voltage waveform; identifying a first time at which the first inflection point occurs from the filtered voltage waveform; and identifying a second time at which the second inflection point occurs from the filtered voltage waveform.

4. The method of claim 1, wherein the voltage waveform is a nonsinusoidal waveform, wherein the plurality of inflection points include a first inflection point and a second inflection point, wherein at the first inflection point, the wafer voltage becomes positive from negative and at the second inflection point, the wafer voltage becomes negative from positive.

5. The method of claim 1, wherein the plurality of inflection points include a first inflection point and a second inflection point, the method further comprising: determining a first voltage difference between a voltage at a start of a charging phase of the plasma chamber and a voltage at the first inflection point; determining a second voltage difference between the voltage at the first inflection point and a peak voltage during the charging phase; determining a third voltage difference between a voltage at a start of a discharging phase of the plasma chamber and a voltage at the second inflection point;determining a fourth voltage difference between a voltage at the second inflection point and a voltage at a start of an ion flux compensation phase; determining whether a first magnitude of a difference between the first voltage difference and the second voltage difference is greater than, equal to, or less than a second magnitude of a difference between the third voltage difference and the fourth voltage difference; determining whether an ion energy distribution in the plasma chamber is critically compensated, undercompensated, or overcompensated based on whether the first magnitude is greater than, equal to, or less than the second magnitude.

6. The method of claim 1, wherein the voltage waveform has a plurality of cycles, the method further comprising: computing a first statistical value from voltages of the voltage waveform; computing a second statistical value from the wafer voltage; determining a direct current (DC) bias from the first statistical value and the second statistical value.

7. The method of claim 1, wherein at each of the plurality of infection points, the wafer voltage is zero.

8. A controller for controlling a nonsinusoidal bias supply, comprising: a processor configured to: receive a voltage waveform measured at an output of the nonsinusoidal bias power supply coupled to a plasma chamber in which a substrate is processed; determine a plurality of inflection points from the voltage waveform; identify, from the plurality of inflection points, that a wafer voltage at the substrate becomes positive from negative and becomes negative from positive; and control the nonsinusoidal bias supply based on the wafer voltage; and a memory device coupled to the processor.

9. The controller of claim 8, wherein the plasma chamber lacks a voltage sensor for obtaining the wafer voltage at the substrate.

10. The controller of claim 8, wherein the plurality of inflection points include a first inflection point and a second inflection point, wherein to determine the plurality of inflection points, the processor is configured to: compute a derivative of the voltage waveform to output a first derivative waveform; compute a derivative of the first derivative waveform to output a second derivative waveform; and filter the second derivative waveform to output a filtered voltage waveform; identify a first time at which the first inflection point occurs from the filtered voltage waveform; and identify a second time at which the second inflection point occurs from the filtered voltage waveform.

11. The controller of claim 8, wherein the voltage waveform is a nonsinusoidal waveform, wherein the plurality of inflection points include a first inflection point and a second inflection point, wherein at the first inflection point, the wafer voltage becomes positive from negative and at the second inflection point, the wafer voltage becomes negative from positive.

12. The controller of claim 8, wherein the plurality of inflection points include a first inflection point and a second inflection point, wherein the processor is configured to: determine a first voltage difference between a voltage at a start of a charging phase of the plasma chamber and a voltage at the first inflection point; determine a second voltage difference between the voltage at the first inflection point and a peak voltage during the charging phase; determine a third voltage difference between a voltage at a start of a discharging phase of the plasma chamber and a voltage at the second inflection point; determine a fourth voltage difference between a voltage at the second inflection point and a voltage at a start of an ion flux compensation phase; determine whether a first magnitude of a difference between the first voltage difference and the second voltage difference is greater than, equal to, or less than a second magnitude of a difference between the third voltage difference and the fourth voltage difference; determine whether an ion energy distribution in the plasma chamber is critically compensated, undercompensated, or overcompensated based on whether the first magnitude is greater than, equal to, or less than the second magnitude.

13. The controller of claim 8, wherein the voltage waveform has a plurality of cycles, wherein the processor is configured to: compute a first statistical value from voltages of the voltage waveform; compute a second statistical value from the wafer voltage; determine a direct current (DC) bias from the first statistical value and the second statistical value.

14. The controller of claim 8, wherein at each of the plurality of infection points, the wafer voltage is zero.

15. A system for controlling a nonsinusoidal bias supply, comprising: the nonsinusoidal bias supply; a plasma chamber having an electrode coupled to the nonsinusoidal bias supply, wherein the plasma chamber is configured to process a substrate; and a controller coupled to the nonsinusoidal bias supply, wherein the controller is configured to: receive a voltage waveform measured at an output of the nonsinusoidal bias power supply; determine a plurality of inflection points from the voltage waveform; identify, from the plurality of inflection points, that a wafer voltage at the substrate becomes positive from negative and becomes negative from positive; and control the nonsinusoidal bias supply based on the wafer voltage.

16. The system of claim 15, wherein the plasma chamber lacks a voltage sensor for obtaining the wafer voltage at the substrate.

17. The system of claim 15, wherein the plurality of inflection points include a first inflection point and a second inflection point, wherein to determine the plurality of inflection points, the controller is configured to: compute a derivative of the voltage waveform to output a first derivative waveform; compute a derivative of the first derivative waveform to output a second derivative waveform; and filter the second derivative waveform to output a filtered voltage waveform; identifying a first time at which the first inflection point occurs from the filtered voltage waveform; andidentify a second time at which the second inflection point occurs from the filtered voltage waveform.

18. The system of claim 15, wherein the voltage waveform is a nonsinusoidal waveform, wherein the plurality of inflection points include a first inflection point and a second inflection point, wherein at the first inflection point, the wafer voltage becomes positive from negative and at the second inflection point, the wafer voltage becomes negative from positive.

19. The controller of claim 15, wherein the plurality of inflection points include a first inflection point and a second inflection point, wherein the controller is configured to: determine a first voltage difference between a voltage at a start of a charging phase of the plasma chamber and a voltage at the first inflection point; determine a second voltage difference between the voltage at the first inflection point and a peak voltage during the charging phase; determine a third voltage difference between a voltage at a start of a discharging phase of the plasma chamber and a voltage at the second inflection point; determine a fourth voltage difference between a voltage at the second inflection point and a voltage at a start of an ion flux compensation phase; determine whether a first magnitude of a difference between the first voltage difference and the second voltage difference is greater than, equal to, or less than a second magnitude of a difference between the third voltage difference and the fourth voltage difference; determine whether an ion energy distribution in the plasma chamber is critically compensated, undercompensated, or overcompensated based on whether the first magnitude is greater than, equal to, or less than the second magnitude.

20. The system of claim 15, wherein the voltage waveform has a plurality of cycles, wherein the controller is configured to: compute a first statistical value from voltages of the voltage waveform; compute a second statistical value from the wafer voltage; determine a direct current (DC) bias from the first statistical value and the second statistical value.

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