Display substrate and display apparatus

Abstract

Provided are a display substrate and a display apparatus. The display substrate comprises: a base substrate (BS); a plurality of pixel circuits (200) located on the base substrate (BS); a first planarization layer (201) located on the base substrate (BS); a plurality of first via holes (V1) penetrating through the first planarization layer (201); and a plurality of first electrodes (211) located on the side of the first planarization layer (201) away from the base substrate (BS), at least one first electrode (211) among the plurality of first electrodes (211) having a main body portion (P1), and the orthographic projection of the main body portion (P1) on the base substrate (BS) not overlapping with the orthographic projections of the plurality of first via holes (V1) on the base substrate (BS), thereby improving the display effect.

Description

Display substrate and display device Technical Field

[0001] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0002] Active-matrix organic light-emitting diode (AMOLED) display devices have advantages such as self-illumination, wide color gamut, high contrast, flexibility, high response, and adaptability, and have broad application prospects.

[0003] With the rapid development of AMOLED display devices, customers' demand for large-size AMOLED products is becoming increasingly prominent. Summary of the Invention

[0004] This disclosure provides a display substrate and a display device to improve display performance.

[0005] In a first aspect, embodiments of this disclosure provide a display substrate, comprising: a substrate; a first planarization layer located on the substrate; a plurality of first vias penetrating the first planarization layer; and a plurality of first electrodes located on a side of the first planarization layer away from the substrate; wherein at least one of the plurality of first electrodes has a main body portion, and the orthographic projection of the main body portion on the substrate does not overlap with the orthographic projection of the plurality of first vias on the substrate.

[0006] For example, at least one of the plurality of first electrodes has a clearance opening, the orthographic projection of the clearance opening on the substrate overlaps with the orthographic projection of at least one of the plurality of first vias on the substrate.

[0007] For example, the orthographic projection of at least one of the plurality of first electrodes on the substrate does not overlap with the orthographic projection of at least one first via located in the edge enclosure region of the first electrode on the substrate.

[0008] For example, at least one of the plurality of first electrodes also has at least one clearance notch, and the orthographic projection of the clearance notch on the substrate and the orthographic projection of at least one first via adjacent to the first electrode on the substrate do not overlap.

[0009] For example, the first electrode has a clearance notch on each side of the clearance opening.

[0010] For example, the display substrate further includes a pixel defining layer, wherein the pixel defining layer is located on the plurality of first electrodes and has a plurality of pixel openings exposing the plurality of first electrodes, wherein the pixel openings at at least one first electrode having a clearance opening are annular, and the orthographic projection of the inner region of the annulus on the substrate overlaps with the orthographic projection of at least one first via located in the edge enclosure region of the first electrode on the substrate.

[0011] For example, the first electrode with the clearance opening corresponds to the blue sub-pixel.

[0012] For example, the plurality of first electrodes includes a first electrode without a clearance opening, the size of the pixel opening corresponding to the first electrode without a clearance opening being smaller than the size of the pixel opening corresponding to the first electrode with a clearance opening.

[0013] For example, the first electrode without an avoidance opening corresponds to either a red sub-pixel or a green sub-pixel.

[0014] For example, the area of ​​a ring-shaped pixel opening is larger than the area of ​​the clearance opening of the first electrode corresponding to that pixel opening.

[0015] For example, the area of ​​a ring-shaped pixel opening is at least three times larger than the area of ​​the clearance opening of the first electrode corresponding to that pixel opening.

[0016] For example, the display substrate also includes signal lines and a plurality of pixel circuits, wherein the plurality of pixel circuits and the signal lines are located on the substrate, the signal lines are connected to at least one of the plurality of pixel circuits, and the orthographic projection of the clearance opening on the substrate overlaps with the orthographic projection of the signal lines on the substrate.

[0017] For example, the display substrate further includes a plurality of pixel circuits, a plurality of connection electrodes, and a second planarization layer, wherein the plurality of pixel circuits are located on the substrate, the first planarization layer is located on the plurality of pixel circuits, the plurality of connection electrodes are respectively connected to the plurality of pixel circuits through a plurality of first vias penetrating the first planarization layer; the second planarization layer is located on the plurality of connection electrodes, the first electrodes are connected to their corresponding pixel circuits through second vias penetrating the second planarization layer, and the orthographic projection of the second vias on the substrate overlaps with the orthographic projection of the clearance opening on the substrate.

[0018] For example, the first electrode has a protrusion at the second via that extends toward the interior of the clearance opening.

[0019] For example, the display substrate also includes multiple signal lines located on the substrate. The orthographic projection of the main body on the substrate and the orthographic projection of the signal lines on the substrate have at least two overlapping regions, and the two overlapping regions are independent of each other.

[0020] For example, the two overlapping regions are spaced apart from each other.

[0021] For example, the display substrate also includes a light-emitting functional layer, the orthographic projection of which overlaps with the orthographic projection of the clearance opening on the substrate.

[0022] For example, the display substrate also includes a second electrode located on the light-emitting functional layer, and the orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the clearance opening on the substrate.

[0023] For example, the first electrode is ring-shaped.

[0024] For example, the outer edge of the first electrode is rectangular or has a missing corner.

[0025] Secondly, embodiments of this disclosure also provide a display substrate, comprising: a substrate; a plurality of signal lines located on the substrate; and a plurality of first electrodes located on the side of the plurality of signal lines away from the substrate, wherein at least one of the plurality of first electrodes has a main body portion, and the orthographic projection of the main body portion on the substrate and the orthographic projection of the signal lines on the substrate have at least two overlapping regions, the two overlapping regions being independent of each other.

[0026] For example, the two overlapping regions are spaced apart from each other in the direction of extension of the signal line.

[0027] For example, the display substrate further includes a first planarization layer and a plurality of first vias, wherein the first planarization layer is located on the substrate, the plurality of first vias penetrate the first planarization layer, and the orthographic projection of at least one of the plurality of first electrodes on the substrate does not overlap with the orthographic projection of at least one first via located in the edge enclosure area of ​​the first electrode on the substrate.

[0028] For example, at least one of the plurality of first electrodes has a clearance opening, the orthographic projection of the clearance opening on the substrate overlaps with the orthographic projection of at least one of the plurality of first vias on the substrate.

[0029] For example, the display substrate further includes a plurality of pixel circuits, a plurality of connection electrodes, and a second planarization layer, wherein the plurality of pixel circuits are located on the substrate, the first planarization layer is located on the plurality of pixel circuits, the plurality of connection electrodes are respectively connected to the plurality of pixel circuits through a plurality of first vias penetrating the first planarization layer; the second planarization layer is located on the plurality of connection electrodes, the first electrodes are connected to their corresponding pixel circuits through second vias penetrating the second planarization layer, and the orthographic projection of the second vias on the substrate overlaps with the orthographic projection of the clearance opening on the substrate.

[0030] This disclosure also provides a display device, including any of the display substrates described in the first or second aspect above. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0032] Figure 1 is a plan view of a display substrate.

[0033] Figure 2 is a cross-sectional view along line M1-M2 in Figure 1.

[0034] Figure 3 is a plan view of a display substrate provided in an embodiment of this disclosure.

[0035] Figure 4 is a cross-sectional view along line M3-M4 in Figure 3.

[0036] Figure 5 is a plan view of a display substrate provided in an embodiment of this disclosure.

[0037] Figure 6 is a cross-sectional view along line M5-M6 in Figure 5.

[0038] Figure 7 is a plan view of a display substrate provided in an embodiment of this disclosure.

[0039] Figure 8 is a cross-sectional view along line M7-M8 in Figure 7.

[0040] Figure 9 is a plan view of a display substrate provided in an embodiment of this disclosure.

[0041] Figure 10 is a plan view of a display substrate provided in an embodiment of the present disclosure.

[0042] Figure 11 is a plan view of a display substrate provided in an embodiment of the present disclosure.

[0043] Figure 12 is a plan view of a display substrate provided in an embodiment of the present disclosure.

[0044] Figure 13 is a plan view of a display substrate provided in an embodiment of the present disclosure.

[0045] Figure 14 is a schematic diagram of a pixel circuit of a display substrate provided in an embodiment of the present disclosure. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0048] Compared to small-sized products such as mobile phones, medium and large-sized display devices suffer greater yield and cost losses due to defects (lower chip count). Therefore, the pixel design of medium and large-sized products must take into account the characteristics of medium and large-sized products, PPI and process difficulty, adjust the design concept, and solve process defects through design optimization to improve the overall product yield.

[0049] Due to differences in product specifications, the area of ​​the subpixel apertures in medium and large-sized products is increased, and the area of ​​the anode is larger than that of the anode in conventional small-sized products such as mobile phones, thus exposing the following problems.

[0050] (1) The increased area of ​​the anode makes it difficult to avoid the bottom drive circuit traces and adapter holes, making it difficult to ensure the flatness of the anode, increasing the difficulty of the process and aggravating the color deviation problem.

[0051] (2) The dark spot defect rate of large-size products (especially blue sub-pixels) is higher than that of small-size products such as mobile phones. The material used to make the anode includes silver. During the anode formation process, silver particles remain. These silver particles can penetrate the light-emitting functional layer, causing a short circuit between the anode and cathode, resulting in dark spots. The larger the area of ​​the sub-pixel, the easier it is to produce grown silver particles. The light-emitting functional layer of the blue sub-pixel, located between the cathode and anode, is the thinnest. Silver particles easily penetrate the light-emitting functional layer of the blue sub-pixel. Approximately 95% of silver particle dark spots occur on the blue sub-pixel, and approximately 5% occur on the green sub-pixel, where the light-emitting functional layer is thicker than that of the blue sub-pixel.

[0052] (3) In the conventional design of a single anode (the anode itself does not have an opening) plus a tailing adapter hole (connected downward through the adapter hole at the tail of the anode), the spacing between anodes is reduced, and the yield loss caused by process residue increases. In addition, under the usual design, in order to improve uniformity for the laser drilling process that may be introduced later, additional pads are required (the pads can be located in the same film layer as the anode, as shown in Figure 11). The size and number of pads are limited, and the process and design are very difficult.

[0053] Figure 1 is a plan view of a display substrate. Figure 2 is a cross-sectional view along line M1-M2 in Figure 1. For clarity, Figure 1 only shows a portion of the structure of the display substrate.

[0054] As shown in Figures 1 and 2, the display substrate includes multiple sub-pixels 100, each sub-pixel 100 including a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. Each pair of the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 emits a different color.

[0055] As shown in Figures 1 and 2, a layer structure LY0 is provided on the substrate BS. A conductive pattern layer LY1 is provided on the layer structure LY0. A first planarization layer 201 is provided on the conductive pattern layer LY1. A conductive pattern layer LY2 is provided on the first planarization layer 201. A second planarization layer 202 is provided on the conductive pattern layer LY2. A plurality of first electrodes 211 are provided on the second planarization layer 202. A pixel defining layer 220 is provided on the plurality of first electrodes 211. The pixel defining layer 220 has pixel openings 221 that expose the first electrodes 211.

[0056] For example, layer structure LY0 and conductive pattern layer LY1 constitute a driving circuit layer. For example, the driving circuit layer includes multiple pixel circuits 200. For example, pixel circuit 200 includes transistors and capacitors. The driving circuit layer can have a conventional structure. The embodiments of this disclosure do not limit the number of transistors and capacitors included in the pixel circuit 200; these can be set as needed.

[0057] Figure 2 shows a plurality of first electrodes 211. A plurality of connection electrodes CE are respectively connected to a plurality of pixel circuits 200 through a plurality of first vias V1 penetrating the first planarization layer 201.

[0058] As shown in Figures 1 and 2, the first electrode 211 is located directly above the first via V1. As a result, the flatness of the first electrode 211 will be affected, leading to color shift and affecting the display effect.

[0059] Figure 1 shows three second vias V2, through which the first electrode 211 is connected to the corresponding pixel circuit 200 via the second vias V2 penetrating the second planarization layer 202. The unfilled rounded rectangles shown in Figure 1 represent first vias V1. Figure 1 shows ten first vias V1.

[0060] The accompanying drawings of embodiments of this disclosure illustrate directions X and Y, both of which are parallel to the main surface of the substrate. The main surface of the substrate is the surface used to fabricate various components. Directions X and Y intersect. Further, for example, direction X is perpendicular to direction Y. Direction Z is perpendicular to the main surface of the substrate. Direction Z is perpendicular to both direction X and direction Y.

[0061] The embodiments disclosed herein are illustrated using the following example: the first sub-pixel 101 is a red sub-pixel (R) emitting red light, the second sub-pixel 102 is a green sub-pixel (G) emitting green light, and the third sub-pixel 103 is a blue sub-pixel (B) emitting blue light. It should be noted that the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 can also emit other colors of light as needed; for example, the first sub-pixel 101 emits red light, the second sub-pixel 102 emits blue light, and the third sub-pixel 103 emits green light.

[0062] The pixel arrangement of the display substrate shown in Figure 1 is arranged in a repeating unit array as shown in Figure 1. Therefore, the pixel arrangement is as follows: In one column of sub-pixels (the column of sub-pixels on the left side of Figure 1), in the Y direction, the first sub-pixel 101 and the second sub-pixel 102 are arranged alternately. In another column of sub-pixels adjacent to this column (the column of sub-pixels on the right side of Figure 1), the third sub-pixel 103 is arranged along the Y direction. In the repeating unit, the first sub-pixel 101 and the second sub-pixel 102 are arranged along the Y direction and are both located on one side of the third sub-pixel 103.

[0063] Figure 3 is a plan view of a display substrate provided in an embodiment of the present disclosure. Figure 4 is a cross-sectional view along line M3-M4 of Figure 3. For clarity, Figure 3 only shows a portion of the structure of the display substrate.

[0064] As shown in Figures 3 and 4, embodiments of this disclosure provide a display substrate, including: a substrate BS, a plurality of pixel circuits 200, a first planarization layer 201, a plurality of connection electrodes CE, a second planarization layer 202, and a plurality of first electrodes 211; the plurality of pixel circuits 200 are located on the substrate BS; the first planarization layer 201 is located on the plurality of pixel circuits 200; the plurality of connection electrodes CE are respectively connected to the plurality of pixel circuits 200 through a plurality of first vias V1 penetrating the first planarization layer 201; the second planarization layer 202 is located on the plurality of connection electrodes CE; the plurality of first electrodes 211 are located on the second planarization layer 202; at least one of the plurality of first electrodes 211 has a clearance opening 216, and the orthographic projection of the first electrode 211 on the substrate BS does not overlap with the orthographic projection of at least one first via V1 located in the edge enclosure region of the first electrode 211 on the substrate BS. The edge enclosure region of the first electrode 211 refers to the region within the outer edge of the first electrode 211. As shown in Figure 3, for the first electrode 211 of the first sub-pixel 101, the edge-enclosed region of the first electrode 211 refers to the area where the first electrode 211 is located. As shown in Figure 3, for the first electrode 211 of the second sub-pixel 102, the edge-enclosed region of the first electrode 211 refers to the area where the first electrode 211 is located. As shown in Figure 3, for the first electrode 211 of the third sub-pixel 103, the edge-enclosed region of the first electrode 211 refers to the sum of the area where the first electrode 211 is located and the area where the clearance opening 216 is located. The clearance opening 216 is located within the edge of the first electrode 211.

[0065] The display substrate provided in the embodiments of this disclosure has at least one first electrode 211 with a clearance opening 216, and the orthographic projection of the first electrode 211 on the substrate BS does not overlap with the orthographic projection of at least one first via V1 located in the edge-enclosed area of ​​the first electrode 211 on the substrate BS. This reduces the impact of the first via V1 on the flatness of the first electrode 211, improves the flatness of the first electrode 211, reduces color shift, and improves the display effect. The clearance opening 216 on the first electrode 211 reduces its area, which can simultaneously reduce dark spot defects.

[0066] Figure 3 shows an example where the orthographic projection of the first electrode 211 on the substrate BS does not overlap with the orthographic projection of a first via V1 located in the edge area of ​​the first electrode 211 on the substrate BS. In other embodiments, the orthographic projection of the first electrode 211 on the substrate BS does not overlap with the orthographic projections of multiple first vias V1 located in the edge area of ​​the first electrode 211 on the substrate BS.

[0067] Compared with the display substrate shown in Figure 1, the first electrode 211 of the display substrate shown in Figure 3 has an avoidance opening 216. The rest can be found in the description of Figure 1, and will not be repeated here.

[0068] As shown in Figures 3 and 4, the orthographic projection of the clearance opening 216 on the substrate BS overlaps with the orthographic projection of at least one first via V1 located in the edge enclosure area of ​​the first electrode 211 on the substrate BS.

[0069] As shown in FIG. 4, the display substrate further includes a pixel defining layer 220, which is located on a plurality of first electrodes 211 and has a plurality of pixel openings 221 exposing the plurality of first electrodes 211. As shown in FIG. 4, the pixel defining layer 220 also includes a cover portion 226. As shown in FIG. 3 and FIG. 4, the cover portion 226 is located in the pixel opening 221. As shown in FIG. 3 and FIG. 4, the orthographic projection of the cover portion 226 on the substrate BS covers the orthographic projection of the first via V1 overlapping with the avoidance opening 216 on the substrate BS.

[0070] Figure 5 is a plan view of a display substrate provided in an embodiment of the present disclosure. Figure 6 is a cross-sectional view along line M5-M6 of Figure 5. For clarity, Figure 5 only shows a portion of the structure of the display substrate.

[0071] For example, as shown in Figures 5 and 6, at least one of the plurality of first electrodes 211 also has at least one clearance notch 218, and the orthographic projection of the clearance notch 218 on the substrate BS does not overlap with the orthographic projection of at least one first via V1 adjacent to the first electrode 211 on the substrate BS. The clearance notch 218 is provided so that the first electrode 211 avoids the first via V1 located at the edge of the first via V1, thereby further improving the flatness of the first electrode 211, reducing color shift, and improving the display effect. The clearance notch 218 further reduces the area of ​​the first electrode 211. The clearance notch is located at the edge of the first electrode 211.

[0072] For example, as shown in Figures 5 and 6, in order to avoid the first through hole V1 at the opposite edge of the first electrode 211, the first electrode 211 has an avoidance notch 218 on each side of the avoidance opening 216.

[0073] For example, as shown in Figures 5 and 6, the pixel opening 221 at at least one first electrode 211 with the clearance opening 216 is annular. The orthographic projection of the inner region (covering portion 226) of the annulus on the substrate BS overlaps with the orthographic projection of at least one first via V1 located in the edge enclosure region of the first electrode 211 on the substrate BS. The covering portion 226 is provided at the clearance opening 216 to remove the middle portion of the pixel opening 221, forming an annular pixel opening 221, further improving the display effect.

[0074] The embodiments of this disclosure use a first electrode 211 having one clearance opening 216 as an example. In other embodiments, the first electrode 211 may have multiple clearance openings 216. When there are multiple clearance openings 216, the shape of the first electrode 211 may be referred to as annular with respect to each clearance opening 216. That is, for the first electrode 211, the annular portion may have an opening.

[0075] When the first electrode 211 has multiple clearance openings 216, the pixel defining layer (PDL) can correspondingly provide multiple cover portions 226. The positions of the cover portions 226 correspond to the positions of the clearance openings 216, and the number of cover portions 226 is the same as the number of clearance openings 216. With multiple clearance openings 216 and multiple cover portions 226, for each cover portion 226, the pixel opening 221 can be described as annular; that is, for the pixel opening 221, the annular portion can have an opening.

[0076] As shown in Figure 3, in the X direction, the distances between the clearance opening 216 and the edge of the first electrode 211 are distance D1 and distance D2, respectively. Distances D1 and D2 can be greater than or equal to 1 micrometer, depending on the process limitations.

[0077] As shown in Figure 3, in the Y direction, the distances between the clearance opening 216 and the edge of the first electrode 211 are distance D3 and distance D4, respectively. Distance D3 is generally greater than distance D1 and greater than distance D2. Distance D4 is greater than distance D1 and greater than distance D2.

[0078] As shown in Figure 3, the minimum distance between the orthographic projection of the cover portion 226 on the substrate and the orthographic projection of the clearance opening 216 on the substrate is distance D7, and the distance between the outer edge of the pixel opening 221 and the outer edge of the first electrode 211 is D6. For example, distance D7 is less than distance D6 to reduce the impact on the light extraction efficiency within the pixel opening.

[0079] As shown in Figure 3, the projection overlap width (distance D7) between the cover portion 216 and the first electrode 211 can be smaller than the overlap width (distance D6) between the outer edge of the pixel defining layer 220 and the first electrode 211, so as to reduce the impact on the light emission efficiency within the pixel opening.

[0080] For example, as shown in Figures 3 and 5, the first electrode 211 with the clearance opening 216 corresponds to the blue sub-pixel to reduce dark spot defects. Setting the first electrode 211 of the larger blue sub-pixel to have the clearance opening 216 helps to maximize the flatness of the first electrode 211 and thus maximize the display effect.

[0081] For example, as shown in FIG5, a plurality of first electrodes 211 include first electrodes 211 without clearance openings 216, wherein the size of the pixel opening 221 corresponding to the first electrode 211 without clearance openings 216 is smaller than the size of the pixel opening 221 corresponding to the first electrode 211 with clearance openings 216. FIG5 takes the example of the first electrode 211 of the first sub-pixel 101 without clearance openings 216 and the first electrode 211 of the second sub-pixel 102 without clearance openings 216.

[0082] As shown in Figure 5, the size of the pixel opening 221 of the first sub-pixel 101 is smaller than the size of the pixel opening 221 of the third sub-pixel 103.

[0083] As shown in Figure 5, the size of the pixel opening 221 of the second sub-pixel 102 is smaller than the size of the pixel opening 221 of the third sub-pixel 103.

[0084] As shown in Figure 5, the size of the pixel opening 221 of the second sub-pixel 102 is smaller than the size of the pixel opening 221 of the second sub-pixel 102, but it is not limited to this.

[0085] For example, as shown in Figure 5, the first electrode 211 without the clearance opening 216 corresponds to the red or green sub-pixel. Sub-pixels with smaller areas can remain unchanged without the clearance opening 216 to reduce design changes.

[0086] For example, as shown in Figures 3 and 5, in order to reduce the impact of the clearance opening 216 on the display, the area of ​​the annular pixel opening 221 is larger than the area of ​​the clearance opening 216 of the first electrode 211 corresponding to the pixel opening 221. The pixel opening 221 is the light-emitting area of ​​the sub-pixel.

[0087] For example, as shown in Figures 3 and 5, in order to reduce the impact of the clearance opening 216 on the display, the area of ​​the annular pixel opening 221 is at least three times larger than the area of ​​the clearance opening 216 of the first electrode 211 corresponding to the pixel opening 221.

[0088] For example, as shown in Figures 3 and 5, the display substrate also includes a signal line SL, which is connected to at least one of the multiple pixel circuits 200. To avoid the signal line SL and reduce its load, the orthographic projection of the opening 216 on the substrate BS is avoided from overlapping with the orthographic projection of the signal line SL on the substrate BS. For example, the signal line SL can be at least one of the following in the display substrate: a high-level power supply signal line (a power supply signal line connected to the voltage terminal VDD shown in Figure 14), a low-level power supply signal line (a power supply signal line connected to the voltage terminal VSS shown in Figure 14), an initialization signal line (an initialization signal line connected to the first initialization voltage terminal Vinit1 shown in Figure 14 or an initialization signal line connected to the second initialization voltage terminal Vinit2 shown in Figure 14), a reset signal line (a reset control signal line providing the first reset control signal Re shown in Figure 14 or a reset control signal line providing the first reset control signal Rst shown in Figure 14), and a gate drive signal line.

[0089] Figure 7 is a plan view of a display substrate provided in an embodiment of this disclosure. Figure 8 is a cross-sectional view along line M7-M8 of Figure 7. For clarity, Figure 7 only shows a portion of the display substrate structure. The second connection electrode CE (connection electrode CE0) and the other connection electrode CE shown in Figure 8 are integral structures. For example, the second connection electrode CE shown in Figure 8 and an adjacent connection electrode CE (e.g., the connection electrode to the left or right of connection electrode CE0) are integral structures, but are not limited thereto. Thus, the second connection electrode CE is also connected to the structure below it through a first via V1.

[0090] For example, as shown in Figures 7 and 8, the first electrode 211 is connected to the corresponding pixel circuit 200 through a second via V2 penetrating the second planarization layer 202. The orthographic projection of the second via V2 on the substrate BS overlaps with the orthographic projection of the clearance opening 216 on the substrate BS. By placing the portion of the first electrode 211 connected to the pixel circuit 200 within the clearance opening 216 (with the second via V2 built in), the space at the clearance opening 216 can be fully utilized, further reducing the area of ​​the first electrode 211 and eliminating the trailing edge of the first electrode 211 (the trailing edge can be seen in Figure 5, where the first electrode corresponds to the second via V2, indicated by the dashed circle C1). This design facilitates increasing the spacing between adjacent first electrodes 211, increasing the process margin, and reducing yield loss caused by process residue. The large process space under this design allows for the placement of pads in the same layer as the first electrodes 211 between adjacent first electrodes 211, which is beneficial for laser drilling. The size and quantity of the connectors offer high flexibility, reducing the difficulty of the process and design, and improving the yield rate.

[0091] For example, as shown in Figure 7, a second through hole V2 and a first through hole V1 are provided within the same clearance opening 216.

[0092] For example, as shown in Figure 7, the first electrode 211 has a protrusion PR extending toward the interior of the clearance opening 216 at the second via V2. The protrusion PR facilitates the connection between the first electrode 211 and the pixel circuit.

[0093] For example, the material of the first planarization layer 201 includes an organic material. For example, organic materials include, but are not limited to, resins.

[0094] For example, the material of the second planarization layer 202 includes organic materials. Organic materials include, for example, resins, but are not limited to.

[0095] For example, as shown in FIG7, similar to the third sub-pixel 103, the first electrode 211 of the first sub-pixel 101 has a clearance opening 216 and the second via V2 is disposed in the clearance opening 216, and the first electrode 211 of the second sub-pixel 102 has a clearance opening 216 and the second via V2 is disposed in the clearance opening 216.

[0096] For example, as shown in FIG8, the display substrate further includes a light-emitting functional layer EL, the orthographic projection of the light-emitting functional layer EL on the substrate BS overlapping the orthographic projection of the clearance opening 216 on the substrate BS. The arrangement of the light-emitting functional layer EL of the display substrate provided in other embodiments can be referred to FIG8, but is not limited thereto.

[0097] For example, as shown in Figure 8, the light-emitting functional layer EL overlaps with the second via V2. The covering part 226 can effectively separate the second via V2 from the light-emitting functional layer EL, avoiding the impact of water vapor erosion caused by the second via V2 on the lifespan of the light-emitting functional layer and the display effect.

[0098] The luminescent functional layer EL overlaps with the clearance opening 216, which facilitates the fabrication process.

[0099] For example, as shown in FIG8, the display substrate further includes a second electrode 212, which is located on the light-emitting functional layer EL. The orthographic projection of the second electrode 212 on the substrate BS overlaps with the orthographic projection of the clearance opening 216 on the substrate BS. The arrangement of the second electrode 212 of the display substrate provided in other embodiments can be seen with reference to FIG8, but is not limited thereto.

[0100] For example, as shown in Figure 8, a first electrode 211, a second electrode 212, and a light-emitting functional layer EL located between them constitute a light-emitting element 300. A sub-pixel 100 includes the light-emitting element 300 and a pixel circuit 200 connected thereto. For example, the light-emitting element 300 may include a light-emitting diode, but is not limited thereto.

[0101] For example, the first electrode 211 is the anode, and the second electrode 212 is the cathode. The materials of the first electrode 211 and the second electrode 212 of the light-emitting element can be selected as needed. In some embodiments, the first electrode 211 may be made of at least one of a transparent conductive metal oxide and silver, but is not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode 211 may have a structure in which three sublayers of ITO-Ag-ITO are stacked. In some embodiments, the second electrode 212 may be a metal with low work function, and may be made of at least one of magnesium and silver, but is not limited thereto.

[0102] For example, the material of the first electrode 211 may include indium tin oxide and silver, but is not limited thereto. For example, the first electrode 211 may include multiple sublayers. For example, the sublayer of the first electrode 211 away from the substrate may be a silver layer. For example, the material of the second electrode 212 may include silver, but is not limited thereto.

[0103] As shown in Figures 3, 4, and 8, the first electrode 211 includes a first electrode portion 2116 and a second electrode portion 2118. The first electrode portion 2116 and the second electrode portion 2118 are respectively provided on both sides of the clearance opening 216. As shown in Figure 3, the first electrode portion 2116 and the second electrode portion 2118 are respectively provided on the left and right sides of the clearance opening 216. The first electrode portion 2116 and the second electrode portion 2118 are an integral structure. The first electrode portion 2116 and the second electrode portion 2118 are different parts of the same first electrode 211.

[0104] Figure 9 is a plan view of a display substrate provided in an embodiment of the present disclosure. Compared with the display substrate shown in Figure 7, the first electrode 221 of the first sub-pixel 101 of the display substrate shown in Figure 9 does not have an avoidance opening, and the first electrode 221 of the second sub-pixel 102 does not have an avoidance opening.

[0105] Figure 10 is a plan view of a display substrate provided in an embodiment of the present disclosure. Compared with the display substrate shown in Figure 3, the shape of the pixel opening 221 of the first sub-pixel 103 of the display substrate shown in Figure 10 is different. The outer shape of the pixel opening 221 of the first sub-pixel 103 of the display substrate shown in Figure 10 is a notched rectangle to improve the flatness of the light-emitting area.

[0106] Figure 11 is a plan view of a display substrate provided in an embodiment of the present disclosure. Compared with the display substrate shown in Figure 10, the shape of the first electrode 211 of each sub-pixel of the display substrate shown in Figure 10 is adjusted, and the trailing is no longer provided. The second via V2 is provided at one corner of the first electrode 211, and the corner adopts a stepped shape to facilitate increasing the distance between the first electrodes of adjacent sub-pixels.

[0107] Figure 12 is a plan view of a display substrate provided in an embodiment of the present disclosure. Compared with the display substrate shown in Figure 10, the shape of the first electrode 211 of the third sub-pixel 103 of the display substrate shown in Figure 10 is adjusted, and the second via V2 is disposed at one corner of the first electrode 211, and the corner adopts a stepped shape to facilitate increasing the distance between the first electrodes of adjacent sub-pixels.

[0108] Figure 13 is a plan view of a display substrate provided in an embodiment of the present disclosure. Compared with the display substrate shown in Figure 3, Figure 13 does not have an avoidance opening 216, but only has a covering portion through the pixel opening 221, so that the pixel opening 221 is annular so that the main body portion P1 of the first electrode 221 avoids the first opening V1.

[0109] Figures 3, 5, 7, and 9 to 13 show the main body portion P1 and the non-main body portion P2 of the first electrode 221. The main body portion P1 is the portion of the first electrode 211 corresponding to the pixel opening 221. The non-main body portion P2 is the portion of the first electrode 221 other than the main body portion P1.

[0110] For example, as shown in Figures 3, 5, 7, and 9 to 13, an embodiment of this disclosure provides a display substrate, including: a substrate BS; a first planarization layer 201 located on the substrate BS; a plurality of first vias V1 penetrating the first planarization layer 201; and a plurality of first electrodes 211 located on the side of the first planarization layer 201 away from the substrate BS; at least one of the plurality of first electrodes 211 has a main body P1, and the orthographic projection of the main body P1 on the substrate BS does not overlap with the orthographic projection of the plurality of first vias V1 on the substrate BS, so as to avoid the influence of the first vias V1 on the light emission, reduce color shift, and improve the display effect.

[0111] For example, as shown in FIG3, an embodiment of the present disclosure provides a display substrate, including: a substrate BS; multiple signal lines SL located on the substrate BS; and multiple first electrodes 211 located on the side of the multiple signal lines SL away from the substrate BS. At least one of the multiple first electrodes 211 has a main body P1. The orthographic projection of the main body P1 on the substrate BS and the orthographic projection of the signal lines SL on the substrate BS have at least two overlapping regions (overlapping region Aa and overlapping region Ab), and the two overlapping regions (overlapping region Aa and overlapping region Ab) are independent of each other. FIG5, FIG7, and FIG9 to FIG13 are not labeled accordingly, but can be referred to FIG3.

[0112] For example, as shown in Figure 3, overlapping regions Aa and Ab are spaced apart by a clearance opening 216. For example, as shown in Figure 3, overlapping regions Aa and Ab are spaced apart in the direction of extension of signal line SL.

[0113] For example, as shown in Figures 3, 5, 7, and 9 to 12, the first electrode 211 is annular. The first electrode 211 is annular due to the provision of the clearance opening 216. The irregularly shaped perforated design of the first electrode 211 improves its flatness by forming an annular shape. In some embodiments, the first electrode 211 is a rectangular ring.

[0114] For example, as shown in Figures 10 to 12, the outer edge of the first electrode 211 is rectangular or a rectangle with a missing corner. The shape of the first electrode 211 can also be a rectangle with a trailing edge. A rectangular outer edge reduces design modifications. A rectangle with a missing corner facilitates increasing the spacing between the first electrodes 211, such as the placement of pads. Figure 11 shows a pad 213, which is co-layered with the first electrode 211 and formed from the same thin film using the same patterning process. The second electrode 212 can be connected to the pad 213, which is connected to a low-level power signal line (VSS) in the underlying film layer. The placement of the pad 213 helps improve the uniformity of the display substrate.

[0115] Figures 2, 4, 6, and 8 also show a connecting element 208, which is connected to the pixel circuitry in the layer structure LY0. Alternatively, the connecting element 208 can also be viewed as a structure within the driving circuit layer. The connecting electrode CE can be directly or indirectly connected to the pixel circuitry.

[0116] Figure 14 is a schematic diagram of the pixel circuit and light-emitting element of a sub-pixel in a display panel provided in some embodiments of this disclosure.

[0117] For example, as shown in Figure 14, sub-pixel P includes pixel circuit 1120 and light-emitting element 1110, wherein pixel circuit 1120 is configured to drive light-emitting element 1110. Constant voltage line 60 is configured to provide a constant voltage to pixel circuit 1120.

[0118] Figure 14 shows a circuit diagram of the pixel circuit of a display substrate provided in some embodiments of the present disclosure. The specific structure of the pixel circuit provided in some embodiments of the present disclosure is briefly described below with reference to Figure 14.

[0119] For example, multiple pixel circuits, including multiple sub-pixels P, are disposed on a substrate BS, as shown in FIG1, and are disposed in the display area R1 of the substrate BS. For example, the gate driving circuit can be configured to output multiple output signals to multiple pixel circuits to control the multiple pixel circuits to generate multiple driving currents to drive the light-emitting elements in the multiple sub-pixels P to emit corresponding light, thereby realizing image display.

[0120] For example, as shown in Figure 14, each sub-pixel P includes a pixel circuit 1120 and a light-emitting element 1110.

[0121] For example, as shown in FIG14, pixel circuit 1120 is configured to generate drive current to control light-emitting element 1110 to emit light.

[0122] For example, the light-emitting element 1110 includes a first electrode E1, a second electrode E2, and a light-emitting functional layer disposed between the first electrode E1 and the second electrode E2, as shown in FIG14. The first electrode E1 of the light-emitting element 1110 is electrically connected to the pixel circuit 1120, and the second electrode E2 of the light-emitting element 1110 is electrically connected to the voltage terminal VSS. When the driving current generated by the pixel circuit 1120 flows through the light-emitting element 1110, the light-emitting functional layer of the light-emitting element 1110 emits light with a brightness corresponding to the magnitude of the driving current.

[0123] For example, the light-emitting element 1110 can be a light-emitting diode (LED). The LED can be a micro LED, an organic light-emitting diode (OLED), or a quantum dot LED (QLED). The light-emitting element 1110 is configured to receive a light-emitting signal (e.g., a driving current) and emit light of an intensity corresponding to the light-emitting signal during operation. The first electrode of the light-emitting element 1110 can be an anode, and the second electrode of the LED can be a cathode. It should be noted that, in the embodiments of this disclosure, the light-emitting functional layer of the light-emitting element 1110 can include the electroluminescent layer itself and common layers located on both sides of the electroluminescent layer. For example, the common layers can include a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer, etc. In practical applications, the specific structure of the light-emitting element 1110 can be designed and determined according to the actual application environment, and is not limited here. For example, the light-emitting element 1110 has a light-emitting threshold voltage, and the light-emitting element 1110 emits light when the voltage between the first electrode and the second electrode of the light-emitting element 1110 is greater than or equal to the light-emitting threshold voltage.

[0124] For example, as shown in Figure 14, the pixel circuit 1120 includes a driving sub-circuit 1121, a data writing sub-circuit 1122, a storage sub-circuit 1123, a compensation sub-circuit 1124, a light emission control sub-circuit 1125, a first reset sub-circuit 1126, and a second reset sub-circuit 1127.

[0125] For example, the driving sub-circuit 1121 includes a first terminal, a second terminal, and a control terminal, and is configured to generate a driving current that drives the light-emitting element 1110 to emit light. For example, as shown in FIG14, the control terminal of the driving sub-circuit 1121 is electrically connected to node Nd1, the first terminal of the driving sub-circuit 1121 is electrically connected to node Nd2, and the second terminal of the driving sub-circuit 1121 is electrically connected to node Nd3.

[0126] For example, as shown in Figure 14, the data writing sub-circuit 1122 is electrically connected to the first terminal (i.e., node Nd2) of the driving sub-circuit 1121 and the data signal line, respectively, and is configured to write the data signal Vdata provided by the data signal line to the first terminal of the driving sub-circuit 1121 in response to the scan signal Ga1.

[0127] For example, as shown in Figure 14, the storage sub-circuit 1123 is electrically connected to the voltage terminal VDD and the control terminal (i.e. node Nd1) of the drive sub-circuit 1121, and is configured to store the compensation signal obtained based on the data signal Vdata.

[0128] For example, as shown in Figure 14, the compensation sub-circuit 1124 is electrically connected to the second terminal (i.e., node Nd3) and node Nd1 of the drive sub-circuit 1121, respectively, and is configured to perform threshold compensation on the drive sub-circuit 1121 in response to the compensation control signal Ga2. The compensation signal stored in the storage sub-circuit 1123 represents the signal obtained after threshold compensation.

[0129] For example, as shown in Figure 14, the light-emitting control sub-circuit 1125 is electrically connected to the first and second terminals of the driving sub-circuit 1121, and is configured to control the driving current generated by the driving sub-circuit 1121 to be transmitted to the light-emitting element 1110 in response to the light-emitting control signal EM. For example, the light-emitting control sub-circuit 1125 includes a first light-emitting control sub-circuit 1125A and a second light-emitting control sub-circuit 1125B. The first light-emitting control sub-circuit 1125A is electrically connected to the first terminal (i.e., node Nd2) and the voltage terminal VDD of the driving sub-circuit 1121, and is configured to turn the connection between the driving sub-circuit 1121 and the voltage terminal VDD on or off in response to the light-emitting control signal EM. The second light-emitting control sub-circuit 1125B is electrically connected to the second terminal (i.e. node Nd3) of the driving sub-circuit 1121 and the first electrode E1 of the light-emitting element 1110, respectively, and is configured to turn on or off the connection between the driving sub-circuit 1121 and the light-emitting element 1110 (e.g., the first electrode E1 of the light-emitting element 1110) in response to the light-emitting control signal EM.

[0130] For example, as shown in Figure 14, the first reset sub-circuit 1126 is electrically connected to node Nd1 (the control terminal of the drive sub-circuit 1121) and the first initialization voltage terminal Vinit1, respectively, and is configured to reset the control terminal (i.e., node Nd1) of the drive sub-circuit 1121 in response to the first reset control signal Re. For example, the first reset sub-circuit 1126 can write the first initialization voltage provided by the first initialization voltage terminal Vinit1 into the control terminal (i.e., node Nd1) of the drive sub-circuit 1121 to reset the control terminal of the drive sub-circuit 1121.

[0131] For example, as shown in Figure 14, the second reset sub-circuit 1127 is electrically connected to the first electrode and the second initialization voltage terminal Vinit2 of the light-emitting element 1110, respectively, and is configured to reset the first electrode E1 of the light-emitting element 1110 in response to the second reset control signal Rst. For example, the second reset sub-circuit 1127 can write the second initialization voltage provided by the second initialization voltage terminal Vinit2 into the first electrode E1 of the light-emitting element 1110 to reset the first electrode E1 of the light-emitting element 1110.

[0132] For example, as shown in Figure 14, the driving sub-circuit 1121 includes a driving transistor T3, the control terminal of the driving sub-circuit 1121 includes the gate of the driving transistor T3, the first terminal of the driving sub-circuit 1121 includes the first electrode of the driving transistor T3, and the second terminal of the driving sub-circuit 1121 includes the second electrode of the driving transistor T3.

[0133] For example, as shown in Figure 14, the data writing sub-circuit 1122 includes a data writing transistor T4. The gate of the data writing transistor T4 is configured to receive a scan signal Ga1. The first terminal of the data writing transistor T4 is electrically connected to the data signal line, and the second terminal of the data writing transistor T4 is electrically connected to the first terminal of the driving transistor T3. That is, the second terminal of the data writing transistor T4 is electrically connected to node Nd2.

[0134] For example, as shown in Figure 14, the storage sub-circuit 1123 includes a storage capacitor Cst. The first end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, that is, the first end (first plate) of the storage capacitor Cst is electrically connected to node Nd1, and the second end (second plate) of the storage capacitor Cst is electrically connected to the voltage terminal VDD.

[0135] For example, as shown in Figure 14, the compensation sub-circuit 1124 includes a compensation transistor T2, the gate of which is configured to receive a compensation control signal Ga2, the second terminal of which is electrically connected to the second terminal of the driving transistor T3, that is, the second terminal of which is electrically connected to node Nd3, and the first terminal of which is electrically connected to node Nd1.

[0136] For example, as shown in Figure 14, the first light-emitting control sub-circuit 1125A includes a first light-emitting control transistor T5, and the second light-emitting control sub-circuit 1125B includes a second light-emitting control transistor T6. For example, the gate of the first light-emitting control transistor T5 is configured to receive a light-emitting control signal EM, the first electrode of the first light-emitting control transistor T5 is connected to the voltage terminal VDD, and the second electrode of the first light-emitting control transistor T5 is electrically connected to the first terminal of the driving sub-circuit 1221, that is, the second electrode of the first light-emitting control transistor T5 is electrically connected to node Nd2; the gate of the second light-emitting control transistor T6 is configured to receive a light-emitting control signal EM, the first electrode of the second light-emitting control transistor T6 is electrically connected to the second terminal of the driving sub-circuit 1221, that is, the first electrode of the second light-emitting control transistor T6 is electrically connected to node Nd3, and the second electrode of the second light-emitting control transistor T6 is electrically connected to the first electrode E1 of the light-emitting element 1110.

[0137] It should be noted that the signals used to control the first light-emitting control transistor T5 and the signals used to control the second light-emitting control transistor T6 may also be different.

[0138] For example, as shown in Figure 14, the first reset sub-circuit 1126 includes a first reset transistor T1, and the second reset sub-circuit 1127 includes a second reset transistor T7. The first electrode of the first reset transistor T1 is electrically connected to the first initialization voltage terminal Vinit1, and the second electrode of the first reset transistor T1 is electrically connected to node Nd1. The gate of the first reset transistor T1 is configured to receive a first reset control signal Re. The first electrode of the second reset transistor T7 is electrically connected to the second initialization voltage terminal Vinit2, and the second electrode of the second reset transistor T7 is electrically connected to the first electrode E1 of the light-emitting element 1110. The gate of the second reset transistor T7 is configured to receive a second reset control signal Rst.

[0139] For example, the voltage value of the second initialization voltage terminal Vinit2 is greater than the voltage value of the first initialization voltage terminal Vinit1. By increasing the second initialization voltage of the second initialization voltage terminal Vinit2, the charge carriers inside the light-emitting element 1110 are reset, reducing charge carrier defects, increasing device stability, and further improving the screen flicker problem. However, the embodiments of this disclosure are not limited to this; the voltage value of the second initialization voltage terminal Vinit2 can also be equal to the voltage value of the first initialization voltage terminal Vinit1.

[0140] For example, the first reset transistor T1, compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second reset transistor T7 are all polysilicon thin-film transistors, for example, low-temperature polysilicon (LTPS) thin-film transistors. The embodiments of the present disclosure are not limited thereto, and at least some of the first reset transistor T1, compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second reset transistor T7 may also be oxide transistors.

[0141] For example, the first reset transistor T1, compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second reset transistor T7 are all P-type transistors. However, the embodiments of the present disclosure are not limited thereto, and at least some of the first reset transistor T1, compensation transistor T2, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second reset transistor T7 may also be N-type transistors.

[0142] For example, one of the voltages output by the voltage terminal VDD and the voltage output by the voltage terminal VSS is a high voltage, and the other is a low voltage. For example, in the embodiment shown in FIG. 14, the voltage output by the voltage terminal VDD is a constant positive voltage; and the voltage output by the voltage terminal VSS is a constant negative voltage. For example, in some examples, the voltage terminal VSS may be grounded.

[0143] For example, in specific implementation, in the embodiments of the present disclosure, the second initialization voltage Vi2 output by the second initialization voltage terminal Vinit2 and the voltage Vss output by the voltage terminal VSS may satisfy the following formula: Vi2 - Vss < VEL, so as to avoid the light-emitting element 1110 from emitting light during the non-light-emitting stage. VEL represents the light-emitting threshold voltage of the light-emitting element 1110.

[0144] 2]It should be noted that in addition to the pixel circuit of 7T1C (7 transistors and 1 capacitor), the pixel circuit may also be a circuit with other suitable structures, such as 7T2C, 8T2C, 9T2C, 6T1C, 6T2C and other circuit structures, which will not be elaborated here.

[0145] The pixel arrangement of the display substrate provided by the embodiments of the present disclosure is not limited to that shown in the figure and can be set as needed.

[0146] The transistors in the pixel circuit of the embodiments of the present disclosure are all thin-film transistors. For example, the conductive pattern layer LY1 and the conductive pattern layer LY2 are both made of metal materials. The layer structure LY0 includes a semiconductor layer and a conductive pattern layer. {

[0147] For example, the conductive pattern layer in the layer structure LY0 can be formed using metallic materials such as nickel or aluminum, but is not limited to these. For example, conductive pattern layers LY1 and LY2 can be formed using materials such as titanium or aluminum, but are not limited to these. For example, conductive pattern layers LY1 and LY2 can be structures formed by three sublayers: Ti / Al / Ti, respectively, but are not limited to these. For example, the substrate can be a glass substrate or a polyimide substrate, but is not limited to these, and can be selected as needed.

[0148] Embodiments of this disclosure also provide a display device including any of the above-described display substrates. For example, the display device can be a medium-to-large-sized or large-sized display product. Of course, the display device can also be applied to small-sized display products.

[0149] For example, display devices include OLEDs or products that include OLEDs. For example, display devices include any product or component with display function, such as televisions, digital cameras, mobile phones, watches, tablets, laptops, navigation devices, and in-vehicle displays, that contain the aforementioned display substrate.

[0150] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: Substrate; A first planarization layer is located on the substrate. Multiple first vias penetrate the first planarization layer; as well as Multiple first electrodes are located on the side of the first planarization layer away from the substrate. In this embodiment, at least one of the plurality of first electrodes has a main body portion, and the orthographic projection of the main body portion on the substrate does not overlap with the orthographic projection of the plurality of first vias on the substrate.

2. The display substrate according to claim 1, wherein, At least one of the plurality of first electrodes has a clearance opening, the orthographic projection of the clearance opening on the substrate overlaps with the orthographic projection of at least one of the plurality of first vias on the substrate.

3. The display substrate according to claim 2, wherein, At least one of the plurality of first electrodes has a projection on the substrate that does not overlap with the projection on the substrate of at least one first via located within the edge enclosure region of the first electrode.

4. The display substrate according to claim 2 or 3, wherein, At least one of the plurality of first electrodes also has at least one clearance notch, and the orthographic projection of the clearance notch on the substrate and the orthographic projection of at least one first via adjacent to the first electrode on the substrate do not overlap.

5. The display substrate according to claim 4, wherein, The first electrode has a clearance notch on each side of the clearance opening.

6. The display substrate according to any one of claims 2-4, further comprising a pixel defining layer, wherein, The pixel defining layer is located on the plurality of first electrodes and has a plurality of pixel openings that expose the plurality of first electrodes. The pixel opening at at least one first electrode with a clearance opening is annular. The orthographic projection of the inner region of the annulus on the substrate overlaps with the orthographic projection of at least one first via located in the edge enclosure region of the first electrode on the substrate.

7. The display substrate according to claim 6, wherein, The first electrode with the clearance opening corresponds to the blue sub-pixel.

8. The display substrate according to claim 7, wherein, The plurality of first electrodes includes a first electrode without a clearance opening, wherein the size of the pixel opening corresponding to the first electrode without a clearance opening is smaller than the size of the pixel opening corresponding to the first electrode with a clearance opening.

9. The display substrate according to claim 8, wherein, The first electrode without an avoidance opening corresponds to either the red or green sub-pixel.

10. The display substrate according to any one of claims 6-9, wherein, The area of ​​the annular pixel opening is larger than the area of ​​the clearance opening of the first electrode corresponding to the pixel opening.

11. The display substrate according to claim 10, wherein, The area of ​​the annular pixel opening is at least three times larger than the area of ​​the clearance opening of the first electrode corresponding to the pixel opening.

12. The display substrate according to any one of claims 2-11, further comprising signal lines and a plurality of pixel circuits, wherein, The plurality of pixel circuits and the signal lines are located on the substrate. The signal line is connected to at least one of the plurality of pixel circuits, and the orthographic projection of the clearance opening on the substrate overlaps with the orthographic projection of the signal line on the substrate.

13. The display substrate according to any one of claims 1-11, further comprising a plurality of pixel circuits, a plurality of connection electrodes, and a second planarization layer, wherein, The plurality of pixel circuits are located on the substrate. The first planarization layer is located on the plurality of pixel circuits. The plurality of connection electrodes are respectively connected to the plurality of pixel circuits through the plurality of first vias penetrating the first planarization layer; The second planarization layer is located on the plurality of connection electrodes. The first electrode is connected to the corresponding pixel circuit through a second via penetrating the second planarization layer, and the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the clearance opening on the substrate.

14. The display substrate according to claim 13, wherein, The first electrode has a protrusion at the second via that extends toward the interior of the clearance opening.

15. The display substrate according to any one of claims 1-11 further includes a plurality of signal lines located on the substrate, wherein the orthographic projection of the main body on the substrate and the orthographic projection of the signal lines on the substrate have at least two overlapping regions, and the two overlapping regions are independent of each other.

16. The display substrate according to claim 15, wherein the two overlapping regions are spaced apart from each other.

17. The display substrate according to any one of claims 2-14, further comprising a light-emitting functional layer, wherein, The orthographic projection of the light-emitting functional layer on the substrate overlaps with the orthographic projection of the avoidance opening on the substrate.

18. The display substrate according to claim 17, further comprising a second electrode, wherein, The second electrode is located on the light-emitting functional layer, and the orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the clearance opening on the substrate.

19. The display substrate according to any one of claims 1-18, wherein, The first electrode is ring-shaped.

20. The display substrate according to any one of claims 1-19, wherein, The outer edge of the first electrode is rectangular or has a missing corner.

21. A display substrate, comprising: Substrate; Multiple signal lines are located on the substrate. Multiple first electrodes are located on the side of the multiple signal lines away from the substrate. In this embodiment, at least one of the plurality of first electrodes has a main body portion, and the orthographic projection of the main body portion on the substrate and the orthographic projection of the signal line on the substrate have at least two overlapping regions, the two overlapping regions being independent of each other.

22. The display substrate according to claim 21, wherein, The two overlapping regions are spaced apart from each other in the direction of extension of the signal line.

23. The display substrate according to claim 21 or 22, further comprising a first planarization layer and a plurality of first vias, wherein, The first planarization layer is located on the substrate, the plurality of first vias penetrate the first planarization layer, and the orthographic projection of at least one of the plurality of first electrodes on the substrate does not overlap with the orthographic projection of at least one first via located in the edge enclosure area of ​​the first electrode on the substrate.

24. The display substrate according to claim 23, wherein, At least one of the plurality of first electrodes has a clearance opening, the orthographic projection of the clearance opening on the substrate overlaps with the orthographic projection of at least one of the plurality of first vias on the substrate.

25. The display substrate according to claim 24, further comprising a plurality of pixel circuits, a plurality of connection electrodes, and a second planarization layer, wherein, The plurality of pixel circuits are located on the substrate. The first planarization layer is located on the plurality of pixel circuits. The plurality of connection electrodes are respectively connected to the plurality of pixel circuits through the plurality of first vias penetrating the first planarization layer; The second planarization layer is located on the plurality of connection electrodes. The first electrode is connected to the corresponding pixel circuit through a second via penetrating the second planarization layer, and the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the clearance opening on the substrate.

26. A display device comprising a display substrate according to any one of claims 1-25.

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