Display panel and display apparatus

Abstract

Disclosed in the present disclosure are a display panel and a display apparatus. The display panel comprises a base substrate (10), a plurality of light-emitting devices (20), and a reference trace layer (30). The reference trace layer (30) comprises a first trace combination (31) at least partially located in a display area (11), and a second trace combination (32) located in a non-display area (12), wherein the first trace combination (31) is connected to cathodes of the light-emitting devices (20), and the second trace combination (32) includes a trace collection portion (321), at least three first connection lines (322), and at least two second connection lines (323), the second connection lines (323) being used for connecting to a display drive chip.

Description

Display panel and display device Cross-references to related applications

[0001] This application claims priority to Chinese patent application No. 202411958768X, filed on December 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0003] AMOLED (Active-matrix organic light-emitting diode) has advantages such as self-emission, wide color gamut, high contrast, flexibility, and high response, and has broad application prospects. Compared with conventional collectors, medium and large-sized products require higher brightness, and given the larger load of these products, optimization is needed to reduce current density. Summary of the Invention

[0004] This disclosure provides a display panel and display device aimed at at least partially solving the problem of reducing current density.

[0005] In a first aspect of this disclosure, a display panel is provided, the display panel comprising: a substrate having a display area and a non-display area; a plurality of light-emitting devices spaced apart in the display area; each light-emitting device comprising an anode, a light-emitting portion, and a cathode, the light-emitting portion being connected to the anode and the cathode respectively; and a reference wiring layer comprising a first wiring assembly at least partially located in the display area and a second wiring assembly located in the non-display area; the first wiring assembly being connected to the cathode of each of the light-emitting devices; the second wiring assembly comprising a wiring convergence portion, at least three first connecting lines, and at least two second connecting lines, the wiring convergence portion being connected to the first connecting lines and the second connecting lines respectively; the first connecting lines being connected to the first wiring assembly, and the second connecting lines being used to connect to a display driver chip.

[0006] In some embodiments, the first connecting line, the wiring convergence portion, and the second connecting line may be arranged sequentially along a first direction away from the display area; the non-display area includes a first border area located on one side of the display area and a peripheral area located on the side of the first border area away from the display area; the first connecting line is located in the first border area, the wiring convergence portion is at least partially located in the first border area, and the second connecting line is located in the peripheral area.

[0007] In some embodiments, in a second direction parallel to the substrate and perpendicular to the first direction, the width of the wiring convergence may be greater than the sum of the widths of each of the second connecting lines in the second wiring assembly; the wiring convergence is also located in the peripheral area.

[0008] In some embodiments, in the first direction, the length of the wiring convergence portion may be greater than the length of the second connecting line.

[0009] In some embodiments, the first wiring combination may include: a plurality of first voltage lines spaced apart in the display area; and a voltage connecting line disposed along the boundary line of the display area and connected to the first voltage lines and the first connecting line respectively.

[0010] In some embodiments, the first wiring assembly may further include: a plurality of second voltage lines spaced apart in the display area and cross-connected with the plurality of first voltage lines to form a mesh structure; the voltage connecting lines at least partially surround the mesh structure.

[0011] In some embodiments, the reference trace layer is located between the light-emitting device and the substrate, and the cathode of the light-emitting device can be connected to the first trace through a first through-hole; the orthographic projection of the first through-hole on the substrate is located between the orthographic projections of two adjacent light-emitting devices on the substrate.

[0012] In some embodiments, the display panel may further include: a first adapter portion located in the display area; the cathode of the light-emitting device is connected to the first adapter portion through the first connecting hole, and the first adapter portion is connected to the first wiring assembly through the second connecting hole.

[0013] In some embodiments, the second connecting holes can be evenly distributed within the display area.

[0014] In some embodiments, the reference trace layer is located on the side of the anode of the light-emitting device away from the cathode of the light-emitting device, and the first transition portion may be disposed on the same layer as the anode of the light-emitting device.

[0015] In some embodiments, the display panel may further include: a second adapter portion located in the first frame area; the cathode of the light-emitting device is connected to the first trace assembly through the second adapter portion.

[0016] In some embodiments, the second adapter may be disposed on the same layer as the first adapter.

[0017] In some embodiments, the display panel may further include a protective line disposed along the boundary line of the display panel.

[0018] In some embodiments, the width of the protective line can be 10 μm to 50 μm in a third direction parallel to the substrate and perpendicular to the extension direction of the protective line.

[0019] In a second aspect of this disclosure, a display device is provided, which may include a display panel as provided in the first aspect.

[0020] A display panel and display device according to one or more embodiments of this disclosure include a substrate, a plurality of light-emitting devices, and a reference wiring layer. The substrate has a display area and a non-display area, and the plurality of light-emitting devices are spaced apart in the display area. Each light-emitting device includes an anode, a light-emitting portion, and a cathode, with the light-emitting portion connected to the anode and cathode respectively. The reference wiring layer includes a first wiring assembly located at least partially in the display area and a second wiring assembly located in the non-display area. The first wiring assembly is connected to the cathode of each light-emitting device. The second wiring assembly includes a wiring convergence portion, at least three first connecting lines, and at least two second connecting lines. The wiring convergence portion is connected to the first and second connecting lines respectively. The first connecting lines are connected to the first wiring assembly, and the second connecting lines are used to connect to a display driver chip. Thus, a reference voltage signal provided by the display driver chip, after being transmitted to the wiring convergence portion via the second connecting lines, is transmitted to the first wiring assembly via at least three first connecting lines to be transmitted to the cathode of each light-emitting device. By increasing the number of first connecting lines to optimize the reference wiring layer, the current of each first connecting line can be effectively dispersed, the current density reduced, and current concentration avoided at the reference voltage signal access location. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 shows a schematic diagram of the structure of a display panel in the related art.

[0023] Figure 2 shows a schematic diagram of the temperature distribution of the display panel in Figure 1 when it is lit.

[0024] Figure 3 shows a schematic diagram of the structure of a display panel according to some embodiments of the present disclosure.

[0025] Figure 4 shows a top view of the reference routing layer in Figure 3.

[0026] Figure 5 shows a partial structural diagram of the area near the outer perimeter of Figure 3.

[0027] Figure 6 shows a top view of a reference routing layer according to some embodiments of the present disclosure.

[0028] Figure 7 shows a top view of a reference wiring layer according to some embodiments of the present disclosure.

[0029] Figure 8 shows a top view of a reference wiring layer according to some embodiments of the present disclosure.

[0030] Figure 9 shows a top view of a reference wiring layer according to some embodiments of the present disclosure.

[0031] Figure 10 shows a top view schematic diagram of some light-emitting devices according to some embodiments of the present disclosure.

[0032] Figure 11 shows a partial structural schematic diagram of the display panel containing the light-emitting device in Figure 10 along the A-A' section line.

[0033] Figure 12 shows a schematic diagram of the structure of the left and right bezels of the display panel in Figure 11.

[0034] Figure 13 shows a schematic diagram of the structure of the left and right bezels of the display panel where the reference wiring layers of Figures 8 and 9 are located.

[0035] Figure 14 shows a schematic diagram of the structure of the upper bezel of the display panel in Figure 11.

[0036] Figure 15 shows a schematic diagram of the structure of the upper bezel of the display panel where the reference wiring layers of Figures 8 and 9 are located.

[0037] Figure 16 shows a partial structural schematic diagram of the display panel in Figure 4.

[0038] Figure 17 shows a partial structural schematic diagram of the display panel in Figure 7.

[0039] Figure 18 shows a partial structural schematic diagram of the display panel in Figure 8.

[0040] Figure 19 shows a partial structural schematic diagram of the display panel in Figure 9.

[0041] Figure 20 shows a partial structural schematic diagram of a display panel according to some embodiments of the present disclosure.

[0042] Figure 21 shows a partial structural schematic diagram of a display panel according to some embodiments of the present disclosure.

[0043] Figure 22 shows a partial structural schematic diagram of a display panel according to some embodiments of the present disclosure.

[0044] Figure 23 shows a partial structural schematic diagram of a display panel according to some embodiments of the present disclosure.

[0045] Explanation of reference numerals: 10': Substrate; 11': Display area; 12': Border area; 13': Peripheral area; 20': Reference wiring layer; 21': Mesh structure; 22': Ring structure; 23': Wiring convergence point; 24': First connecting line; 25': Second connecting line; 10: Substrate; 11: Display area; 12: Non-display area; 121: First border area; 122: Peripheral area; 123: Second border area; 124: Third border area; 125: Fourth border area; 20: Light-emitting device; 21: First electrode layer; 22: Light-emitting layer; 23: Second electrode layer; 30: Reference wiring Layer; 31: First wiring assembly; 311: First voltage line; 312: Voltage connecting line; 313: Second voltage line; 314: Strip connecting line; 32: Second wiring assembly; 321: Wiring convergence section; 322: First connecting line; 323: Second connecting line; 33: Third wiring assembly; 331: First wiring convergence block; 332: Third connecting line; 34: Fourth wiring assembly; 341: Second wiring convergence block; 342: Fourth connecting line; 343: Fifth connecting line; 41: First connecting hole; 42: Second connecting hole; 51: First transition section; 52: Second transition section; 53: Protective wire. Detailed Implementation

[0046] To enable those skilled in the art to more clearly understand this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0047] Figure 1 is a schematic diagram of the structure of a display panel in the related art. Referring to Figure 1, the display panel includes a substrate 10' and a reference wiring layer 20' located on the substrate 10'. The substrate 10' has a display area 11', a bezel area 12', and a peripheral area 13'. The bezel area 12' surrounds the display area 11'. The peripheral area 13' is located on the side of the bezel area 12' away from the display area 11'. The reference wiring layer 20' includes a mesh structure 21', a strip structure 22', multiple wiring convergence portions 23', and their corresponding first connecting lines 24' and second connecting lines 25'. The mesh structure 21' is located on the side of the display area 11' and the bezel area 12' closer to the display area 11'. Multiple wiring convergence points 23' and their corresponding first connecting lines 24' are located on the side of the border area 12' near the outer perimeter area 13'. The multiple wiring convergence points 23' are arranged sequentially and at intervals along the boundary line of the mesh structure 21', and each wiring convergence point 23' is connected to the mesh structure 21' via two corresponding first connecting lines 24'. The second connecting line 25' corresponding to each wiring convergence point 23' is located in the outer perimeter area 13', and one end of the second connecting line 25' is connected to the wiring convergence point 23'. A strip structure 22' is located in other areas of the border area 12' and partially surrounds the mesh structure 21'. The side of the mesh structure 21' furthest from the outer perimeter area 13' is connected to the strip structure 22'.

[0048] The inventors analyzed that the magnitude of the current density in the traces can be represented by the temperature in the lit state. Based on the temperature distribution of the display panel in the lit state, the current density distribution in the traces can be determined. Figure 2 is a schematic diagram of the temperature distribution of the display panel in the lit state shown in Figure 1. Referring to Figure 2, the temperature of the areas corresponding to various colors on the left increases from top to bottom, that is, the temperature of the blue area, the green area, the yellow area, and the red area gradually increases. The red areas at positions 1, 2, and 3 have higher temperatures, indicating that the current density at positions 1, 2, and 3 is larger. Since positions 1, 2, and 3 correspond to the first connecting lines 24' corresponding to the three trace convergence points 23' in Figure 1 (circled in Figure 1), the first connecting lines 24' corresponding to the trace convergence points 23' need to be optimized.

[0049] Figure 3 is a structural schematic diagram of a display panel according to one or more embodiments of the present disclosure, and Figure 4 is a top view of the reference wiring layer in Figure 3. Referring to Figures 3 and 4, a first aspect embodiment of the present disclosure provides a display panel, which includes a substrate 10, a plurality of light-emitting devices 20, and a reference wiring layer 30. The substrate 10 has a display area 11 and a non-display area 12. The plurality of light-emitting devices 20 are spaced apart in the display area 11. Each light-emitting device 20 includes an anode, a light-emitting portion, and a cathode, with the light-emitting portion connected to the anode and cathode respectively. The reference wiring layer 30 includes a first wiring assembly 31 at least partially located in the display area 11 and a second wiring assembly 32 located in the non-display area 12. The first wiring assembly 31 is connected to the cathode of each light-emitting device 20. The second wiring assembly 32 includes a wiring convergence portion 321, at least three first connecting lines 322, and at least two second connecting lines 323, with the wiring convergence portion 321 connected to the first connecting lines 322 and the second connecting lines 323 respectively. The first connecting line 322 is connected to the first wiring assembly 31, and the second connecting line 323 is used to connect to the display driver chip. At this time, the reference voltage signal provided by the display driver chip is transmitted sequentially through the second connecting line 323, the wiring assembly 321, the first connecting line 322, and the first wiring assembly 31 to the cathode of each light-emitting device 20.

[0050] The aforementioned display panel includes a substrate 10, a plurality of light-emitting devices 20, and a reference wiring layer 30. The substrate 10 has a display area 11 and a non-display area 12, with the plurality of light-emitting devices 20 spaced apart in the display area 11. Each light-emitting device 20 includes an anode, a light-emitting portion, and a cathode, with the light-emitting portion connected to the anode and cathode respectively. The reference wiring layer 30 includes a first wiring assembly 31 at least partially located in the display area 11 and a second wiring assembly 32 located in the non-display area 12. The first wiring assembly 31 is connected to the cathode of each light-emitting device 20. The second wiring assembly 32 includes a wiring convergence portion 321, at least three first connecting lines 322, and at least two second connecting lines 323. The wiring convergence portion 321 is connected to the first connecting lines 322 and the second connecting lines 323 respectively. The first connecting lines 322 are connected to the first wiring assembly 31, and the second connecting lines 323 are used to connect to a display driver chip. In this way, the reference voltage signal provided by the display driver chip is transmitted to the wiring assembly 321 through the second connection line 323, and then transmitted to the first wiring combination 31 through at least three first connection lines 322, so as to the cathode of each light-emitting device 20. By increasing the number of first connection lines 322 to optimize the reference wiring layer 30, the current of each first connection line 322 can be effectively dispersed, the current density can be reduced, and the current concentration at the reference voltage signal access point can be avoided.

[0051] In some embodiments, referring to FIG4, the non-display area 12 may include a first border area 121 located on one side of the display area 11 and a peripheral area 122 located on the side of the first border area 121 away from the display area 11.

[0052] Figure 5 is a partial structural diagram of the area near the peripheral region of Figure 3. Referring to Figure 5, exemplarily, the peripheral region 122 may include a bending region 129, a chip bonding region 128 for bonding the display driver chip, a circuit board bonding region 127 for bonding the FPC (Flexible Printed Circuit), and a wiring region 126. The bending region 129, the chip bonding region 128, and the circuit board bonding region 127 are arranged sequentially along a first direction away from the display region 11, and the wiring region 126 is located between the bending region 129, the chip bonding region 128, and the circuit board bonding region 127. The peripheral region 122 may include a plurality of chip bonding regions 128, which are arranged sequentially at intervals along a second direction parallel to the substrate 10 and perpendicular to the first direction. In addition, the data line can be located in the bending area 129, and the power trace combination (represented by the filled figure in the figure) can be located between the bending area 129 and the chip bonding area 128, as well as between two adjacent chip bonding areas 128, and extends from the first border area 121 through the bending area 129 to the circuit board bonding area 127.

[0053] For example, referring to Figure 4, the non-display area 12 may further include a second border area 123, a third border area 124, and a fourth border area 125. The second border area 123 is disposed opposite to the first border area 121 on both sides of the display area 11, and the third border area 124 and the fourth border area 125 are disposed opposite to each other on both sides of the display area 11 and adjacent to the first border area 121. That is, the first border area 121, the third border area 124, the second border area 123, and the fourth border area 125 are connected end to end along the boundary line of the display area 11.

[0054] In some embodiments, the anode, light-emitting portion, and cathode of the light-emitting device 20 may be arranged sequentially along a direction away from the substrate 10.

[0055] In some embodiments, referring to FIG3, the reference wiring layer 30 may be located between the light-emitting device 20 and the substrate 10.

[0056] For example, the reference trace layer 30 may be located on the side of the anode of the light-emitting device 20 away from the cathode of the light-emitting device 20.

[0057] In some embodiments, the second wiring assembly 32 may include three first connecting lines 322, four first connecting lines 322, or five first connecting lines 322, etc. The number of first connecting lines 322 in the second wiring assembly 32 can be designed according to the space size and process precision.

[0058] In some embodiments, referring to FIG4, the first connecting line 322, the wiring convergence portion 321, and the second connecting line 323 may be arranged sequentially along a first direction away from the display area 11.

[0059] For example, the first connecting line 322 is located in the first border area 121, the wiring convergence part 321 is at least partially located in the first border area 121, and the second connecting line 323 is located in the outer perimeter area 122.

[0060] In some embodiments, referring to FIG4, in a second direction parallel to the substrate 10 and perpendicular to the first direction, the width of the wiring assembly 321 may be greater than the sum of the widths of the first connecting lines 322 in the second wiring assembly 32, and may also be greater than the sum of the widths of the second connecting lines 323 in the second wiring assembly 32.

[0061] In one possible embodiment, referring to FIG4, the trace aggregation portion 321 may also be located in the peripheral area 122, that is, the trace aggregation portion 321 is located in both the first border area 121 and the peripheral area 122. By utilizing the fact that the width of the trace aggregation portion 321 is greater than the sum of the widths of each of the second connecting lines 323 in the second trace assembly 32, extending the trace aggregation portion 321 into the peripheral area 122 to partially replace the second connecting lines 323 in the same second trace assembly 32, the overall width can be increased and the current density reduced.

[0062] For example, referring to FIG4, in the first direction, the length of the wiring assembly 321 can be greater than the length of the second connecting line 323. The wiring assembly 321 can be used to increase the overall width and reduce the current density.

[0063] For example, referring to Figure 4, the second connecting line 323 can extend from the wire gathering section 321 to the side of the peripheral area 122 away from the first border area 121.

[0064] Figure 6 is a top view of a reference wiring layer in another embodiment of this disclosure. Referring to Figure 6, in another possible embodiment, the wiring convergence portion 321 may be located only in the first border area 121.

[0065] In some embodiments, referring to Figures 4 and 6, the reference routing layer 30 may include a plurality of second routing combinations 32, which are arranged at intervals along a second direction.

[0066] For example, referring to Figures 4 and 6, the first connecting line 322 and the second connecting line 323 can extend along the first direction and be arranged at intervals along the second direction.

[0067] For example, the second connection line 323 may extend to the FOP (Flexible Printed Circuit on Panel) area in the peripheral area 122, i.e., the circuit board bonding area 127, to connect with the FPC.

[0068] In some embodiments, referring to Figures 4 and 6, the reference routing layer 30 may further include a third routing assembly 33 located only in the first border area 121. The third routing assembly 33 includes a first routing aggregation block 331 and at least three third connecting lines 332. The third connecting lines 332 are connected to the first routing aggregation block 331 and the first routing assembly 31, respectively, that is, the first routing aggregation block 331 is connected to the first routing assembly 31 through at least three third connecting lines 332.

[0069] For example, referring to Figures 4 and 6, the reference routing layer 30 may include a plurality of third routing combinations 33, which are arranged sequentially at intervals along the second direction.

[0070] For example, referring to Figures 4 and 6, the second trace combination 32 can be located between two adjacent third trace combinations 33, that is, the third trace combination 33 and the second trace combination 32 are alternately arranged along the second direction. In practical applications, the second trace combination 32 can be located between two adjacent power trace combinations, and the third trace combination 33 is only located in the first border area 121, which facilitates the setting of power trace combinations in the empty outer area 122. The power trace combinations can be connected one-to-one with the display driver chip.

[0071] For example, referring to Figures 4 and 6, the third connecting line 332 may extend along the first direction and be arranged at intervals along the second direction.

[0072] In some embodiments, referring to Figures 4 and 6, the reference wiring layer 30 may further include a fourth wiring assembly 34. The fourth wiring assembly 34 includes a second wiring aggregation block 341 located only in the first border region 121, two fourth connecting lines 342, and a fifth connecting line 343 located in the peripheral region 122. The second wiring aggregation block 341 is connected to the fourth connecting lines 342 and the fifth connecting line 343, respectively. The fourth connecting line 342 is connected to the first wiring assembly 31. The fifth connecting line 343 is used to connect to the display driver chip.

[0073] For example, referring to Figures 4 and 6, the reference routing layer 30 may include two fourth routing combinations 34. The two fourth routing combinations 34 are located at both ends of the first border area 121 near the outer perimeter area 122, that is, the second routing combination 32 and the third routing combination 33 are both located between the two fourth routing combinations 34.

[0074] For example, referring to Figures 4 and 6, the fourth connecting line 342 and the fifth connecting line 343 can extend along a first direction and be arranged alternately along a second direction. The fifth connecting line 343 can extend from the second wiring assembly block 341 to the FOP area, i.e., the circuit board bonding area 127.

[0075] In some embodiments, referring to Figures 4 and 6, the first wiring assembly 31 may include multiple first voltage lines 311 and voltage connecting lines 312. The multiple first voltage lines 311 are spaced apart in the display area 11. The voltage connecting lines 312 are arranged along the boundary line of the display area 11 and are respectively connected to the first voltage lines 311 and the first connecting lines 322. Thus, the first voltage lines 311 are connected to each other through the voltage connecting lines 312.

[0076] For example, referring to Figures 4 and 6, the first voltage line 311 may extend along a first direction and be arranged at intervals along a second direction.

[0077] For example, referring to Figures 4 and 6, multiple first voltage lines 311 may be located on the side of the display area 11 and the first border area 121 and the second border area 123 close to the display area 11, and voltage connecting lines 312 are at least partially located in the first border area 121, the third border area 124 and the fourth border area 125.

[0078] In one possible embodiment, referring to Figures 4 and 6, the first wiring assembly 31 may further include a plurality of second voltage lines 313. The plurality of second voltage lines 313 are spaced apart in the display area 11 and intersect with the plurality of first voltage lines 311 to form a mesh structure. Voltage connecting lines 312 at least partially surround the mesh structure.

[0079] For example, referring to Figures 4 and 6, the second voltage line 313 may extend along the first direction and be arranged at intervals along the second direction.

[0080] For example, referring to Figures 4 and 6, multiple second voltage lines 313 may be located on the side of the display area 11 and the third border area 124 and the fourth border area 125 close to the display area 11.

[0081] Figure 7 is a top view of the reference wiring layer in another embodiment of this disclosure. Referring to Figure 7, in another possible embodiment, the first wiring assembly 31 includes only multiple first voltage lines 311 and voltage connecting lines 312. The multiple first voltage lines 311 are spaced apart in the display area 11. The voltage connecting lines 312 are arranged along the boundary line of the display area 11 and are respectively connected to the first voltage lines 311 and the first connecting lines 322. That is, the first wiring assembly 31 does not include the second voltage line 313.

[0082] Figures 8 and 9 are top views of the reference trace layer in another embodiment of this disclosure. Referring to Figures 8 and 9, in one possible embodiment, the first trace assembly 31 may further include a strip-shaped connecting line 314 located in the second border region 123, the third border region 124, and the fourth border region 125, with the strip-shaped connecting line 314 partially surrounding the voltage connecting line 312. The strip-shaped connecting line 314 located in the second border region 123 is connected to multiple first voltage lines 311 respectively. The strip-shaped connecting lines 314 located in the third border region 124 and the fourth border region 125 are connected to the cathodes of each light-emitting device 20 via metal traces. At this time, the reference voltage signal provided by the driving display chip is transmitted sequentially through the second trace assembly 32, the voltage connecting line 312, the first voltage line 311, and the strip-shaped connecting line 314 to the cathode of each light-emitting device 20.

[0083] For example, referring to Figures 8 and 9, the two ends of the strip connecting line 314 can be connected to two fourth wiring combinations 34 respectively, specifically to the second wiring aggregation block 341 in the fourth wiring combination 34.

[0084] For example, the width of the strip connecting line 314 can be greater than 500 μm in the direction perpendicular to the extension direction of the strip connecting line 314 and parallel to the substrate 10, such as 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1000 μm, etc.

[0085] Figure 10 is a top view of some light-emitting devices in another embodiment of this disclosure. Referring to Figure 10, in another possible embodiment, the cathode of the light-emitting device 20 can be connected to the first wiring assembly 31 through the first connecting hole 41. The orthographic projection of the first connecting hole 41 on the substrate 10 is located between the orthographic projections of two adjacent light-emitting devices 20 on the substrate 10. At this time, the reference voltage signal provided by the driving display chip is transmitted sequentially through the second wiring assembly 32, the voltage connecting line 312, and the mesh structure (or the first voltage line 311) to the cathode of each light-emitting device 20. This eliminates the need for the strip connecting line 314, which can significantly reduce the bezel width and achieve a narrow bezel. It also helps to disperse the current, avoid current concentration, and reduce the current density.

[0086] Figure 11 is a partial structural schematic diagram of the display panel containing the light-emitting device of Figure 10 along the A-A' section line. Referring to Figures 4-7 and Figure 11, the display panel may, by way of example, further include a first adapter portion 51 located in the display area 11. The cathode of the light-emitting device 20 is connected to the first adapter portion 51 through a first connecting hole 41, and the first adapter portion 51 is connected to the first wiring assembly 31 through a second connecting hole 42.

[0087] Figure 12 is a structural schematic diagram of the left and right borders of the display panel in Figure 11. Figure 13 is a structural schematic diagram of the left and right borders of the display panel where the reference wiring layer in Figures 8 and 9 is located. Referring to Figures 12 and 13, when the strip connecting line 314 is not required, the cathode of the light-emitting device 20 does not need to be led out from the left and right borders of the display panel, and the strip connecting line 314 does not need to be set. The number of barriers can be reduced, and the border width is smaller than when the strip connecting line 314 is set.

[0088] Figure 14 is a structural schematic diagram of the upper frame of the display panel in Figure 11, and Figure 15 is a structural schematic diagram of the upper frame of the display panel where the reference wiring layer in Figures 8 and 9 is located. Referring to Figures 14 and 15, when the strip connecting line 314 is not required, the cathode of the light-emitting device 20 does not need to be led out from the left and right frames of the display panel, and the strip connecting line 314 does not need to be set. The number of barriers can be reduced, and the frame width is smaller than when the strip connecting line 314 is set.

[0089] In one possible embodiment, please refer to Figures 4-6. The first wiring assembly 31 includes multiple first voltage lines 311 and multiple second voltage lines 313. When the multiple first voltage lines 311 and multiple second voltage lines 313 are cross-connected to form a mesh structure, the cathode of the light-emitting device 20 is connected to the mesh structure through the first connecting hole 41, the first transition part 51, and the second connecting hole 42. At this time, the current dispersion effect is better.

[0090] In another possible embodiment, referring to FIG7, when the first wiring assembly 31 does not include the second voltage line 313, the cathode of the light-emitting device 20 is connected to the first voltage line 311 through the first connecting hole 41, the first adapter 51, and the second connecting hole 42.

[0091] For example, referring to Figures 4-7, the second connecting holes 42 can be uniformly distributed within the display area 11, which helps to reduce current density. In practical applications, the distribution density of the second connecting holes 42 can be adjusted according to actual needs.

[0092] For example, referring to Figure 11, the first transition portion 51 can be disposed on the same layer as the anode of the light-emitting device 20. In practical applications, a first electrode layer 21 can be formed first, which includes the anode of each light-emitting device 20 and the first transition portion 51. The first transition portion 51 is connected to the mesh structure through the second connecting hole 42. Then, a light-emitting layer 22 is laid on the first electrode layer 21 to form the light-emitting part of each light-emitting device 20. Next, part of the light-emitting layer 22 is removed by a laser device to open the first connecting hole 41 and expose the first transition portion 51. Finally, a second electrode layer 23 is laid on the light-emitting layer 22 to form the cathode of each light-emitting device 20. The second electrode layer 23 is connected to the first transition portion 51 in the first connecting hole 41. In this way, by overlapping the first transition portion 51 on the same layer as the anode of the light-emitting device 20, the reference traces in the display area 11 can be realized, reducing the trace resistance.

[0093] For example, the orthographic projection of the first connecting hole 41 on the substrate 10 may overlap with the orthographic projection of the second connecting hole 42 on the substrate 10, or may not intersect with the orthographic projection of the second connecting hole 42 on the substrate 10.

[0094] Figure 16 is a partial structural schematic diagram of the display panel of Figure 4, and Figure 17 is a partial structural schematic diagram of the display panel of Figure 7. Referring to Figures 16 and 17, in some embodiments, the display panel may further include a second adapter portion 52, which is at least partially located in the first frame area 121. The cathode of the light-emitting device 20 is connected to the first wiring assembly 31 through the second adapter portion 52.

[0095] Figure 18 is a partial structural schematic diagram of the display panel of Figure 8, and Figure 19 is a partial structural schematic diagram of the display panel of Figure 9. Referring to Figures 18-19, in one possible embodiment, when the second border area 123, the third border area 124, and the fourth border area 125 are provided with a strip connecting line 314, the second transition part 52 can be located in the first border area 121, the third border area 124, the second border area 123, and the fourth border area 125. The second transition part 52 located in the first border area 121 is connected to the wiring convergence part 321, and the second transition part 52 located in the third border area 124, the second border area 123, and the fourth border area 125 is connected to the strip connecting line 314.

[0096] For example, the orthographic projection of the strip connecting line 314 on the substrate 10 may at least partially overlap with the orthographic projection of the second transition portion 52 on the substrate 10.

[0097] For example, referring to Figures 18-19, the orthographic projection of the second transition portion 52 located in the first border region 121 onto the substrate 10 can overlap with the orthographic projection of the trace aggregation portion 321 onto the substrate 10. The orthographic projection of the second transition portion 52 located in the third border region 124, the second border region 123, and the fourth border region 125 onto the substrate 10 can overlap with the orthographic projection of the strip connecting line 314 onto the substrate 10.

[0098] In another possible embodiment, please refer to Figures 16-17. When the second frame area 123, the third frame area 124 and the fourth frame area 125 are not provided with the strip connecting line 314, the second transition part 52 may be located only in the first frame area 121, and the cathode of the light-emitting device 20 is connected to the wiring collection part 321 through the second transition part 52.

[0099] For example, referring to FIG16, the orthographic projection of the second adapter 52 on the substrate 10 can overlap with the orthographic projection of the trace aggregation portion 321 on the substrate 10.

[0100] For example, the second adapter 52 may be disposed on the same layer as the first adapter 51.

[0101] Figures 20, 21, 22 and 23 are partial structural schematic diagrams of the display panel in another embodiment of this disclosure. Referring to Figures 20-23, in some embodiments, the display panel may further include a protection line 53 located in the second border area 123, the third border area 124 and the fourth border area 125. The protection line 53 is set along the boundary line of the display panel and can protect the metal traces such as GOA (Gate On Array) in the display panel to avoid cutting and external electric field influence.

[0102] For example, referring to Figures 20-23, the guard line 53 may partially surround the voltage connection line 312.

[0103] For example, the protective line 53 may be located between the cutout of the display panel and the GOA.

[0104] For example, in a third direction parallel to the substrate 10 and perpendicular to the extension direction of the guard line 53, the width of the guard line 53 can be 10μm to 50μm, such as 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, etc. The width of the guard line 53 is 10μm to 50μm. On the one hand, this avoids the guard line 53 being too narrow, which could lead to ESD (Electro-Static Discharge); on the other hand, it avoids the guard line 53 being too wide, which could affect the implementation of the narrow bezel.

[0105] For example, the guard line 53 may be located on at least two layers. The orthogonal projection portions of the guard lines 53 on the substrate 10 of the at least two layers overlap and are connected through vias. The guard line 53 adopts a jumper design, which can effectively avoid ESD. For example, a portion of the guard line 53 may be disposed on the same layer as the source / drain layer, and another portion may be disposed on the same layer as the gate layer, with the guard line 53 alternately disposed on the source / drain layer and the gate layer in the extension direction.

[0106] For example, guard line 53 can be connected to reference trace layer 30 or power trace combination. Referring to Figure 18, the two ends of guard line 53 can be connected to two fourth trace combinations 34.

[0107] In some embodiments, the display panel can be used in products with at least one COF (Chip On Flex) or COP (Chip On Pi), and can be used in products using technologies such as LTPS (Low Temperature Polycrystalline Oxide) and LTPO (Low Temperature Poly-Silicon).

[0108] A second aspect of this disclosure provides a display device that includes a display panel as provided in any of the above embodiments.

[0109] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0110] In the description of this disclosure, it should be understood that the terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” “outer,” “clockwise,” and “counterclockwise” indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0111] In this disclosure, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0112] Furthermore, the use of terms such as "first" and "second" in this disclosure is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include one or more features. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0113] Although embodiments of the present disclosure have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display panel, comprising: The substrate (10) has a display area (11) and a non-display area (12); Multiple light-emitting devices (20) are spaced apart in the display area (11); each light-emitting device (20) includes an anode, a light-emitting portion, and a cathode stacked on the substrate (10); and The reference wiring layer (30) includes a first wiring combination (31) located at least partially in the display area (11) and a second wiring combination (32) located in the non-display area (12); the first wiring combination (31) is connected to the cathode of each of the light-emitting devices (20); the second wiring combination (32) includes a wiring convergence section (321), at least three first connecting lines (322) and at least two second connecting lines (323), the wiring convergence section (321) being connected to the first connecting lines (322) and the second connecting lines (323) respectively; the first connecting lines (322) are connected to the first wiring combination (31), and the second connecting lines (323) are used to connect to the display driver chip.

2. The display panel according to claim 1, wherein, The first connecting line (322), the wiring convergence part (321), and the second connecting line (323) are arranged sequentially along a first direction away from the display area (11); The non-display area (12) includes a first border area (121) located on one side of the display area (11) and a peripheral area (122) located on the side of the first border area (121) away from the display area (11); the first connecting line (322) is located in the first border area (121), the wiring convergence part (321) is at least partially located in the first border area (121), and the second connecting line (323) is located in the peripheral area (122).

3. The display panel according to claim 2, wherein, In a second direction parallel to the substrate (10) and perpendicular to the first direction, the width of the wiring assembly (321) is greater than the sum of the widths of each of the second connecting lines (323) in the second wiring assembly (32); the wiring assembly (321) is also located in the peripheral area (122).

4. The display panel according to claim 3, wherein, In the first direction, the length of the wiring convergence section (321) is greater than the length of the second connecting line (323).

5. The display panel according to any one of claims 1-4, wherein, The first wiring combination (31) includes: Multiple first voltage lines (311) are spaced apart in the display area (11); and A voltage connection line (312) is provided along the boundary line of the display area (11) and is connected to the first voltage line (311) and the first connection line (322) respectively.

6. The display panel according to claim 5, wherein, The first wiring assembly (31) also includes: Multiple second voltage lines (313) are spaced apart in the display area (11) and cross-connected with the multiple first voltage lines (311) to form a mesh structure; the voltage connecting line (312) at least partially surrounds the mesh structure.

7. The display panel according to claim 5, wherein, The reference wiring layer (30) is located between the light-emitting device (20) and the substrate (10). The cathode of the light-emitting device (20) is connected to the first wiring assembly (31) through the first connecting hole (41). The orthographic projection of the first connecting hole (41) on the substrate (10) is located between the orthographic projections of two adjacent light-emitting devices (20) on the substrate (10).

8. The display panel according to claim 7, further comprising: The first adapter (51) is located in the display area (11); the cathode of the light-emitting device (20) is connected to the first adapter (51) through the first connecting hole (41), and the first adapter (51) is connected to the first wiring assembly (31) through the second connecting hole (42).

9. The display panel according to claim 8, wherein, The second connecting hole (42) is evenly distributed within the display area (11).

10. The display panel according to claim 8, wherein, The reference trace layer (30) is located on the side of the anode of the light-emitting device (20) away from the cathode of the light-emitting device (20), and the first adapter (51) is disposed on the same layer as the anode of the light-emitting device (20).

11. The display panel according to claim 10, further comprising: The second adapter (52) is located in the first frame area (121); the cathode of the light-emitting device (20) is connected to the first wiring assembly (31) through the second adapter (52).

12. The display panel according to claim 11, wherein, The second adapter (52) is disposed on the same layer as the first adapter (51).

13. The display panel according to claim 7, further comprising: A protective line (53) is provided along the boundary line of the display panel.

14. The display panel according to claim 13, wherein, In a third direction parallel to the substrate (10) and perpendicular to the extension direction of the protective line (53), the width of the protective line (53) is 10 μm to 50 μm.

15. A display device comprising a display panel as described in claims 1-14.

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