Semiconductor device and manufacturing method therefor, and electronic apparatus

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Provided are a semiconductor device and a manufacturing method therefor, and an electronic apparatus, which aim to improve the reliability of the semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer located on one side of the substrate, a channel portion and a gate semiconductor layer located on the side of the epitaxial layer away from the substrate, a source contact layer located on the side of the channel portion away from the substrate, and a drain located on the side of the substrate away from the epitaxial layer. The channel portion comprises a first channel sub-portion and a second channel sub-portion connected to each other, the first channel sub-portion being located between the epitaxial layer and the second channel sub-portion. The gate semiconductor layer surrounds the first channel sub-portion. The source contact layer is located on the second channel sub-portion, and the source contact layer is spaced apart from the gate semiconductor layer by the second channel sub-portion. The drain is located on the side of the substrate away from the epitaxial layer. The semiconductor device is applied to a power electronic device.

Description

Semiconductor devices and their fabrication methods, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411938192.0, filed on December 25, 2024, entitled "Semiconductor Device and Preparation Method Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and more particularly to a semiconductor device and its fabrication method, and electronic equipment. Background Technology

[0003] Junction field-effect transistors (JFETs) are widely used as electronic control switching structures in traditional silicon (Si) and wide-bandgap semiconductors (such as silicon carbide (SiC) and gallium nitride (GaN)) electronic devices due to their simple structure and reliable performance. A JFET is a unipolar electronic device, meaning that when the JFET is in the on state, only one type of carrier flows in the channel to form a conduction current between the source and drain. The gate and channel of the JFET form a PN junction. In normally-on JFETs, applying a voltage to the gate can reverse-bias the PN junction to the channel pinch-off voltage, thus turning off the JFET.

[0004] JFETs mainly include vertical JFETs, in which the channel extends along the thickness direction of the substrate, and the source and drain are located on the upper and lower sides of the channel. This helps to reduce the area of ​​the vertical JFET and improve the integration of the devices used in the vertical JFET.

[0005] However, vertical JFETs suffer from a low breakdown voltage between the gate and source, which reduces their reliability. Summary of the Invention

[0006] This application provides a service transmission method, device, and system that adjusts carrier power in scenarios where multiple carriers configured on the same UE support different numbers, ensuring that carriers with higher priority have sufficient transmission power.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] In a first aspect, a semiconductor device is provided, comprising: a substrate, an epitaxial layer, a channel portion, a gate semiconductor layer, a source contact layer, and a drain. The epitaxial layer is located on one side of the substrate. The channel portion is located on the side of the epitaxial layer away from the substrate, and the channel portion includes a first channel sub-portion and a second channel sub-portion connected to each other, the first channel sub-portion being located between the epitaxial layer and the second channel sub-portion. The gate semiconductor layer is located on the side of the epitaxial layer away from the substrate and surrounds the first channel sub-portion. The source contact layer is located on the side of the second channel sub-portion away from the substrate. The second channel sub-portion separates the source contact layer and the gate semiconductor layer. The drain is located on the side of the substrate away from the epitaxial layer.

[0009] The semiconductor device provided in some embodiments of this disclosure divides the channel portion into a first channel sub-portion and a second channel sub-portion connected to each other, such that the first channel sub-portion is located between the epitaxial layer and the second channel sub-portion. The arrangement of the gate semiconductor layer and the channel portion is adjusted so that the gate semiconductor layer surrounds the first channel sub-portion, and the second channel sub-portion can be used to separate the gate semiconductor layer and the second channel sub-portion. That is, by adjusting the structure included in the semiconductor device itself, the spacing between the gate semiconductor layer and the second channel sub-portion is increased. This structural adjustment is ingenious and can effectively improve the breakdown voltage between the gate and source without adding additional structures, thereby enhancing the reliability of the semiconductor device.

[0010] In some embodiments, the orthographic projection of the end of the first channel sub-section that contacts the second channel sub-section onto the substrate is located within the orthographic projection range of the end of the second channel sub-section that contacts the first channel sub-section onto the substrate.

[0011] In some embodiments, the first channel sub-section includes a first portion and a second portion connected together, the first portion being located between the epitaxial layer and the second portion. The orthographic projection of the second portion onto the substrate lies within the orthographic projection range of the first portion onto the substrate.

[0012] In some embodiments, the distance between the orthographic projection boundary of the second portion on the substrate and the orthographic projection boundary of the first portion on the substrate ranges from 0.1 μm to 1 μm.

[0013] In some embodiments, the orthographic projection of the second channel sub-part onto the substrate coincides with the orthographic projection of the first part onto the substrate.

[0014] In some embodiments, the semiconductor device further includes a current diffusion layer. The current diffusion layer is located between the epitaxial layer and the first channel sub-section, and is in contact with the first channel sub-section. The orthographic projection of the first channel sub-section onto the substrate is within the orthographic projection range of the current diffusion layer onto the substrate.

[0015] In some embodiments, the current diffusion layer and the first channel sub-section are integrally formed.

[0016] In some embodiments, there are multiple channel portions, and a gate semiconductor layer surrounds the first channel sub-ports of the multiple channel portions. A source contact layer is provided on the side of the second channel sub-port of each channel portion away from the substrate, and at least two source contact layers are electrically connected.

[0017] In some embodiments, the semiconductor device further includes: a source, a first ohmic contact layer, a gate, and a second ohmic contact layer. The source is located on the side of the source contact layer away from the substrate. The first ohmic contact layer is located between the source contact layer and the source. The gate is located on the side of the gate semiconductor layer away from the substrate. The second ohmic contact layer is located between the gate semiconductor layer and the gate.

[0018] In some embodiments, the semiconductor device further includes a plurality of annular bumps and a field-limiting ring. The plurality of annular bumps are located on the side of the epitaxial layer away from the substrate and are arranged in a ring around each other, and the plurality of annular bumps surround the channel portion and the gate semiconductor layer. The field-limiting ring is located on the side of the epitaxial layer away from the substrate and is located between two adjacent annular bumps.

[0019] In some embodiments, the gate semiconductor layer includes a first gate layer and a second gate layer connected together. The first gate layer surrounds a first channel sub-port, and the surface of the second gate layer away from the substrate is lower than the surface of the first gate layer away from the substrate. The second gate layer is made of the same material as the field limiting ring and is disposed in the same layer.

[0020] In some embodiments, the annular protrusion includes a first annular sub-protrusion and a second annular sub-protrusion connected to each other, with the first annular sub-protrusion located between the epitaxial layer and the second annular sub-protrusion. The first annular sub-protrusion and the first channel sub-portion are disposed in the same layer. The second annular protrusion and the second channel sub-portion are made of the same material and are disposed in the same layer.

[0021] In a second aspect, a method for fabricating a semiconductor device is provided, the method comprising: providing a substrate; forming an epitaxial layer, a channel portion, a gate semiconductor layer, and a source contact layer on one side of the substrate; the channel portion being located on the side of the epitaxial layer away from the substrate; the channel portion including a first channel sub-portion and a second channel sub-portion connected to each other, the first channel sub-portion being located between the epitaxial layer and the second channel sub-portion; the gate semiconductor layer being located on the side of the epitaxial layer away from the substrate and surrounding the first channel sub-portion; the source contact layer being located on the side of the second channel sub-portion away from the substrate; the second channel sub-portion separating the source contact layer and the gate semiconductor layer; and forming a drain on the side of the substrate away from the epitaxial layer.

[0022] In some embodiments, forming an epitaxial layer, a channel portion, a gate semiconductor layer, and a source contact layer on one side of a substrate includes: forming an epitaxial thin film on one side of the substrate; performing a first ion implantation from the side of the epitaxial thin film away from the substrate to form a first doped region; forming a first mask pattern on the side of the epitaxial thin film away from the substrate, the first mask pattern covering a portion of the first doped region and exposing another portion of the first doped region; performing a second ion implantation based on the first mask pattern from the side of the epitaxial thin film away from the substrate to form a second doped region; the portion of the first doped region opposite to the second doped region constitutes a second portion of the first channel sub-region, and the second doped region is used to form the gate semiconductor layer; forming a second channel sub-region and a source contact layer on the side of the epitaxial thin film away from the substrate; the second channel sub-region covers the first doped region and a portion of the second doped region.

[0023] In some embodiments, an epitaxial layer, a channel portion, a gate semiconductor layer, and a source contact layer are formed on one side of the substrate, and the method further includes: etching and thinning a second doped region based on the second channel portion and the source contact layer; and performing third ion implantation from the side of the epitaxial film away from the substrate based on the second channel portion and the source contact layer to form a third doped region, wherein the third doped region is connected to the second doped region to form a gate semiconductor layer.

[0024] In some embodiments, the epitaxial film has a termination region and an active region, with the termination region surrounding the active region; a channel portion and a gate semiconductor layer are located in the active region. During the formation of a second channel sub-portion and a source contact layer on the side of the epitaxial film away from the substrate, a second annular sub-bump is also formed on the side of the epitaxial film away from the substrate; the second annular sub-bump is located in the termination region. During the etching and thinning of the second doped region based on the second channel sub-portion and the source contact layer, the portion of the epitaxial film located in the termination region is also thinned based on the second channel sub-portion and the source contact layer. During the formation of the third doped region, a third ion implantation is performed on the portion of the epitaxial film located in the termination region based on the second annular sub-bump to form a field confinement ring; the portion located between the second annular sub-bump and the substrate, and in contact with the field confinement ring, constitutes a first annular sub-bump.

[0025] In some embodiments, before forming the drain on the side of the substrate away from the epitaxial layer, the fabrication method further includes: forming a first ohmic contact layer on the side of the source contact layer away from the substrate, and forming a second ohmic contact layer on the side of the gate semiconductor layer away from the substrate. A dielectric layer covering the first and second ohmic contact layers is formed. A source and a gate are formed; the source extends through the dielectric layer to the first ohmic contact layer, and the gate extends through the dielectric layer to the second ohmic contact layer.

[0026] Thirdly, an electronic device is provided, comprising: a semiconductor device and a circuit board, the circuit board being electrically connected to the semiconductor device. The semiconductor device is the semiconductor device as described in any one of the first aspects.

[0027] The technical effects of any of the embodiments in the second to third aspects can be found in the technical effects of the different embodiments in the first aspect, and will not be repeated here. Attached Figure Description

[0028] Figure 1 is a structural diagram of an electronic device according to some embodiments;

[0029] Figure 2 is a structural diagram of a semiconductor device according to some embodiments;

[0030] Figure 3 is a structural diagram of a semiconductor device according to some embodiments;

[0031] Figure 4 is a simulated electric field distribution between the gate and source of a semiconductor device according to some embodiments;

[0032] Figure 5 is a sampling line distribution curve of the simulated electric field intensity of a semiconductor device according to some embodiments along the Y-axis shown in Figure 4;

[0033] Figure 6 is a structural diagram of a semiconductor device according to some embodiments;

[0034] Figure 7 is a structural diagram of a semiconductor device according to some embodiments;

[0035] Figure 8 is a structural diagram of a semiconductor device according to some embodiments;

[0036] Figure 9 is a structural diagram of a semiconductor device according to some embodiments;

[0037] Figure 10 is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0038] Figures 11a-11l are structural diagrams corresponding to each step in the fabrication method of a semiconductor device according to some embodiments;

[0039] Figures 12a-12c are structural diagrams corresponding to each step in the fabrication method of a semiconductor device according to some embodiments;

[0040] Figure 13a is a transfer characteristic curve of the semiconductor device shown in Figure 2;

[0041] Figure 13b is a transfer characteristic curve of a semiconductor device according to some embodiments;

[0042] Figure 14a is a diagram of the off-state breakdown current-voltage curve of the semiconductor device shown in Figure 2.

[0043] Figure 14b is a diagram of the off-state breakdown current-voltage curve of a semiconductor device according to some embodiments. Detailed Implementation

[0044] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0045] In the description of this disclosure, unless the context requires otherwise, the term "comprising" is interpreted throughout the specification and claims as open-ended and encompassing, meaning "including, but not limited to." In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0046] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0047] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0048] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0049] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0050] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0051] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0052] In this disclosure, the meaning of “on the side away from” should be interpreted in the broadest sense, such that “on the side away from” means not only “directly on the side away from”, but also includes the meaning of “on the side away from” where there are intermediate features or layers.

[0053] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0054] Some embodiments of this application provide an electronic device. This electronic device can be a power electronic device, that is, a device whose main functional components are power electronic devices (also known as semiconductor devices or power semiconductor devices). For example, the electronic device can be a converter, electronic switch, electronic AC power controller, power factor correction (PFC) circuit, etc. The converter includes, but is not limited to, a DC-DC converter (or DC to DC power supply), a rectifier (AC / DC, or AC-DC converter), an inverter (DC / AC, or DC-AC converter), etc., and the electronic switch includes, but is not limited to, a power switching power supply circuit, etc. The embodiments of this application do not impose any special limitations on the specific type of this electronic device.

[0055] Figure 1 shows a schematic diagram of the structure of an electronic device 1000. The electronic device 1000 includes a semiconductor device 100 and a circuit board 200, which are electrically connected to the semiconductor device 100. The circuit board 200 is used to provide the required electrical signals to the semiconductor device 100.

[0056] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 1000. In other embodiments of this application, the electronic device 1000 may include more components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0057] Some embodiments of this disclosure also provide a semiconductor device. This semiconductor device can be applied to the aforementioned electronic device 1000. Optionally, the semiconductor device provided in the embodiments of this application can be used as a semiconductor device in the aforementioned electronic device 1000. Of course, the specific application scenarios of the aforementioned semiconductor device are not limited thereto. It is understood that any electronic device that requires the use of a power semiconductor device falls within the application scenarios of the embodiments of this application. Alternatively, the semiconductor device provided in the embodiments of this application can be used alone.

[0058] Figure 2 shows a structural diagram of a semiconductor device. In some examples, as shown in Figure 2, the semiconductor device may include a substrate 1, an epitaxial layer 2, a channel 3, a gate semiconductor layer 4, a source contact layer 5, a gate 6, a source 7, and a drain 8. The channel 3, the gate semiconductor layer 4, the source contact layer 5, the gate 6, the source 7, and the drain 8 can constitute a JFET.

[0059] Referring again to Figure 2, the epitaxial layer 2 is located on one side of the substrate 1. Exemplarily, both the substrate 1 and the epitaxial layer 2 are made of wide-bandgap semiconductor materials, including but not limited to silicon carbide, gallium nitride, and diamond. Optionally, the substrate 1 and the epitaxial layer 2 may be made of the same material, for example, both of which may be silicon carbide.

[0060] For example, the substrate 1 described above is an N+ substrate, meaning that substrate 1 has undergone N-type heavy doping treatment (or heavy doping treatment), which can reduce the resistivity of substrate 1. The epitaxial layer 2 described above is an N- epitaxial layer, meaning that epitaxial layer 2 has undergone N-type light doping treatment. Epitaxial layer 2 can also be referred to as an N-drift region.

[0061] The aforementioned channel portion 3 and gate semiconductor layer 4 are both located on the side of epitaxial layer 2 away from substrate 1, and the gate semiconductor layer 4 surrounds the channel portion 3. The source contact layer 5 is located on the side of channel portion 3 away from substrate 1 and is in contact with the channel portion 3. The aforementioned gate 6 is located on the side of gate semiconductor layer 4 away from substrate 1 and is in contact with the gate semiconductor layer 4; the source 7 is located on the side of source contact layer 5 away from substrate 1 and is in contact with the source contact layer 5; the drain 8 is located on the side of substrate 1 away from epitaxial layer 2.

[0062] For example, the gate 6 and source 7 are made of the same material. Optionally, the material of either the gate 6 or the source 7 includes, but is not limited to, metals such as titanium, aluminum, gold, silver, and copper, and their alloys, or conductive materials such as heavily doped polycrystalline silicon, titanium nitride, and indium tin oxide. The material of the drain 8 includes, but is not limited to, metals such as nickel, aluminum, titanium, and tungsten, and their alloys.

[0063] When the aforementioned semiconductor device is in the conducting state, the gate 6 can receive a suitable voltage, which can be distributed on the gate semiconductor layer 4 to control the semiconductor device to conduct. The current will flow out from the source 7 and be conducted downwards, passing through the source contact layer 5, the channel portion 3, the epitaxial layer 2 and the substrate 1 in sequence to the drain 8.

[0064] In some possible implementations, the channel portion 3 is formed by ion implantation of the semiconductor structure protruding from the epitaxial layer 2, the source contact layer 5 is formed by ion implantation of the top of the channel portion 3, and the gate semiconductor layer 4 is formed by ion implantation of the sidewalls and bottom of the channel portion 3. Furthermore, the channel portion 3 and the source contact layer 5 have the same doping type, while the doping type of the channel portion 3 is opposite to that of the gate semiconductor layer 4. Optionally, the channel portion 3 and the source contact layer 5 are both N-type doped, and the gate semiconductor layer 4 is P-type doped.

[0065] To form the gate semiconductor layer 4, an inclined ion implantation method is required during the ion implantation process on the sidewalls and bottom of the channel portion 3. This means the ion implantation angle is at a certain angle to the extension direction of the channel portion 3. This necessitates precise control over the ion implantation angle, depth, and dosage, increasing the fabrication difficulty of the semiconductor device. Furthermore, using an inclined ion implantation method to form the gate semiconductor layer 4 results in a very small gap between the gate semiconductor layer 4 and the source contact layer 5, leading to a lower breakdown voltage between the gate 6 and the source 7, thus reducing the reliability of the semiconductor device.

[0066] Based on this, some embodiments of the present disclosure have made improvements to the above-described semiconductor device 100, wherein FIG3 illustrates a structural diagram of a semiconductor device.

[0067] In some embodiments, as shown in FIG3, the semiconductor device 100 may include a substrate 1, an epitaxial layer 2, a channel portion 3, a gate semiconductor layer 4, a source contact layer 5, a gate 6, a source 7, and a drain 8. For details regarding the substrate 1, epitaxial layer 2, gate 6, source 7, and drain 8, please refer to the relevant descriptions above; they will not be repeated here.

[0068] In some examples, the channel portion 3 is located on the side of the epitaxial layer 2 away from the substrate 1. The channel portion 3 extends along the thickness direction of the substrate 1. The thickness direction of the substrate 1 refers to the stacking direction of the substrate 1, the epitaxial layer 2, and the channel portion 3.

[0069] Referring again to Figure 3, the channel portion 3 includes a first channel sub-portion 31 and a second channel sub-portion 32 connected to each other, and the first channel sub-portion 31 is located between the epitaxial layer 2 and the second channel sub-portion 32. The first channel sub-portion 31 and the second channel sub-portion 32 are in direct contact. For example, the first channel sub-portion 31 and the second channel sub-portion 32 are two independent structures with a relatively obvious interface between them.

[0070] In some examples, as shown in FIG3, the gate semiconductor layer 4 is located on the side of the epitaxial layer 2 away from the substrate 1 and surrounds the first channel sub-section 31. For example, relative to the substrate 1, the surface of the gate semiconductor layer 4 away from the substrate 1 is flush with the surface of the first channel sub-section 31 away from the substrate 1. The gate semiconductor layer 4 does not surround the second channel sub-section 32; in the direction perpendicular to the thickness direction of the substrate 1, the gate semiconductor layer 4 and the second channel sub-section 32 do not overlap.

[0071] For example, the gate semiconductor layer 4 is in direct contact with the sidewall of the first channel sub-section 31. For instance, both the first channel sub-section 31 and the gate semiconductor layer 4 are formed by doping a semiconductor material, and the doping type of the first channel sub-section 31 is opposite to that of the gate semiconductor layer 4. Optionally, the first channel sub-section 31 is N-type doped, and the gate semiconductor layer 4 is P-type doped.

[0072] In some examples, as shown in Figure 3, the source contact layer 5 is located on the side of the second channel sub-section 32 away from the substrate 1. The gate semiconductor layer 4 is located below the second channel sub-section 32, which separates the source contact layer 5 from the gate semiconductor layer 4, meaning the source contact layer 5 and the gate semiconductor layer 4 are not in direct contact.

[0073] Correspondingly, the spacing between the source contact layer 5 and the gate semiconductor layer 4 is increased. This effectively improves the breakdown voltage between the gate 6 and the source 7.

[0074] This disclosure embodiment simulates the semiconductor devices shown in Figures 2 and 3, and the simulation results are shown in Figure 4. Figure 4(a) shows the electric field distribution between the gate 6 and source 7 in the semiconductor device shown in Figure 2, and Figure 4(b) shows the electric field distribution between the gate 6 and source 7 in the semiconductor device shown in Figure 3. Figure 5 shows the sampling line distribution curves of the simulated electric field intensity of the semiconductor devices shown in Figures 2 and 3 along the Y-axis shown in Figure 4.

[0075] As shown in Figures 4(a) and 5, when the voltage difference (VGS) between the gate 6 and the source 7 is -20V, the semiconductor device is turned off. At this time, there is a high field (approximately 3.2MV / cm) between the gate 6 and the source 7 in the semiconductor device shown in Figure 2. This means that the PN junction formed between the gate 6 and the source 7 has been reverse-biased. However, at the same VGS, as shown in Figures 4(b) and 5, the electric field strength of the PN junction formed between the gate 6 and the source 7 in the semiconductor device shown in Figure 3 is less than 1.5MV / cm, which is less than the breakdown electric field. This means that the gate voltage range of the semiconductor device shown in Figure 3 is improved, and the breakdown voltage range between the gate 6 and the source 7 is improved.

[0076] Therefore, the semiconductor device 100 provided in some embodiments of this disclosure divides the channel portion 3 into a first channel sub-portion 31 and a second channel sub-portion 32 connected to each other, such that the first channel sub-portion 31 is located between the epitaxial layer 2 and the second channel sub-portion 32, and adjusts the arrangement between the gate semiconductor layer 4 and the channel portion 3 so that the gate semiconductor layer 4 surrounds the first channel sub-portion 31, and the second channel sub-portion 32 can be used to separate the gate semiconductor layer 4 and the second channel sub-portion 32. That is, by adjusting the structure included in the semiconductor device 100 itself, the spacing between the gate semiconductor layer 4 and the second channel sub-portion 32 is increased. This structural adjustment is quite ingenious, and can effectively improve the breakdown voltage between the gate 6 and the source 7 without adding additional structures, thereby enhancing the reliability of the semiconductor device 100.

[0077] Moreover, this makes the semiconductor device 100 more suitable for high-voltage normally open JFETs and cascode devices commonly used in high-voltage normally open JFETs, and helps to reduce or even prevent damage to the semiconductor device 100 from transient gate voltage spikes when applied to cascode devices.

[0078] In some embodiments, the spacing between the source contact layer 5 and the gate semiconductor layer 4 along the thickness direction of the substrate 1 is, for example, the same as the thickness of the second channel sub-section 32. Accordingly, by adjusting the thickness of the second channel sub-section 32, the breakdown voltage range between the gate 6 and the source 7 of the semiconductor device 100 can be adjusted, resulting in a more suitable breakdown voltage between the gate 6 and the source 7. Here, the thickness of the second channel sub-section 32 can be selected and set according to actual design requirements.

[0079] In some embodiments, as shown in Figures 3 and 6, the orthographic projection of the end of the first channel sub-section 31 that contacts the second channel sub-section 32 onto the substrate 1 is located within the orthographic projection range of the end of the second channel sub-section 32 that contacts the first channel sub-section 31 onto the substrate 1. Correspondingly, the orthographic projection area of ​​the end of the first channel sub-section 31 that contacts the second channel sub-section 32 onto the substrate 1 is smaller than the orthographic projection area of ​​the end of the second channel sub-section 32 that contacts the first channel sub-section 31 onto the substrate 1.

[0080] Understandably, the semiconductor device 100 has a first direction that is perpendicular to the thickness direction of the substrate 1. Accordingly, the first direction can be any direction parallel to the contact surface between the substrate 1 and the epitaxial layer 2. As shown in Figures 3 and 6, along the first direction, the end of the first channel sub-section 31 that contacts the second channel sub-section 32 is recessed relative to the end of the second channel sub-section 32 that contacts the first channel sub-section 31.

[0081] For example, as shown in Figure 6, along the first direction, the dimension of the end of the first channel sub-section 31 that contacts the second channel sub-section 32 is D1, and the dimension of the end of the second channel sub-section 32 that contacts the first channel sub-section 31 is D2, where D1 < D2. The edge of the end of the second channel sub-section 32 that contacts the first channel sub-section 31 extends beyond the end of the first channel sub-section 31 that contacts the second channel sub-section 32. The ends of the second channel sub-section 32 and the first channel sub-section 31 that contact the second channel sub-section 32 form a T-shaped structure.

[0082] This allows the end of the gate semiconductor layer 4 furthest from the substrate 1 to be located below the surface of the second channel sub-section 32 closest to the substrate 1 and to be in contact with the surface of the second channel sub-section 32 closest to the substrate 1. This ensures that the second channel sub-section 32 can cover the end of the gate semiconductor layer 4 furthest from the substrate 1, thereby ensuring that the second channel sub-section 32 has a better spacing effect on the gate semiconductor layer 4 and the source contact layer 5, effectively ensuring a high breakdown voltage between the gate 6 and the source 7.

[0083] In some examples, as shown in Figures 3 and 6, the first channel sub-section 31 includes a first portion 311 and a second portion 312 connected together, for example, the first portion 311 and the second portion 312 are integrally formed. The first portion 311 is located between the epitaxial layer 2 and the second portion 312. The second portion 312 is in contact with the second channel sub-section 32. Accordingly, the orthographic projection of the second portion 312 onto the substrate 1 lies within the orthographic projection range of the second channel sub-section 32 onto the substrate 1. Along a first direction, the second portion 312 is recessed relative to the end of the second channel sub-section 32 that is in contact with the first channel sub-section 31.

[0084] Furthermore, the orthographic projection of the second portion 312 onto the substrate 1 lies within the orthographic projection range of the first portion 311 onto the substrate 1. Along the first direction, the second portion 312 is recessed relative to the first portion 311. For example, as shown in FIG6, along the first direction, the size of the second portion 312 is D1, and the size of the first portion 311 is D3, where D1 < D3. The edge of the first portion 311 extends beyond the second portion 312. The first channel sub-portion 31 is generally stepped, and the channel portion 3 is generally H-shaped.

[0085] Understandably, during the turn-off process of the JFET, the narrower portion of the channel is clamped first. Correspondingly, during the turn-off process of the semiconductor device 100, the first channel sub-section 31 in the channel portion 3 is clamped first, and further, the second portion 312 in the first channel sub-section 31 is clamped first. The second portion 312 has a smaller dimension in the first direction, which can easily increase the channel resistance of the semiconductor device 100.

[0086] By dividing the first channel sub-section 31 into two parts, and making the dimension of the first part 311, which is farther away from the first channel sub-section 31, in the first direction larger than the dimension of the second part 312 in the first direction, the channel resistance of the semiconductor device 100 can be reduced by utilizing the second part 312, thereby avoiding affecting or even improving the conduction characteristics of the semiconductor device 100.

[0087] For example, the distance between the orthographic projection boundary of the second portion 312 on the substrate 1 and the orthographic projection boundary of the first portion 311 on the substrate 1 ranges from 0.1 μm to 1 μm. That is, along the first direction, the minimum distance between the sidewalls of the second portion 312 and the sidewalls of the first portion 311 ranges from 0.1 μm to 1 μm; the difference between the dimension D3 of the first portion 311 and the dimension D1 of the second portion 312 ranges from 0.2 μm to 2 μm.

[0088] Optionally, the distance between the orthographic projection boundary of the second part 312 on the substrate 1 and the orthographic projection boundary of the first part 311 on the substrate 1 can be 0.1μm, 0.2μm, 0.4μm, 0.6μm, 0.8μm or 1μm, etc.

[0089] By adopting the above-mentioned size range, on the one hand, the difficulty of fabricating the first part 311, the second part 312 and the gate semiconductor layer 4 can be reduced, and the gate parasitic resistance can be reduced; on the other hand, the situation that the drain 8 cannot clamp the first channel sub-part 31 in the channel part 3 under high voltage can be avoided, and the voltage withstand capability between the source 7 and the drain 8 can be avoided.

[0090] In some examples, as shown in Figures 3 and 6, the orthographic projection of the second channel sub-section 32 onto the substrate 1 coincides with the orthographic projection of the first portion 311 of the first channel sub-section 31 onto the substrate 1. Correspondingly, along the first direction, the dimension D2 of the second channel sub-section 32 is equal to the dimension D3 of the first portion 311 of the first channel sub-section 31. The orthographic projection area of ​​the second channel sub-section 32 onto the substrate 1 is equal to the orthographic projection area of ​​the first portion 311 of the first channel sub-section 31 onto the substrate 1.

[0091] This helps to reduce the area occupied by the orthogonal projection of the channel portion 3 on the substrate 1, reduce the area occupied by the JFET in the semiconductor device 100, and improve the integration density of the semiconductor device 100.

[0092] In some embodiments, as shown in FIG7, the semiconductor device 100 has a plurality of channel portions 3 and a plurality of source contact layers 5. The plurality of channel portions 3 and the plurality of source contact layers 5 are arranged in a one-to-one correspondence. For example, a source contact layer 5 is provided on the side of the second channel sub-portion 32 of each channel portion 3 away from the substrate 1. The plurality of channel portions 3 may be spaced apart along a first direction. Each channel portion 3, for example, constitutes a JFET.

[0093] For example, continuing to refer to FIG7, the gate semiconductor layer 4 surrounds the first channel sub-section 31 of the plurality of channel portions 3, and at least two source contact layers 5 are electrically connected. Accordingly, the gates of the plurality of JFETs are electrically connected together, and the sources of at least two JFETs are electrically connected together, such that at least two JFETs can form a common-source, common-gate configuration device.

[0094] Here, the at least two source contact layers 5 can be electrically connected in various ways. Optionally, continuing to refer to FIG7, the source electrodes 7 located on the side of the at least two source contact layers 5 away from the substrate 1 are connected, that is, the at least two source contact layers 5 are electrically connected together through the source electrodes 7. For example, the source electrodes 7 on the side of the at least two source contact layers 5 away from the substrate 1 are of a single structure.

[0095] It is understood that the semiconductor device 100 described above may also include other structures, which will be illustrated below with reference to the accompanying drawings.

[0096] In some embodiments, as shown in Figures 6 and 7, the semiconductor device 100 may further include a current diffusion layer 9. The current diffusion layer 9 is located between the epitaxial layer 2 and the first channel sub-section 31, and is in contact with the first channel sub-section 31. The orthographic projection of the first channel sub-section 31 onto the substrate 1 lies within the orthographic projection range of the current diffusion layer 9 onto the substrate 1. Accordingly, along a first direction, the edge of the current diffusion layer 9 extends beyond the first channel sub-section 31.

[0097] For example, the projected area of ​​the first channel sub-section 31 on the substrate 1 is smaller than the projected area of ​​the current diffusion layer 9 on the substrate 1. Along the first direction, the size of the first channel sub-section 31 is smaller than the size of the current diffusion layer 9.

[0098] This allows the current diffusion layer 9 to further reduce the channel resistance of the semiconductor device 100, avoiding affecting or even improving the conduction characteristics of the semiconductor device 100.

[0099] In some examples, the current diffusion layer 9 and the first channel sub-section 31 are integrally formed. That is, the current diffusion layer 9 and the first channel sub-section 31 are made of the same or substantially the same material, and they are continuous and unbroken.

[0100] In this way, the current diffusion layer 9 and the first channel sub-section 31 can be formed simultaneously during the fabrication of the semiconductor device 100, which helps to simplify the fabrication process of the semiconductor device 100.

[0101] For example, as shown in Figures 6 and 7, the current diffusion layer 9 may also be located between the gate semiconductor layer 4 and the epitaxial layer 2, and in contact with the side surface of the gate semiconductor layer 4 near the substrate 1. Alternatively, the current diffusion layer 9 may be embedded within the gate semiconductor layer 4, that is, relative to the substrate 1, the side surface of the gate semiconductor layer 4 near the substrate 1 is lower than the side surface of the current diffusion layer 9 near the substrate 1.

[0102] In some embodiments, as shown in FIG7, FIG8 and FIG9, the semiconductor device 100 may further include: a first ohmic contact layer 10 and a second ohmic contact layer 11.

[0103] The first ohmic contact layer 10 is located between the source contact layer 5 and the source electrode 7, and is in direct contact with both the source contact layer 5 and the source electrode 7. This helps to reduce the contact resistance between the source contact layer 5 and the source electrode 7, and the provision of the source contact layer 5 can further reduce the contact resistance between the channel portion 3 and the source electrode 7.

[0104] The second ohmic contact layer 11 is located between the gate semiconductor layer 4 and the gate 6, and makes direct contact with both the gate semiconductor layer 4 and the gate 6. This helps to reduce the contact resistance between the gate semiconductor layer 4 and the gate 6.

[0105] In some embodiments, as shown in Figures 8 and 9, the semiconductor device 100 may further include a plurality of annular bumps 12 and a field limiting ring 13. The field limiting ring 13 may also be referred to as a terminal field limiting ring.

[0106] The aforementioned plurality of annular protrusions 12 are located on the side of the epitaxial layer 2 away from the substrate 1 and are arranged in a ring-like configuration. Exemplarily, the orthographic projection shape of the plurality of annular protrusions 12 on the substrate 1 includes, but is not limited to, a circular ring, a square ring, etc. The orthographic projection shape of each annular protrusion 12 on the substrate 1 can be the same or different. For example, along the first direction, the inner diameters of the plurality of annular protrusions 12 are different, and at least one annular protrusion 12 surrounds another annular protrusion 12. Optionally, the plurality of annular protrusions 12 are concentric and spaced apart.

[0107] The aforementioned field limiting ring 13 is located on the side of the epitaxial layer 2 away from the substrate 1, and is situated between two adjacent annular protrusions 12. For example, along the first direction, the annular protrusions 12 and the field limiting ring 13 are alternately arranged. The number of field limiting rings 13 can be one or more.

[0108] Furthermore, the aforementioned plurality of annular protrusions 12 surround the channel portion 3 and the gate semiconductor layer 4. The channel portion 3, the gate semiconductor layer 4, and the source contact layer 5, source electrode 7, and other structures located on the side of the channel portion 3 away from the substrate 1 are located within the area enclosed by the plurality of annular protrusions 12.

[0109] The annular protrusion 12 with the smallest inner diameter among the above-mentioned plurality of annular protrusions 12, for example, is in contact with the gate semiconductor layer 4 and separates the gate semiconductor layer 4 from the field limiting ring 13 with the smallest inner diameter.

[0110] By setting the field limiting loop 13, the problem of electric field concentration at the edge of the semiconductor device 100 can be alleviated or even eliminated, thereby further improving the breakdown voltage of the semiconductor device 100.

[0111] In some examples, as shown in FIG9, the gate semiconductor layer 4 includes a first gate layer 41 and a second gate layer 42 connected together. The first gate layer 41 surrounds the first channel sub-section 31. The surface of the second gate layer 42 away from the substrate 1 is lower than the surface of the first gate layer 41 away from the substrate 1. Accordingly, the cross-sectional pattern of the first gate layer 41 and the second gate layer 42 is L-shaped.

[0112] Furthermore, the second gate layer 42 is made of the same material as the field limiting ring 13 and is disposed in the same layer.

[0113] In this paper, "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same photomask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0114] In this way, the second gate layer 42 and the field limiting ring 13 can be fabricated simultaneously in the same fabrication process, which avoids the need to add process steps due to the setting of the field limiting ring 13 and helps to simplify the fabrication process of the semiconductor device 100.

[0115] In some examples, as shown in Figure 9, the annular protrusion 12 includes a first annular sub-protrusion 121 and a second annular sub-protrusion 122 connected together, with the first annular sub-protrusion 121 located between the epitaxial layer 2 and the second annular sub-protrusion 122. The first annular sub-protrusion 121 and the first channel sub-section 31 are disposed in the same layer, and the second annular protrusion 122 and the second channel sub-section 32 are made of the same material and are disposed in the same layer.

[0116] In this way, the first annular sub-protrusion 121 and the first channel sub-section 31 can be fabricated simultaneously in the same fabrication process, and the second annular sub-protrusion 122 and the second channel sub-section 32 can be fabricated simultaneously in the same fabrication process. This avoids the need to add process steps due to the setting of the annular protrusion 12, and helps to simplify the fabrication process of the semiconductor device 100.

[0117] Some embodiments of this application also provide a method for fabricating a semiconductor device, such as the semiconductor device 100 described in some of the above embodiments. FIG10 illustrates a flowchart of a method for fabricating a semiconductor device; FIGS. 11a-11l and 12a-12c respectively illustrate structural diagrams corresponding to each step in the method for fabricating a semiconductor device. It should be understood that the steps shown in FIG10 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in FIG10. Furthermore, some of the steps may be performed simultaneously or in a different order than that shown in FIG10.

[0118] The following is a schematic description of the semiconductor device fabrication method with reference to the accompanying drawings. As shown in Figure 10, the fabrication method includes steps S100-S300.

[0119] S100 provides a substrate.

[0120] Regarding the substrate, please refer to the relevant explanation above, which will not be repeated here.

[0121] S200, referring to Figures 11a-11i, an epitaxial layer 2, a channel portion 3, a gate semiconductor layer 4, and a source contact layer 5 are formed on one side of the substrate 1. The channel portion 3 is located on the side of the epitaxial layer 2 away from the substrate 1. The channel portion 3 includes a first channel sub-portion 31 and a second channel sub-portion 32 connected to each other, with the first channel sub-portion 31 located between the epitaxial layer 2 and the second channel sub-portion 32. The gate semiconductor layer 4 is located on the side of the epitaxial layer 2 away from the substrate 1 and surrounds the first channel sub-portion 31. The source contact layer 5 is located on the side of the second channel sub-portion 32 away from the substrate 1, and the second channel sub-portion 32 separates the source contact layer 5 and the gate semiconductor layer 4.

[0122] For example, embodiments of this disclosure may employ epitaxial processes, ion implantation processes, etching processes, etc., to prepare and form an epitaxial layer 2, a channel portion 3, a gate semiconductor layer 4, and a source contact layer 5.

[0123] S300, as shown in Figure 11l, a drain electrode 8 is formed on the side of the substrate 1 away from the epitaxial layer 2.

[0124] For example, in this embodiment of the present disclosure, a deposition process can be used to deposit conductive material on the side of the substrate 1 away from the epitaxial layer 2 to form a drain 8. Then, a high-temperature annealing process is used to treat the drain 8, so that the drain 8 and the substrate 1 form an ohmic contact. Optionally, the material of the drain 8 includes, but is not limited to, metals such as nickel, aluminum, titanium, and tungsten, and their alloys. Along the thickness direction of the substrate 1, the thickness of the drain 8 ranges, for example, from 0.02 μm to 2 μm.

[0125] The semiconductor device fabrication method provided in some embodiments of this disclosure allows for adjustments to the fabrication processes of the epitaxial layer 2, channel portion 3, gate semiconductor layer 4, and source contact layer 5. This allows the formed channel portion 3 to include a first channel sub-portion 31 and a second channel sub-portion 32 connected together, with the first channel sub-portion 31 located between the epitaxial layer 2 and the second channel sub-portion 32. The gate semiconductor layer 4 surrounds the first channel sub-portion 31. This allows the second channel sub-portion 32 to separate the gate semiconductor layer 4 and the second channel sub-portion 32, increasing the spacing between the gate semiconductor layer 4 and the second channel sub-portion 32. This effectively improves the breakdown voltage between the gate 6 and the source 7 without requiring additional structures, thereby enhancing the reliability of the fabricated semiconductor device 100.

[0126] In some embodiments, in the above S200, an epitaxial layer 2, a channel portion 3, a gate semiconductor layer 4 and a source contact layer 5 are formed on one side of the substrate 1, including: S210-S250.

[0127] S210, as shown in Figure 11a, forms an epitaxial thin film 2a on one side of the substrate 1.

[0128] For example, in embodiments of this disclosure, an epitaxial process can be used to grow and form an epitaxial thin film 2a. The thickness of the epitaxial thin film 2a is, for example, 1 μm to 100 μm. The epitaxial thin film 2a is, for example, lightly doped with N-type, and the doping concentration is, for example, from 1 × 10¹⁴ cm⁻³ to 1 × 10¹⁷ cm⁻³.

[0129] The materials of the epitaxial thin film 2a all include wide bandgap semiconductor materials, including but not limited to silicon carbide, gallium nitride, diamond, etc.

[0130] S220, as shown in Figure 11b, a first ion implantation is performed from the side of the epitaxial thin film 2a away from the substrate 1 to form a first doped region A1.

[0131] For example, as shown in FIG11b, before performing the first ion implantation, a mask film can be formed on the side of the epitaxial film 2a away from the substrate 1. Then, the mask film is etched using a photolithography process to obtain a second mask layer M2. The second mask layer M2 has a plurality of spaced openings, each opening exposing a portion of the epitaxial film 2a. The position of each opening corresponds to the position of the channel to be formed. Then, based on the second mask layer M2, the first ion implantation can be performed on the epitaxial film 2a to form a plurality of first doped regions A1. Afterwards, the second mask layer M2 can be removed.

[0132] For example, the implanted ions are N-type ions, including but not limited to nitrogen ions, phosphorus ions, etc. The depth range of the first doped region A1 is, for example, 0.1 μm-4 μm, and the doping concentration range of the first doped region A1 is, for example, 1×10¹⁴ cm⁻³-1×10²⁰ cm⁻³.

[0133] S230, as shown in FIG11c, a first mask pattern 14 is formed on the side of the epitaxial thin film 2a away from the substrate 1. The first mask pattern 14 covers a part of the first doped region A1 and exposes another part of the first doped region A1.

[0134] For example, a mask film can be formed on the side of the epitaxial film 2a away from the substrate 1 using dielectric materials such as silicon oxide (SiO2) and silicon nitride (SiNx) or photoresist, and then the mask film can be etched by photolithography to obtain a first mask layer M1. The first mask layer M1 includes a plurality of first mask patterns 14 spaced apart, and each first mask pattern 14 is in the form of a block.

[0135] In this configuration, multiple first mask patterns 14 and multiple first doped regions A1 are arranged in a one-to-one correspondence, with each first mask pattern 14 covering a portion of the corresponding first doped region A1 and exposing another portion of the first doped region A1. The exposed portion of the first doped region A1 is, for example, ring-shaped.

[0136] S240, as shown in FIG11c, based on the first mask pattern 14, a second ion implantation is performed from the side of the epitaxial thin film 2a away from the substrate 1 to form a second doped region A2. The portion of the first doped region A1 opposite to the second doped region A2 constitutes the second portion of the first channel sub-section 31, and the second doped region A2 is used to form the gate semiconductor layer.

[0137] For example, the second doped region A2 surrounds each of the first doped regions A1. For instance, the ions implanted in the second doped region A2 are P-type ions, including but not limited to aluminum ions, boron ions, etc. Accordingly, the second doped region A2 can also be referred to as a P-type region. The depth range of the second doped region A2 is, for example, 0.1 μm-4 μm, and the doping concentration range of the second doped region A2 is, for example, 1 × 10¹⁶ cm⁻³-1 × 10²⁰ cm⁻³. Along the first direction, the size range of the portion of the first doped region A1 opposite to the second doped region A2 (i.e., the second portion of the first channel sub-section 31) is, for example, 0.5 μm-5 μm.

[0138] The second ion implantation described above is, for example, vertical ion implantation, with the ion implantation direction parallel or approximately parallel to the thickness direction of the substrate 1.

[0139] Here, after the second doped region A2 is formed, the first mask layer M1 can be removed, and the surface of the epitaxial film 2a away from the substrate 1 can be cleaned.

[0140] S250, as shown in FIG11e, a second channel sub-section 32 and a source contact layer 5 are formed on the side of the epitaxial thin film 2a away from the substrate 1. The second channel sub-section 32 covers a portion of the first doped region A1 and the second doped region A2.

[0141] For example, referring to Figures 11d and 11e, a method for forming the second channel sub-section 32 and the source contact layer 5 includes: using an epitaxial process to grow a channel film 32a on the side of the epitaxial film 2a away from the substrate 1; then, epitaxially growing or ion implanting to form a source contact film 5a on the side of the channel film 32a away from the substrate 1; subsequently, using a photolithography process to form a third mask layer M3 on the side of the source contact film 5a away from the substrate 1, the third mask layer M3 including a plurality of block-shaped second mask patterns, and the plurality of second mask patterns and a plurality of first doped regions A1 are correspondingly arranged one-to-one, each second mask pattern covering a portion of the first doped region A1 and the second doped region A2; then, based on the third mask layer M3, a dry etching process can be used to etch the source contact film 5a and the channel film 3a to obtain a plurality of second channel sub-sections 32 and a plurality of source contact layers 5.

[0142] For example, the thickness of the aforementioned channel film 32a ranges from 0.2 μm to 2 μm. The channel film 32a is, for example, N-type doped, with a doping concentration ranging from 1 × 10¹⁶ cm⁻³ to 1 × 10²⁰ cm⁻³. The thickness of the source contact film 5a ranges from, for example, 0.1 μm to 0.5 μm. The source contact film 5a is, for example, heavily N-type doped, with a doping concentration ranging from, for example, 1 × 10¹⁷ cm⁻³ to 1 × 10²⁰ cm⁻³. Along the first direction, the size of the second channel sub-section 32 is less than or equal to the size of the portion of the first doped region A1 that is not opposite the second doped region A2.

[0143] Understandably, the second channel sub-section 32 and the source contact layer 5 are etched and formed in the same patterning process, and are fabricated using a process independent of the first channel sub-section 31. The second channel sub-section 32 can isolate the source contact layer 5 and the second doped region A2, correspondingly isolating the source contact layer 5 and the gate semiconductor layer to be formed. The process is relatively simple and can effectively increase the breakdown voltage between the source and gate of the semiconductor device.

[0144] Furthermore, in the above S200, the formation of an epitaxial layer 2, a channel portion 3, a gate semiconductor layer 4, and a source contact layer 5 on one side of the substrate 1 may also include S260-S270.

[0145] S260, as shown in Figure 11e, the second doped region A2 is etched and thinned based on the second channel sub-section 32 and the source contact layer 5.

[0146] Specifically, the second doped region A2 is etched and thinned based on the third mask layer M3 located on the side of the second channel sub-section 32 and the source contact layer 5 away from the substrate 1.

[0147] Optionally, the etching of the source contact film 5a and the channel film 32a, as well as the etching of the second doped region A2, can be performed in the same etching process. Here, the etching depth ranges, for example, from 0.3 μm to 4.5 μm.

[0148] S270, as shown in Figure 11f, based on the second channel sub-section 32 and the source contact layer 5, a third ion implantation is performed from the side of the epitaxial thin film 2a away from the substrate 1 to form a third doped region A3. The third doped region A3 is connected to the second doped region A2 to form a gate semiconductor layer 4.

[0149] Specifically, a third ion implantation is performed based on the third mask layer M3 located on the side of the second channel sub-section 32 and the source contact layer 5 away from the substrate 1. For example, the implanted ions are P-type ions, the depth range of the third doped region A3 is, for example, 0.1 μm-2 μm, and the doping concentration range of the third doped region A3 is, for example, 1×10¹⁶ cm⁻³-1×10²⁰ cm⁻³. Afterwards, the third mask layer M3 can be removed.

[0150] The portion of the first doped region A1 opposite to the third doped region A3 forms the first portion 311 of the first channel sub-region 31. As shown in FIG11f, by controlling the depth of the third doped region A3, the bottom of the first doped region A1 can be made to form a current diffusion layer 9.

[0151] Here, along the first direction, the spacing between the edge of the third doped region A3 and the edge of the second doped region A2 is, for example, 0.1 μm to 1 μm. This avoids excessive removal of the second doped region A2, which would make it difficult to control the overlay accuracy of the process and prevent an increase in gate parasitic resistance. Furthermore, it prevents the sidewall of the third doped region A3 from being too large in the first direction, which could lead to the inability to clamp the first channel sub-section 31 under high drain voltage, thus reducing the breakdown voltage between the source and drain of the semiconductor device.

[0152] It is understandable that, in the aforementioned channel portion 3, the second portion 312 has the smallest size in the first direction, and correspondingly, the second ion implantation in S240 controls the threshold voltage of the channel portion 3. The third ion implantation in S270 and the formation of the second channel sub-portion 32 in S250 are unrelated to the size of the second portion 312 in the first direction and will not affect the size of the second portion 312 in the first direction.

[0153] In the semiconductor device shown in Figure 2, the channel portion 3 is made of a wide bandgap semiconductor material. Typically, a dry etching process is used to etch the wide bandgap semiconductor material to form grooves, thereby obtaining the channel portion 3. Etching wide bandgap semiconductor materials is difficult, requiring hard masks and high-power etching equipment. It is challenging to precisely control the dimensions of the etched channel portion 3 in the first direction, resulting in poor uniformity of the dimensions of different etched channel portions 3 in the first direction. Since the channel portion 3 has a relatively high carrier concentration, variations in the dimensions of the etched channel portion 3 in the first direction during fabrication will lead to significant changes in the threshold voltage and breakdown voltage capability of the final semiconductor device.

[0154] In this embodiment, the threshold voltage of the semiconductor device is determined by the second portion 312 of the channel 3. During the formation of the second portion 312, the first mask layer M1 used can also be called an ion implantation mask. The material of this ion implantation mask is typically easy to etch, and correspondingly, the etching size is easy to control, resulting in high process uniformity. Consequently, the dimensional accuracy of the first mask pattern 14 is high, and the dimensional accuracy of the prepared second portion 312 is also high. This avoids the adverse effects on the threshold voltage and the breakdown voltage between the source and drain caused by directly etching the channel.

[0155] In addition, by forming the third doped region A3 through third ion implantation, the breakdown voltage capability of the semiconductor device can be improved, while avoiding affecting the threshold voltage of the semiconductor device.

[0156] The embodiments of this disclosure simulate the transfer characteristic curves and off-state breakdown current-voltage curves of the semiconductor device (e.g., shown in Figure 11l) prepared by the preparation method provided in the embodiments of this disclosure.

[0157] As can be seen from Figures 13a and 13b, in the semiconductor device shown in Figure 2, when the size of the channel portion 3 in the first direction changes from 1.2 μm to 1.6 μm, the threshold voltage experiences a large drift; while in the semiconductor device shown in the embodiments of this disclosure, when the size of the second portion 312 of the first channel sub-portion 31 changes from 1.2 μm to 1.6 μm in the first direction, the threshold voltage remains stable and is basically stable at around -9V.

[0158] As can be seen from Figures 14a and 14b, in the semiconductor device shown in Figure 2, when the dimension of the channel portion 3 in the first direction changes from 1.2 μm to 1.6 μm, the off-state drain breakdown voltage is significantly degraded, and breakdown occurs before the rated voltage; while in the semiconductor device shown in the embodiment of this disclosure, when the dimension of the second portion 312 of the first channel sub-portion 31 in the first direction changes from 1.2 μm to 1.6 μm, the off-state drain breakdown voltage is not degraded.

[0159] In other words, the method for fabricating the channel portion 3 in the semiconductor device provided in this disclosure can decouple the size of the second portion 312 of the first channel sub-portion 31 in the first direction from the threshold voltage and the off-state drain breakdown voltage, effectively improving the problems of threshold voltage drift and off-state drain breakdown voltage degradation caused by the change in the size of the second portion 312 of the first channel sub-portion 31 in the first direction.

[0160] In some embodiments, prior to S300, the preparation method further includes S281-S283.

[0161] S281, as shown in FIG11i, a first ohmic contact layer 10 is formed on the side of the source contact layer 5 away from the substrate 1, and a second ohmic contact layer 11 is formed on the side of the gate semiconductor layer 4 away from the substrate 1.

[0162] For example, as shown in FIG11g, before forming the first ohmic contact layer 10 and the second ohmic contact layer 11, a dielectric material can be deposited on the side of the gate semiconductor layer 4 and the source contact layer 5 away from the substrate 1 to form a dielectric film 15a. The dielectric film 15a also covers the sidewalls of the gate semiconductor layer 4, the sidewalls of the second channel sub-section 32 and the sidewalls of the source contact layer 5. Then, in conjunction with FIG11g and FIG11h, for example, an anisotropic dry etching process is used to etch the dielectric film 15a to remove the portion of the dielectric film 15a located on the side of the gate semiconductor layer 4 and the source contact layer 5 away from the substrate 1, while retaining the portion of the dielectric film 15a covering the sidewalls of the gate semiconductor layer 4, the sidewalls of the second channel sub-section 32 and the sidewalls of the source contact layer 5 to form a sidewall 15. Subsequently, as shown in Figure 11i, ohmic metal material is deposited on the side of the gate semiconductor layer 4 and the source contact layer 5 away from the substrate 1, and annealing is performed using a high-temperature annealing process to obtain the first ohmic contact layer 10 and the second ohmic contact layer 11.

[0163] Optionally, the thickness of the dielectric film 15a can range from 0.02 μm to 2 μm, and the material of the dielectric film 15a includes, but is not limited to, dielectric materials such as silicon oxide and silicon nitride. The thickness of the first ohmic contact layer 10 and the second ohmic contact layer 11 is, for example, the same, and the thickness range is, for example, 0.02 μm to 0.2 μm. The materials of the first ohmic contact layer 10 and the second ohmic contact layer 11 are the same, for example, including but not limited to, metal materials such as nickel, aluminum, titanium, and tungsten and their alloy materials.

[0164] The first ohmic contact layer 10 and the second ohmic contact layer 11 are formed simultaneously in the same fabrication process, which helps to simplify the fabrication process of semiconductor devices.

[0165] S282, as shown in FIG11j, a dielectric layer 16 is formed covering the first ohmic contact layer 10 and the second ohmic contact layer 11.

[0166] For example, a dielectric material can be deposited on the side of the first ohmic contact layer 10 and the second ohmic contact layer 11 away from the substrate 1 using a deposition process to form a dielectric layer 16. The dielectric layer 16 also covers the sidewalls 15.

[0167] S283, as shown in Figure 11k, forms a source 7 and a gate 6. The source 7 extends through the dielectric layer 16 to the first ohmic contact layer 10, and the gate 6 extends through the dielectric layer 16 to the second ohmic contact layer 11.

[0168] For example, before forming the source 7 and gate 6, a first via and a second via can be formed in the dielectric layer 16. The first via penetrates the dielectric layer 16 and exposes the first ohmic contact layer 10; the second via penetrates the dielectric layer 16 and exposes the second ohmic contact layer 11. Then, conductive material is deposited on the first via, the second via, and the side of the dielectric layer 16 away from the substrate 1 to obtain the source 7 and gate 6. The source 7 contacts the first ohmic contact layer 10 through the first via, and the gate 6 contacts the second ohmic contact layer 11 through the second via. There is a certain distance between the source 7 and the gate 6 to avoid leakage between them.

[0169] For information on the materials of source 7 and gate 6, please refer to the relevant descriptions above; they will not be repeated here.

[0170] In some embodiments, as shown in Figures 12a-12c, the epitaxial thin film 2a has a termination region B1 and an active region B2. The termination region B1 is, for example, annular and surrounds the active region B2. The channel portion 3 and the gate semiconductor layer 4 are located in the active region B2. Furthermore, the source contact layer 5 and the source electrode 7 on the side of the channel portion 3 away from the substrate 1, and the gate electrode 6 on the side of the gate semiconductor layer 4 away from the substrate 1, are also located in the active region B2.

[0171] In some examples, as shown in FIG12a, in the above S250, during the process of forming the second channel sub-section 32 and the source contact layer 5 on the side of the epitaxial film 2a away from the substrate 1, a second annular sub-protrusion 122 is also formed on the side of the epitaxial film 2a away from the substrate 1, and the second annular sub-protrusion 122 is located in the termination region B1.

[0172] Specifically, the channel film 3a and the source contact film 5a are located not only in the active region B2 but also in the termination region B1; a portion of the second mask pattern in the third mask layer M3 is also located in the termination region B1, and the portion of the second mask pattern located in the termination region B1 is annular. During the etching of the portion of the source contact film 5a and the channel film 3a located in the active region B2 based on the third mask layer M3, the portion of the source contact film 5a and the channel film 3a located in the termination region B1 is also etched to obtain the second annular sub-protrusion 122.

[0173] As shown in Figure 12b, in the above S260, during the etching and thinning process of the second doped region A2 based on the second channel sub-section 32 and the source contact layer 5, the portion of the epitaxial film 2a located in the termination region B1 is also thinned based on the second channel sub-section 32 and the source contact layer 5.

[0174] Specifically, based on a portion of the second mask pattern located in the termination region B1 of the third mask layer M3, the epitaxial thin film 2a is etched and thinned.

[0175] As shown in Figure 12c, during the formation of the third doped region A3 in S270, a third ion implantation is performed on the portion of the epitaxial film 2a located in the termination region B1 based on the second annular sub-bump 122 to form a field confinement ring 13; the portion located between the second annular sub-bump 122 and the substrate 1, and in contact with the field confinement ring 13, constitutes the first annular sub-bump 121. The first annular sub-bump 121 and the second annular sub-bump 122 constitute the annular bump 12.

[0176] Specifically, a third ion implantation is performed on the epitaxial film 2a based on a portion of the second mask pattern located in the termination region B1 of the third mask layer M3. Subsequently, during the removal of the third mask layer M3, a portion of the source contact film on the side of the second annular sub-protrusion 122 away from the substrate 1 is also removed, for example. The subsequently formed dielectric layer 16 further covers the annular protrusion 12 and the field confinement ring 13.

[0177] By simultaneously fabricating the annular bump 12 and the field confinement ring 13 during the fabrication of the second channel sub-section 32, the source contact layer 5, and the gate semiconductor layer 4, the fabrication process of the semiconductor device can be simplified.

[0178] Of course, the annular protrusion 12 and the field limiting ring 13 can also be fabricated independently of the fabrication process of the second channel sub-section 32, the source contact layer 5 and the gate semiconductor layer 4, and this embodiment does not limit this.

[0179] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate; An epitaxial layer is located on one side of the substrate; A channel portion is located on the side of the epitaxial layer away from the substrate; the channel portion includes a first channel sub-portion and a second channel sub-portion connected to each other, the first channel sub-portion being located between the epitaxial layer and the second channel sub-portion; A gate semiconductor layer is located on the side of the epitaxial layer away from the substrate and surrounds the first channel sub-section; A source contact layer is located on the side of the second channel sub-section away from the substrate; the second channel sub-section separates the source contact layer and the gate semiconductor layer; The drain is located on the side of the substrate away from the epitaxial layer.

2. The semiconductor device according to claim 1, wherein, The orthographic projection of the end of the first channel sub-section that contacts the second channel sub-section onto the substrate is located within the orthographic projection range of the end of the second channel sub-section that contacts the first channel sub-section onto the substrate.

3. The semiconductor device according to claim 2, wherein, The first channel sub-section includes a first portion and a second portion connected to each other, the first portion being located between the epitaxial layer and the second portion; The orthographic projection of the second part onto the substrate is within the orthographic projection range of the first part onto the substrate.

4. The semiconductor device according to claim 3, wherein, The distance between the orthographic projection boundary of the second part on the substrate and the orthographic projection boundary of the first part on the substrate ranges from 0.1 μm to 1 μm.

5. The semiconductor device according to claim 3, wherein, The orthographic projection of the second channel sub-part onto the substrate coincides with the orthographic projection of the first part onto the substrate.

6. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: a current diffusion layer, the current diffusion layer being located between the epitaxial layer and the first channel sub-section, and being in contact with the first channel sub-section; The orthographic projection of the first channel sub-section onto the substrate is located within the orthographic projection range of the current diffusion layer onto the substrate.

7. The semiconductor device according to claim 6, wherein, The current diffusion layer and the first channel sub-section are integrally structured.

8. The semiconductor device according to claim 1, wherein, The number of the channel portions is multiple, and the gate semiconductor layer surrounds the first channel sub-ports of the multiple channel portions; Each of the second channel sub-sections of the channel portion has a source contact layer on the side away from the substrate, and at least two of the source contact layers are electrically connected.

9. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: The source electrode is located on the side of the source electrode contact layer away from the substrate; A first ohmic contact layer is located between the source contact layer and the source electrode; The gate is located on the side of the gate semiconductor layer away from the substrate; A second ohmic contact layer is located between the gate semiconductor layer and the gate.

10. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: Multiple annular protrusions are located on the side of the epitaxial layer away from the substrate and are arranged in a ring around each other in sequence; the multiple annular protrusions surround the channel portion and the gate semiconductor layer. A field limiting ring is located on the side of the epitaxial layer away from the substrate and between two adjacent annular protrusions.

11. The semiconductor device according to claim 10, wherein, The gate semiconductor layer includes a first gate layer and a second gate layer connected to each other; the first gate layer surrounds the first channel sub-section, and the surface of the second gate layer away from the substrate is lower than the surface of the first gate layer away from the substrate. The second gate layer is made of the same material as the field limiting ring and is disposed in the same layer.

12. The semiconductor device according to claim 10, wherein, The annular protrusion includes a first annular sub-protrusion and a second annular sub-protrusion connected to each other, wherein the first annular sub-protrusion is located between the epitaxial layer and the second annular protrusion; The first annular sub-protrusion and the first channel sub-section are disposed in the same layer; The second annular sub-protrusion and the second channel sub-section are made of the same material and are arranged in the same layer.

13. A method for fabricating a semiconductor device, the method comprising: Provide substrate; An epitaxial layer, a channel portion, a gate semiconductor layer, and a source contact layer are formed on one side of the substrate; the channel portion is located on the side of the epitaxial layer away from the substrate; the channel portion includes a first channel sub-portion and a second channel sub-portion connected to each other, the first channel sub-portion being located between the epitaxial layer and the second channel sub-portion; the gate semiconductor layer is located on the side of the epitaxial layer away from the substrate and surrounds the first channel sub-portion; the source contact layer is located on the side of the second channel sub-portion away from the substrate; the second channel sub-portion separates the source contact layer and the gate semiconductor layer; A drain electrode is formed on the side of the substrate away from the epitaxial layer.

14. The preparation method according to claim 13, wherein, The formation of an epitaxial layer, a channel, a gate semiconductor layer, and a source contact layer on one side of the substrate includes: An epitaxial thin film is formed on one side of the substrate; A first ion implantation is performed from the side of the epitaxial film away from the substrate to form a first doped region; A first mask pattern is formed on the side of the epitaxial film away from the substrate, the first mask pattern covering a portion of the first doped region and exposing another portion of the first doped region; Based on the first mask pattern, a second ion implantation is performed from the side of the epitaxial film away from the substrate to form a second doped region; the portion of the first doped region opposite to the second doped region constitutes the second portion of the first channel sub-section, and the second doped region is used to form the gate semiconductor layer; A second channel sub-section and a source contact layer are formed on the side of the epitaxial film away from the substrate; the second channel sub-section covers the first doped region and a portion of the second doped region.

15. The preparation method according to claim 14, wherein, The method of forming an epitaxial layer, a channel portion, a gate semiconductor layer, and a source contact layer on one side of the substrate further includes: Based on the second channel sub-section and the source contact layer, the second doped region is etched and thinned. Based on the second channel sub-region and the source contact layer, a third ion implantation is performed from the side of the epitaxial film away from the substrate to form a third doped region. The third doped region is connected to the second doped region to form the gate semiconductor layer.

16. The preparation method according to claim 15, wherein, The epitaxial thin film has a termination region and an active region, the termination region surrounding the active region; the channel portion and the gate semiconductor layer are located in the active region; During the process of forming the second channel sub-section and the source contact layer on the side of the epitaxial film away from the substrate, a second annular sub-protrusion is also formed on the side of the epitaxial film away from the substrate; the second annular sub-protrusion is located in the termination region; During the etching and thinning process of the second doped region based on the second channel sub-section and the source contact layer, the portion of the epitaxial film located in the termination region is also thinned based on the second channel sub-section and the source contact layer. During the formation of the third doped region, the third ion implantation is also performed on the portion of the epitaxial film located in the termination region based on the second annular sub-bump to form a field confinement ring; the portion located between the second annular sub-bump and the substrate and in contact with the field confinement ring constitutes the first annular sub-bump.

17. The preparation method according to claim 13, wherein, Before forming the drain on the side of the substrate away from the epitaxial layer, the fabrication method further includes: A first ohmic contact layer is formed on the side of the source contact layer away from the substrate, and a second ohmic contact layer is formed on the side of the gate semiconductor layer away from the substrate; A dielectric layer is formed covering the first ohmic contact layer and the second ohmic contact layer; A source and a gate are formed; the source extends through the dielectric layer to the first ohmic contact layer, and the gate extends through the dielectric layer to the second ohmic contact layer.

18. An electronic device, the electronic device comprising: The semiconductor device is the semiconductor device as described in any one of claims 1-12; The circuit board is electrically connected to the semiconductor device.

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