Uncooled infrared detector readout circuit and uncooled infrared detector
By introducing a logic control module and a pixel gating module into the readout circuit of the uncooled infrared detector, and using preset logic gate circuits to control some pixels from being gated, the high power consumption problem caused by the performance improvement of the infrared focal plane array is solved, and power consumption is reduced.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HANGZHOU HIKMICRO SENSING TECH CO LTD
- Filing Date
- 2025-12-25
- Publication Date
- 2026-07-02
Smart Images
Figure CN2025145676_02072026_PF_FP_ABST
Abstract
Description
Uncooled infrared detector readout circuit and uncooled infrared detector Technical Field
[0001] This application relates to, but is not limited to, the field of infrared imaging technology, and in particular to an uncooled infrared detector readout circuit and an uncooled infrared detector. Background Technology
[0002] The thermistor inside an uncooled infrared detector absorbs the radiant energy of a target object and converts it into heat energy. This heat energy alters the physical properties of the thermistor. By converting this change in physical properties into an electrical signal, the target object can be detected.
[0003] With the trend of infrared focal plane arrays becoming larger, smaller, and faster, power consumption is increasing while performance is improving. Summary of the Invention
[0004] A first aspect of this application provides an uncooled infrared detector readout circuit, comprising: an uncooled infrared focal plane array including a plurality of infrared sensitive pixels arranged in the array; a pixel gating module connected to the plurality of infrared sensitive pixels; a logic control module, wherein the logic control module and the pixel gating module are connected to a preset infrared sensitive pixel among the plurality of infrared sensitive pixels through a preset logic gate circuit, and the logic control module is configured to control that none of the preset infrared sensitive pixels connected to the logic control module are selected; and a readout circuit module configured to read out signals from the selected infrared sensitive pixels among the plurality of infrared sensitive pixels.
[0005] In some embodiments, the logic control module is configured to provide a logic control signal to a preset infrared sensitive pixel, and the pixel gating module is configured to send a pixel gating signal to a plurality of infrared sensitive pixels. The logic control signal controls whether the preset infrared sensitive pixel is gated by controlling whether the pixel gating signal of the preset infrared sensitive pixel is invalidated.
[0006] In some embodiments, the pixel gating module includes a row gating module and a column gating module, and the logic gate circuit includes a two-stage logic gate circuit including a first-stage logic gate circuit and a second-stage logic gate circuit; both the first-stage logic gate circuit and the second-stage logic gate circuit have input terminals and output terminals; wherein, the logic gate circuit includes two first-stage logic gate circuits and one second-stage logic gate circuit; the input terminal of one first-stage logic gate circuit is connected to the row gating module and the logic control module, the input terminal of the other first-stage logic gate circuit is connected to the column gating module and the logic control module, and the output terminals of the two first-stage logic gate circuits are connected to the input terminal of the second-stage logic gate circuit; or, the logic gate circuit includes one first-stage logic gate circuit and one second-stage logic gate circuit; the input terminal of the one first-stage logic gate circuit is connected to one of the row gating module and the column gating module and the logic control module; the output terminal of the one first-stage logic gate circuit and the other of the row gating module and the column gating module are connected to the input terminal of the second-stage logic gate circuit.
[0007] In some embodiments, the logic gate is an AND gate, or the logic gate is a combination of a NOR gate and an AND gate.
[0008] In some embodiments, the logic control module is configured to: when the logic control signal is a low-level signal, control that preset infrared sensitive pixels connected to the logic control module are not selected.
[0009] In some embodiments, the uncooled infrared detector readout circuit further includes a power supply circuit that provides power to the plurality of infrared sensitive pixels, and the logic control module is further configured to control the preset infrared sensitive pixels connected to the logic control module to disconnect from the power supply circuit.
[0010] In some embodiments, a preset infrared sensitive pixel connected to the logic control module is connected to the power supply circuit via a switch module, and the switch module is connected to the logic gate circuit; the logic control module is also configured to control the switch module to disconnect.
[0011] In some embodiments, the logic control module is configured to control all preset infrared sensitive pixels connected to the logic control module to be selected, so that all infrared sensitive pixels of the uncooled infrared focal plane array are selected.
[0012] In some embodiments, the logic control module is configured to provide a logic control signal to a preset infrared sensitive pixel, and the logic control module is configured to control all preset infrared sensitive pixels connected to the logic control module to be selected when the logic control signal is a high-level signal.
[0013] In some embodiments, the uncooled infrared detector readout circuit further includes: a prompting module, which is connected to the readout circuit module and the logic control module. The prompting module is configured to generate a prompting signal when the electrical signal read out by the readout circuit module is not within a preset electrical signal range. The logic control module is configured to control the preset infrared sensitive pixels connected to the logic control module to be selected according to the prompting signal.
[0014] In some embodiments, the logic control module is configured to provide a logic control signal according to the prompt signal; the logic control signal has the same waveform as the waveform output by the prompt signal, and the logic control signal and the waveform output by the prompt signal are consistent in timing.
[0015] In some embodiments, the uncooled infrared detector readout circuit further includes a digital control module, wherein the logic control module is integrated in the digital control module or located outside the digital control module, and the digital control module is configured to: provide row gating signals and column gating signals to the pixel gating module, and provide logic control signals to the logic control module to control that the preset infrared sensitive pixels connected to the logic control module are not gating, and to control that the infrared sensitive pixels among the plurality of infrared sensitive pixels that are not connected to the logic control module are gating.
[0016] In some embodiments, the logic control module includes logic control signal lines connected to the preset infrared sensitive pixels. The logic control signal lines, the corresponding row selection signal lines of the preset infrared sensitive pixels, and the corresponding column selection signal lines of the preset infrared sensitive pixels are connected through the logic gate circuits. The logic gate circuit includes two first-level logic gate circuits and one second-level logic gate circuit. The input terminal of one first-level logic gate circuit is connected to the logic control signal line and the row strobe signal line, and the input terminal of the other first-level logic gate circuit is connected to the logic control signal line and the column strobe signal line. The output terminals of the two first-level logic gate circuits are connected to the input terminal of the second-level logic gate circuit, and the output terminal of the second-level logic gate circuit is connected to the corresponding preset infrared sensitive pixel. Alternatively, the logic gate circuit includes one first-level logic gate circuit and one second-level logic gate circuit. The input terminal of the first-level logic gate circuit is connected to one of the row strobe signal line and the column strobe signal line, as well as the logic control signal line. The other of the row strobe signal line and the column strobe signal line, as well as the output terminal of the first-level logic gate circuit, are connected to the input terminal of the second-level logic gate circuit, and the output terminal of the second-level logic gate circuit is connected to the corresponding preset infrared sensitive pixel.
[0017] In some embodiments, the uncooled infrared focal plane array includes M rows and N columns of infrared sensitive pixels, wherein the preset infrared sensitive pixels are located in rows 3 to (M / 2-1) and rows (M / 2+2) to (M-2) and / or columns 3 to (N / 2-1) and columns (N / 2+2) to (N-2) in the uncooled infrared focal plane array.
[0018] A second aspect of this application provides an uncooled infrared detector, the uncooled infrared detector including the uncooled infrared detector readout circuit described above.
[0019] The uncooled infrared detector readout circuit and uncooled infrared detector provided in this application embodiment include a logic control module in the readout circuit. The logic control module and the pixel selection module are connected to some infrared sensitive pixels through preset logic gate circuits, so that the infrared sensitive pixels connected to the logic control module are not selected, thereby narrowing the detection window of the uncooled infrared detector readout circuit. The unselected infrared sensitive pixels do not perform detection work, which helps to reduce the power consumption of the uncooled infrared detector readout circuit.
[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0022] Figure 1 is a schematic diagram of the structure of an uncooled infrared detector readout circuit provided in an embodiment of this application.
[0023] Figure 2 is a schematic diagram of a preset infrared sensitive pixel and its circuit connection provided in an embodiment of this application.
[0024] Figure 3 is a schematic diagram of another preset infrared sensitive pixel and its circuit connection provided in an embodiment of this application.
[0025] Figure 4 is a truth table of the circuits corresponding to Figures 2 and 3 provided in an embodiment of this application.
[0026] Figure 5 shows an infrared sensitive pixel gating timing provided in an embodiment of this application.
[0027] Figure 6 is a schematic diagram of an uncooled infrared focal plane array with preset infrared sensitive pixels not selected, provided in an embodiment of this application.
[0028] Figure 7 is a schematic diagram of an uncooled infrared focal plane array provided in an embodiment of this application, in which all infrared sensitive pixels are selected.
[0029] Figure 8 is a schematic diagram of another uncooled infrared detector readout circuit provided in an embodiment of this application.
[0030] Figure 9 is a schematic diagram of another preset infrared sensitive pixel and its circuit connection provided in an embodiment of this application. Detailed Implementation
[0031] The embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. In the following description, when referring to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.
[0032] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture; if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.
[0033] While the performance of infrared focal plane arrays has improved, power consumption has also increased. When reading out large-area pixel arrays, if all pixels are selected and read out in each detection, a large amount of power consumption is required.
[0034] In view of this, embodiments of this application provide an uncooled infrared detector readout circuit and an uncooled infrared detector. The uncooled infrared detector readout circuit and uncooled infrared detector of this application embodiment will be described in detail below with reference to Figures 1 to 9. Unless otherwise specified, the features of the following embodiments and implementations can complement or combine with each other.
[0035] The uncooled infrared detector readout circuit 100 provided in this application embodiment includes an uncooled infrared focal plane array (UFPA) 10, a pixel gating module 20, a logic control module 70, and a readout circuit module 40.
[0036] The uncooled infrared focal plane array 10 includes a plurality of infrared sensitive pixels 101 arranged in an array. For ease of explanation, the uncooled infrared focal plane array 10 is described below as having M rows and N columns of infrared sensitive pixels 101. Where M and N are both positive integers.
[0037] The pixel gating module 20 is connected to each infrared sensitive pixel 101 and is used to gating the infrared sensitive pixels 101.
[0038] A portion of the multiple infrared sensitive pixels 101 are designated as preset infrared sensitive pixels 1011 and connected to the logic control module 70. The logic control module 70 and the pixel selection module 20 can be connected to the corresponding preset infrared sensitive pixels 1011 via preset logic gate circuits 80.
[0039] The logic control module 70 is configured to control that preset infrared sensitive pixels 1011 connected to the logic control module 70 are not selected.
[0040] The readout circuit module 40 is configured to read out signals from the selected infrared sensitive pixel 101.
[0041] The uncooled infrared detector readout circuit 100 described above includes a logic control module 70. The logic control module 70 and the pixel selection module 20 are connected to the corresponding preset infrared sensitive pixels 1011 through a preset logic gate circuit 80. This prevents the preset infrared sensitive pixels 1011 connected to the logic control module 70 from being selected, while the infrared sensitive pixels 101 not connected to the logic control module 70 are selected. This reduces the detection window of the uncooled infrared detector readout circuit 100 (corresponding to the size of the selected pixel array). The unselected infrared sensitive pixels do not perform detection work, which helps to reduce the power consumption of the uncooled infrared detector readout circuit 100.
[0042] The logic control module 70 is configured to provide corresponding logic control signals en to each of the connected preset infrared sensitive pixels 1011. The pixel gating module 20 is configured to send pixel gating signals to each infrared sensitive pixel 101. The logic control signal en controls whether the preset infrared sensitive pixel 1011 is selected by controlling whether the pixel gating signal of the preset infrared sensitive pixel 1011 is invalid.
[0043] Referring to Figures 2 to 7, in some embodiments, the uncooled infrared detector readout circuit 100 may further include a digital control module 30. The logic control module 70 may be integrated into the digital control module 30 or located outside the digital control module 30.
[0044] The digital control module 30 is responsible for coordinating and managing the operation of the uncooled infrared detector readout circuit 100. This includes acquiring readout signals through the readout circuit module 40, processing the signals, providing an interface for communication with external devices, supporting data transmission with internal modules or external devices, receiving signals from external sources (such as signals transmitted via a computer, or signals input from interactive interfaces like buttons on the detector with the uncooled infrared detector readout circuit 100), and controlling the operation of modules such as the pixel gating module 20 and the logic control module 70. When the digital control module 30 controls the pixel gating module 20 and the logic control module 70, it can send corresponding control signals to the relevant modules as needed, thereby controlling the gating operation of the corresponding pixels.
[0045] As shown in Figure 1, the pixel gating module 20 includes a row gating module 21 and a column gating module 22, which are respectively connected to each infrared sensitive pixel 101.
[0046] Accordingly, the digital control module 30 is also configured to provide corresponding row selection signals row and column selection signals col to the row selection module 21 and column selection module 22 respectively, and to provide a logic control signal en to the logic control module 70, so as to control that the preset infrared sensitive pixels 1011 connected to the logic control module 70 are not selected, and to control that the infrared sensitive pixels 1012 not connected to the logic control module 70 are selected.
[0047] The row gating module 21 can be connected to the infrared sensitive pixel 101 of the corresponding row through the corresponding row gating signal line ROW, and the column gating module 22 can be connected to the infrared sensitive pixel 101 of the corresponding column through the corresponding column gating signal line COL.
[0048] In some embodiments, the readout circuit module 40 can be connected to the corresponding infrared sensitive pixel 101 via signal line 1013. A corresponding switch module 1014 is provided at the connection point between the signal line 1013 and the corresponding infrared sensitive pixel 101. When an infrared sensitive pixel 101 is selected, the switch module 1014 connected to that infrared sensitive pixel 101 is closed, allowing the readout circuit module 40 to read signals via the connected signal line 1013. Conversely, when an infrared sensitive pixel 101 is not selected, the switch module 1014 connected to that infrared sensitive pixel 101 is open, preventing the readout circuit module 40 from reading the corresponding signal.
[0049] It should be noted that each row of infrared sensitive pixels corresponds to one row gating signal line ROW. The uncooled infrared detector readout circuit 100 has M row gating signal lines, namely ROW1, ROW2, ROW3...ROW(M). The row gating module 21 is connected to the infrared sensitive pixel 101 corresponding to each row through the row gating signal lines ROW.
[0050] Each column of infrared sensitive pixels corresponds to one column gating signal line COL. The uncooled infrared detector readout circuit 100 has N column gating signal lines, namely COL1, COL2, COL3...COL(N). The column gating module 22 is connected to the infrared sensitive pixel 101 corresponding to each column through the column gating signal line COL.
[0051] The logic control module 70 of the uncooled infrared detector readout circuit 100 may include a logic control signal line En. The logic control signal line En is connected to a portion of the infrared sensitive pixels 101 (i.e., preset infrared sensitive pixels 1011). The logic control signal line En, the row strobe signal line ROW of the preset infrared sensitive pixel 1011, and the column strobe signal line COL of the preset infrared sensitive pixel 1011 can be connected through a preset logic gate circuit 80.
[0052] In some embodiments, the logic gate circuit 80 may include two levels of logic gate circuits. Accordingly, the logic control module 70, the row strobe signal line ROW of the preset infrared sensitive pixel 1011, and the column strobe signal line COL of the preset infrared sensitive pixel 1011 may be connected to the preset infrared sensitive pixel 1011 using two levels of logic gates.
[0053] In some embodiments, the logic control module 70 and the row and column strobe signal lines connected to the preset infrared sensitive pixel 1011 are connected to the preset infrared sensitive pixel 1011 through a preset two-stage logic gate circuit. The two-stage logic gate circuit may include two connected first-stage logic gate circuits and one second-stage logic gate circuit. Both the first-stage and second-stage logic gate circuits have input and output terminals. The input terminal of one first-stage logic gate circuit is connected to the logic control signal line En and the row strobe signal line ROW to connect to the logic control module 70 and the row strobe module 21; the input terminal of the other first-stage logic gate circuit is connected to the logic control signal line En and the column strobe signal line COL to connect to the logic control module 70 and the column strobe module 22. The output terminals of the two first-stage logic gate circuits are respectively connected to different input terminals of the second-stage logic gate circuit. The output terminal of the second-stage logic gate circuit is connected to the preset infrared sensitive pixel 1011 as the output terminal of the entire logic gate circuit.
[0054] As shown in Figures 1 and 2, the logic control signal line En includes two logic control signal lines 71 and 72. Each row strobe signal line ROW connected to the preset infrared sensitive pixel 1011 can be connected to the logic control signal line 71 through a first-level logic gate circuit 81. Each column strobe signal line COL connected to the preset infrared sensitive pixel 1011 can be connected to the logic control signal line 72 through a first-level logic gate circuit 82. The corresponding two first-level logic gate circuits 81 and 82 are connected to the second-level logic gate circuit 83. Finally, the output terminal of the second-level logic gate circuit 83 is connected to the preset infrared sensitive pixel 1011.
[0055] Continuing with Figures 1 and 2, the row select signal lines ROW connecting the 3rd to (M / 2-1)th and (M / 2+2)th to (M-2)th rows of the uncooled infrared focal plane array 10 are respectively connected to the logic control signal line 71 through a first-level logic gate circuit 81. The column select signal lines COL connecting the 3rd to (N / 2-1)th and (N / 2+2)th to (N-2)th columns of the uncooled infrared focal plane array 10 are respectively connected to the logic control signal line 72 through a first-level logic gate circuit 82. In this configuration, the infrared sensitive pixels 101 located in rows 3 to (M / 2-1), rows (M / 2+2) to (M-2), columns 3 to (N / 2-1), and columns (N / 2+2) to (N-2) in the uncooled infrared focal plane array 10 are designated as preset infrared sensitive pixels 1011. Two first-level logic gates 81 and 82 corresponding to each preset infrared sensitive pixel 1011 are connected to a corresponding second-level logic gate 83, and the output terminal N1 of the corresponding second-level logic gate 83 is connected to the preset infrared sensitive pixel 1011.
[0056] As shown in Figure 2, in some embodiments, the logic gate circuit 80 is an AND gate circuit.
[0057] In the above implementation method using two levels of logic gates, each level of logic gate circuit 80, namely logic gate circuits 81, 82, and 83, is an AND gate circuit.
[0058] In other embodiments, as shown in Figures 1 and 3, the row select signal lines ROW connecting the 3rd to (M / 2-1)th and (M / 2+2)th to (M-2)th rows of the uncooled infrared focal plane array 10 are respectively connected to the logic control signal line 71 through a first-level logic gate circuit 84, and the column select signal lines COL connecting the 3rd to (N / 2-1)th and (N / 2+2)th to (N-2)th columns of the uncooled infrared focal plane array 10 are respectively connected to the logic control signal line 72 through a first-level logic gate circuit 85. In this configuration, the infrared sensitive pixels 101 located in rows 3 to (M / 2-1), rows (M / 2+2) to (M-2), columns 3 to (N / 2-1), and columns (N / 2+2) to (N-2) of the uncooled infrared focal plane array 10 are designated as preset infrared sensitive pixels 1011. Two first-level logic gates 84 and 85 corresponding to each preset infrared sensitive pixel 1011 are connected to a corresponding second-level logic gate 86, and the output terminal N1 of the corresponding second-level logic gate 86 is connected to the preset infrared sensitive pixel 1011. Specifically, the output terminal N1 of the second-level logic gate 86 can be connected to a corresponding switch module 1014 to control the connection with the corresponding signal line 1013.
[0059] As shown in Figure 3, in some embodiments, the logic gate circuit 80 is a combination of a NOR gate circuit and an AND gate circuit. Furthermore, each NOR gate circuit (shown as a curved triangle in Figure 3) also has a NOT gate (shown as a triangle in Figure 3) at its input terminal.
[0060] In the above implementation using two levels of logic gates, logic gates 84 and 85 of logic gate circuit 80 are NOR gates, and logic gate circuit 86 is an AND gate.
[0061] As shown in Figure 8, in some embodiments, specifically in the uncooled infrared detector readout circuit 200, the logic control module 70 and the row strobe signal line connected to the preset infrared sensitive pixel 1011 are connected to the preset infrared sensitive pixel 1011 through a preset two-stage logic gate circuit. The two-stage logic gate circuit may include a first-stage logic gate circuit and a second-stage logic gate circuit. Both the first-stage and second-stage logic gate circuits have input and output terminals. The input terminal of the first-stage logic gate circuit is connected to the logic control signal line En and the row strobe signal line ROW, respectively, to connect to the logic control module 70 and the row strobe module 21. The output terminal of the first-stage logic gate circuit and the column strobe signal line COL are respectively connected to different input terminals of the second-stage logic gate circuit. The output terminal of the second-stage logic gate circuit serves as the output terminal of the entire logic gate circuit and is connected to the preset infrared sensitive pixel 1011.
[0062] As shown in Figures 8 and 9, the logic control signal line En may include a logic control signal line 71. Each row strobe signal line ROW connected to the preset infrared sensitive pixel 1011 can be connected to the logic control signal line 71 through a first-level logic gate circuit 81. The corresponding first-level logic gate circuit 81 and the corresponding column strobe signal line COL are connected to the second-level logic gate circuit 83. Finally, the output terminal of the second-level logic gate circuit 83 is connected to the preset infrared sensitive pixel 1011.
[0063] Continuing with Figures 8 and 9, the row select signal lines ROW connecting the infrared sensitive pixels 101 in rows 3 to (M / 2-1) and (M / 2+2) to (M-2) of the uncooled infrared focal plane array 10 are respectively connected to the logic control signal line 71 through a first-level logic gate circuit 81. The infrared sensitive pixels 101 located in rows 3 to (M / 2-1) and (M / 2+2) to (M-2) of the uncooled infrared focal plane array 10 are designated as preset infrared sensitive pixels 1011. The first-level logic gate circuit 81 and the corresponding column select signal line COL corresponding to each preset infrared sensitive pixel 1011 are connected to the corresponding second-level logic gate circuit 83, and the output terminal N1 of the corresponding second-level logic gate circuit 83 is connected to the preset infrared sensitive pixel 1011.
[0064] As shown in Figure 9, in some embodiments, the logic gate circuit 80 is an AND gate circuit.
[0065] In the above implementation method using two levels of logic gates, each level of logic gate circuit 80, 81 and 83, is an AND gate circuit.
[0066] Of course, in some other embodiments, the logic control module 70 and the row selection signal line connected to the preset infrared sensitive pixel 1011 are connected to the preset infrared sensitive pixel 1011 through a preset two-level logic gate circuit. The logic gate circuit can also be a NOR gate circuit.
[0067] It should be noted that the logic control module 70 and the column strobe signal line connected to the preset infrared sensitive pixel 1011 are connected to the preset infrared sensitive pixel 1011 through a preset two-stage logic gate circuit. The two-stage logic gate circuit may include a first-stage logic gate circuit and a second-stage logic gate circuit. Both the first-stage and second-stage logic gate circuits have input and output terminals. The input terminal of the first-stage logic gate circuit is connected to the logic control signal line En and the column strobe signal line COL. The output terminal of the first-stage logic gate circuit and the row strobe signal line ROW are respectively connected to different input terminals of the second-stage logic gate circuit. The output terminal of the second-stage logic gate circuit serves as the output terminal of the entire logic gate circuit and is connected to the preset infrared sensitive pixel 1011. In this embodiment, the two-stage logic gate circuit can be an AND gate circuit, or a combination of a NOR gate circuit and an AND gate circuit.
[0068] Of course, in other embodiments, the logic control signal lines, row strobe signal lines, and column strobe signal lines can also be connected to the corresponding infrared sensitive pixels through other logic gate circuits. For example, the logic control signal lines, row strobe signal lines, and column strobe signal lines can be connected to the corresponding infrared sensitive pixels through a logic gate circuit with three inputs and one output.
[0069] In some embodiments, the digital control module 30 is configured to control the preset infrared sensitive pixels 1011 connected to the logic control module 70 to be deselected when the logic control signal en is a low level signal.
[0070] As shown in Figure 4, in some embodiments, the low-level signal is 0 and the high-level signal is 1. Referring to Figure 4, when the logic control signal en is a low-level signal (0), regardless of whether the row strobe signal row or the column strobe signal col is a high-level signal or a low-level signal, the output result is 0. That is, the preset infrared sensitive pixel 1011 connected to the logic control module 70 will not be selected.
[0071] In some embodiments, the logic control module 70 includes an enable module, and the logic control signal en is an enable signal.
[0072] In some embodiments, the uncooled infrared detector readout circuit 100 further includes a power supply circuit 60, and each infrared sensitive pixel 101 is connected to the power supply circuit 60. Controlling the preset infrared sensitive pixels 1011 connected to the logic control module 70 to not be selected includes: controlling the preset infrared sensitive pixels 1011 connected to the logic control module 70 to disconnect from the power supply circuit 60.
[0073] It should be noted that a switch module 601 may be provided at the connection point between the power supply circuit 60 and each infrared sensitive pixel 101.
[0074] The logic control module 70, the row selection module 21, and the column selection module 22 are connected to the switching module 601 of each preset infrared sensitive pixel 1011 through a preset logic gate circuit 80.
[0075] Accordingly, the control of the preset infrared sensitive pixel 1011 connected to the logic control module 70 is disconnected from the power supply circuit 60, including: controlling the switch module 601 to disconnect.
[0076] Referring to Figures 1 to 3, in some embodiments, the output terminal N1 of the second-level logic gate circuit 86 can be connected to the switching module 601 of the power supply circuit 60 to control the switching module 601 to disconnect.
[0077] Accordingly, the digital control module 30 can disconnect the preset infrared sensitive pixel 1011 connected to the logic control module 70 from the power circuit 60 by controlling the switch module 601 to disconnect it.
[0078] In some embodiments, the digital control module 30 is further configured to: control all infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 to be selected, and control all power circuits 60 connected to all infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 to be turned on. That is, the digital control module 30 is configured to control preset infrared sensitive pixels 1011 connected to the logic control module 70 and infrared sensitive pixels 1012 not connected to the logic control module 70 to be selected, and control all power circuits 60 connected to the preset infrared sensitive pixels 1011 and infrared sensitive pixels 1012 to be turned on.
[0079] In some embodiments, the digital control module 30 is configured to control the selection of a preset infrared sensitive pixel 1011 connected to the logic control module 70 when the logic control signal en is a high-level signal.
[0080] As shown in Figure 4, in some embodiments, the low-level signal is 0 and the high-level signal is 1. Referring to Figure 4, when the logic control signal en is a high-level signal (1), all preset infrared sensitive pixels 1011, i.e., the infrared sensitive pixels 101 connected to the logic control module 70, are selected. That is, the row selection module and the column selection module can select all infrared sensitive pixels 101. When the row selection signal row and the column selection signal col are high-level signals, the output result is 1, and each infrared sensitive pixel 101 of the uncooled infrared focal plane array 10 can be selected sequentially.
[0081] In some embodiments, the uncooled infrared detector readout circuit 100 further includes a prompting module 50.
[0082] The prompting module 50 is connected to the readout circuit module 40 and the logic control module 70. It generates a prompting signal Alarm when the electrical signal read out by the readout circuit module 40 is not within the preset electrical signal range. The logic control module 70 can control all preset infrared sensitive pixels 1011 connected to the logic control module 70 to be selected according to the prompting signal Alarm, so that all infrared sensitive pixels 101 of the uncooled infrared focal plane array are selected.
[0083] The preset electrical signal range can be set according to specific needs. For example, if the infrared sensitive pixel connected to the logic control module 70 is not selected, while other infrared sensitive pixels are selected, and the image generated by the electrical signal read by the readout circuit module 40 has an abnormality, then it is necessary to add more selected infrared sensitive pixels to further confirm the target to be detected.
[0084] In some embodiments, the prompting module 50 can be connected to the logic control module 70 by connecting to the digital control module 30. The prompting module 50 can provide a prompting signal Alarm to the digital control module 30. The digital control module 30 generates a logic control signal en based on the corresponding prompting signal Alarm. Furthermore, the digital control module 30 can provide the corresponding logic control signal en to the logic control module 70 to control all infrared sensitive pixels of the uncooled infrared focal plane array 10 to be selected.
[0085] Referring to Figure 5, in some embodiments, the waveforms output by the logic control signal en and the prompt signal Alarm are the same, and the waveforms output by the logic control signal en and the prompt signal Alarm are consistent in timing, so as to intelligently control all infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 to be selected, thereby meeting the requirement that all infrared sensitive pixels 101 need to perform detection work.
[0086] It should be noted that in some other embodiments, the digital control module 30 can also control the selection of the preset infrared sensitive pixel 1011 connected to the logic control module 70 in other ways. For example, an external signal can be input to the digital control module 30 via a button or other means, so that the digital control module 30 inputs a corresponding logic control signal en (such as a high-level signal) to the logic control module 70.
[0087] Based on the above description and referring to Figures 4 to 7, the uncooled infrared focal plane array 10 includes M rows and N columns of infrared sensitive pixels 101. The row selection signal lines ROW connecting the 3rd to (M / 2-1)th and (M / 2+2)th to (M-2)th rows of infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 are respectively connected to the logic control signal line 71 through a first-level logic gate circuit 81. The column selection signal lines COL connecting the 3rd to (N / 2-1)th and (N / 2+2)th to (N-2)th columns of infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 are respectively connected to the logic control signal line 72 through a first-level logic gate circuit 82. The two first-level logic gate circuits 81 and 82 corresponding to each preset infrared sensitive pixel 1011 are connected to the corresponding second-level logic gate circuit 83, and the output terminal of the corresponding second-level logic gate circuit 83 is connected to the preset infrared sensitive pixel 1011. The uncooled infrared focal plane array 10, comprising 10 rows and 8 columns of infrared sensitive pixels 101, is used as an example for illustration. The timing diagram only shows the digital timing of the first 3 rows and 3 columns. The START signal is the control signal for the global operation of the entire uncooled infrared detector readout circuit 100. A low START signal indicates that the uncooled infrared detector readout circuit 100 has started operating. The default Alarm signal is low, meaning no abnormality has occurred in the image. When the logic control signal en is low, a low-power mode is enabled. In this low-power mode, the preset infrared sensitive pixels 1011 are not selected, while other infrared sensitive pixels 1012 are selected, as shown in Figure 6. In Figure 6, the infrared sensitive pixels corresponding to the black areas are the selected infrared sensitive pixels 1012, and the infrared sensitive pixels corresponding to the white areas are the unselected preset infrared sensitive pixels 1011. Based on the timing diagram of the first 3 rows and 3 columns, only the infrared sensitive pixels 101 in the first and second rows are selected. At this time, the corresponding infrared sensitive pixels 1012 in the first row and first column, and the infrared sensitive pixels 1012 in the second row and first column are selected. When the prompting module 50 detects that the electrical signal read by the readout circuit module 40 is not within the range of the preset electrical signal (such as voltage or current signal), that is, when the image generated by the electrical signal read out by the uncooled infrared detector readout circuit 100 has an abnormality and requires additional selected infrared sensitive pixels to further confirm the target to be detected, the Alarm signal generated by the prompting module 50 is high. Correspondingly, the logic control signal en is converted to high level, and all infrared sensitive pixels 101 included in the uncooled infrared focal plane array 10 can be selected, as shown in Figure 7. The pixel array is output row by row.
[0088] This application also provides an uncooled infrared detector, which includes the uncooled infrared detector readout circuit 100 described in any of the above embodiments. The uncooled infrared detector of this application can achieve, through simple logic circuitry, deselect the preset infrared sensitive pixel 1011 connected to the logic control module 70, while selecting the infrared sensitive pixel 1012 not connected to the logic control module 70. This reduces the detection window of the uncooled infrared detector readout circuit 100, which helps to reduce the power consumption of the uncooled infrared detector readout circuit 100 and improve its detection efficiency.
[0089] It should be noted that the technical solutions or features described in the above embodiments can be combined or complemented by each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings. All modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A non-cooled infrared detector readout circuit (100, 200), characterized by, The uncooled infrared detector readout circuit (100, 200) includes: An uncooled infrared focal plane array (10) includes multiple infrared sensitive pixels (101) arranged in an array; A pixel gating module (20) is connected to the plurality of infrared sensitive pixels (101); A logic control module (70) and a pixel selection module (20) are connected to a preset infrared sensitive pixel (1011) among the plurality of infrared sensitive pixels (101) via a logic gate circuit (80). The logic control module (70) is configured to control the preset infrared sensitive pixels (1011) connected to the logic control module (70) to not be selected. The readout circuit module (40) is configured to read out signals from the selected infrared sensitive pixels (1012) among the plurality of infrared sensitive pixels (101).
2. The uncooled infrared detector readout circuit (100, 200) as described in claim 1, characterized in that, The logic control module (70) is configured to provide a logic control signal (en) to the preset infrared sensitive pixel (1011). The pixel gating module (20) is configured to send pixel gating signals to the plurality of infrared-sensitive pixels (101). The logic control signal (en) controls whether the preset infrared sensitive pixel (1011) is selected by controlling whether the pixel gating signal of the preset infrared sensitive pixel (1011) is invalidated.
3. The uncooled infrared detector readout circuit (100, 200) as described in claim 1 or 2, characterized in that, The pixel selection module (20) includes a row selection module (21) and a column selection module (22). The logic gate circuit (80) includes a two-stage logic gate circuit consisting of a first-stage logic gate circuit (81, 82; 84, 85) and a second-stage logic gate circuit (83, 86). Both the first-stage logic gate circuit (81, 82; 84, 85) and the second-stage logic gate circuit (83, 86) have input terminals and output terminals. The logic gate circuit (80) includes two first-level logic gate circuits (81, 82; 84, 85) and one second-level logic gate circuit (83, 86); the input of one first-level logic gate circuit (81, 82; 84, 85) is connected to the row selection module (21) and the logic control module (70), the input of the other first-level logic gate circuit (81, 82; 84, 85) is connected to the column selection module (22) and the logic control module (70), and the outputs of the two first-level logic gate circuits (81, 82; 84, 85) are connected to the input of the second-level logic gate circuit (83, 86); or The logic gate circuit (80) includes a first-level logic gate circuit (81) and a second-level logic gate circuit (83); the input terminal of the first-level logic gate circuit (81) is connected to one of the row selection module (21) and the column selection module (22) and the logic control module (70); the output terminal of the first-level logic gate circuit (81) and the other of the row selection module (21) and the column selection module (22) are connected to the input terminal of the second-level logic gate circuit (83).
4. The uncooled infrared detector readout circuit (100, 200) as described in any one of claims 1 to 3, characterized in that, The logic gate circuit (80) is an AND gate circuit, or The logic gate circuit (80) is a combination of NOR gate circuit and AND gate circuit.
5. The uncooled infrared detector readout circuit (100, 200) of claim 2, wherein, The logic control module (70) is configured to control the preset infrared sensitive pixels (1011) connected to the logic control module (70) to be unselected when the logic control signal (en) is a low level signal.
6. The uncooled infrared detector readout circuit (100, 200) as described in any one of claims 1 to 5, further comprising a power supply circuit (60) for providing power to the plurality of infrared sensitive pixels (101), The logic control module (70) is also configured to control the preset infrared sensitive pixel (1011) connected to the logic control module (70) to disconnect from the power supply circuit (60).
7. The uncooled infrared detector readout circuit (100, 200) as described in claim 6, characterized in that, The preset infrared sensitive pixel (1011) connected to the logic control module (70) is connected to the power supply circuit (60) through the switch module (601), and the switch module (601) is connected to the logic gate circuit (80). The logic control module (70) is also configured to control the switch module (601) to disconnect.
8. The uncooled infrared detector readout circuit (100, 200) according to any one of claims 1 to 7, characterized in that The logic control module (70) is configured to control all preset infrared sensitive pixels (1011) connected to the logic control module (70) to be selected, so that all infrared sensitive pixels (101) of the uncooled infrared focal plane array (10) are selected.
9. The uncooled infrared detector readout circuit (100, 200) as described in claim 8, characterized in that, The logic control module (70) is configured to provide a logic control signal (en) to the preset infrared sensitive pixel (1011). The logic control module (70) is configured to control all preset infrared sensitive pixels (1011) connected to the logic control module (70) to be selected when the logic control signal (en) is a high-level signal.
10. The uncooled infrared detector readout circuit (100, 200) as described in claim 8 or 9, further comprising: An alert module (50) is connected to the readout circuit module (40) and the logic control module (70). The alert module (50) is configured to generate an alert signal (Alarm) when the electrical signal read by the readout circuit module (40) is outside a preset electrical signal range. The logic control module (70) is configured to select all the preset infrared sensitive pixels (1011) connected to the logic control module (70) according to the alarm signal.
11. The uncooled infrared detector readout circuit (100, 200) of claim 10, wherein, The logic control module (70) is configured to provide the logic control signal (en) according to the alarm signal; The waveforms output by the logic control signal (en) and the prompt signal (Alarm) are the same, and the timing of the waveforms output by the logic control signal (en) and the prompt signal (Alarm) is consistent.
12. The uncooled infrared detector readout circuit (100, 200) as described in claim 1 further includes a digital control module (30), wherein the logic control module (70) is integrated into the digital control module (30) or located outside the digital control module (30). The digital control module (30) is configured to provide row selection signals (row) and column selection signals (col) to the pixel selection module (20) and to provide logic control signals (en) to the logic control module (70) to control that the preset infrared sensitive pixels (1011) connected to the logic control module (70) are not selected, and to control that the infrared sensitive pixels (1012) among the plurality of infrared sensitive pixels (101) that are not connected to the logic control module (70) are selected.
13. The uncooled infrared detector readout circuit (100, 200) as described in claim 1, characterized in that, The logic control module (70) includes a logic control signal line (En), which is connected to the preset infrared sensitive pixel (1011). The logic control signal line (En), the corresponding row strobe signal line (ROW) of the preset infrared sensitive pixel (1011), and the corresponding column strobe signal line (COL) of the preset infrared sensitive pixel (1011) are connected through the logic gate circuit (80). The logic gate circuit (80) includes two first-level logic gate circuits (81, 82; 84, 85) and one second-level logic gate circuit (83, 86). The input terminal of one first-level logic gate circuit (81, 82; 84, 85) is connected to the logic control signal line (En) and the row strobe signal line (ROW). The input terminal of the other first-level logic gate circuit (81, 82; 84, 85) is connected to the logic control signal line (En) and the column strobe signal line (COL). The output terminals of the two first-level logic gate circuits (81, 82; 84, 85) are connected to the input terminals of the second-level logic gate circuit (83, 86). The output terminal of the second-level logic gate circuit (83, 86) is connected to the corresponding preset infrared sensitive pixel (1011); or The logic gate circuit (80) includes a first-level logic gate circuit (81) and a second-level logic gate circuit (83). The input terminal of the first-level logic gate circuit (81) is connected to one of the row strobe signal line (ROW) and the column strobe signal line (COL) and the logic control signal line (En). The other of the row strobe signal line (ROW) and the column strobe signal line (COL) and the output terminal of the first-level logic gate circuit (81) are connected to the input terminal of the second-level logic gate circuit (83). The output terminal of the second-level logic gate circuit (83) is connected to the corresponding preset infrared sensitive pixel (1011).
14. The uncooled infrared detector readout circuit (100, 200) as described in claim 1, characterized in that, The uncooled infrared focal plane array (10) includes M rows and N columns of infrared sensitive pixels (101), and the preset infrared sensitive pixels (1011) are located in the 3rd row to the (M / 2-1)th row and the (M / 2+2)th row to the (M-2)th row in the uncooled infrared focal plane array (10), and / or the 3rd column to the (N / 2-1)th column and the (N / 2+2)th column to the (N-2)th column.
15. A uncooled infrared detector, comprising: The uncooled infrared detector includes the uncooled infrared detector readout circuit (100, 200) as described in any one of claims 1 to 14.