Optoelectronic device with solderable contacts and manufacture thereof

Abstract

The invention concerns an optoelectronic device, in particular, a surface-emitting LED, comprising solderable electrical contacts featuring a structural design that allows achievement of horizontal stability and significant reduction of tilting during mounting and operation. A manufacturing process that achieves the proposed structural design in a simple and cost-effective process is also introduced.

Description

[0001] 2024PF01056

[0002] OPTOELECTRONIC DEVICE WITH SOLDERABLE CONTACTS AND MANUFACTURE THEREOF

[0003] The present application claims priority from DE application DE 10 2024 139 656.3 dated December 23 , 2024 , the disclosure of which is incorporated herein by reference in its entirety.

[0004] The present invention concerns a light emitting device comprising solderable contact surfaces, in particular, for use in optical data communication applications .

[0005] BACKGROUND

[0006] Semiconductor light emitting diodes (LEDs ) have found widespread application in the field of optical data communication, where they are commonly used in combination with fiber optic transmission elements . High light coupling efficiency to fiber optics is essential for optimal electrical power consumption, particularly in data centers .

[0007] Optical devices based on semiconductor LEDs are frequently used in conjunction with fiber optic elements for data communication applications . Such optical communication devices are commonly characterized by switching speeds in the Gbit / s range, and are often required to operate at high current densities , generally exceeding 1000A / cm2. For optimal operation over the desired lifetime, in some cases, up to 100 , 000 h, it is necessary to ensure high efficiency of light coupling to the fiber optic transmission channels . To achieve this , semiconductor LEDs with minimal topographical differences, in particular, minimal tilting of the light emission surface, are required .

[0008] It is an obj ect of the present application to introduce a manufacturing method that provides improved precision in alignment of mounted LEDs , in particular, for optical data communication in fiber optic-based applications .

[0009] SUMMARY OF THE INVENTION2024PF01056

[0010] Accurate and reliable realization of solderable mounting surfaces that are substantially coplanar, and preferably, substantially parallel to the light emission surface is technically challenging . A simple manufacturing approach allowing achievement of substantially coplanar contact surfaces without necessitating multiple topographical process steps in the semiconductor layers and / or the contact layers is required .

[0011] This and other obj ects are addressed by the subject matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0012] The proposed invention meets the requirements of optical data communication through a manufacturing process resulting in a lateral LED without a topography step in solder connections to the p-doped and n-doped semiconductor layers . This avoids tilting, thereby allowing high accuracy in coupling to fiber optic structures . The proposed invention is in some aspects implemented as an array of lateral LEDs on a CMOS substrate, but is not limited thereto .

[0013] The inventors propose an optoelectronic device, in particular, a surface-emitting light-emitting device . The proposed optoelectronic device features a primary mesa structure for light emission and a secondary mesa structure for defining usable area for soldering . The primary and secondary mesa structures are formed from a common semiconductor stack, thus providing a substantially coplanar surface on which electrical contacts are preferably simultaneously formed . The resultant device is thus advantageously configured to achieve optimal alignment, in particular, when coupled with fiber optic structures for optical communication, without requiring topography steps during manufacture . Additionally, the surface-emitter configuration is associated with more compact size, with overall thickness of the proposed optoelectronic device being less than 30pm. Conductive layers associated with the optoelectronic device, in particular, metal layers , are preferably limited to thicknesses below 1 pm, in particular, thicknesses in the range of a few 100 nm.2024PF01056

[0014] In some aspects , the proposed optoelectronic device comprises at least one first mesa structured layer stack on which a first electrical contact is arranged, serving as the primary mesa structure, and a second electrical contact comprising a conductive metal arranged around at least one corresponding semiconductor core, wherein the semiconductor core serves as the secondary mesa structure . The mesa structured layer stack and the associated core each comprise an active layer arranged between a first doped semiconductor layer and a first region of a second doped semiconductor layer . The active layer is configured to emit electromagnetic radiation, in particular, from the first mesa structured layer stack . In some aspects, the active layer comprises a multi-quantum well structure, wherein alternating sublayers of semiconductor material with different bandgap are used to form alternating quantum well and quantum barrier layers . The material composition, dopant concentration and thickness of the sublayers within the multi-quantum well structure is dependent on desired device characteristics .

[0015] The semiconductor layers may comprise any suitable semiconductor material, in particular, semiconductor nitrides, phosphides and / or arsenides . The first doped layer and the second doped layer comprise dopants of different polarities . In some exemplary aspects , the first doped layer is a p-doped layer, and the second doped layer is an n-doped layer . While this description will primarily focus on aspects based on GaN-based semiconductor devices with a first doped layer comprising p-dopant, the proposed invention is not limited to the aforementioned materials or structure .

[0016] The mesa structured layer stack protrudes from a first lateral surface of the second doped semiconductor layer, said first lateral surface corresponding to an upper surface of a second region of the second doped semiconductor layer . In some aspects, the at least one mesa structured layer stack is completely laterally surrounded by the first lateral surface, such that sidewalls of the mesa structured layer stack are at a lateral distance from sidewalls of the second region of the second doped semiconductor layer . In other aspects , the at least one mesa structured layer stack and the second region of the second doped2024PF01056

[0017] semiconductor layer feature partially coplanar sidewalls, m particular, at a periphery of the semiconductor material . In some aspects wherein the optoelectronic device is implemented as an array of lateral micro-LEDs, the sidewalls bounding the second region of the second doped layer correspond to device boundaries . In other aspects , the sidewalls of the second doped semiconductor layer correspond to boundaries used for subsequent individualization or singulation of optoelectronic devices .

[0018] The second doped semiconductor layer comprises a second lateral surface opposite the first lateral surface . In some aspects , the second lateral surface comprises the main light emission surface . In particular, the main light emission surface is configured to be smaller than the second lateral surface . The main light emission surface is associated with and aligned to the at least one mesa structured layer stack. During operation, the second lateral surface is characterized by a first area comprising the main light emission surface and a second area laterally surrounding the main light emission surface, the second area being characterized by substantially reduced light emission, in particular, wherein light emitted through the second area is associated with diffusion of light generated in the at least one mesa structured layer stack .

[0019] To improve light emission characteristics , in particular, to increase intensity of emitted light, some aspects comprise a roughening and / or structuring on the second lateral surface . The structuring may, for example, be in the form of regular or irregular inverted pyramids , conical structures , truncated frustums, pillar-like structures or any other topography achievable by a roughening and / or structuring process . The structuring is in some aspects positioned within an area corresponding to a proj ection of the mesa structured layer stack onto the second lateral surface, and thereby substantially limited to the main light emission surface . However, in some aspects, the lateral boundaries of the structuring are not confined to the position and dimensions of the mesa structured layer stack. Thus, the position and dimensions of the structuring can vary, depending on the emission2024PF01056

[0020] characteristics desired, as well as optical and structural properties of the semiconductor material layers .

[0021] The at least one semiconductor core similarly protrudes from the first lateral surface of the second region and is laterally surrounded thereby along a plane corresponding to the bottom surface of the core .

[0022] The first contact electrically connecting the first doped layer of the mesa structured layer stack preferably comprises a metal, in particular, a solderable metal . Suitable materials include alloys comprising various combinations of metals such as Sn, Pb, Au, Cu, Ag, Bi, In, Zn and Sb . In general, preferred materials exhibit properties such as stability against oxidation, decomposition and electromigration . High thermal conductivity is also desirable to reduce thermal damage to semiconductor layers during mounting and operation .

[0023] In some aspects , a first conductive layer is arranged between the first contact and the first doped layer . In aspects where the first doped layer comprises a p-dopant, suitable materials for the first conductive layer typically include materials such as ITO, Ag, Pt, Pd, Ni, Au, Rh or Ru. In some aspects , the first conductive layer further comprises a capping layer comprising, for example, Ti, TiW, Pt, Pd, Ni, Cr, ITO or ZnO . The first conductive layer is in some aspects laterally smaller than the first contact, in particular, such that the conductive layer is encapsulated within material of the first contact . Such a structure may be advantageously employed to improve thermal conductivity of the contact elements connected to the first doped layer .

[0024] In other aspects, the first conductive layer comprises a lateral surface area greater than that of the first contact, such that the first contact is laterally surrounded by material of the first conductive layer . This configuration allows increasing of the overall contact area to the first doped layer, which corresponds to a reduction in current density in quantum wells in the active region . In some aspects, in particular, wherein the semiconductor material comprises AlInGaN, variation in the surface area of the first conductive layer2024PF01056

[0025] may be used m association with a droop curve to adjust the resultant brightness , allowing either increase or decrease thereof .

[0026] The conductive metal surrounding the semiconductor core to form the second contact in some aspects comprises a material substantially identical to the first contact . In particular, the conductive metal comprises a solderable metal .

[0027] In some aspects , in particular, in aspects comprising the first conductive layer on the mesa structured layer stack, the second contact further comprises the first conductive layer, in particular, arranged between the conductive metal and the second doped layer of the core . The first conductive layer in some such aspects completely covers the surface of the semiconductor core facing away from the first doped layer . In such aspects , the thickness of the first conductive layer on the mesa structured mesa stack and on the at least one semiconductor core is substantially equal, thereby reducing or eliminating the need for a subsequent topography step to avoid tilting of the device .

[0028] The second contact in some aspects of the proposed invention further comprises a first conductive envelope enclosing the core and optionally extending laterally onto the upper surface of the second region of the second doped layer . In some such aspects, the first conductive envelope is dimensioned such that the lateral extension on the lateral surface remains encapsulated within the conductive metal . Parts of the conductive metal thereby remain in direct contact with the second doped layer . In other aspects , the first conductive envelope extends laterally beyond sidewalls of the conductive metal, such that the envelope forms an interface between the conductive metal and semiconductor material .

[0029] The first conductive envelope improves the thermal and electrical characteristics of the second contact and may comprise materials including but not limited to Al, Ti, Cr, V, ITO or ZnO . For applications where a barrier layer between the second contact and the semiconductor core is a design requirement, the first conductive envelope may comprise material such as Ti, Pt, Cr, Ni or Ru . In such aspects , the2024PF01056

[0030] conductive envelope is typically configured to laterally extend beyond the sidewalls of the conductive metal .

[0031] Some aspects of the proposed principle comprise the first conductive layer and the first conductive envelope arranged on both the mesa structured layer stack and the semiconductor core . On the mesa structured layer stack, the first conductive layer is configured to be embedded within the first conductive envelope . The first conductive envelope in some such aspects comprises smaller lateral dimensions than the first contact, such that the first conductive envelope is laterally surrounded by material of the first contact . In other aspects , the first conductive envelope comprises larger lateral dimensions than the first contact, such that the first contact is physically separated from the first doped layer by material of the first conductive envelope .

[0032] Further aspects of the proposed invention relate to a first dielectric layer arranged on the lateral surface of the second region of the second doped layer . The first dielectric layer may optionally be arranged on the sidewalls of the second region . In some aspects, the sidewalls and part of an upper surface of the mesa structured layer stack laterally adjacent to the first contact comprises the first dielectric layer . In aspects comprising a conductive layer with lateral dimensions greater than the first contact, the dielectric layer is arranged to cover surfaces of the conductive layer extending beyond the first contact, such that the first dielectric layer is laterally adjacent to sidewalls of the first contact .

[0033] The first dielectric layer comprises any suitable dielectric material, including but not limited to at least one of SiO2, SiNx, A12O3, Nb2O5, TiO2and HfO2. The first dielectric layer may be deposited by such processes as atomic layer deposition (ALD) , sputtering, chemical vapor deposition (CVD) , or any other suitable process . The first dielectric layer serves as a protective layer for the underlying semiconductor layers , and further improves lateral isolation between the first and second contacts, preventing short-circuiting .2024PF01056

[0034] Further aspects of the proposed invention comprise a second dielectric layer arranged on the second lateral surface of the second doped layer, which in some aspects forms an emission surface of the optoelectronic device . The second dielectric layer passivates the second doped layer, protecting it against external forces or foreign material . Furthermore, the presence of the dielectric layer influences the light extraction efficiency of the optoelectronic device . In some aspects, this is advantageously exploited by implementation of the second dielectric layer as a distributed Bragg Reflector (DBR) structure . The sublayers of the DBR can be configured to achieve refractive index matching or interference, depending on the application . In other aspects , the DBR structure is configured as a filter to screen out undesired wavelengths . Some aspects featuring a structured and / or roughened second lateral surface benefit from a selective increase in reflectance by the DBR, wherein flat surfaces of the second doped layer are characterized by an increased reflectance whereas structured areas are not affected . Thus, the light intensity in the structured region is increased .

[0035] Some aspects of the proposed invention further comprise a third dielectric layer arranged at least partially along the sidewalls of the core . The third dielectric layer may be implemented as a sidewall spacer layer .

[0036] Further aspects of the proposed invention relate to alternative arrangement of the mesa structured layer stack in relation to the second contact . In some such aspects, the mesa structured layer stack is at least partially surrounded by the second contact, for example, in a concentric arrangement . The second contact in such aspects is structured substantially in the form of a continuous or broken ring surrounding the mesa structured layer stack, with a lateral separation between the mesa structured layer stack and the second contact . Such a configuration is not limited to substantially circular mesa structured layer stacks , and may be implemented, for example, as hexagonal, square or rectangular forms . In other aspects , the second contact forms the central element, and is surrounded by a mesa structured layer stack in the form of a continuous or broken ring . Such configurations may, in2024PF01056

[0037] particular, find application m semiconductor LEDs whose dimensions fall within the mini-LED range and above .

[0038] Further aspects of the proposed principle relate to a method of processing an optoelectronic device . In an initial step, a semiconductor layer stack comprising an active layer arranged between a first doped layer and a second doped layer is provided. In particular, the active layer is configured to emit electromagnetic radiation. In some aspects , the semiconductor layer stack is arranged on a substrate on which it has been epitaxially grown. Such a growth substrate may comprise silicon, sapphire, or any other suitable growth substrate . The material, structure and thickness of the semiconductor layers depends on design requirements . For example, in some aspects , the doped layers may comprise multiple sublayers with different material and / or thickness and / or dopant concentrations . The active layer may comprise a multi quantum well (MQW) structure, with alternating quantum wells and quantum barriers . In some aspects , a doped layer corresponding to the light output side is thicker than a doped layer corresponding to a backside of the optoelectronic device .

[0039] Subsequently, the semiconductor layer stack is etched to form at least one mesa structured layer stack and at least one core, with the depth of etching configured to correspond to the first doped layer, the active layer and a first region of the second doped layer . The mesa structured layer stack and the at least one core thus protrude from a first lateral surface corresponding to an upper surface of a second region of the second doped layer . Any suitable wet and / or dry etch process may be employed in this step, with process parameters depending on design requirements . In some aspects , the mesa structured layer stack and the at least one core are laterally distanced from each other .

[0040] The mesa structured layer stack forms the light-emitting structure and is dimensioned depending on the desired emission characteristics . In some aspects , the lateral dimensions of the semiconductor core are configured depending on soldering requirements , with the usable area for soldering being defined by the semiconductor core . In some aspects ,2024PF01056

[0041] m particular, wherein the dimensions of the optoelectronic device are within the pLED range, that is , less than 100 pm, the semiconductor core is configured to comprise a surface area corresponding to at least 10% of the chip area . For aspects of the optoelectronic device outside the pLED range of dimensions , the size of the semiconductor core may fall outside the given range, and depends on the desired bond characteristics, material composition used for subsequently deposited solderable contacts, among other design requirements .

[0042] In some aspects , a subsequent etch is performed on the structured layer stack thereby defining the sidewalls of the second region of the second doped layer . In some such aspects, the subsequent etch is configured to form a sidewall that is laterally distanced from sidewalls of the at least one mesa structured layer stack and the semiconductor core, forming a stepped configuration. In such aspects , the mesa structured layer stack is laterally surrounded by the first lateral surface of the second region of the second doped layer . In other aspects, the subsequent etch is configured such that the sidewalls of the second doped layer are partially continuous with sidewalls of the mesa structured layer stack . In such aspects , the mesa structured layer stack is positioned at a periphery of the semiconductor layer stack and is thus only partially surrounded by the first lateral surface of the second region of the second doped layer .

[0043] The subsequent etch is in some aspects characterized by an etching depth substantially greater than the initial etch for the formation of the mesa structured layer stack and the semiconductor core . In an exemplary aspect involving manufacture of a pLED, the first etch is configured to form a shallow mesa with a depth of 1 pm, while the subsequent etch results in a 3 pm deep mesa . In some aspects , the deep mesa formed during the subsequent etch is used for singulation during further chip processing .

[0044] In some aspects , a first conductive layer is deposited on the first doped layer of the mesa structured layer stack. In some such aspects , the first conductive layer comprises at least one of ITO, Ag, Pt, Pd, Ni, Au, Rh and / or Ru . Depending on the material composition of the2024PF01056

[0045] semiconductor layer stack and the structure of the doped layers , other suitable materials may be employed. In some aspects , a capping layer is deposited on the first conductive layer, resulting in a multi-layer structure . Such a capping layer may comprise at least one of Ti, TiW, Pt, Pd, Ni, Cr, ITO or ZnO .

[0046] Some aspects of the proposed method further involve depositing the first conductive layer on the semiconductor core . For a simplified process, the first conductive layer is formed on both the mesa structured layer stack and the semiconductor core through common deposition processes . The first conductive layer on the semiconductor core is configured to cover the first doped layer of the semiconductor core .

[0047] Further aspects of the proposed method comprise a step of depositing a second conductive layer to enclose the semiconductor core, encapsulating the semiconductor core within material of the second conductive layer . In aspects involving a GaN-based semiconductor stack with the first doped layer corresponding to a p-doped layer, the second conductive layer corresponds to an n-contact . The second conductive layer may extend laterally along the lateral first surface of the second region, such that a base of the semiconductor core is laterally surrounded by material of the second conductive layer . In some aspects , the second conductive layer comprises at least one of Al, Ti, Cr, V, ITO or ZnO . In other aspects, the second conductive layer additionally or alternatively comprises a barrier metal such as Ti, Pt, Cr, Ni or Ru . Other materials may be employed, including the materials used for the first conductive layer .

[0048] In some aspects of the proposed method, the second conductive layer is deposited on the mesa structured layer stack, in particular, such that the first conductive layer is encapsulated within the second conductive layer . In some such aspects , the lateral dimensions of the second conductive layer on the mesa structured layer stack are configured to be smaller than the lateral dimensions of the first electrical contact, such that the second conductive layer is enclosed within the first2024PF01056

[0049] electrical contact . In other aspects, the second conductive layer extends laterally beyond the first electrical contact .

[0050] A subsequent step involves depositing a metal layer, in particular, a solderable metal, to form at least one first electrical contact on the mesa structured layer stack and a conductive metal surrounding the semiconductor core . The conductive metal and the semiconductor core form a second contact of the optoelectronic device . The first contact and the second contact are laterally distanced from each other . The first contact electrically connects the first doped layer of the mesa structured layer stack and the second contact electrically connects the second doped layer .

[0051] Formation of the first contact and the second contact using a common deposition process improves the uniformity of the solder layer, with improved accuracy achieved in terms of solder thickness and coplanarity of the upper surfaces of the first and second contacts . In some exemplary aspects, the first and second contacts comprise AuSn . The current invention is however not restricted thereto, and other soldering alloys comprising different combinations of metals such as Au, Ag, Sn, Sb, Bi, etc . may be used, depending on desired bond characteristics and material composition of the semiconductor layer stack .

[0052] In some aspects, the first electrical contact is deposited to surround and enclose the first conductive layer . In such aspects, in particular, wherein the first conductive layer comprises a non-metallic material, the encapsulation of the first conductive layer within the first electrical contact improves thermal conductivity. In other aspects , the first electrical contact is deposited such that it is laterally surrounded by material of the first conductive layer . Such a configuration increases the contact area of the first conductive layer, reducing current density in quantum wells in the active layer . Suitable dimensioning of the contact area may be used to increase or decrease emission brightness in AlInGaN based semiconductors based on a droop curve .2024PF01056

[0053] Deposition of the conductive metal forming the second contact is m some aspects performed in a two-step process , wherein a first step involves depositing the solderable metal to a height corresponding to the semiconductor core and the associated mesa structured layer stack . A subsequent second step involves forming the first electrical contact on the mesa structured layer mask and depositing an additional layer of solderable metal on the semiconductor core, wherein, optionally, the conductive metal forming the second contact comprises a stepped structure resulting from a reduction in cross-sectional area during the second deposition step . A two-step deposition process may be particularly advantageous in aspects wherein the additional layers deposited on the mesa structured layer stack differ from the layers deposited on the semiconductor core .

[0054] Some aspects of the proposed method involve depositing a first dielectric layer on the lateral first surface surrounding the mesa structured layer stack, and optionally, on the sidewalls of the second region of the second doped layer prior to depositing the solderable metal . In some such aspects , the first dielectric layer is deposited to additionally cover the sidewalls and part of an upper surface of the mesa structured layer stack . The first dielectric layer is subsequently structured before depositing the conductive metal . The first dielectric layer may comprise any suitable dielectric material, including but not limited to SiO2, SiNx, A12O3, Nb2O5, TiO2and Hf 02. Structuring of the dielectric layer may involve any suitable dry or wet etching process .

[0055] In some aspects of the proposed method, parts of a second lateral surface of the second doped layer facing away from the first lateral surface are locally roughened and / or otherwise structured to form an uneven surface . The roughening and / or structuring is configured to align with the mesa structured layer stack and increases the light extraction efficiency of the optoelectronic device . In some aspects , the structuring comprises pyramids or inverted pyramids , conical structures , frustums , and / or other regular or irregular textural features resulting from the roughening process . The structuring is in some aspects positioned within a proj ection of the mesa structured2024PF01056 14

[0056] layer stack onto the second lateral surface . In other aspects , at least part of the structuring may extend beyond the projection of the mesa structured layer stack onto the second lateral surface .

[0057] A second dielectric layer is in some aspects deposited on the second surface of the second doped layer . In some such aspects, the second dielectric layer comprises a distributed Bragg reflector (DBR) structure . The material and thickness of the DBR sublayers are advantageously selected to achieve desired emission characteristics . For example, in some aspects, the DBR is configured to achieve refractive index matching or interference . In other aspects , the DBR is configured to filter out unwanted wavelengths . The DBR may additionally or alternatively be configured to increase reflectance at flat areas of the second lateral surface and produce no reflectance-related effect at structured and / or roughened areas . The light intensity in the roughened area is thereby increased .

[0058] Further aspects of the proposed method may involve depositing a third dielectric layer on sidewalls of the semiconductor core . The depositing of the third dielectric layer may be implemented as a spacer formation process, in particular, using approaches applied to the formation of sidewall spacers in semiconductor devices .

[0059] SHORT DESCRIPTION OF THE DRAWINGS

[0060] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0061] Figure 1 shows an exemplary aspect of a proposed optoelectronic device;

[0062] Figures 2 to 8 illustrate various aspects of the proposed optoelectronic;

[0063] Figures 9A to 9D show some steps in a proposed method for processing an optoelectronic device;2024PF01056

[0064] DETAILED DESCRIPTION

[0065] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise, different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado, without this contradicting the principle according to the invention . Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without, however, contradicting the inventive idea .

[0066] In addition, the individual figures and aspects are not necessarily shown in the correct size, nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged. However, terms such as "above", "over", "below", "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0067] Figure 1 shows an optoelectronic device according to some aspects of the proposed invention. The exemplary optoelectronic device comprises a mesa structured layer stack ( 110 ) with a first contact ( 114 ) arranged thereupon and a corresponding second contact ( 124 ) comprising a semiconductor core ( 120 ) embedded within a conductive metal ( 122 ) . The mesa structured layer stack ( 110 ) and the semiconductor core ( 120 ) comprise substantially identical multilayer structures , each being characterized by an active layer ( 112 ) arranged between a first doped layer ( 110 ) and a first region ( 113 ) of a second doped layer ( 100 ) . The active layer ( 112 ) is configured to emit electromagnetic radiation and comprises at least one quantum well arranged between quantum barrier sublayers . In some aspects, the active layer comprises a multiquantum well structure .2024PF01056 16

[0068] The mesa structured layer stack is laterally surrounded by a f rst lateral surface ( 103 ) of a second region ( 101 ) of the second doped layer ( 100 ) and protrudes therefrom . The semiconductor core ( 120 ) similarly protrudes from the first lateral surface ( 103 ) of the second region ( 101 ) and is positioned at a lateral distance from the mesa structured layer stack ( 110 ) . A second lateral surface ( 104 ) of the second doped layer ( 100 ) opposite the first lateral surface ( 103 ) comprises a main light-emission surface associated with the mesa structured layer stack ( 110 ) . The boundaries of the light-emission surface correspond to a proj ection of the mesa-structured layer stack ( 110 ) onto the second lateral surface ( 104 ) . During operation, the light-emission surface forms a first area of the second lateral surface ( 104 ) , the first area being surrounded by a second area of the second lateral surface . Most of the emitted light exits the optoelectronic device through the first area , with the second area being characterized by substantially reduced light emission intensity .

[0069] The first contact ( 114 ) connects electrically to the first doped layer ( 111 ) of the mesa structured layer stack ( 110 ) , and the second contact ( 124 ) connects electrically to the second doped layer ( 100 ) of the optoelectronic device . In some aspects , the first contact ( 114 ) and at least part of the second contact ( 124 ) are formed using a common deposition process , thus comprising the same material , preferably a solderable metal such as AuSn . The second contact ( 124 ) may comprise a stepped structure , wherein the conductive metal ( 122 ) is characterized by a first sidewall region ( 123a ) extending from the first lateral surface ( 103 ) of the second region to a plane corresponding to an upper surface of the semiconductor core ( 120 ) , and a second sidewall region ( 123b ) formed above the upper surface of the semiconductor core ( 120 ) .

[0070] Simultaneous deposition of the electrical contacts enables formation of substantially coplanar upper surfaces on the first contact ( 114 ) and the second contact ( 124 ) . The optoelectronic device can subsequently be mounted to a carrier substrate , for example , a CMOS logic circuit board by soldering . The substantially coplanar upper surfaces achieved by the proposed invention result in significant reduction or substantial elimination of tilting during mounting ,2024PF01056

[0071] allowing for easy alignment of the emission surface with fiber optic elements .

[0072] In some aspects , the mesa structured layer stack ( 110 ) further comprises a first conductive layer ( 116 ) arranged between the first contact ( 114 ) and the first doped layer ( 111 ) . The first conductive layer ( 116 ) allows improved thermal and electrical conductivity between the first doped layer ( 111 ) and the first contact ( 114 ) . In the illustrated aspect , the first conductive layer ( 116 ) is embedded within and laterally surrounded by the first contact ( 114 ) , such that the effective contact area is dependent on the lateral dimensions of the first contact .

[0073] The first lateral surface ( 103 ) and the sidewalls of the second region ( 101 ) comprise a first dielectric layer ( 105 ) , which, in the illustrated aspect , extends to cover sidewalls and part of an upper lateral surface of the mesa structured layer stack ( 110 ) . In some aspects , the second lateral surface ( 104 ) of the second doped layer ( 100 ) comprises a structured region ( 106 ) aligned with the mesa structured layer stack ( 110 ) for improvement of emission characteristics of the optoelectronic device . In particular , the structured region ( 106 ) corresponds to the main light-emission surface which, during operation, forms the first area of the second lateral surface ( 104 ) from which most of the emitted light exits the optoelectronic device . The structuring ( 106 ) may be in the form of inverted pyramids , as illustrated, or may alternatively comprise conical or frustum-shaped structures , or complex irregular patterning formed by a roughening process .

[0074] In Figures 2 to 8 , various aspects of the proposed invention are illustrated . In some aspects , as shown in Figure 2 , the first conductive layer ( 116a, 116b ) is arranged on the first doped layer of the mesa structured layer stack ( 110 ) and the semiconductor core ( 120 ) . Reduction of complexity in the manufacturing process is achieved through a common deposition process for both surfaces , thereby allowing achievement of substantially identical layer thickness , and correspondingly allowing formation of coplanar top surfaces of the2024PF01056

[0075] first and second contacts ( 114 , 124 ) , providing that the underlying mesa structured layer stack ( 110 ) and semiconductor core ( 120 ) are processed to have substantially coplanar upper surfaces . The conductive layer ( 116b ) on the semiconductor core ( 120 ) is in the illustrated embodiment arranged to completely cover the first doped layer . This may allow reduced complexity in the topographical structure of the second contact ( 124 ) .

[0076] Figure 3 illustrates some aspects of the proposed invention, wherein the first conductive layer ( 116a ) on the mesa structured layer stack ( 110 ) is characterized by lateral dimensions larger than the first electrical contact ( 114 ) , such that the conductive layer ( 114 ) laterally surrounds the first electrical contact . The increased contact area allows configuration of output brightness based on a droop curve , in particular, for AlInGaN based devices . Additionally, the current density in the quantum wells is reduced .

[0077] In some aspects , a second conductive layer ( 121 ) is arranged to surround and encapsulate the semiconductor core ( 120 ) . In some such aspects , the second conductive layer extends laterally along a basal plane of the semiconductor core to cover part of the second doped layer . The lateral extension of the second conductive layer ( 121 ) may be configured such that the second conductive layer is encapsulated within and surrounded by the conductive metal forming the second contact , as illustrated in Figure 4 . Alternatively, as shown in Figures 5 and 6 , the lateral extension of the second conductive layer at the base of the semiconductor core is such that material of the second conductive layer separates the conductive metal ( 122 ) from the second doped layer adj acent to the semiconductor core ( 120 ) . The first dielectric layer ( 105 ) is arranged to partially cover the second conductive layer ( 121 ) , in particular, enclosing material of the second conductive layer extending laterally beyond the conductive metal ( 122 ) . Figure 6 illustrates further aspects wherein the second conductive layer ( 121a , 121b ) is arranged to encapsulate the first conductive layer ( 116a , 116b ) on the mesa structured layer stack and on the semiconductor core . Due to the substantially identical layers involved in this2024PF01056 19

[0078] configuration, the optoelectronic device is characterized by improved horizontal stability and reduction of tilting during mounting .

[0079] Figure 7 illustrates some aspects of the proposed invention wherein a third dielectric layer ( 125 ) is arranged on the sidewalls of the semiconductor core . The third dielectric layer may be implemented as a sidewall spacer . In some aspects, as illustrated, the first conductive layer ( 116b) on the semiconductor core comprises a cross section smaller than an upper surface of the semiconductor core, such that the first conductive layer ( 116b) is laterally distanced from the third dielectric layer ( 125 ) .

[0080] In Figure 8 , some aspects of the proposed principle wherein a second dielectric layer ( 108 ) is arranged on the second lateral surface ( 104 ) of the second doped layer are shown . The second dielectric layer ( 108 ) in some aspects comprises a distributed Bragg reflector (DBR) structure .

[0081] Figures 9A to 9D illustrate some steps in a method of processing an optoelectronic device according to the proposed principle . A semiconductor layer stack comprising an active layer arranged between a first doped layer and a second doped layer is etched to form a mesa structured layer stack ( 110 ) and a semiconductor core ( 120 ) protruding from a first lateral surface ( 103 ) of a second region ( 101 ) of the second doped layer, as shown in Figure 9A. In a subsequent deep mesa etch, shown in Figure 9B, sidewalls of the second region of the second doped layer are defined. In some aspects, as illustrated, the sidewalls of the second region ( 101 ) are laterally distanced from the sidewalls of the mesa structured layer stack ( 101 ) . Thereafter, as shown in Figure 9C, the first conductive layer ( 116 ) is deposited on the mesa structured laser stack . A subsequent step, illustrated in Figure 9D involves depositing a solderable metal to form a first electrical contact ( 114 ) on the mesa structured layer stack and a second contact ( 124 ) comprising a conductive metal ( 122 ) surrounding the semiconductor core ( 120 ) .2024PF01056

[0082] LIST OF REFERENCES

[0083] 100 second doped layer

[0084] 101 second region of second doped layer 103 first lateral surface

[0085] 104 second lateral surface

[0086] 105 first dielectric layer

[0087] 106 structured region

[0088] 108 second dielectric layer

[0089] 110 mesa structured layer stack

[0090] 111 first doped layer

[0091] 112 active layer

[0092] 113 first region of second doped layer 114 first electrical contact

[0093] 116 first conductive layer

[0094] 120 semiconductor core

[0095] 121 second conductive layer

[0096] 122 conductive metal

[0097] 123a first sidewall region

[0098] 123b second sidewall region

[0099] 124 second electrical contact

[0100] 125 third dielectric layer

Claims

2024PF01056CLAIMS1 . Optoelectronic device comprising :- A mesa structured layer stack ( 110 ) comprising an active layer ( 112 ) arranged between a first doped semiconductor layer ( 111 ) and a first region ( 113 ) of a second doped semiconductor layer ( 100 ) ;- A second region ( 101 ) of the second doped semiconductor layer ( 100 ) having a first lateral surface ( 103 ) at least partially surrounding the layer stack ( 110 ) and a second lateral surface ( 104 ) opposite the first lateral surface ( 103 ) , wherein the second lateral surface ( 104 ) comprises the main light emission surface of the optoelectronic device ;- A first contact ( 114 ) electrically connecting the first doped semiconductor layer ( 111 ) ;- A second contact ( 124 ) on the first lateral surface ( 103 ) laterally distanced from the mesa structured layer stack ( 110 ) , said second contact comprising :o A core ( 120 ) comprising a layer stack having a structure substantially identical to the mesa structured layer stack o A conductive metal ( 122 ) arranged on the surface and sidewalls of the core and extend above an adj acent portion of the lateral surface surrounding the core .2 . Device according to claim 1 , further comprising a first conductive layer ( 116 ) arranged between the first contact ( 114 ) and the mesa structured layer stack ( 110 ) .3 . Device according to claim 2 , wherein part of the first conductive layer ( 116 ) laterally adj oins and surrounds the first contact ( 114 ) .4 . Device according to claim 2 , wherein the first conductive layer ( 116 ) is embedded within the first contact ( 114 ) .5 . Device according to any of the preceding claims 2 to 4 , wherein the second contact ( 124 ) further comprises the first conductive layer2024PF01056( 116 ) arranged between the core ( 120 ) and the conductive metal ( 122 ) .6 . Device according to any of the preceding claims 2 to 5 , wherein the first conductive layer ( 116 ) is enclosed within a second conductive layer ( 121 ) .7 . Device according to any of the preceding claims , wherein a top surface of the first contact ( 114 ) is substantially flush with a top surface of the second contact ( 124 ) .8 . Device according to any of the preceding claims , wherein the second contact further comprises the second conductive layer ( 121 ) enclosing the core ( 120 ) and optionally extending laterally onto the first lateral surface ( 103 ) .9 . Device according to claim 8 , wherein the conductive metal ( 122 ) is separated from the first lateral surface ( 103 ) by material of the first conductive layer ( 121 ) .10 . Device according to any of the preceding claims , further comprising at least one of :- a first dielectric layer ( 105 ) arranged on the first lateral surface ( 103 ) , and optionally, on the second doped layer and sidewalls of the mesa structured layer stack ( 110 ) , such that the first contact ( 114 ) is laterally surrounded by the first dielectric layer ( 105 ) ; and / or- a second dielectric layer arranged on a second lateral surface ( 104 ) of the second doped semiconductor layer ( 100 ) opposite the first lateral surface ( 103 ) .11 . Device according to claim 10 , wherein the second dielectric layer comprises a distributed Bragg reflector layer .12 . Device according to any of the preceding claims , further comprising a third dielectric layer ( 125 ) arranged at least partially on the sidewalls of the core ( 120 ) .2024PF0105613 . Device according to any of the preceding claims , further comprising a structured and / or roughened region ( 106 ) on the second lateral surface ( 104 ) , in particular, wherein the structuring and / or roughening is located at least partially within a proj ection of the mesa structured layer stack ( 110 ) onto the second lateral surface ( 104 ) .14 . Device according to any of the preceding claims , wherein part of the sidewalls of the mesa structured layer stack ( 110 ) and part of the sidewalls of the second region ( 101 ) of the second doped layer are substantially coplanar .15 . Device according to any of the preceding claims , wherein at least one mesa structured layer stack ( 110 ) and at least one second contact ( 124 ) comprise substantially concentric shapes such that :- the at least one mesa-structured layer stack ( 110 ) is at least partially laterally surrounded by the at least one second contact ( 124 ) ; or- the at least one second contact ( 124 ) is at least partially laterally surrounded by the at least one mesa-structured layer stack ( 110 ) .16 . Method of processing an optoelectronic device , comprising the steps :- Providing a semiconductor layer stack comprising a first doped layer ( 111 ) , an active layer ( 112 ) and a second doped layer ( 100 ) ;- Etching through the semiconductor layer stack to form at least one mesa structured layer stack ( 110 ) and at least one core ( 120 ) , each protruding from a first lateral surface ( 103 ) of a second region ( 101 ) of the second doped layer, wherein the at least one mesa structured layer stack ( 110 ) is laterally distanced from the at least one core ( 120 ) , and wherein the at least one mesa structured layer stack ( 110 ) is at least partially surrounded by the first lateral surface ( 103 ) .- Depositing at least one first contact ( 114 ) electrically connecting the first doped layer ( 111 ) of the at least one mesa structured layer stack ( 110 ) , and a conductive metal2024PF01056 24( 122 ) surrounding the at least one core ( 120 ) , and electrically connecting the second doped semiconductor layer ( 100 ) .17 . Method according to claim 16 , wherein the step of etching through the semiconductor layer stack comprises a first etch to form sidewalls of the at least one mesa structured layer stack and the at least one core , and a second etch to form sidewalls of the second region of the second doped layer , optionally forming a stepped sidewall structure .18 . Method according to any of claims 16 to 17 , further comprising a step of depositing at least one first conductive layer ( 116 ) on the first doped layer ( 113 ) of the at least one mesa structured layer stack ( 110 ) and optionally, the first doped layer of the core ( 120 ) .19 . Method according to any of claims 16 to 18 , further comprising at least one of :- depositing a second conductive layer ( 121 ) enclosing the at least one core ( 120 ) and optionally extending laterally on the first lateral surface ( 103 ) ; and / or - depositing a second conductive layer ( 121 ) enclosing the at least one first conductive layer ( 116 ) on the mesa structured layer stack ( 110 ) .20 . Method according to any of claims 18 or 19 , wherein the step of depositing at least one first contact ( 114 ) is such that the first conductive layer and optionally, the second conductive layer is laterally confined within an area defined by a proj ection of at least one first contact .21 . Method according to any of claims 16 to 20 , further comprising a step of depositing a first dielectric layer on at least one of :- the sidewalls and partially on the first doped layer of the mesa structured layer stack; and / or- the first lateral surface ( 103 ) ; and / or- the sidewalls of the second region .2024PF01056 2522 . Method according to any of claims 16 to 21 , further comprising a step of roughening and / or structuring at least part of a second lateral surface ( 104 ) of the second doped layer facing away from the first lateral surface ( 103 ) , in particular , such that the 5 structuring ( 106 ) is positioned at least partially within a proj ection of the first mesa structured layer stack ( 110 ) onto the second surface ( 104 ) .23 . Method according to any of claims 16 to 22 , further comprising a 0 step of depositing a second dielectric layer ( 108 ) on the second lateral surface ( 104 ) , optionally wherein the second dielectric layer comprises a distributed Bragg reflector layer .24 . Method according to any of claims 16 to 22 , further comprising a 5 step of depositing a third dielectric layer ( 125 ) on sidewalls of the at least one second semiconductor mesa stack .

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