Semiconductor device and method for producing semiconductor device

Abstract

Provided is a robust semiconductor device. The present invention involves first to fourth transistors, all of which are vertical transistors. Source electrodes or drain electrodes of the first transistor and the second transistor are connected to each other, and the first transistor and the second transistor share a semiconductor layer, a gate insulating layer, and a gate electrode. Similarly, source electrodes or drain electrodes of the third transistor and the fourth transistor are connected to each other, and the third transistor and the fourth transistor share a semiconductor layer, a gate insulating layer, and a gate electrode. The connected source electrodes or drain electrodes of the first transistor and the second transistor are connected to the connected source electrodes or drain electrodes of the third transistor and the fourth transistor.

Description

Semiconductor device and method for manufacturing a semiconductor device.

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a display device, a display module, and electronic equipment. Another aspect of the present invention relates to a method for manufacturing a transistor and a method for manufacturing a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), electronic devices having the same, methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] In recent years, display devices have been applied to a wide variety of uses. Examples of large-scale display devices include home television systems, digital signage, and PID (Public Information Display). Display devices are also widely used in smartphones and tablet devices equipped with touch panels.

[0005] As a display device, a light-emitting device (also called a light-emitting element) has been developed. Light-emitting devices that utilize the electroluminescence (EL) phenomenon (also called EL devices or EL elements) have features such as being easy to make thin and light, being able to respond quickly to input signals, and being able to be driven using a DC constant voltage power supply. For example, Patent Document 1 discloses an example of a display device using an organic EL element.

[0006] Furthermore, in order to reduce the production cost and mounting area of ​​driver ICs (Integrated Circuits) provided in display devices, a technique is disclosed in Patent Document 2 in which a part of the circuit constituting the source driver is formed on a glass substrate, similar to the pixel circuit.

[0007] Japanese Patent Publication No. 2002-324673 Japanese Patent Publication No. 2019-20687

[0008] A display device is equipped with a drive circuit (gate driver) for selecting pixels and a drive circuit (source driver) for supplying data to the selected pixels. Furthermore, a display device with touch panel functionality is also equipped with a drive circuit for driving touch sensors.

[0009] IC chips are used in some or all of these driving circuits. These IC chips can be mounted on the bezel of the substrate on which the pixel circuits are formed, but the manufacturing cost of the display device increases as the number of IC chips to be mounted increases. It also hinders the narrowing of the bezel. To address these issues, it is desirable to form some or all of the driving circuits monolithically on the same substrate as the pixel circuits.

[0010] To form a drive circuit, it is necessary to use transistors suitable for high-speed operation. Generally, it is preferable to use transistors with a large on-current to improve charge and discharge characteristics.

[0011] One way to increase the on-current of a transistor is to shorten its channel length. However, it is known that shortening the channel length of a transistor makes it more susceptible to several adverse effects collectively known as short-channel effects. For example, when a transistor is turned on, electrons accelerated by the strong electric field between the source and drain (so-called hot carriers or hot electrons) are injected into the gate insulating film near the drain. This can damage the injection site, causing the on-current to plateau (i.e., the drain current does not increase as easily as the gate voltage increases) and inducing other problems (so-called hot carrier degradation).

[0012] Therefore, transistors used in drive circuits are expected to incorporate features to suppress hot carrier degradation.

[0013] Therefore, one aspect of the present invention aims to provide a highly reliable semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can suppress hot carrier degradation and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a minutely sized transistor and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a small semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a narrow-bezel display device. Alternatively, one aspect of the present invention aims to provide a highly reliable display device. Alternatively, one aspect of the present invention aims to provide an electronic device having the above-mentioned display device. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device, display device, or electronic device.

[0014] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0015] One aspect of the present invention comprises a first conductive layer to a seventh conductive layer, a first semiconductor layer and a second semiconductor layer, a first insulating layer and a second insulating layer, wherein the first to fourth conductive layers are each located in different regions on the same plane, the first insulating layer is located in an island-like manner on the first to fourth conductive layers such that it has regions overlapping with each of the first to fourth conductive layers, the fifth conductive layer is located on the first insulating layer, and the first semiconductor layer is located on the upper surface of the first conductive layer, the upper surface of the second conductive layer, a part of the side surface of the first insulating layer, and the fifth The semiconductor device is configured such that the second semiconductor layer is in contact with a portion of the side surface of the conductive layer and a portion of the upper surface of the fifth conductive layer, the second semiconductor layer is in contact with the upper surface of the third conductive layer, the upper surface of the fourth conductive layer, another portion of the side surface of the first insulating layer, another portion of the side surface of the fifth conductive layer, and another portion of the upper surface of the fifth conductive layer, the second insulating layer is located on the first semiconductor layer and the second semiconductor layer, the sixth conductive layer is located on the second insulating layer such that it has a region overlapping with the first semiconductor layer, and the seventh conductive layer is located on the second insulating layer such that it has a region overlapping with the second semiconductor layer.

[0016] Furthermore, in the above, it is preferable that the first semiconductor layer and the second semiconductor layer are each a metal oxide containing indium, the first insulating layer comprises a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer, the third insulating layer and the fifth insulating layer each contain silicon and nitrogen, and the fourth insulating layer contains silicon and oxygen.

[0017] Furthermore, in the above, it is preferable that a sixth insulating layer is located below the first to fourth conductive layers, the upper surface of the sixth insulating layer is in contact with the first to fourth conductive layers, and the sixth insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0018] Furthermore, one aspect of the present invention includes a first conductive layer to a seventh conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer to a fifth insulating layer, wherein the first insulating layer is located in an island shape on a first region of the first conductive layer, the second insulating layer is located in an island shape on a second region of the first conductive layer, the third insulating layer is located in an island shape on a third region of the first conductive layer, the fourth insulating layer is located in an island shape on a fourth region of the first conductive layer, the second conductive layer is located on the first insulating layer, the third conductive layer is located on the second insulating layer, the fourth conductive layer is located on the third insulating layer, the fifth conductive layer is located on the fourth insulating layer, and the first semiconductor layer is The semiconductor device comprises a second semiconductor layer in contact with a portion of the upper surface of the first conductive layer, a side surface of the first insulating layer, the upper and side surfaces of the second conductive layer, a side surface of the second insulating layer, and the upper and side surfaces of the third conductive layer, and the second semiconductor layer in contact with another portion of the upper surface of the first conductive layer, a side surface of the third insulating layer, the upper and side surfaces of the fourth conductive layer, a side surface of the fourth insulating layer, and the upper and side surfaces of the fifth conductive layer, the fifth insulating layer located on the first and second semiconductor layers, the sixth conductive layer located on the fifth insulating layer such that it overlaps with the first semiconductor layer, and the seventh conductive layer located on the fifth insulating layer such that it overlaps with the second semiconductor layer.

[0019] Furthermore, in the above, the first semiconductor layer and the second semiconductor layer are each a metal oxide containing indium, the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer, the second insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer, the third insulating layer has a twelfth insulating layer, a thirteenth insulating layer on the twelfth insulating layer, and a fourteenth insulating layer on the thirteenth insulating layer. Preferably, the fourth insulating layer comprises a 15th insulating layer, a 16th insulating layer on the 15th insulating layer, and a 17th insulating layer on the 16th insulating layer, and the sixth insulating layer, eighth insulating layer, ninth insulating layer, eleventh insulating layer, twelfth insulating layer, fourteenth insulating layer, fifteenth insulating layer, and seventeenth insulating layer each contain silicon and nitrogen, and the seventh insulating layer, tenth insulating layer, thirteenth insulating layer, and sixteenth insulating layer each contain silicon and oxygen.

[0020] Furthermore, in the above, it is preferable that the 18th insulating layer is located below the first to fourth insulating layers, the upper surface of the 18th insulating layer is in contact with the first to fourth insulating layers, and the 18th insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0021] Furthermore, one aspect of the present invention includes a first to ninth conductive layer, a first semiconductor layer and a second semiconductor layer, and a first to third insulating layer, wherein the first to fifth conductive layers are each located in different regions on the same plane, the first insulating layer is located on the first conductive layer, on the third conductive layer and on the first region such that it has a region overlapping with the first region of the first conductive layer, the third conductive layer and the fifth conductive layer, the second insulating layer is located on the second conductive layer, on the fourth conductive layer and on the second region such that it has a region overlapping with the second region of the second conductive layer, the fourth conductive layer and the fifth conductive layer, the sixth conductive layer is located on the first insulating layer, the seventh conductive layer is located on the second insulating layer, and the first semiconductor layer is located on the upper surface of the first conductive layer, the upper surface of the second conductive layer and on the fifth conductive layer The semiconductor device is configured such that the eighth conductive layer is located on the third conductive layer, the ninth conductive layer is located on the third conductive layer, and

[0022] Furthermore, in the above, it is preferable that the first semiconductor layer and the second semiconductor layer are each a metal oxide containing indium, the first insulating layer has a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer, the second insulating layer has a seventh insulating layer, an eighth insulating layer on the seventh insulating layer, and a ninth insulating layer on the eighth insulating layer, the fourth insulating layer, the sixth insulating layer, the seventh insulating layer, and the ninth insulating layer each contain silicon and nitrogen, and the fifth insulating layer and the eighth insulating layer each contain silicon and oxygen.

[0023] Furthermore, in the above, it is preferable that a 10th insulating layer is located below the first to fifth conductive layers, the upper surface of the 10th insulating layer is in contact with the first to fifth conductive layers, and the 10th insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0024] Furthermore, one aspect of the present invention comprises a first conductive layer to a ninth conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer to a sixth insulating layer, wherein the first conductive layer and the second conductive layer are located in different regions on the same plane, the first insulating layer is located on a first region of the first conductive layer, the second insulating layer is located on a second region of the first conductive layer, the third insulating layer is located on a third region of the second conductive layer, and the fourth insulating layer is The second conductive layer is located on the fourth region of the second conductive layer, the fifth insulating layer is located on the fifth region of the first conductive layer and on the sixth region of the second conductive layer, the third conductive layer is located on the first insulating layer, the fourth conductive layer is located on the second insulating layer, the fifth conductive layer is located on the third insulating layer, the sixth conductive layer is located on the fourth insulating layer, the seventh conductive layer is located on the fifth insulating layer, and the first semiconductor layer is located on a part of the upper surface of the first conductive layer and on the second conductive layer. The second semiconductor layer is in contact with a part of the surface, the side surface of the first insulating layer, the side surface of the third insulating layer, a part of the side surface of the fifth insulating layer, the side surface of the third conductive layer, the top surface of the third conductive layer, the side surface of the fifth conductive layer, a part of the side surface of the seventh conductive layer, and a part of the top surface of the seventh conductive layer, and the second semiconductor layer is in contact with another part of the top surface of the first conductive layer, another part of the top surface of the second conductive layer, the side surface of the second insulating layer, the side surface of the fourth insulating layer, another part of the side surface of the fifth insulating layer, and the fourth conductive layer The semiconductor device is in contact with the side surface, the upper surface of the fourth conductive layer, the side surface of the sixth conductive layer, the upper surface of the sixth conductive layer, another part of the side surface of the seventh conductive layer, and another part of the upper surface of the seventh conductive layer, the sixth insulating layer is located on the first semiconductor layer and the second semiconductor layer, the eighth conductive layer is located on the sixth insulating layer such that it has a region overlapping with the first semiconductor layer, and the ninth conductive layer is located on the sixth insulating layer such that it has a region overlapping with the second semiconductor layer.

[0025] Furthermore, in the above, the first semiconductor layer and the second semiconductor layer are each a metal oxide containing indium, the first insulating layer has a seventh insulating layer, an eighth insulating layer on the seventh insulating layer, and a ninth insulating layer on the eighth insulating layer, the second insulating layer has a tenth insulating layer, an eleventh insulating layer on the tenth insulating layer, and a twelfth insulating layer on the eleventh insulating layer, the third insulating layer has a thirteenth insulating layer, a fourteenth insulating layer on the thirteenth insulating layer, and a fifteenth insulating layer on the fourteenth insulating layer, the fourth insulating layer has a sixteenth insulating layer, and a seventeenth insulating layer on the sixteenth insulating layer The fifth insulating layer comprises a 19th insulating layer, a 20th insulating layer on the 19th insulating layer, and a 21st insulating layer on the 20th insulating layer. Preferably, the seventh, ninth, tenth, twelfth, thirteenth, fifteenth, sixteenth, eighteenth, nineteenth, and 21st insulating layers each contain silicon and nitrogen, while the eighth, eleventh, fourteenth, seventeenth, and 20th insulating layers each contain silicon and oxygen.

[0026] Furthermore, in the above, it is preferable that a 22nd insulating layer is located below the first conductive layer and the second conductive layer, the upper surface of the 22nd insulating layer is in contact with the first conductive layer and the second conductive layer, and the 22nd insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0027] Furthermore, in one aspect of the present invention, a first conductive layer to a fourth conductive layer is formed, a first insulating film and a first conductive film are formed in this order on the first conductive layer to the fourth conductive layer, the first conductive film and the first insulating film are processed to have regions that overlap with the first conductive layer to the fourth conductive layer, respectively, to form a fifth conductive layer and a first insulating layer, respectively, and a first semiconductor layer is formed that is in contact with the upper surface of the first conductive layer, the upper surface of the second conductive layer, a part of the side surface of the first insulating layer, a part of the side surface of the fifth conductive layer, and a part of the upper surface of the fifth conductive layer. This is a method for manufacturing a semiconductor device, comprising: forming a second semiconductor layer in contact with the upper surface of the third conductive layer, the upper surface of the fourth conductive layer, another part of the side surface of the first insulating layer, another part of the side surface of the fifth conductive layer, and another part of the upper surface of the fifth conductive layer; forming a second insulating layer in contact with the upper surfaces of the first and second semiconductor layers, respectively; forming a sixth conductive layer in contact with the second insulating layer such that it overlaps with the first semiconductor layer; and forming a seventh conductive layer in contact with the second insulating layer such that it overlaps with the second semiconductor layer.

[0028] According to one aspect of the present invention, a highly reliable semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device capable of suppressing hot carrier degradation and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a minute-sized transistor and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a miniature semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a narrow-bezel display device can be provided. Alternatively, according to one aspect of the present invention, a highly reliable display device can be provided. Alternatively, according to one aspect of the present invention, an electronic device having the above-mentioned display device can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device, display device, or electronic device can be provided.

[0029] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0030] Figure 1A is a plan view showing an example of a semiconductor device. Figures 1B and 1C are cross-sectional views showing an example of a semiconductor device. Figures 2A and 2B are perspective views showing an example of a semiconductor device. Figures 3A and 3B are perspective views showing an example of a semiconductor device. Figure 4A is a plan view showing an example of a semiconductor device. Figures 4B and 4C are cross-sectional views showing an example of a semiconductor device. Figures 5A and 5B are perspective views showing an example of a semiconductor device. Figures 6A and 6B are perspective views showing an example of a semiconductor device. Figures 7A and 7B are circuit diagrams illustrating a semiconductor device. Figure 8A is a plan view showing an example of a semiconductor device. Figure 8B is a cross-sectional view showing an example of a semiconductor device. Figures 9A and 9B are perspective views showing an example of a semiconductor device. Figures 10A and 10B are perspective views showing an example of a semiconductor device. Figure 11A is a plan view showing an example of a semiconductor device. Figure 11B is a cross-sectional view showing an example of a semiconductor device. Figures 12A and 12B are perspective views showing an example of a semiconductor device. Figures 13A and 13B are perspective views showing an example of a semiconductor device. Figures 14A and 14B are circuit diagrams illustrating a semiconductor device. Figure 15A is a plan view showing an example of a semiconductor device manufacturing method. Figures 15B and 15C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 16A is a plan view showing an example of a semiconductor device manufacturing method. Figures 16B and 16C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 17A is a plan view showing an example of a semiconductor device manufacturing method. Figures 17B and 17C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 18A is a plan view showing an example of a semiconductor device manufacturing method. Figures 18B and 18C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 19A is a plan view showing an example of a semiconductor device manufacturing method. Figures 19B and 19C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 20 is a circuit diagram showing an example of a semiconductor device. Figures 21A, 21B, 21C, and 21D are circuit diagrams illustrating an example of operation of a conventional semiconductor device. Figures 22A and 22B are circuit diagrams illustrating an example of operation of a semiconductor device. Figures 23A and 23B are circuit diagrams illustrating an example of the operation of a semiconductor device.Figures 24A and 24B are circuit diagrams illustrating an example of semiconductor device operation. Figure 25 is a circuit diagram illustrating an example of semiconductor device operation. Figure 26 is a circuit diagram illustrating an example of semiconductor device operation. Figure 27 is a circuit diagram illustrating an example of semiconductor device operation. Figure 28 is a circuit diagram illustrating an example of semiconductor device operation. Figure 29 is a circuit diagram illustrating an example of semiconductor device operation. Figure 30 is a circuit diagram illustrating an example of semiconductor device operation. Figure 31 is a circuit diagram showing an example configuration of a shift register circuit. Figure 32A is a block diagram showing an example configuration of a sequential circuit. Figures 32B and 32C are timing charts illustrating an example of shift register circuit operation. Figures 33A, 33B, 33C, and 33D are diagrams illustrating an example of electronic equipment. Figures 34A, 34B, 34C, 34D, 34E, and 34F are diagrams illustrating an example of electronic equipment. Figures 35A, 35B, 35C, 35D, 35E, and 35F are diagrams illustrating an example of electronic equipment.

[0031] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0032] Furthermore, the ordinal numbers "first," "second," and "third" in this specification are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Also, for example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0033] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0034] The positions, sizes, and extents of each component shown in the drawings may not represent their actual positions, sizes, and extents for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the drawings.

[0035] In addition, in drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X axis, and unless explicitly stated, the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction".

[0036] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0037] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0038] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, etc., depending on the situation.

[0039] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0040] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0041] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0042] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0043] Furthermore, even if an element is shown as a single element in a circuit diagram, it may be composed of multiple elements as long as there is no functional disadvantage. For example, multiple transistors that act as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0044] Furthermore, a single conductor may have multiple functions such as wiring, electrodes, and terminals, and in this specification, multiple names may be used for the same element. Also, even if elements are shown as directly connected in a circuit diagram, they may actually be connected via one or more conductors, and in this specification, such configurations are included in the category of direct connection.

[0045] In this specification, a series connection of transistors means that in two adjacent transistors, the drain of one transistor is connected to the source of the other transistor. Furthermore, while the semiconductor device used in one embodiment of the present invention is assumed to have an n-type conductivity, it is not limited to this, and a p-type transistor can also be used by switching the high and low potentials of the supplied power supply.

[0046] In this specification, among the transistors connected in series, the transistor closest to the high-potential power line will be referred to as the "front-end transistor," and the transistor closest to the low-potential power line will be referred to as the "last-end transistor." Furthermore, among the source and drain terminals of each transistor connected in series, the terminal that is on the high-potential side when conducting will be referred to as the drain, and the terminal that is on the low-potential side when conducting will be referred to as the source. Among the transistors connected in series, the drain of the front-end transistor is connected to the high-potential power line, and the source of the last-end transistor is connected to the low-potential power line.

[0047] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0048] In this specification, "approximately matching top surface shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in these cases, it may also be said that the "top surface shapes are approximately matching."

[0049] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0050] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 70 degrees or more and 110 degrees or less.

[0051] Furthermore, in this specification, "approximately matching height" refers to a configuration in which the height from a reference surface (for example, a flat surface such as the substrate surface) is approximately equal in a cross-sectional view. For example, when a planarization treatment (typically chemical mechanical polishing (CMP) treatment) is performed, the treated surface will have approximately matching height. However, even after a planarization treatment, the height may not be exactly the same depending on the film material, but in this specification, this is also considered to be "approximately matching height".

[0052] (Embodiment 1) In this embodiment, an example of the configuration and manufacturing method of a semiconductor device according to one aspect of the present invention will be described.

[0053] One aspect of the present invention is a semiconductor device having a function to suppress the degradation of hot carriers in a transistor. This semiconductor device can be used, for example, as an element of a drive circuit for a display device.

[0054] A semiconductor device according to one aspect of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first insulating layer.

[0055] The first to fourth transistors are all vertical transistors in which the source electrode and drain electrode are provided at different heights relative to the substrate surface, and the drain current flows in the vertical direction. Therefore, they can be made smaller and have a smaller footprint than planar transistors in which the source electrode and drain electrode are provided on the same plane. The first to fourth transistors having the above-described structure makes it possible to miniaturize and highly integrate semiconductor devices.

[0056] The first and second transistors share a conductive layer that functions as either the source electrode or the drain electrode of their respective transistors. In other words, the first and second transistors are connected in series.

[0057] Furthermore, the first transistor and the second transistor share a semiconductor layer that functions as their respective channel-forming region. Also, the first transistor and the second transistor share an insulating layer that functions as their respective gate insulating layer. Furthermore, the first transistor and the second transistor share a conductive layer that functions as their respective gate electrode.

[0058] The configuration combining the first and second transistors described above can be considered equivalent to a single transistor whose channel length is the sum of the channel lengths of the individual transistors. Therefore, the overall channel length of the transistor can be made longer than in the case of a configuration with only one of the transistors, and the breakdown voltage of the transistor (resistance to voltage, specifically the breakdown voltage between the source and drain of the transistor) can be increased.

[0059] The third and fourth transistors also have the same combination configuration as the first and second transistors described above. That is, the third and fourth transistors are connected in series and share a conductive layer that functions as either the source electrode or the drain electrode of each other, a semiconductor layer that functions as a channel forming region, an insulating layer that functions as a gate insulating layer, and a conductive layer that functions as a gate electrode. As a result, the combination of the third and fourth transistors can enjoy the same effects as the combination of the first and second transistors described above.

[0060] The combination of the first transistor and the second transistor, and the combination of the third transistor and the fourth transistor, are provided in parallel with each other. That is, a semiconductor device according to one aspect of the present invention has a configuration in which two combinations of series-connected transistors (a combination of the first transistor and the second transistor, and a combination of the third transistor and the fourth transistor) are provided in parallel.

[0061] Furthermore, a conductive layer that functions as either the source electrode or drain electrode shared by the first and second transistors can also function as either the source electrode or drain electrode shared by the third and fourth transistors. In other words, the first through fourth transistors share a conductive layer that functions as either the source electrode or drain electrode among the four transistors.

[0062] The first insulating layer is provided in an island-like manner, having a region sandwiched between the source electrode and drain electrode of each of the first to fourth transistors.

[0063] A semiconductor device according to one aspect of the present invention has the above-described configuration, so that, for example, when the first transistor and the second transistor are turned on, the potential generated at one of their source electrodes or drain electrodes can also be applied to one of the source electrodes or drain electrodes of the third transistor and the fourth transistor.

[0064] For example, consider the case where the first and second transistors are turned on, and then the third and fourth transistors are turned on. In this case, a certain potential is supplied in advance to either the source electrode or the drain electrode of the third and fourth transistors. Therefore, it is possible to prevent the transistors from being turned on when an extremely large potential difference is generated between the source electrode and drain electrode of the third and fourth transistors. Consequently, the possibility of hot carrier degradation of the transistors can be reduced compared to when the third and fourth transistors are turned on from the beginning.

[0065] Thus, in one aspect of the present invention, a highly reliable semiconductor device can be realized by providing two sets of series-connected transistors in parallel and sharing either the source electrode or the drain electrode of all transistors.

[0066] A semiconductor device according to one aspect of the present invention has at least four transistors. However, as described above, vertical transistors can be used for each transistor, and some components can be shared. Therefore, compared to, for example, the case where four planar transistors are provided adjacent to each other on the same plane, the area occupied by the semiconductor device on the substrate can be significantly reduced. In addition, vertical transistors can have extremely short channel lengths, making it easier to increase the on-current compared to planar transistors. Therefore, a semiconductor device according to one aspect of the present invention can be suitably applied to circuits that perform high-speed operation. For example, by applying a semiconductor device according to one aspect of the present invention to the drive circuit of a display device, a display device that achieves both high-speed operation and a narrow bezel can be realized.

[0067] In the following section, a specific example of the configuration of a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0068] <Example of Semiconductor Device Configuration 1> Figure 1A shows a plan view (also called a top view) of the semiconductor device 100A. Figure 1B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 1A, and Figure 1C shows a cross-sectional view along the dashed line B1-B2 shown in Figure 1A. Note that in Figure 1A, some of the components of the semiconductor device 100A (such as the insulating layer) are omitted. In subsequent drawings of semiconductor devices, some of the components may also be omitted, similar to Figure 1A.

[0069] The semiconductor device 100A includes transistors 10A1_1, 10A1_2, 10A2_1, 10A2_2, an insulating layer 110, and an insulating layer 109.

[0070] The insulating layer 109 is provided on the substrate 102. Transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 are each provided in different regions on the insulating layer 109.

[0071] In Figures 1B and 1C, an example is shown in which the insulating layer 110 has a laminated structure comprising insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b. The insulating layer 110b is made of an insulating material that contains oxygen and can release oxygen. The insulating layers 110a and 110c are made of insulating materials that can suppress oxygen permeation (insulating materials that have barrier properties against oxygen), respectively.

[0072] In this specification, the term "barrier film" refers to a film that possesses barrier properties. Barrier properties refer to one or both of the following functions: a function that makes it difficult for a target substance to diffuse, thereby suppressing the permeation of the substance through the film (also known as low permeability); and a function that captures or fixes the substance (also known as gettering). For example, an insulating layer that possesses barrier properties can be called a barrier insulating layer.

[0073] The transistor 10A1_1 has a conductive layer 104_1, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a1_1, and a conductive layer 112b12. The conductive layer 104_1 functions as a gate electrode. A portion of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a1_1 functions as either a source electrode or a drain electrode. The conductive layer 112b12 functions as either a source electrode or a drain electrode. Of the semiconductor layer 108_1, the region that overlaps with the gate electrode via the gate insulating layer between the source electrode and the drain electrode functions as a channel forming region. Furthermore, of the semiconductor layer 108_1, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region.

[0074] The description relating to transistor 10A1_1 described above can be applied to transistor 10A1_2 by replacing conductive layer 112a1_1 with conductive layer 112a1_2.

[0075] The description relating to transistor 10A1_1 above can be applied to transistor 10A2_1 by replacing the conductive layer 112a1_1, semiconductor layer 108_1, and conductive layer 104_1 with conductive layer 112a2_1, semiconductor layer 108_2, and conductive layer 104_2, respectively.

[0076] The description relating to transistor 10A1_1 above can be applied to transistor 10A2_2 by replacing the conductive layer 112a1_1, semiconductor layer 108_1, and conductive layer 104_1 with conductive layer 112a2_2, semiconductor layer 108_2, and conductive layer 104_2, respectively.

[0077] Transistors 10A1_1 and 10A1_2 share some components, specifically the conductive layer 112b12, the semiconductor layer 108_1, the insulating layer 106, and the conductive layer 104_1, respectively.

[0078] Since transistors 10A1_1 and 10A1_2 share the other side of either the source electrode or the drain electrode (conductive layer 112b12), they can be said to be connected in series.

[0079] Furthermore, transistors 10A1_1 and 10A1_2 share each other's semiconductor layer (semiconductor layer 108_1), gate insulating layer (insulating layer 106), and gate electrode (conductive layer 104_1). Therefore, the configuration combining transistors 10A1_1 and 10A1_2 can be considered equivalent to a single transistor whose channel length is the sum of the channel lengths of each transistor. Consequently, the overall channel length of the transistor can be made longer than in the case of a configuration with only one of the transistors, and the breakdown voltage of the transistor (specifically, the breakdown voltage between the source and drain of the transistor) can be increased.

[0080] Since transistors can operate as switches, the combination of transistors 10A1_1 and 10A1_2 (corresponding to a single transistor with a long channel length) is shown as switch 100A1 in Figures 1A and 1B.

[0081] The same description relating to transistors 10A1_1 and 10A1_2 (description relating to the connection relationship between the two transistors, etc.) can be applied to transistors 10A2_1 and 10A2_2 by replacing semiconductor layer 108_1 and conductive layer 104_1 with semiconductor layer 108_2 and conductive layer 104_2, respectively. In Figures 1A and 1C, the combination of transistor 10A2_1 and transistor 10A2_2 is shown as switch 100A2.

[0082] As shown in Figures 1A to 1C, transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 share a conductive layer (conductive layer 112b12) that functions as the other of their respective source or drain electrodes. The semiconductor device 100A has two switches (switch 100A1 and switch 100A2) arranged in parallel with each other, and these two switches are connected by the conductive layer 112b12. Figure 7A shows a circuit diagram illustrating the configuration of the semiconductor device 100A.

[0083] For example, in semiconductor device 100A, when switch 100A1 is turned ON, the potential generated at the connection point (first node) between the source electrode and drain electrode of transistors 10A1_1 and 10A1_2 can also be applied to the connection point (second node) between the source electrode and drain electrode of transistors 10A2_1 and 10A2_2 in switch 100A2 via the conductive layer 112b12.

[0084] For example, consider the case where switch 100A2 is turned on after switch 100A1 has been turned on. In this case, a certain magnitude of potential (the same magnitude as the potential generated at the first node) is supplied to the second node of switch 100A2 in advance. Therefore, it is possible to prevent switch 100A2 from being turned on when an extremely large potential difference is generated between the source and drain of transistor 10A2_1 and the source and drain of transistor 10A2_2. Consequently, the possibility of hot carrier degradation of transistors 10A2_1 and 10A2_2 can be reduced compared to the case where switch 100A2 is operated without going through the operation of switch 100A1.

[0085] Figure 2A shows a perspective view of the semiconductor device 100A. Some insulating layers (insulating layer 110 and insulating layer 106) are shown as transparent, with only their outlines indicated by dashed lines. Figure 2B is a perspective view from Figure 2A, with conductive layer 104_1, conductive layer 104_2, and insulating layer 106 omitted. Figure 3A is a perspective view from Figure 2B, with semiconductor layer 108_1 and semiconductor layer 108_2 omitted. In the perspective view of Figure 3A, the outline of insulating layer 110 is shown with a solid line. Figure 3B is a perspective view from Figure 3A, with conductive layer 112b12 and insulating layer 110 omitted. In subsequent drawings, as with Figure 2A, some insulating layers may be shown as transparent in the perspective views of the semiconductor device. Also, the outlines of insulating layers may be shown with dashed lines.

[0086] The conductive layers (conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2) that function as either the source electrode or the drain electrode of transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2, respectively, are provided in different regions on the insulating layer 109, as shown in Figure 3B and the like. Each of the conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2 can be configured to extend in the Y direction, for example.

[0087] As shown in Figure 3A and the like, the insulating layer 110 is provided in an island-like manner on conductive layer 112a1_1, conductive layer 112a1_2, conductive layer 112a2_1, conductive layer 112a2_2, and insulating layer 109, with regions overlapping with each of the conductive layers 112a1_1, conductive layer 112a1_2, conductive layer 112a2_1, and conductive layer 112a2_2. Figure 3A and the like show an example in which the insulating layer 110 is provided extending in the Y direction.

[0088] The conductive layer 112b12, which functions as the other source or drain electrode of transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2, is provided on the insulating layer 110, as shown in Figure 3A and the like. The conductive layer 112b12 and the insulating layer 110 have substantially the same top surface shape. That is, as shown in Figures 1B, 1C, and the like, the side surface of the conductive layer 112b12 is aligned with the side surface of the insulating layer 110.

[0089] The semiconductor layer 108_1, which functions as a semiconductor layer having channel formation regions for transistors 10A1_1 and 10A1_2 respectively, is provided on the conductive layer 112a1_1 and conductive layer 112a1_2, spanning the island-shaped insulating layer 110 and conductive layer 112b12, as shown in Figure 2B and the like. The semiconductor layer 108_1 has regions that are in contact with the upper surface of conductive layer 112a1_1, the upper surface of conductive layer 112a1_2, the side surface of insulating layer 110, the side surface of conductive layer 112b12, and the upper surface of conductive layer 112b12, respectively.

[0090] The above description relating to transistors 10A1_1 and 10A1_2 can also be applied to semiconductor layer 108_2, which functions as a semiconductor layer having channel formation regions for transistors 10A2_1 and 10A2_2, by replacing conductive layer 112a1_1, conductive layer 112a1_2, and semiconductor layer 108_1 with conductive layer 112a2_1, conductive layer 112a2_2, and semiconductor layer 108_2, respectively.

[0091] The insulating layer 106, which functions as the gate insulating layer for transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2, is provided covering semiconductor layers 108_1 and 108_2, as shown in Figures 1B and 1C. The insulating layer 106 has regions that are in contact with the top and side surfaces of semiconductor layer 108_1, semiconductor layer 108_2, conductive layer 112a1_1, conductive layer 112a1_2, conductive layer 112a2_1, conductive layer 112a2_2, conductive layer 112b12, the side surfaces of insulating layer 110, and the top surface of insulating layer 109.

[0092] The conductive layer 104_1, which functions as the gate electrode of transistor 10A1_1 and transistor 10A1_2 respectively, is provided in contact with the insulating layer 106 such that it has a region that overlaps with the semiconductor layer 108_1, as shown in Figure 2A and the like. Similarly, the conductive layer 104_2, which functions as the gate electrode of transistor 10A2_1 and transistor 10A2_2 respectively, is also provided in contact with the insulating layer 106 such that it has a region that overlaps with the semiconductor layer 108_2. Figure 2A and the like show an example in which the conductive layer 104_1 and conductive layer 104_2 are provided so that they extend in the X direction.

[0093] The conductive layer 104_1 has regions facing two sides of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108_1. This allows the regions of the semiconductor layer 108_1 facing these two sides to function as channel formation regions for transistors 10A1_1 and 10A1_2, respectively.

[0094] Similarly, the conductive layer 104_2 has regions facing two sides of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108_2. This allows the regions of the semiconductor layer 108_2 facing these two sides to function as channel formation regions for transistors 10A2_1 and 10A2_2, respectively.

[0095] It is preferable that conductive layer 104_1 and conductive layer 104_2 cover the entire semiconductor layer 108_1 and semiconductor layer 108_2, respectively. As shown in Figure 1A, it is preferable that conductive layer 104_1 and conductive layer 104_2 encompass semiconductor layer 108_1 and semiconductor layer 108_2, respectively, in a plan view. By covering semiconductor layer 108_1 with conductive layer 104_1, it is possible to suppress damage to semiconductor layer 108_1 when layers are formed on transistor 10A1_1 and transistor 10A1_2.

[0096] Similarly, by covering the semiconductor layer 108_2 with the conductive layer 104_2, damage to the semiconductor layer 108_2 can be suppressed when layers are formed on transistors 10A2_1 and 10A2_2.

[0097] This makes it possible to realize transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 that exhibit good electrical characteristics and are highly reliable. Furthermore, semiconductor layers 108_1 and 108_2 can also be configured to have regions that are not covered by conductive layers 104_1 and 104_2, respectively.

[0098] As shown in Figure 1B and the like, in transistor 10A1_1, a step is formed by a region on the conductive layer 112a1_1 where the insulating layer 110 and the conductive layer 112b12 are provided, and a region on the conductive layer 112a1_1 where the insulating layer 110 and the conductive layer 112b12 are not provided, and a semiconductor layer 108_1, an insulating layer 106, and a conductive layer 104_1 can be provided along this step.

[0099] Similarly, in transistor 10A1_2, a step is formed by a region on the conductive layer 112a1_2 where the insulating layer 110 and the conductive layer 112b12 are provided, and a region on the conductive layer 112a1_2 where the insulating layer 110 and the conductive layer 112b12 are not provided, and a semiconductor layer 108_1, an insulating layer 106, and a conductive layer 104_1 can be provided along this step.

[0100] Furthermore, as shown in Figure 1C and the like, in the transistor 10A2_1, a step is formed by a region on the conductive layer 112a2_1 where the insulating layer 110 and the conductive layer 112b12 are provided, and a region on the conductive layer 112a2_1 where the insulating layer 110 and the conductive layer 112b12 are not provided, and a semiconductor layer 108_2, an insulating layer 106, and a conductive layer 104_2 can be provided along this step.

[0101] Similarly, in transistor 10A2_2, a step is formed by a region on the conductive layer 112a2_2 where the insulating layer 110 and the conductive layer 112b12 are provided, and a region on the conductive layer 112a2_2 where the insulating layer 110 and the conductive layer 112b12 are not provided, and a semiconductor layer 108_2, an insulating layer 106, and a conductive layer 104_2 can be provided along this step.

[0102] In each of the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2, the source electrode and drain electrode are positioned at different heights relative to the surface of the substrate 102, and the drain current flows perpendicular to, or approximately perpendicular to, the surface of the substrate 102. In each of the aforementioned transistors, it can also be said that the drain current flows in the vertical direction. Therefore, a transistor according to one aspect of the present invention can be called a vertical channel transistor, a vertical transistor, or a VFET (Vertical Field Effect Transistor).

[0103] The four transistors (transistor 10A1_1, transistor 10A1_2, transistor 10A2_1, and transistor 10A2_2) in the semiconductor device 100A have channel lengths that can be controlled by the thickness of the insulating layer 110 provided between their respective source and drain electrodes. Therefore, transistors with channel lengths shorter than the minimum exposure dimension of the exposure apparatus used to manufacture the transistors can be manufactured with high precision. Furthermore, variations in the electrical characteristics between each transistor can be reduced. As a result, the operation of the semiconductor device 100A becomes more stable and reliable. In addition, reducing the variations in the electrical characteristics between each transistor increases the degree of freedom in circuit design, and the operating voltage of the semiconductor device 100A can be lowered. As a result, the power consumption of the semiconductor device 100A can be reduced.

[0104] A semiconductor device 100A according to one aspect of the present invention has at least four transistors (transistor 10A1_1, transistor 10A1_2, transistor 10A2_1, and transistor 10A2_2). However, as described above, vertical transistors can be used for each transistor, and some components can be shared. Therefore, for example, compared to the case where four planar transistors are provided adjacent to each other on the same plane, the area occupied by the semiconductor device on the substrate can be significantly reduced. In addition, vertical transistors can have extremely short channel lengths, making it easier to increase the on-current compared to planar transistors. Therefore, a semiconductor device 100A according to one aspect of the present invention can be suitably applied to circuits that perform high-speed operation. For example, by applying a semiconductor device 100A according to one aspect of the present invention to the driving circuit of a display device, a display device that achieves both high-speed operation and a narrow bezel can be realized.

[0105] The semiconductor materials used in semiconductor layer 108_1 and semiconductor layer 108_2 are not particularly limited. For example, semiconductors made of elemental materials or compound semiconductors can be used. Examples of semiconductors made of elemental materials include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). It is also possible to have these semiconductor materials contain impurities that act as dopants.

[0106] The crystallinity of the semiconductor material used in semiconductor layer 108_1 and semiconductor layer 108_2 is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0107] For example, silicon can be used for each of the semiconductor layers 108_1 and 108_2. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). Transistors using amorphous silicon for the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon for the channel formation region have high field-effect mobility and can operate at high speed. Furthermore, transistors using microcrystalline silicon for the channel formation region have higher field-effect mobility than transistors using amorphous silicon and can operate at high speed.

[0108] It is preferable that semiconductor layer 108_1 and semiconductor layer 108_2 each have a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties. Transistors using oxide semiconductors (hereinafter referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have a remarkably low off-current and can retain the charge stored in a capacitor connected in series with the transistor for a long period of time. In addition, by applying OS transistors, the power consumption of semiconductor devices can be reduced. When an oxide semiconductor is used for the semiconductor layer, the semiconductor layer can be called an oxide semiconductor layer or a metal oxide layer.

[0109] As the insulating layer 110, one or both of an inorganic insulating layer and an organic insulating layer can be used. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. Preferably, the insulating layer 110 has one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0110] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0111] The insulating layer 110 has regions that are in contact with the semiconductor layer 108_1 and the semiconductor layer 108_2, respectively. When metal oxides are used for each of the semiconductor layer 108_1 and the semiconductor layer 108_2, it is preferable that at least a portion of the regions of the insulating layer 110 that are in contact with the semiconductor layer 108_1 and the semiconductor layer 108_2 have oxygen in order to improve the interface characteristics between the semiconductor layer 108_1 and the insulating layer 110, respectively. Specifically, it is preferable that the portion of the insulating layer 110 that is in contact with the channel formation region of the semiconductor layer 108_1 and the portion of the insulating layer 110 that is in contact with the channel formation region of the semiconductor layer 108_2 have oxygen. One or more oxides and oxiditrides can be suitably used in the portion of the insulating layer 110 that is in contact with the channel formation region of the semiconductor layer 108_1 and the portion of the insulating layer 110 that is in contact with the channel formation region of the semiconductor layer 108_2, respectively.

[0112] When metal oxides are used for semiconductor layer 108_1 and semiconductor layer 108_2, it is preferable that at least a portion of the region of the insulating layer 110 that is in contact with semiconductor layer 108_1 and semiconductor layer 108_2 releases oxygen when heat is applied. This supplies oxygen from the insulating layer 110 to semiconductor layer 108_1 and semiconductor layer 108_2, thereby reducing oxygen deficiencies (V) in semiconductor layer 108_1 and semiconductor layer 108_2. Ｏ : Oxygen vacancy), and a defect in which hydrogen is present in the oxygen vacancy (hereinafter referred to as V Ｏ This can reduce the amount of H (which is denoted as H).

[0113] The insulating layer 109 is provided between the transistors 10A1_1, 10A1_2, 10A2_1, 10A2_2, and the insulating layer 110 and the substrate 102. The insulating layer 109 has regions that are in contact with the conductive layers 112a1_1, 112a1_2, 112a2_1, 112a2_2, and the insulating layer 110. The insulating layer 109 can be made from the same materials as those used for the insulating layer 110.

[0114] The insulating layer 109 preferably has barrier properties. It is preferable to use a material for the insulating layer 109 that does not easily allow impurities (e.g., water and hydrogen) contained in the substrate 102 to diffuse. This makes it possible to suppress the diffusion of impurities from the substrate 102 to each of the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2.

[0115] The insulating layer 109, which functions as a barrier film, can be made from, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, an aluminum nitride, an aluminum nitride, an aluminum nitride, and an oxide silicon nitride. Specifically, the insulating layer 109 can preferably be made from, for example, one or more aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0116] The insulating layer 109 contains impurities (e.g., water and hydrogen) that lower the electrical resistance of the semiconductor layers 108_1 and 108_2, and it is preferable to use a material that releases these impurities. The impurities released from the insulating layer 109 diffuse into the regions of the conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2 that are in contact with the insulating layer 109. Furthermore, the impurities diffused into the conductive layer 112a1_1 or 112a1_2 diffuse into the region of the semiconductor layer 108_1 that is in contact with the conductive layer 112a1_1 or 112a1_2, thereby containing the impurities and lowering the electrical resistance of that region. Similarly, impurities diffused into the conductive layer 112a2_1 or conductive layer 112a2_2 diffuse into the region of the semiconductor layer 108_2 that is in contact with the conductive layer 112a2_1 or conductive layer 112a2_2, thereby containing impurities and lowering the electrical resistance of that region. In other words, the electrical resistance of either the source region or the drain region of each of the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 can be lowered. Consequently, each can be made into a transistor with a large on-current, and a high-speed semiconductor device 100A can be made.

[0117] When metal oxides are used for semiconductor layer 108_1 and semiconductor layer 108_2, it is more preferable that the impurities released by the insulating layer 109 include hydrogen. The hydrogen contained in the insulating layer 109 diffuses into the semiconductor layer 108_1 via the conductive layer 112a1_1 or conductive layer 112a1_2, so that the region of the semiconductor layer 108_1 in contact with the conductive layer 112a1_1 or conductive layer 112a1_2 contains hydrogen, and the carrier concentration in that region increases. Similarly, the hydrogen contained in the insulating layer 109 diffuses into the semiconductor layer 108_2 via the conductive layer 112a2_1 or conductive layer 112a2_2, so that the region of the semiconductor layer 108_2 in contact with the conductive layer 112a2_1 or conductive layer 112a2_2 contains hydrogen, and the carrier concentration in that region increases. In other words, the electrical resistance of either the source region or the drain region of each of the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 can be reduced. The insulating layer 109 preferably has, for example, silicon and hydrogen. Typically, silicon nitride containing hydrogen can be suitably used for the insulating layer 109.

[0118] It is more preferable to use a material for the insulating layer 109 that releases impurities that lower the electrical resistance of each of the conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2. This makes it possible to lower the electrical resistance of the conductive layers.

[0119] Each of the conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2 can be, for example, a conductive metal oxide (also called an oxide conductor). Examples of oxide conductors (OC) include indium oxide (also called indium oxide), zinc oxide, In-Sn oxide (also called ITO), In-Zn oxide (also called IZO®), In-W oxide (also called IWO), In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called silicon-containing ITO or ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide. In particular, since indium-containing oxide conductors have high conductivity, they can be suitably used in each of the conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2.

[0120] When metal oxides are used for each of the conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2, it is more preferable that the impurities released by the insulating layer 109 include hydrogen. The impurities released from the insulating layer 109 diffuse into the conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2, causing the conductive layers to contain the impurities. This increases the carrier concentration of the conductive layer, thereby lowering its electrical resistance. Furthermore, since the conductive layer can function as wiring, a semiconductor device 100A with low wiring resistance can be realized. The impurities that lower the electrical resistance of the conductive layer can be the same as the impurities that lower the electrical resistance of semiconductor layers 108_1 and 108_2. Alternatively, these impurities can have different configurations. It is more preferable that the conductive layer is permeable to impurities. It is more preferable that the conductive layer is less likely to adsorb impurities.

[0121] The thickness of the insulating layer 109 is preferably, for example, 5 nm to 100 nm, more preferably 10 nm to 100 nm, more preferably 20 nm to 100 nm, and more preferably 20 nm to 50 nm.

[0122] If the thickness of the insulating layer 109 is too high and the amount of impurities released from the insulating layer 109 becomes too large, the amount of impurities that diffuse into the semiconductor layer 108_1 and semiconductor layer 108_2 will increase, resulting in oxygen vacancies (V) generated by these impurities. Ｏ ) and V Ｏ The amount of H is the oxygen deficiency (V) that is repaired by the oxygen supplied from the insulating layer 110b. Ｏ ) and V Ｏ There is a risk that the amount of H will be greater than the amount of other elements. On the other hand, if the thickness of the insulating layer 109 is thin, the amount of impurities diffusing into each of the conductive layers 112a1_1, 112a1_2, 112a2_1, 112a2_2, semiconductor layer 108_1, and semiconductor layer 108_2 will decrease, and there is a risk that the electrical resistance of the conductive layer, as well as the electrical resistance of either the source region or the drain region of each of the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2, will increase. By setting the thickness of the insulating layer 109 to the aforementioned range, the oxygen deficiency (V) in the channel formation region of the transistor can be reduced. Ｏ ) and V Ｏ This can suppress the increase in H and lower these electrical resistances. Note that the thickness of the insulating layer 109 is not limited to the range described above.

[0123] Furthermore, if the electrical resistance of each of the conductive layers 112a1_1, 112a1_2, 112a2_1, 112a2_2, semiconductor layer 108_1, and semiconductor layer 108_2 is sufficiently low, and there is no risk of impurities contained in the substrate 102 diffusing into semiconductor layers 108_1 and 108_2, the insulating layer 109 may be omitted. This reduces the number of manufacturing steps for the semiconductor device 100A.

[0124] The insulating layer 110 preferably has a laminated structure. In FIGS. 1B and 1C, an example is shown in which the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. For the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c, the materials listed for the insulating layer 110 can be used respectively.

[0125] In each of the transistors 10A1_1 and 10A1_2, the region of the semiconductor layer 108_1 that contacts the insulating layer 110b functions as a channel formation region. Similarly, in each of the transistors 10A2_1 and 10A2_2, the region of the semiconductor layer 108_2 that contacts the insulating layer 110b functions as a channel formation region. As described above, the insulating layer 110b preferably contains oxygen, and preferably uses one or more of the above-mentioned oxides and oxynitrides. Typically, for the insulating layer 110b, one or both of silicon oxide and silicon oxynitride can be preferably used.

[0126] It is more preferable to use a material that releases oxygen when heat is applied to the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 100A, the insulating layer 110b releases oxygen, so that oxygen can be supplied to each of the semiconductor layer 108_1 and the semiconductor layer 108_2. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108_1 and the semiconductor layer 108_2, particularly to the channel formation regions of the semiconductor layer 108_1 and the semiconductor layer 108_2 respectively, the oxygen deficiency (V Ｏ ) in the region is repaired, and the oxygen deficiency (V Ｏ ) can be reduced. Also, the V Ｏ H in the region can be reduced. Therefore, transistors 10A1_1 and 10A1_2, and transistors 10A2_1 and 10A2_2 that exhibit good electrical characteristics and high reliability can be realized.

[0127] For example, oxygen can be supplied to the insulating layer 110b by performing a heat treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by forming a film on the upper surface of the insulating layer 110b in an oxygen-containing atmosphere using a sputtering method. It is preferable to then remove the film. The method for supplying oxygen to the insulating layer 110b will be specifically explained in <Examples of Semiconductor Device Manufacturing Methods>.

[0128] The insulating layer 110b is preferably deposited using sputtering or plasma chemical vapor deposition (PECVD: Plasma Enhanced Chemical Vapor Deposition, also known as plasma CVD). In particular, by using sputtering and depositing the film without using hydrogen-containing gases (e.g., hydrogen gas and ammonia gas) as the deposition gas, a film with an extremely low hydrogen content can be obtained. This suppresses the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2.

[0129] The insulating layer 110a is provided between the insulating layer 110b and the conductive layers 112a1_1, 112a1_2, 112a2_1, 112a2_2, and 109. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b12. It is preferable that the insulating layer 110a and the insulating layer 110c each release small amounts of impurities (e.g., hydrogen and water). Furthermore, it is preferable that the insulating layer 110a and the insulating layer 110c each impose poorly on substances. It can also be said that the insulating layer 110a and the insulating layer 110c function as barrier films. Specifically, it is preferable that the insulating layer 110a and the insulating layer 110c each impose poorly on substances. This makes it possible to suppress the diffusion of impurities contained in the insulating layer 110a and the insulating layer 110c into the channel-forming region. Therefore, transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2, which exhibit good electrical characteristics and are highly reliable, can be realized, respectively.

[0130] As mentioned above, it is preferable to use materials that are impermeable to oxygen for the insulating layer 110a and insulating layer 110c. This suppresses the diffusion of oxygen contained in insulating layer 110b through insulating layer 110a to the conductive layer 112a1_1 side, conductive layer 112a1_2 side, conductive layer 112a2_1 side, and conductive layer 112a2_2 side. Similarly, it suppresses the diffusion of oxygen contained in insulating layer 110b through insulating layer 110c to the conductive layer 112b12 side. This increases the amount of oxygen supplied from insulating layer 110b to the respective channel formation regions of semiconductor layer 108_1 and semiconductor layer 108_2, thereby reducing oxygen deficiencies (V) in the channel formation regions. Ｏ ) and V Ｏ H can be reduced. Therefore, transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 that exhibit good electrical characteristics and are highly reliable can be realized, respectively.

[0131] Furthermore, the oxygen contained in the insulating layer 110b prevents oxidation of the conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2, thereby suppressing an increase in the electrical resistance of each conductive layer. Similarly, the oxygen contained in the insulating layer 110b prevents oxidation of the conductive layer 112b12, thereby suppressing an increase in the electrical resistance of the conductive layer 112b12. Therefore, transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 with large on-currents can be realized.

[0132] The insulating layer 110a and insulating layer 110c can be made from the materials listed above for the barrier film. For example, the insulating layer 110a and insulating layer 110c can preferably be made from one or more of the following materials: aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. The insulating layer 110a and insulating layer 110c can be made from the same material, or different materials can be used for the insulating layer 110a and insulating layer 110c.

[0133] In this specification, "different materials" means materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0134] One or more of the insulating layers 110a, 110b, and 110c can also be arranged in a laminated structure. For example, the insulating layer 110c can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0135] The thickness of the insulating layer 110c is preferably, for example, 3 nm to 500 nm, more preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, more preferably 20 nm to 300 nm, more preferably 50 nm to 300 nm, more preferably 100 nm to 300 nm, and more preferably 100 nm to 200 nm.

[0136] The thickness of the insulating layer 110c is preferably such that it functions as a barrier film against oxygen. The thickness of the insulating layer 110c can be thinner than the thickness of the insulating layer 110a. If the thickness of the insulating layer 110c is thick, the amount of impurities released from the insulating layer 110c will increase, and the amount of impurities diffusing into the channel formation regions of transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 may increase. On the other hand, if the thickness of the insulating layer 110c is thin, the oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112b12 side through the insulating layer 110c, and the amount of oxygen supplied to the channel formation region of the transistor may decrease. By setting the thickness of the insulating layer 110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, and the oxygen deficiency (V) in the channel formation region can be reduced. Ｏ ) and V Ｏ H can be reduced. In addition, oxidation of the conductive layer 112b12 by oxygen contained in the insulating layer 110b can be suppressed, which would increase the electrical resistance of the conductive layer 112b12. Note that the thickness of the insulating layer 110c is not limited to the range described above.

[0137] The thickness of the insulating layer 110a is preferably, for example, 3 nm to 500 nm, more preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, more preferably 20 nm to 300 nm, more preferably 50 nm to 300 nm, more preferably 100 nm to 300 nm, more preferably 100 nm to 250 nm, and more preferably 150 nm to 250 nm.

[0138] If the thickness of the insulating layer 110a is thin, oxygen contained in the insulating layer 110b may diffuse through the insulating layer 110a to the conductive layer 112a1_1 side, conductive layer 112a1_2 side, conductive layer 112a2_1 side, and conductive layer 112a2_2 side, potentially reducing the amount of oxygen supplied to the channel formation regions of transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2. On the other hand, if the thickness of the insulating layer 110a is thick, the amount of impurities released from the insulating layer 110a increases, potentially increasing the amount of impurities that diffuse into the channel formation regions. By setting the thickness of the insulating layer 110a within the aforementioned range, the amount of oxygen supplied to the channel formation regions can be increased, thereby reducing the oxygen deficiency (V) in the channel formation regions. Ｏ ) and V Ｏ H can be reduced. Furthermore, the oxidation of conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2 by oxygen contained in the insulating layer 110b can be suppressed, which would increase the electrical resistance of the conductive layers. Note that the thickness of the insulating layer 110a is not limited to the range described above.

[0139] At least one of the regions of semiconductor layer 108_1 and semiconductor layer 108_2 that are in contact with the insulating layer 110a, and at least one of the regions that are in contact with the insulating layer 110c, can be a region with lower electrical resistance (hereinafter also referred to as a low-resistance region) compared to the channel formation regions of transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2. This region can also be described as a region with a higher carrier concentration or a higher oxygen vacancy density compared to the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) in the insulating layer 110a, the regions of semiconductor layer 108_1 and semiconductor layer 108_2 that are in contact with the insulating layer 110a can contain impurities, making these regions low-resistance regions. Similarly, by using a material that releases impurities in the insulating layer 110c, the regions of semiconductor layer 108_1 and semiconductor layer 108_2 that are in contact with the insulating layer 110c can contain impurities, making these regions low-resistance regions. The low-resistance region can function as a buffer region to mitigate the drain electric field. Furthermore, these low-resistance regions can also function as the source or drain region of each transistor.

[0140] Furthermore, impurities released from the insulating layer 110a may diffuse into the channel formation region via the insulating layer 110b, or via either the source region or the drain region of the semiconductor layer 108_1 and the semiconductor layer 108_2. Similarly, impurities released from the insulating layer 110c may diffuse into the channel formation region via the insulating layer 110b, or via the other of the source region or the drain region of the semiconductor layer 108_1 and the semiconductor layer 108_2. However, at least the regions of the semiconductor layer 108_1 and the semiconductor layer 108_2 that are in contact with the insulating layer 110b are supplied with oxygen from the insulating layer 110b, thus preventing oxygen deficiencies (V) in the channel formation region. Ｏ ) and V ＯH can be reduced. This suppresses the shift of the threshold voltage to the normally-on side, making it possible to realize transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 that achieve both a small cutoff current (drain current when the gate voltage is 0V) and a large on current. Therefore, a semiconductor device 100A that achieves both low power consumption and high performance can be realized.

[0141] However, if the amount of impurities released from insulating layer 110a and insulating layer 110c becomes too large, the amount of impurities contained in semiconductor layer 108_1 and semiconductor layer 108_2 will increase. As a result, oxygen vacancies (V) will be generated in semiconductor layer 108_1 and semiconductor layer 108_2. Ｏ ) and V Ｏ The amount of H is the oxygen deficiency (V) that is repaired by the oxygen supplied from the insulating layer 110b. Ｏ ) and V Ｏ There is a risk that the amount of H may exceed the amount of H. Even when materials that release impurities are used for the insulating layer 110a and insulating layer 110c, it is more preferable that the amount of released impurities be small.

[0142] The insulating layer 110a has regions that are in contact with the upper surface of the insulating layer 109, the upper and side surfaces of the conductive layer 112a1_1, the upper and side surfaces of the conductive layer 112a1_2, the upper and side surfaces of the conductive layer 112a2_1, and the upper and side surfaces of the conductive layer 112a2_2, respectively. This suppresses the diffusion of impurities contained in the insulating layer 109, conductive layer 112a1_1, conductive layer 112a1_2, conductive layer 112a2_1, and conductive layer 112a2_2 into the respective channel-forming regions of the semiconductor layer 108_1 and semiconductor layer 108_2 via the insulating layer 110b.

[0143] The insulating layer 109 preferably has a region with a higher hydrogen content than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109.

[0144] Furthermore, for analyzing the hydrogen content of the insulating layer 109, etc., secondary ion mass spectrometry (SIMS) can be used, for example.

[0145] Furthermore, impurities released from the insulating layer 109 may diffuse into the respective channel-forming regions of semiconductor layer 108_1 and semiconductor layer 108_2 via conductive layer 112a1_1, conductive layer 112a1_2, conductive layer 112a2_1, conductive layer 112a2_2, one of the source or drain regions of semiconductor layer 108_1, and one of the source or drain regions of semiconductor layer 108_2. However, at least the regions of semiconductor layer 108_1 and semiconductor layer 108_2 that are in contact with the insulating layer 110b are supplied with oxygen from the insulating layer 110b, thus reducing oxygen deficiencies in the channel-forming regions (V Ｏ ) and V Ｏ H can be reduced. This suppresses the shift of the threshold voltage to the normally-on side, making it possible to realize transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 that achieve both a small cutoff current and a large on current. Therefore, a semiconductor device 100A that achieves both low power consumption and high performance can be realized.

[0146] The amount of hydrogen released can be adjusted by differentiating the film formation conditions for the insulating layer 109 and the insulating layer 110a. Specifically, one or more of the following can be made different for the insulating layer 109 and the insulating layer 110a: film formation power (film formation power density), film formation pressure, type of film formation gas, film formation gas flow rate ratio, film formation temperature, and the distance between the substrate and the electrode. For example, by making the film formation power density of the insulating layer 109 lower than that of the insulating layer 110a, the hydrogen content in the insulating layer 109 can be made higher than that in the insulating layer 110a. This increases the amount of hydrogen released from the insulating layer 109 due to the heat applied to it.

[0147] The film-forming gas used to form the insulating layer 109 preferably has a higher hydrogen content than the film-forming gas used to form the insulating layer 110a. Specifically, when forming a silicon nitride film or a silicon nitride oxide film on the insulating layer 109 and the insulating layer 110a using the PECVD method, the ratio of the flow rate of ammonia gas to the total film-forming gas used to form the insulating layer 109 (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the film-forming gas used to form the insulating layer 110a. By forming the insulating layer 109 under conditions of a high ammonia flow rate ratio, the hydrogen content in the insulating layer 109 can be increased. In addition, the amount of hydrogen released from the insulating layer 109 due to the heat applied to it can be increased.

[0148] It is more preferable that the film density of the insulating layer 110a is higher than that of the insulating layer 109. This suppresses the diffusion of hydrogen contained in the insulating layer 109 into the respective channel-forming regions of the semiconductor layer 108_1 and semiconductor layer 108_2 via the insulating layers 110a and 110b. For evaluation of film density, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectivity (XRR) can be used. Differences in film density can sometimes be evaluated using a transmission electron microscope (TEM) image of the cross-section. In TEM observation, a high film density results in a darker (darker) transmitted electron (TE) image, while a low film density results in a fainter (brighter) transmitted electron (TE) image. Therefore, in the transmitted electron (TE) image, the insulating layer 110a may appear darker (darker) than the insulating layer 109. Even when the same material is applied to the insulating layer 109 and the insulating layer 110a, the difference in film density may allow the boundary between them to be observed as a difference in contrast in the cross-sectional TEM image.

[0149] Although the insulating layer 110 is shown here as a three-layer laminated structure, the present invention is not limited to this. Preferably, the insulating layer 110 has at least an insulating layer 110b. It is also possible to have a configuration that does not have one or both of the insulating layers 110a and 110c. Furthermore, it is also possible to have a configuration in which the insulating layer 110 has a laminated structure of four or more layers.

[0150] [Semiconductor layer 108_1, semiconductor layer 108_2] The metal oxides that can be used in semiconductor layer 108_1 and semiconductor layer 108_2 will be described in detail. Examples of metal oxides include indium oxide. Examples of metal oxides include gallium oxide and zinc oxide. It is preferable that the metal oxide contains at least indium. It is also preferable that the metal oxide contains one or both of indium and zinc. Furthermore, it is preferable that the metal oxide has one or more elements selected from indium, element M, and zinc. Element M is a metal element or metalloid with a high bond energy with oxygen, for example, a metal element or metalloid with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferable because they have high bonding energy with oxygen and similar ionic radii to indium or zinc. Furthermore, tin is more preferable because its tetravalent state enhances carrier mobility. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the term "metallic elements" as used here may include metalloid elements.

[0151] For example, indium oxide can be used for each of the semiconductor layers 108_1 and 108_2. Furthermore, for each of the semiconductor layers 108_1 and 108_2, for example, In-Zn oxide, In-Sn-Si oxide, In-Ti oxide, In-Ga oxide, In-W oxide, In-Ga-Al oxide, In-Ga-Sn oxide (also known as IGTO), Ga-Zn oxide (also known as GZO), Al-Zn oxide (also known as AZO), In-Al-Zn oxide (also known as IAZO), In-Sn-Zn oxide (also known as ITZO®), In-Ti-Zn oxide, In-Ga-Zn oxide (also known as IGZO), In-Ga-Sn-Zn oxide (also known as IGZTO), In-Ga-Al-Zn oxide (also known as IGAZO, IGZAO, or IAGZO) can be used. Alternatively, In-Sn-Si oxide, Ga-Sn oxide, Al-Sn oxide, etc., can be used.

[0152] Furthermore, the metal oxide can be composed of one or more metal elements with high periodic numbers in the periodic table, either in place of indium or in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including metal elements with high periodic numbers, the field-effect mobility of the transistor can be increased. Examples of metal elements with high periodic numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0153] Metal oxides can also be composed of one or more nonmetallic elements. The presence of nonmetallic elements in a metal oxide can increase carrier concentration or reduce the band gap, potentially improving the field-effect mobility of a transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0154] By increasing the ratio of indium atoms to the sum of all metal element atoms in the metal oxide, the field-effect mobility of the transistor can be increased. Furthermore, a transistor with a high on-current can be realized.

[0155] In this specification, the ratio of the number of indium atoms to the sum of the total number of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. If element M contains multiple elements, the sum of the ratios of the number of atoms of element M to the sum of the total number of atoms of all contained metal elements may be referred to as the element M content.

[0156] By increasing the zinc content in a metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities within the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and its reliability can be improved.

[0157] By increasing the content of element M in the metal oxide, a metal oxide with a large band gap can be obtained. Furthermore, oxygen vacancies (V) can be added to the metal oxide. Ｏ The formation of oxygen deficiency (V) is suppressed, Ｏ This suppresses carrier generation caused by (), preventing the transistor's threshold voltage from shifting to the normally-on side. As a result, the cutoff current can be reduced, allowing for a normally-off transistor. It also allows for a transistor with a small off-current. Furthermore, fluctuations in the transistor's electrical characteristics are suppressed, improving reliability.

[0158] The electrical characteristics and reliability of a transistor differ depending on the composition of the metal oxide applied to semiconductor layer 108_1 and semiconductor layer 108_2, respectively. Therefore, by varying the composition of the metal oxide according to the required electrical characteristics and reliability of the transistor, it is possible to create a semiconductor device that achieves both excellent electrical characteristics and high reliability.

[0159] When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In: Compositions such as M:Zn=5:1:9, In:M:Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions near these. In this specification, "nearby composition" includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0160] The atomic ratio of In in an In-M-Zn oxide can be less than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these. By increasing the proportion of element M atoms in the metal oxide, oxygen deficiency (V) can be reduced. Ｏ This can suppress the generation of ()

[0161] Furthermore, if element M comprises multiple elements, the sum of their atomic ratios can be used as the atomic ratio of element M.

[0162] By using materials with a high indium content for semiconductor layer 108_1 and semiconductor layer 108_2, the on-current or field-effect mobility of the transistor can be increased. Furthermore, the presence of element M allows for oxygen deficiency (V Ｏ The generation of ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, more preferably 0.1% to 10%, more preferably 0.1% to 8%, more preferably 0.1% to 6%, and more preferably 0.1% to 4%. This makes it possible to make a transistor with good electrical properties. For example, it is preferable to use metal oxides of In:M:Zn = 40:1:10 and nearby elements. Element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides of In:Sn:Zn = 40:1:10 and nearby elements can be suitably used. Alternatively, metal oxides of In:Al:Zn = 40:1:10 and nearby elements can be suitably used.

[0163] A metal oxide that does not contain element M can be applied to each of the semiconductor layers 108_1 and 108_2. When the metal oxide is an In-Zn oxide, examples of atomic ratios of the metal elements include In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions near these values. Furthermore, it is more preferable that the atomic ratio of In is greater than or equal to that of Zn. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0164] For the analysis of the composition of semiconductor layer 108_1 and semiconductor layer 108_2, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), or Electron Spectrometry for Chemical Analysis (ESCA), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled radio frequency plasma emission spectroscopy (ICP-AES) can be used. Plasma-Atomic Emission Spectrometry can be used. Alternatively, a combination of these methods can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and then identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by the analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or the content of element M may not be detected.

[0165] For depositing metal oxide films, sputtering or atomic layer deposition (ALD) can be suitably used. However, when depositing metal oxide films by sputtering, the composition of the deposited metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the deposited metal oxide film may decrease to about 50% of the content in the sputtering target.

[0166] It is preferable to use a crystalline metal oxide for semiconductor layer 108_1 and semiconductor layer 108_2, respectively. Examples of crystalline metal oxide structures include CAAC (C-Axis Aligned Crystal) structure, polycrystalline structure, microcrystalline structure, and nanocrystalline (nc: nano-crystalline) structure. By using a crystalline metal oxide, the defect level density in semiconductor layer 108_1 and semiconductor layer 108_2 can be reduced, thereby realizing a highly reliable semiconductor device.

[0167] It is preferable to use CAAC-OS or nc-OS for semiconductor layer 108_1 and semiconductor layer 108_2, respectively.

[0168] CAAC-OS has multiple layered crystals. The c-axis of the crystals is oriented in the direction normal to the surface to be formed. It is preferable that semiconductor layer 108_1 and semiconductor layer 108_2 each have layered crystals that are parallel or approximately parallel to the surface to be formed. For example, it is preferable that semiconductor layer 108_1 and semiconductor layer 108_2 each have layered crystals that are parallel or approximately parallel to the upper surface of the conductive layer 112b12 in the region in contact with the upper surface of the conductive layer 112b12, and layered crystals that are parallel or approximately parallel to the side surface in the region in contact with the side surface of the conductive layer 112b12. In particular, it is preferable that semiconductor layer 108_1 and semiconductor layer 108_2 each have layered crystals that are parallel or approximately parallel to the side surface, which is the surface to be formed, in the region in contact with the side surface of the insulating layer 110. With this configuration, the layered crystals of semiconductor layer 108_1 and semiconductor layer 108_2 are formed parallel or approximately parallel to each other in the channel length direction of the transistor, making it possible to create a transistor with a large on-current.

[0169] By using a highly crystalline metal oxide in the channel formation region, the defect level density in the channel formation region can be reduced. On the other hand, by using a less crystalline metal oxide, it is possible to realize a transistor that can carry a large current.

[0170] The higher the substrate temperature during metal oxide film deposition, the more crystalline the metal oxide film can be formed. The substrate temperature during deposition can be adjusted, for example, by the temperature of the stage on which the substrate is placed during deposition. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for film formation, or the higher the oxygen partial pressure in the processing chamber, the more crystalline the metal oxide film can be formed.

[0171] The crystallinity of semiconductor layer 108_1 and semiconductor layer 108_2 can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods can be used for the analysis.

[0172] When metal oxides are used for semiconductor layer 108_1 and semiconductor layer 108_2, the channel formation region V Ｏ It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. In this way, V Ｏ To obtain a metal oxide with sufficiently reduced H content, impurities such as water and hydrogen must be removed from the metal oxide (sometimes referred to as dehydration and dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V). Ｏ It is important to repair ). Ｏ By using metal oxides with sufficiently reduced defects such as H in the channel formation region of a transistor, stable electrical characteristics can be provided. Furthermore, by supplying oxygen to the metal oxide, oxygen deficiencies (V) can be reduced. Ｏ The process of repairing this is sometimes referred to as oxygenation treatment.

[0173] When metal oxides are used for semiconductor layer 108_1 and semiconductor layer 108_2, the carrier concentration in the channel formation region is 1 × 10⁻⁶. １８ cm −３ The following is preferable: 1 × 10 １７ cm −３ It is more preferable that it be less than 1 × 10 １６ cm −３ It is even more preferable that it be less than 1 × 10 １３ cm −３ It is even more preferable that it be less than 1 × 10 １２ cm −３ It is even more preferable that it be less than 1. There is no limit to the lower limit of the carrier concentration in the channel-forming region, but for example, 1 × 10⁻⁶ −９ cm −３ It can be done this way.

[0174] OS transistors exhibit small fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, protons, and neutrons).

[0175] The semiconductor layer 108_1 and semiconductor layer 108_2 can each be configured to have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystalline structure. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be realized.

[0176] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as a channel formation region in transistors is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe２ ) are some examples.

[0177] The semiconductor layer 108_1 and the semiconductor layer 108_2 can each have a laminated structure having two or more metal oxide layers. The two or more metal oxide layers in each of the semiconductor layer 108_1 and the semiconductor layer 108_2 can have the same or substantially the same composition. By having a laminated structure of metal oxide layers with the same composition, for example, they can be formed using the same sputtering target, thus reducing manufacturing costs. When the two or more metal oxide layers in each of the semiconductor layer 108_1 and the semiconductor layer 108_2 have the same or substantially the same composition, it may not be possible to clearly identify the boundaries (interfaces) of these metal oxide layers.

[0178] The channel length and channel width of the transistors (transistor 10A1_1, transistor 10A1_2, transistor 10A2_1, and transistor 10A2_2) in the semiconductor device 100A will be explained using Figures 1A and 1B. In the following explanation, the channel length and channel width will be explained using transistor 10A1_2 as the subject, but the same explanation can be applied to other transistors by appropriately substituting the components of transistor 10A1_2.

[0179] In Figure 1B, the channel length L10A1_2 of transistor 10A1_2 is indicated by a dashed double arrow. The channel length L10A1_2 of transistor 10A1_2 corresponds to the length of the region in contact between the semiconductor layer 108_1 and the side surface of the insulating layer 110b in a cross-sectional view. In other words, the channel length L10A1_2 is determined by the thickness of the insulating layer 110b and the angle θ110b between the side surface of the insulating layer 110b (in this case, the side surface on the A2 side) and the surface of the insulating layer 110b to be formed (in this case, the upper surface of the insulating layer 110a). Therefore, the channel length L10A1_2 can be set to a value smaller than the minimum exposure dimension of the exposure apparatus, making it possible to realize transistors of a very small size. Specifically, it is possible to realize transistors with extremely short channel lengths, which were difficult to achieve with conventional exposure apparatuses for mass production of flat panel displays (for example, with a minimum dimension of about 2 μm or 1.5 μm). Furthermore, it is possible to realize transistors with channel lengths of less than 10 nm without using the extremely expensive exposure equipment used in state-of-the-art LSI technology.

[0180] The channel length L10A1_2 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L10A1_2 can also be 100 nm or more and 1 μm or less.

[0181] By shortening the channel length L10A1_2, the on-current of transistor 10A1_2 can be increased. Using transistor 10A1_2, a circuit capable of high-speed operation can be fabricated. Furthermore, the circuit's occupied area can be reduced. Therefore, a compact semiconductor device can be made. For example, when a semiconductor device according to one aspect of the present invention is applied to a large display device or a high-resolution display device, even when the number of wires increases, the signal delay in each wire can be reduced, and display unevenness can be suppressed. In addition, since the circuit's occupied area can be reduced, the bezel of the display device can be narrowed.

[0182] The channel length L10A1_2 can be controlled by adjusting the thickness and angle θ110b of the insulating layer 110b.

[0183] The thickness of the insulating layer 110b can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less.

[0184] The side surface of the insulating layer 110 is preferably tapered (a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface or the surface to be formed). The angle θ110b is preferably less than 90 degrees. By reducing the angle θ110b, the coverage of the layer formed on the insulating layer 110 (for example, the semiconductor layer 108_1) can be improved. Also, the smaller the angle θ110b, the longer the channel length L10A1_2 can be made, and the larger the angle θ110b, the shorter the channel length L10A1_2 can be made.

[0185] Although Figure 1B and other figures show the angle θ110b as less than 90 degrees, the present invention is not limited to this. The angle θ110b can also be 90 degrees or approximately 90 degrees. This allows the channel length L10A1_2 of the transistor 10A1_2 to be shortened and the occupied area of ​​the semiconductor device 100A to be reduced.

[0186] The angle θ110b can be, for example, 30 degrees or more and 90 degrees or less, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 75 degrees or less, 50 degrees or more and 70 degrees or less, 55 degrees or more and 70 degrees or less, 60 degrees or more and 70 degrees or less, or 65 degrees or more and 70 degrees or less.

[0187] Figure 1B and others show a configuration in which the side shape of the insulating layer 110 is straight in a cross-sectional view, but the present invention is not limited to this. In a cross-sectional view, the side shape of the insulating layer 110 can be curved. Alternatively, the insulating layer 110 can include both a region where the side shape is straight and a region where it is curved.

[0188] The upper surface shape of the conductive layer 112b12 preferably matches or substantially matches the upper surface shape of the insulating layer 110. Figure 3A, etc., shows a configuration in which the upper surface shape of the conductive layer 112b12 matches the upper surface shape of the insulating layer 110. The conductive layer 112b12 and the insulating layer 110 can be formed using the same mask layer. For example, an insulating film that will become the insulating layer 110 and a conductive film that will become the conductive layer 112b12 on the insulating film are formed, and a mask layer (for example, a resist mask) is formed on the conductive film. Then, by processing the conductive film and the insulating film using the mask layer as a mask, a conductive layer 112b12 and an insulating layer 110 with matching or substantially matching upper surface shapes can be formed. By processing the insulating film that will become the insulating layer 110 and the conductive film that will become the conductive layer 112b12 in the same process, manufacturing costs can be reduced. In Figure 3A, etc., the top surfaces of the conductive layer 112b12 and the insulating layer 110 are shown as rectangles, but the top surfaces of the conductive layer 112b12 and the insulating layer 110 are not particularly limited.

[0189] It is preferable that there is no step between the side surface of the conductive layer 112b12 and the side surface of the insulating layer 110, and that they are flat (i.e., the two surfaces coincide or roughly coincide). This improves the coverage of the layers provided on the insulating layer 110 and the conductive layer 112b12 (for example, the semiconductor layer 108_1). It is also possible to have a configuration in which the side surface of the conductive layer 112b12 and the side surface of the insulating layer 110 are discontinuous. Furthermore, it is also possible to have a configuration in which the upper surface shape of the conductive layer 112b12 does not coincide with the upper surface shape of the insulating layer 110.

[0190] Here, it is preferable that the conductive layer 112b12 does not have a region in contact with the side surface of the insulating layer 110 (in this case, the side surface on the A2 side). If the conductive layer 112b12 is in contact with the side surface of the insulating layer 110, the channel length L10A1_2 of the transistor 10A1_2 may become shorter than the length of the side surface of the insulating layer 110b, making it difficult to control the channel length L10A1_2. Therefore, it is preferable that the upper surface shape of the conductive layer 112b12 and the upper surface shape of the insulating layer 110 are the same or approximately the same. Alternatively, it is preferable that, in a plan view, the insulating layer 110 encompasses the conductive layer 112b12.

[0191] The channel width of transistor 10A1_2 is the length of the region where the channel formation area in semiconductor layer 108_1 and the conductive layer 104_1 overlap in a plan view. In Figure 1A, the channel width W10A1_2 of transistor 10A1_2 is indicated by a double-headed arrow.

[0192] When forming the semiconductor layer 108_1 and the conductive layer 104_1 using lithography, the channel width W10A1_2 is greater than or equal to the minimum exposure dimension of the exposure apparatus. The channel width W10A1_2 can be, for example, 20 nm or more and less than 500 μm, 50 nm or more and 200 μm or less, 100 nm or more and 100 μm or less, 200 nm or more and 50 μm or less, 500 nm or more and 20 μm or less, 1 μm or more and 10 μm or less, or 1 μm or more and 5 μm or less.

[0193] In this explanation, we have used as an example a configuration in which the region of the semiconductor layer 108_1 in contact with the insulating layer 110b functions as a channel formation region, but the present invention is not limited to this. The region of the semiconductor layer 108_1 in contact with the insulating layer 110a may also function as a channel formation region. Similarly, the region of the semiconductor layer 108_1 in contact with the insulating layer 110c may also function as a channel formation region.

[0194] [Conductive layer 112a1_1, conductive layer 112a1_2, conductive layer 112a2_1, conductive layer 112a2_2, conductive layer 112b12, conductive layer 104_1, conductive layer 104_2] Conductive layer 112a1_1, conductive layer 112a1_2, conductive layer 112a2_1, conductive layer 112a2_2, conductive layer 112b12, conductive layer 104_1, and conductive layer 104_2 can each be a single layer or a laminated structure of two or more layers. Materials that can be used for the conductive layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. The conductive layer can preferably be made of a conductive material with low electrical resistivity, containing one or more of copper, silver, gold, and aluminum. Copper or aluminum are particularly preferred due to their excellent mass-productivity.

[0195] Oxide conductors can be used for conductive layers 112a1_1, 112a1_2, 112a2_1, 112a2_2, 112b12, 104_1, and 104_2, respectively. For details on oxide conductors, please refer to the above description.

[0196] Oxygen vacancies (V) in metal oxides with semiconductor properties Ｏ When hydrogen is added to the oxygen vacancy, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has turned into a conductor can be called an oxide conductor.

[0197] The conductive layers 112a1_1, 112a1_2, 112a2_1, 112a2_2, 112b12, 104_1, and 104_2 can each be a laminated structure of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0198] Conductive layers 112a1_1, 112a1_2, 112a2_1, 112a2_2, 112b12, 104_1, and 104_2 can each be coated with a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, processing can be performed by wet etching, thereby reducing manufacturing costs.

[0199] Furthermore, the same material can be used for conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2, conductive layer 112b12, conductive layer 104_1, and conductive layer 104_2. Alternatively, different materials can be used for at least one of them.

[0200] The conductive layers 112a1_1, 112a1_2, and 112b12 each have a region in contact with the semiconductor layer 108_1. Furthermore, the conductive layers 112a2_1, 112a2_2, and 112b12 each have a region in contact with the semiconductor layer 108_2. When an oxide semiconductor is used for the semiconductor layer 108_1, if easily oxidizable metals (e.g., aluminum) are used for the conductive layers 112a1_1 and 112a1_2, or the conductive layer 112b12, an insulating oxide (e.g., aluminum oxide) may form between the conductive layers 112a1_1 and 112a1_2, or the conductive layer 112b12, and the semiconductor layer 108_1, potentially hindering conductivity. Therefore, it is preferable to use conductive materials that are resistant to oxidation, conductive materials that maintain low electrical resistance even when oxidized, or oxide conductors for conductive layers 112a1_1, 112a1_2, and 112b12. The same applies to conductive layers 112a2_1 and 112a2_2, which have regions in contact with semiconductor layer 108_2.

[0201] It is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel for conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2, or conductive layer 112b12, respectively. These are preferred because they are conductive materials that are resistant to oxidation, or materials that maintain low electrical resistance even when oxidized. When conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2, or conductive layer 112b12 have a laminated structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with semiconductor layer 108_1 and semiconductor layer 108_2.

[0202] The conductive layers 112a1_1, 112a1_2, 112a2_1, 112a2_2, and 112b12 can each be made from the aforementioned oxide conductors. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, silicon-containing In-Sn oxide, and gallium-doped zinc oxide can be used. In particular, oxide conductors containing indium have high conductivity and are therefore suitable for use in these conductive layers.

[0203] The conductive layers 112a1_1, 112a1_2, 112a2_1, 112a2_2, and 112b12 can each be made of nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0204] [Insulating layer 106] The insulating layer 106 preferably has one or more inorganic insulating layers. The insulating layer 106 can be made of the same material that can be used for the insulating layer 110.

[0205] The insulating layer 106 has regions that are in contact with each of the semiconductor layers 108_1, 108_2, 112a1_1, 112a1_2, 112a2_1, 112a2_2, 112b12, 104_1, and 104_2. When metal oxides are used for each of the semiconductor layers 108_1 and 108_2, it is preferable that at least the films constituting the insulating layer 106 that are in contact with each of the semiconductor layers 108_1 and 108_2 use either of the aforementioned oxides or oxiditrides. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxiditride, or aluminum oxide can be suitably used for the insulating layer 106.

[0206] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxidized nitrides having aluminum and hafnium, oxides having silicon and hafnium, oxidized nitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0207] Although the insulating layer 106 is shown as a single layer in Figure 1B, etc., the present invention is not limited to this. The insulating layer 106 can be a laminated structure of two or more layers.

[0208] When the insulating layer 106 has a laminated structure, it is preferable to use oxides or oxidized nitrides for the insulating layers on the semiconductor layer 108_1 side and the semiconductor layer 108_2 side. For example, one or more silicon oxide, silicon oxidized nitride, or aluminum oxide can be suitably used. Alternatively, nitrides or nitride oxides can be used. For example, aluminum nitride can be suitably used.

[0209] Preferably, one or more layers constituting the insulating layer 106 function as a barrier film. By providing a barrier film, it is possible to suppress the diffusion of metal components contained in conductive layers 104_1 and 104_2, as well as impurities (e.g., water and hydrogen) contained in the layers formed on transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2, to semiconductor layers 108_1 and 108_2, respectively, through the insulating layer 106. Furthermore, it is possible to suppress the diffusion of oxygen contained in the insulating layer 110b to the conductive layer 104_1 side and the conductive layer 104_2 side, respectively, through the insulating layer 106. As a result, the amount of oxygen supplied from the insulating layer 110b to the respective channel formation regions of semiconductor layers 108_1 and 108_2 increases, reducing oxygen deficiencies (V) in the channel formation regions. Ｏ) and V Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be realized.

[0210] Furthermore, the oxidation of conductive layers 104_1 and 104_2 by oxygen contained in the insulating layer 110b can be suppressed, which would increase the electrical resistance of conductive layers 104_1 and 104_2. As a result, a transistor exhibiting good electrical characteristics and high reliability can be realized. The aforementioned materials can be used as the barrier film. For example, silicon nitride, aluminum oxide, and one or more of the aluminum nitride can be suitably used in one or more of the layers constituting the insulating layer 106.

[0211] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or resin substrates can be used as the substrate 102. In addition, a substrate on which semiconductor elements are provided can be used as the substrate 102. A substrate with an insulating film formed on its surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited and can be circular or rectangular, for example.

[0212] A flexible substrate can be used as the substrate 102, and the semiconductor device 100A, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the semiconductor device 100A, etc. By providing a release layer, the semiconductor device can be partially or completely completed on it, then separated from the substrate 102 and transferred to another substrate. In this case, the semiconductor device 100A, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0213] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, and does not concern itself with elasticity or the ability to restore to its original shape.

[0214] For example, flexible electronic devices can deform in response to external forces. Flexible electronic devices can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Similarly, flexible display devices (also called flexible display devices, flexible display devices, flexible displays, etc.) can deform in response to external forces. Flexible display devices can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Furthermore, flexible substrates (also called flexible substrates, flexible substrates, etc.) can deform in response to external forces. Flexible substrates can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Note that "deforms in response to external forces" above means that it can be deformed by an average adult's hand without requiring excessive force. Note that flexibility can be quantified as the deformation of an object in response to an external force using testing machines capable of stress-strain measurement (tensile testing machines, compression testing machines, etc.).

[0215] Furthermore, in this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may also have parts that do not have flexibility (also called rigid parts).

[0216] Furthermore, in this specification, a highly flexible object is defined as the object that deforms more when two objects are deformed with the same external force. Also, when a first part and a second part of an object are deformed with the same external force, the part that deforms more is considered to be the highly flexible part.

[0217] The following describes a semiconductor device configuration example that differs in some aspects from the previously described configuration example. Note that in the following, explanations of parts that overlap with the previously described configuration example may be omitted. Also, in the drawings shown below, parts having the same function as the previously described configuration example may use the same hatching pattern and may not be labeled with reference numerals.

[0218] <Example of semiconductor device configuration 2> Figures 4A to 4C show an example of the configuration of a semiconductor device 100B, which has a different configuration from the semiconductor device 100A shown in Figures 1A to 1C. Figure 4A is a plan view of the semiconductor device 100B. Figure 4B is a cross-sectional view corresponding to the dashed line A1-A2 shown in Figure 4A, and Figure 4C is a cross-sectional view corresponding to the dashed line B1-B2 shown in Figure 4A.

[0219] The semiconductor device 100B includes transistor 10B1_1, transistor 10B1_2, transistor 10B2_1, transistor 10B2_2, insulating layer 110, and insulating layer 109.

[0220] The transistor 10B1_1 has a conductive layer 104_1, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a12, and a conductive layer 112b1_1. The conductive layer 104_1 functions as a gate electrode. A portion of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a12 functions as either a source electrode or a drain electrode. The conductive layer 112b1_1 functions as either a source electrode or a drain electrode. Of the semiconductor layer 108_1, the region between the source electrode and the drain electrode that overlaps with the gate electrode via the gate insulating layer functions as a channel forming region. Furthermore, of the semiconductor layer 108_1, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region.

[0221] The description relating to transistor 10B1_1 described above can be applied to transistor 10B1_2 by replacing conductive layer 112b1_1 with conductive layer 112b1_2.

[0222] The description relating to transistor 10B1_1 above can be applied to transistor 10B2_1 by replacing the conductive layer 112b1_1, semiconductor layer 108_1, and conductive layer 104_1 with conductive layer 112b2_1, semiconductor layer 108_2, and conductive layer 104_2, respectively.

[0223] The description relating to transistor 10B1_1 above can be applied to transistor 10B2_2 by replacing the conductive layer 112b1_1, semiconductor layer 108_1, and conductive layer 104_1 with conductive layer 112b2_2, semiconductor layer 108_2, and conductive layer 104_2, respectively.

[0224] Transistors 10B1_1 and 10B1_2 share some components, specifically the conductive layer 112a12, the semiconductor layer 108_1, the insulating layer 106, and the conductive layer 104_1, respectively.

[0225] Since transistors 10B1_1 and 10B1_2 share either a source electrode or a drain electrode (conductive layer 112a12), they can be said to be connected in series.

[0226] Furthermore, transistors 10B1_1 and 10B1_2 share each other's semiconductor layer (semiconductor layer 108_1), gate insulating layer (insulating layer 106), and gate electrode (conductive layer 104_1). Therefore, the configuration combining transistors 10B1_1 and 10B1_2 can be considered equivalent to a single transistor whose channel length is the sum of the channel lengths of each transistor.

[0227] In Figures 4A and 4B, the combination of transistors 10B1_1 and 10B1_2 (corresponding to a single transistor with a long channel length) is shown as switch 100B1.

[0228] The same description relating to transistors 10B1_1 and 10B1_2 (description relating to the connection relationship between the two transistors, etc.) can be applied to transistors 10B2_1 and 10B2_2 by replacing semiconductor layer 108_1 and conductive layer 104_1 with semiconductor layer 108_2 and conductive layer 104_2, respectively. In Figures 4A and 4C, the combination of transistor 10B2_1 and transistor 10B2_2 is shown as switch 100B2.

[0229] As shown in Figures 4A to 4C, transistors 10B1_1, 10B1_2, 10B2_1, and 10B2_2 share a conductive layer (conductive layer 112a12) that functions as either the source electrode or the drain electrode of each transistor. The semiconductor device 100B has two switches (switch 100B1 and switch 100B2) arranged in parallel with each other, and these two switches are connected by the conductive layer 112a12. Figure 7B shows a circuit diagram illustrating the configuration of the semiconductor device 100B.

[0230] As shown in Figures 7A and 7B, semiconductor device 100A and semiconductor device 100B have the same circuit configuration. Therefore, the same effects as those of semiconductor device 100A can be obtained with semiconductor device 100B.

[0231] Figure 5A shows a perspective view of the semiconductor device 100B. Note that some insulating layers (insulating layer 110 and insulating layer 106) are made transparent, with only their outlines shown as dashed lines. Figure 5B is a perspective view from Figure 5A, with conductive layer 104_1, conductive layer 104_2, and insulating layer 106 omitted. Figure 6A is a perspective view from Figure 5B, with semiconductor layer 108_1 and semiconductor layer 108_2 omitted. Note that in the perspective view of Figure 6A, the outline of insulating layer 110 is shown as a solid line. Figure 6B is a perspective view from Figure 6A, with conductive layer 112b1_1, conductive layer 112b1_2, conductive layer 112b2_1, conductive layer 112b2_2, and insulating layer 110 omitted.

[0232] The conductive layer (conductive layer 112a12), which functions as either the source electrode or the drain electrode of each of the transistors 10B1_1, 10B1_2, 10B2_1, and 10B2_2, can be configured to extend in the Y direction, for example, as shown in Figure 6B.

[0233] As shown in Figure 6A and the like, the insulating layer 110 is provided in island-like formations on the conductive layer 112a12 and on the insulating layer 109, respectively, so as to have regions that overlap with four different locations on the conductive layer 112a12. The four island-like insulating layers 110 can, for example, each be provided extending in the Y direction.

[0234] The conductive layers 112b1_1, 112b1_2, 112b2_1, and 112b2_2, which function as the other source or drain electrode of transistors 10B1_1, 10B1_2, 10B2_1, and 10B2_2 respectively, are each provided on four island-shaped insulating layers 110, as shown in Figure 6A, etc. The top surfaces of the four island-shaped insulating layers 110 and the conductive layers 112b1_1, 112b1_2, 112b2_1, and 112b2_2 located on top of it are roughly identical. That is, as shown in Figures 4B, 4C, etc., the side surface of conductive layer 112b1_1 is aligned with the side surface of the insulating layer 110 below it. The side surface of conductive layer 112b1_2 is aligned with the side surface of the insulating layer 110 below it. The side surface of conductive layer 112b2_1 is aligned with the side surface of the insulating layer 110 beneath it. The side surface of conductive layer 112b2_2 is aligned with the side surface of the insulating layer 110 beneath it.

[0235] The semiconductor layer 108_1, which functions as a semiconductor layer having channel-forming regions for transistors 10B1_1 and 10B1_2 respectively, is provided to cover the groove between the island-shaped insulating layer 110 and conductive layer 112b1_1, and the island-shaped insulating layer 110 and conductive layer 112b1_2, as shown in Figure 5B, etc. The semiconductor layer 108_1 has regions that are in contact with the upper surface of the conductive layer 112a12, the side surface of the insulating layer 110, the side surface and upper surface of the conductive layer 112b1_1, and the side surface and upper surface of the conductive layer 112b1_2, respectively.

[0236] The above description relating to transistors 10B1_1 and 10B1_2 can also be applied to semiconductor layer 108_2, which functions as a semiconductor layer having channel formation regions for transistors 10B2_1 and 10B2_2, by replacing conductive layer 112b1_1, conductive layer 112b1_2, and semiconductor layer 108_1 with conductive layer 112b2_1, conductive layer 112b2_2, and semiconductor layer 108_2, respectively.

[0237] The insulating layer 106, which functions as the gate insulating layer for transistors 10B1_1, 10B1_2, 10B2_1, and 10B2_2, is provided covering semiconductor layers 108_1 and 108_2, as shown in Figures 4B and 4C. The insulating layer 106 has regions that are in contact with the top and side surfaces of semiconductor layer 108_1, semiconductor layer 108_2, conductive layer 112b1_1, conductive layer 112b1_2, conductive layer 112b2_1, conductive layer 112b2_2, conductive layer 112a12, the side surfaces of insulating layer 110, and the top surface of insulating layer 109.

[0238] The conductive layer 104_1, which functions as the gate electrode of transistor 10B1_1 and transistor 10B1_2 respectively, is provided in contact with the insulating layer 106 such that it has a region that overlaps with the semiconductor layer 108_1, as shown in Figure 5A, etc. Similarly, the conductive layer 104_2, which functions as the gate electrode of transistor 10B2_1 and transistor 10B2_2 respectively, is also provided in contact with the insulating layer 106 such that it has a region that overlaps with the semiconductor layer 108_2. Figure 5A, etc., shows an example in which the conductive layer 104_1 and conductive layer 104_2 are provided so that they extend in the X direction.

[0239] The conductive layer 104_1 has regions that face two sides of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108_1. This allows the two regions of the semiconductor layer 108_1 facing the conductive layer 104_1 to function as channel formation regions for transistors 10B1_1 and 10B1_2, respectively.

[0240] Similarly, the conductive layer 104_2 has regions that face two sides of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108_2. This allows the two regions of the semiconductor layer 108_2 facing the conductive layer 104_2 to function as channel formation regions for transistors 10B2_1 and 10B2_2, respectively.

[0241] As shown in Figure 4B and the like, in transistor 10B1_1, a step is formed by a region on the conductive layer 112a12 where the insulating layer 110 and conductive layer 112b1_1 are provided and a region on the conductive layer 112a12 where the insulating layer 110 and conductive layer 112b1_1 are not provided, and a semiconductor layer 108_1, an insulating layer 106, and a conductive layer 104_1 can be provided along this step.

[0242] Similarly, in transistor 10B1_2, a step is formed by a region on the conductive layer 112a12 where the insulating layer 110 and conductive layer 112b1_2 are provided, and a region on the conductive layer 112a12 where the insulating layer 110 and conductive layer 112b1_2 are not provided, and a semiconductor layer 108_1, an insulating layer 106, and a conductive layer 104_1 can be provided along this step.

[0243] Furthermore, as shown in Figure 4C and other figures, in the transistor 10B2_1, a step is formed by a region on the conductive layer 112a12 where the insulating layer 110 and conductive layer 112b2_1 are provided, and a region on the conductive layer 112a12 where the insulating layer 110 and conductive layer 112b2_1 are not provided. Along this step, the semiconductor layer 108_2, insulating layer 106, and conductive layer 104_2 can be provided.

[0244] Similarly, in transistor 10B2_2, a step is formed by a region on the conductive layer 112a12 where the insulating layer 110 and conductive layer 112b2_2 are provided, and a region on the conductive layer 112a12 where the insulating layer 110 and conductive layer 112b2_2 are not provided. Along this step, a semiconductor layer 108_2, an insulating layer 106, and a conductive layer 104_2 can be provided.

[0245] In semiconductor device 100A, the four vertical transistors in the semiconductor device share the electrode (conductive layer 112b12) located on the side furthest from the substrate surface, while semiconductor device 100B differs in that it shares the electrode (conductive layer 112a12) located on the side closer to the substrate surface, either the source electrode or the drain electrode of each of the four vertical transistors in the semiconductor device.

[0246] In other words, the conductive layers connecting the two switches that constitute each semiconductor device are different in semiconductor device 100A and semiconductor device 100B. Thus, in one aspect of the present invention, the conductive layers connecting the two switches of a semiconductor device can be different, as long as the overall circuit configuration of the semiconductor device remains unchanged. For example, the conductive layer can be provided above the insulating layer 110, as in semiconductor device 100A, or below the insulating layer 110, as in semiconductor device 100B. This increases the degree of freedom in manufacturing the semiconductor device.

[0247] For semiconductor device 100B, you can refer to the information provided in semiconductor device 100A for details other than those mentioned above.

[0248] <Example of semiconductor device configuration 3> Figures 8A and 8B show an example of a semiconductor device 100C with a configuration different from that of the semiconductor device 100A shown in Figures 1A to 1C. Figure 8A is a plan view of the semiconductor device 100C. Figure 8B is a cross-sectional view corresponding to the dashed line A1-A2 shown in Figure 8A.

[0249] Figure 9A shows a perspective view of the semiconductor device 100C. Note that some insulating layers (insulating layer 110 and insulating layer 106) are made transparent, with only their outlines shown as dashed lines. Figure 9B is a perspective view from Figure 9A, with conductive layer 104_1, conductive layer 104_2, and insulating layer 106 omitted. Figure 10A is a perspective view from Figure 9B, with semiconductor layer 108_1 and semiconductor layer 108_2 omitted. Note that in the perspective view of Figure 10A, the outline of insulating layer 110 is shown as a solid line. Figure 10B is a perspective view from Figure 10A, with conductive layer 112b12, conductive layer 112b34, and insulating layer 110 omitted.

[0250] The semiconductor device 100C includes transistors 10C1_1, 10C1_2, 10C1_3, 10C1_4, 10C2_1, 10C2_2, 10C2_3, 10C2_4, an insulating layer 110, and an insulating layer 109.

[0251] The semiconductor device 100C differs from the semiconductor device 100A in that it has eight vertical transistors.

[0252] As shown in Figure 10B, the semiconductor device 100C has conductive layers 112a1_1, 112a1_4, 112a2_1, 112a2_4, and 112a23 in different regions on the insulating layer 109.

[0253] As shown in Figure 10A, a first island-shaped insulating layer 110 is provided on conductive layer 112a1_1, conductive layer 112a2_1, conductive layer 112a23, and insulating layer 109, having regions that overlap with conductive layer 112a1_1, conductive layer 112a2_1, and conductive layer 112a23, respectively. Furthermore, a second island-shaped insulating layer 110 is provided on conductive layer 112a1_4, conductive layer 112a2_4, conductive layer 112a23, and insulating layer 109, having regions that overlap with conductive layer 112a1_4, conductive layer 112a2_4, and conductive layer 112a23, respectively.

[0254] As shown in Figure 10A, a conductive layer 112b12 is provided on the first island-shaped insulating layer 110. The top surfaces of the first island-shaped insulating layer 110 and the conductive layer 112b12 are substantially identical. Furthermore, a conductive layer 112b34 is provided on the second island-shaped insulating layer 110. The top surfaces of the second island-shaped insulating layer 110 and the conductive layer 112b34 are substantially identical.

[0255] As shown in Figure 9B, semiconductor layers 108_1 and 108_2 are provided so as to straddle the two island-shaped insulating layers 110. Semiconductor layer 108_1 has regions that are in contact with the upper surface of conductive layer 112a1_1, the upper surface of conductive layer 112a23, the upper surface of conductive layer 112a1_4, the sides of the two island-shaped insulating layers 110, the upper and sides of conductive layer 112b12, and the upper and sides of conductive layer 112b34. Semiconductor layer 108_2 has regions that are in contact with the upper surface of conductive layer 112a2_1, the upper surface of conductive layer 112a23, the upper surface of conductive layer 112a2_4, the sides of the two island-shaped insulating layers 110, the upper and sides of conductive layer 112b12, and the upper and sides of conductive layer 112b34.

[0256] As shown in Figure 9A, an insulating layer 106 is provided on semiconductor layer 108_1 and semiconductor layer 108_2. A conductive layer 104_1 is provided on the insulating layer 106 such that it overlaps with semiconductor layer 108_1. A conductive layer 104_2 is also provided such that it overlaps with semiconductor layer 108_2.

[0257] The conductive layer 104_1 has regions that face the four sides of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108_1. This allows the regions of the semiconductor layer 108_1 facing these four sides to function as channel formation regions for transistors 10C1_1, 10C1_2, 10C1_3, and 10C1_4, respectively.

[0258] Similarly, the conductive layer 104_2 has regions facing the four sides of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108_2. This allows the regions of the semiconductor layer 108_2 facing these four sides to function as channel formation regions for transistors 10C2_1, 10C2_2, 10C2_3, and 10C2_4, respectively.

[0259] Figure 14A shows a circuit diagram illustrating the configuration of the semiconductor device 100C.

[0260] As shown in Figure 14A, in semiconductor device 100C, transistors 10C1_1, 10C1_2, 10C1_3, and 10C1_4 are connected in series. Specifically, transistors 10C1_1 and 10C1_2 are connected by a conductive layer 112b12, transistors 10C1_2 and 10C1_3 are connected by a conductive layer 112a23, and transistors 10C1_3 and 10C1_4 are connected by a conductive layer 112b34. In addition, transistors 10C2_1, 10C2_2, 10C2_3, and 10C2_4 are connected in series. Specifically, transistors 10C2_1 and 10C2_2 are connected by a conductive layer 112b12, transistors 10C2_2 and 10C2_3 are connected by a conductive layer 112a23, and transistors 10C2_3 and 10C2_4 are connected by a conductive layer 112b34.

[0261] Furthermore, as shown in Figure 8B, transistors 10C1_1, 10C1_2, 10C1_3, and 10C1_4 share each other's semiconductor layer (semiconductor layer 108_1), gate insulating layer (insulating layer 106), and gate electrode (conductive layer 104_1). Therefore, the configuration combining transistors 10C1_1, 10C1_2, 10C1_3, and 10C1_4 can be considered equivalent to a single transistor whose channel length is the sum of the channel lengths of each transistor.

[0262] Similarly, transistors 10C2_1, 10C2_2, 10C2_3, and 10C2_4 share each other's semiconductor layers (semiconductor layer 108_2), gate insulating layer (insulating layer 106), and gate electrode (conductive layer 104_2). Therefore, a configuration combining transistors 10C2_1, 10C2_2, 10C2_3, and 10C2_4 can be considered equivalent to a single transistor whose channel length is the sum of the channel lengths of each transistor.

[0263] In Figures 8A, 8B, and 14A, the combination of transistors 10C1_1, 10C1_2, 10C1_3, and 10C1_4 is shown as switch 100C1, and the combination of transistors 10C2_1, 10C2_2, 10C2_3, and 10C2_4 is shown as switch 100C2.

[0264] Switches 100C1 and 100C2 each have a configuration in which four transistors are connected in series. Therefore, the overall channel length can be made longer and the voltage withstand capability can be increased compared to switches 100A1 and 100A2, or switches 100B1 and 100B2, which each have a configuration in which two transistors are connected in series.

[0265] As described above, in one aspect of the present invention, vertical transistors can be used in the transistors of the semiconductor device. Therefore, even when increasing the number of transistors connected in series to increase the breakdown voltage, the occupied area of ​​the semiconductor device can be significantly reduced compared to when planar transistors are used.

[0266] As shown in Figures 8A to 10B and Figure 14A, transistors 10C1_1, 10C1_2, 10C2_1, and 10C2_2 share a conductive layer (conductive layer 112b12) that functions as the other of either the source electrode or the drain electrode. Transistors 10C1_2, 10C1_3, 10C2_2, and 10C2_3 share a conductive layer (conductive layer 112a23) that functions as either the source electrode or the drain electrode. Transistors 10C1_3, 10C1_4, 10C2_3, and 10C2_4 share a conductive layer (conductive layer 112b34) that functions as the other of either the source electrode or the drain electrode. The semiconductor device 100C has two switches (switch 100C1 and switch 100C2) arranged in parallel with each other, and these two switches are connected by conductive layers 112b12, 112a23, and 112b34, respectively.

[0267] Because the semiconductor device 100C has the above-described configuration, for example, when switch 100C1 is turned ON, the potential generated at the connection point (first node) between the source electrode and drain electrode of transistors 10C1_1 and 10C1_2 can also be supplied to the connection point (second node) between the source electrode and drain electrode of transistors 10C2_1 and 10C2_2 in switch 100C2 via the conductive layer 112b12. Furthermore, the potential generated at the connection point (third node) between the source electrode and drain electrode of transistors 10C1_2 and 10C1_3 can also be supplied to the connection point (fourth node) between the source electrode and drain electrode of transistors 10C2_2 and 10C2_3 in switch 100C2 via the conductive layer 112a23. Furthermore, the potential generated at the connection point (fifth node) between the source and drain electrodes of transistors 10C1_3 and 10C1_4 can also be applied to the connection point (sixth node) between the source and drain electrodes of transistors 10C2_3 and 10C2_4 in switch 100C2 via the conductive layer 112b34.

[0268] For example, consider the case where switch 100C2 is turned on after switch 100C1 has been turned on. In this case, the second, fourth, and sixth nodes of switch 100C2 are supplied with a certain magnitude of potential beforehand (a potential of the same magnitude as the potential generated at the first, third, and fifth nodes, respectively). Therefore, it is possible to prevent switch 100C2 from being turned on when an extremely large potential difference occurs between the source and drain of transistor 10C2_1, transistor 10C2_2, transistor 10C2_3, and transistor 10C2_4. Consequently, the possibility of hot carrier degradation in transistors 10C2_1, 10C2_2, 10C2_3, and 10C2_4 can be reduced compared to the case where switch 100C2 is operated without going through the operation of switch 100C1.

[0269] For semiconductor device 100C, you can refer to the information provided in semiconductor device 100A for details other than those mentioned above.

[0270] <Example of semiconductor device configuration 4> Figures 11A and 11B show an example of the configuration of a semiconductor device 100D, which has a different configuration from the semiconductor device 100B shown in Figures 4A to 4C. Figure 11A is a plan view of the semiconductor device 100D. Figure 11B is a cross-sectional view corresponding to the dashed line A1-A2 shown in Figure 11A.

[0271] Figure 12A shows a perspective view of the semiconductor device 100D. Note that some insulating layers (insulating layer 110 and insulating layer 106) are made transparent, and only their outlines are shown with dashed lines. Figure 12B is a perspective view from the perspective view shown in Figure 12A, with conductive layer 104_1, conductive layer 104_2, and insulating layer 106 omitted. Figure 13A is a perspective view from the perspective view shown in Figure 12B, with semiconductor layer 108_1 and semiconductor layer 108_2 omitted. Note that in the perspective view shown in Figure 13A, the outline of insulating layer 110 is shown with a solid line. Figure 13B is a perspective view from the perspective view shown in Figure 13A, with conductive layer 112b1_1, conductive layer 112b1_4, conductive layer 112b23, conductive layer 112b2_1, conductive layer 112b2_4, and insulating layer 110 omitted.

[0272] The semiconductor device 100D includes transistors 10D1_1, 10D1_2, 10D1_3, 10D1_4, 10D2_1, 10D2_2, 10D2_3, 10D2_4, an insulating layer 110, and an insulating layer 109.

[0273] The semiconductor device 100D differs from the semiconductor device 100B in that it has eight vertical transistors.

[0274] As shown in Figure 13B, the semiconductor device 100D has conductive layers 112a12 and 112a34 in different regions on the insulating layer 109.

[0275] As shown in Figure 13A, a first island-shaped insulating layer 110 and a second island-shaped insulating layer 110 are provided on the conductive layer 112a12 and the insulating layer 109, respectively, having regions that overlap with the conductive layer 112a12. Furthermore, a third island-shaped insulating layer 110 and a fourth island-shaped insulating layer 110 are provided on the conductive layer 112a34 and the insulating layer 109, respectively, having regions that overlap with the conductive layer 112a34. In addition, a fifth island-shaped insulating layer 110 is provided on the conductive layer 112a12, the conductive layer 112a34, and the insulating layer 109, respectively, having regions that overlap with the conductive layer 112a12 and the conductive layer 112a34.

[0276] As shown in Figure 13A, a conductive layer 112b1_1 is provided on the first island-shaped insulating layer 110. The top surface shapes of the first island-shaped insulating layer 110 and the conductive layer 112b1_1 are substantially the same. A conductive layer 112b2_1 is provided on the second island-shaped insulating layer 110. The top surface shapes of the second island-shaped insulating layer 110 and the conductive layer 112b2_1 are substantially the same. A conductive layer 112b1_4 is provided on the third island-shaped insulating layer 110. The top surface shapes of the third island-shaped insulating layer 110 and the conductive layer 112b1_4 are substantially the same. A conductive layer 112b2_4 is provided on the fourth island-shaped insulating layer 110. The top surface shapes of the fourth island-shaped insulating layer 110 and the conductive layer 112b2_4 are substantially the same. Furthermore, a conductive layer 112b23 is provided on the fifth island-shaped insulating layer 110. The upper surface shapes of the fifth island-shaped insulating layer 110 and the conductive layer 112b23 are substantially the same.

[0277] As shown in Figure 12B, semiconductor layers 108_1 and 108_2 are provided so as to span three of the five island-shaped insulating layers 110. Semiconductor layer 108_1 has regions that are in contact with the upper surface of conductive layer 112a12, the upper surface of conductive layer 112a34, the sides of the three island-shaped insulating layers 110 (the first island-shaped insulating layer 110, the third island-shaped insulating layer 110, and the fifth island-shaped insulating layer 110), the upper and side surfaces of conductive layer 112b1_1, the upper and side surfaces of conductive layer 112b1_4, and the upper and side surfaces of conductive layer 112b23. Furthermore, the semiconductor layer 108_2 has regions that are in contact with the upper surface of the conductive layer 112a12, the upper surface of the conductive layer 112a34, the sides of the three island-shaped insulating layers 110 (the second island-shaped insulating layer 110, the fourth island-shaped insulating layer 110, and the fifth island-shaped insulating layer 110), the upper and side surfaces of the conductive layer 112b2_1, the upper and side surfaces of the conductive layer 112b2_4, and the upper and side surfaces of the conductive layer 112b23.

[0278] As shown in Figure 12A, an insulating layer 106 is provided on semiconductor layer 108_1 and semiconductor layer 108_2. A conductive layer 104_1 is provided on the insulating layer 106 such that it overlaps with semiconductor layer 108_1. A conductive layer 104_2 is also provided such that it overlaps with semiconductor layer 108_2.

[0279] The conductive layer 104_1 has regions that face a total of four sides of three of the five island-shaped insulating layers 110 (the first island-shaped insulating layer 110, the third island-shaped insulating layer 110, and the fifth island-shaped insulating layer 110) via the insulating layer 106 and the semiconductor layer 108_1. This allows the regions of the semiconductor layer 108_1 facing these four sides to function as channel formation regions for transistors 10D1_1, 10D1_2, 10D1_3, and 10D1_4, respectively.

[0280] Similarly, the conductive layer 104_2 has regions that face a total of four sides of three of the five island-shaped insulating layers 110 (the second island-shaped insulating layer 110, the fourth island-shaped insulating layer 110, and the fifth island-shaped insulating layer 110) via the insulating layer 106 and the semiconductor layer 108_2. This allows the regions of the semiconductor layer 108_2 facing these four sides to function as channel formation regions for transistors 10D2_1, 10D2_2, 10D2_3, and 10D2_4, respectively.

[0281] Figure 14B shows a circuit diagram illustrating the configuration of the semiconductor device 100D.

[0282] As shown in Figure 14B, in the semiconductor device 100D, transistors 10D1_1, 10D1_2, 10D1_3, and 10D1_4 are connected in series. Specifically, transistors 10D1_1 and 10D1_2 are connected by a conductive layer 112a12, transistors 10D1_2 and 10D1_3 are connected by a conductive layer 112b23, and transistors 10D1_3 and 10D1_4 are connected by a conductive layer 112a34. In addition, transistors 10D2_1, 10D2_2, 10D2_3, and 10D2_4 are connected in series. Specifically, transistors 10D2_1 and 10D2_2 are connected by a conductive layer 112a12, transistors 10D2_2 and 10D2_3 are connected by a conductive layer 112b23, and transistors 10D2_3 and 10D2_4 are connected by a conductive layer 112a34.

[0283] Furthermore, as shown in Figure 11B, transistors 10D1_1, 10D1_2, 10D1_3, and 10D1_4 share each other's semiconductor layer (semiconductor layer 108_1), gate insulating layer (insulating layer 106), and gate electrode (conductive layer 104_1). Therefore, the configuration combining transistors 10D1_1, 10D1_2, 10D1_3, and 10D1_4 can be considered equivalent to a single transistor whose channel length is the sum of the channel lengths of each transistor.

[0284] Similarly, transistors 10D2_1, 10D2_2, 10D2_3, and 10D2_4 share each other's semiconductor layers (semiconductor layer 108_2), gate insulating layer (insulating layer 106), and gate electrode (conductive layer 104_2). Therefore, a configuration combining transistors 10D2_1, 10D2_2, 10D2_3, and 10D2_4 can be considered equivalent to a single transistor whose channel length is the sum of the channel lengths of each transistor.

[0285] In Figures 11A, 11B, and 14B, the combination of transistors 10D1_1, 10D1_2, 10D1_3, and 10D1_4 is shown as switch 100D1, and the combination of transistors 10D2_1, 10D2_2, 10D2_3, and 10D2_4 is shown as switch 100D2.

[0286] Switches 100D1 and 100D2 each have a configuration in which four transistors are connected in series. Therefore, the overall channel length can be made longer and the voltage withstand capability can be increased compared to switches 100A1 and 100A2, or switches 100B1 and 100B2, which each have a configuration in which two transistors are connected in series.

[0287] As described above, in one aspect of the present invention, vertical transistors can be used in the transistors of the semiconductor device. Therefore, even when increasing the number of transistors connected in series to increase the breakdown voltage, the occupied area of ​​the semiconductor device can be significantly reduced compared to when planar transistors are used.

[0288] As shown in Figures 11A to 13B and Figure 14B, transistors 10D1_1, 10D1_2, 10D2_1, and 10D2_2 share a conductive layer (conductive layer 112a12) that functions as either the source electrode or the drain electrode. Transistors 10D1_2, 10D1_3, 10D2_2, and 10D2_3 share a conductive layer (conductive layer 112b23) that functions as either the source electrode or the drain electrode. Transistors 10D1_3, 10D1_4, 10D2_3, and 10D2_4 share a conductive layer (conductive layer 112a34) that functions as either the source electrode or the drain electrode. The semiconductor device 100D has two switches (switch 100D1 and switch 100D2) arranged in parallel with each other, and these two switches are connected by conductive layers 112a12, 112b23, and 112a34, respectively.

[0289] Because the semiconductor device 100D has the above-described configuration, for example, when switch 100D1 is turned ON, the potential generated at the connection point (first node) between the source electrode and drain electrode of transistors 10D1_1 and 10D1_2 can also be supplied to the connection point (second node) between the source electrode and drain electrode of transistors 10D2_1 and 10D2_2 in switch 100D2 via the conductive layer 112a12. Furthermore, the potential generated at the connection point (third node) between the source electrode and drain electrode of transistors 10D1_2 and 10D1_3 can also be supplied to the connection point (fourth node) between the source electrode and drain electrode of transistors 10D2_2 and 10D2_3 in switch 100D2 via the conductive layer 112b23. Furthermore, the potential generated at the connection point (fifth node) between the source and drain electrodes of transistors 10D1_3 and 10D1_4 can also be applied to the connection point (sixth node) between the source and drain electrodes of transistors 10D2_3 and 10D2_4 in switch 100D2 via the conductive layer 112a34.

[0290] For example, consider the case where switch 100D2 is turned on after switch 100D1 has been turned on. In this case, the second, fourth, and sixth nodes of switch 100D2 are supplied with a certain magnitude of potential beforehand (a potential of the same magnitude as the potential generated at the first, third, and fifth nodes, respectively). Therefore, it is possible to prevent switch 100D2 from being turned on when an extremely large potential difference is generated between the source and drain of transistors 10D2_1, 10D2_2, 10D2_3, and 10D2_4. Consequently, the possibility of hot carrier degradation in transistors 10D2_1, 10D2_2, 10D2_3, and 10D2_4 can be reduced compared to the case where switch 100D2 is operated without going through the operation of switch 100D1.

[0291] For semiconductor device 100D, you can refer to the information provided for semiconductor device 100B for details other than those mentioned above.

[0292] <Example of Semiconductor Device Manufacturing Method> Below, a method for manufacturing a semiconductor device according to one aspect of the present invention will be described with reference to the drawings. Here, the semiconductor device 100A shown in Figures 1A to 1C will be used as an example.

[0293] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, CVD, vacuum deposition, pulsed laser deposition (PLD), and ALD.

[0294] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0295] CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. Furthermore, depending on the source gas used, they can be divided into metal CVD (MCCVD) and metal-organic CVD (MOCVD).

[0296] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices can become charged by receiving charge from the plasma. This accumulated charge can damage the wiring, electrodes, or components in the semiconductor device. In contrast, thermal CVD, which does not use plasma, avoids this plasma damage, resulting in a higher yield for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0297] As ALD methods, thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses a plasma-excited reactant, can be used.

[0298] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that provide good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable, for example, for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as the CVD method, which has a faster deposition rate.

[0299] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the source gases. For example, in the CVD method, by changing the flow rate ratio of the source gases while deposition is occurring, films with continuously changing compositions can be deposited. When deposition is performed while changing the flow rate ratio of the source gases, the deposition time can be shortened compared to deposition using multiple deposition chambers, because time required for transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0300] Furthermore, the ALD method allows for the deposition of films of any composition by using multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, films of any composition can be deposited by controlling the number of cycles for each precursor.

[0301] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0302] Thin films constituting semiconductor devices can be processed using methods such as photolithography. In addition, thin films can also be processed using nanoimprint lithography, sandblasting, and lift-off methods. Furthermore, island-like thin films can be directly formed using deposition methods that utilize shielding masks such as metal masks.

[0303] Photolithography typically involves two main methods. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, followed by exposure and development, to process the thin film into the desired shape.

[0304] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0305] For etching thin films, methods such as dry etching, wet etching, or sandblasting can be used.

[0306] For planarization of thin films, polishing methods such as the CMP method are typically suitable. Alternatively, the reflow method, which involves heat treatment of the conductive layer to fluidize it, can also be suitably used. Furthermore, a combination of the reflow method and the CMP method can be employed.

[0307] Furthermore, a process can be used in which a planarization film is formed on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching (e.g., dry etching) on ​​the planarization film, or a process in which a planarization film and a photoresist are formed in that order on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching on the planarization film and the photoresist, thereby filling only the planarization film into the depressions and flattening the entire top surface (these processes are sometimes called etch-back processes). When using an etch-back process, high-temperature heating (e.g., around 800°C) like that used in reflow methods is not required, so there is no need to worry about damage to the device during fabrication caused by such heating. In addition, an etch-back process is suitable because it can be applied to devices on large substrates that are difficult to process with the CMP method due to the effects of bending, etc.

[0308] Other thin film planarization treatments that can be used include dry etching and plasma treatment. Polishing, dry etching, and plasma treatment can be performed multiple times, or they can be combined. When combining treatments, the order of the processes is not particularly limited and is preferably set appropriately according to the surface irregularities of the treated surface.

[0309] To precisely process a thin film to a desired thickness, for example, the CMP method can be used. In this method, first, the thin film is polished at a constant processing speed until a portion of its upper surface is exposed. Then, by polishing at a slower processing speed until the thin film reaches the desired thickness, high-precision processing becomes possible.

[0310] Methods for detecting the end point of polishing include optical methods that involve irradiating the surface of the workpiece with light and detecting changes in the reflected light, physical methods that involve detecting changes in the polishing resistance that the processing equipment receives from the workpiece, and methods that use changes in magnetic field lines caused by eddy currents generated when magnetic field lines are applied to the workpiece.

[0311] After the upper surface of the thin film is exposed, the thickness of the thin film can be precisely controlled by performing a polishing process at a slow processing speed while monitoring its thickness using an optical method such as a laser interferometer. If necessary, the polishing process can be repeated multiple times until the thin film reaches the desired thickness.

[0312] Figures 15A to 19C illustrate the method for manufacturing the semiconductor device 100A. In each figure, A shows a plan view corresponding to Figure 1A. In each figure, B shows a cross-sectional view along the dashed line A1-A2 in the plan view shown in Figure 1A. In each figure, C shows a cross-sectional view along the dashed line B1-B2 in the plan view shown in Figure 1A.

[0313] First, an insulating layer 109 is formed on the substrate 102. For example, sputtering or PECVD can be used to form the insulating layer 109.

[0314] Next, conductive films that will become conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2 are formed on the insulating layer 109, and conductive layers 112a1_1, 112a1_2, 112a2_1, and 112a2_2 are formed by removing a portion of the conductive film (Figures 15A to 15C). For example, sputtering can be used to form the conductive films. In addition, either or both of wet etching and dry etching can be used to process the conductive films.

[0315] Next, insulating films 110af, 110bf, and 110cf are formed in this order on the conductive layer 112a1_1, conductive layer 112a1_2, conductive layer 112a2_1, conductive layer 112a2_2, and insulating layer 109.

[0316] The insulating film 110af can be made from any material that can be used for the insulating layer 110a described above.

[0317] As the insulating film 110af, for example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide can be suitably used.

[0318] Specifically, as the insulating film 110af, for example, silicon nitride can be deposited using the sputtering method. Alternatively, for example, silicon nitride can be deposited using the PEALD method. Alternatively, for example, aluminum oxide can be deposited using the sputtering method.

[0319] Furthermore, for example, a configuration in which aluminum oxide and silicon nitride are layered can be used. For instance, aluminum oxide deposited using the sputtering method and silicon nitride deposited using the PEALD method can be used in a layered configuration.

[0320] For the insulating film 110bf, any material that can be used for the insulating layer 110b described above can be used as appropriate.

[0321] For example, silicon oxide, silicon oxide, silicon nitride, etc., can be suitably used as the insulating film 110bf.

[0322] Specifically, as the insulating film 110bf, silicon oxide can be deposited using, for example, a sputtering method. Alternatively, silicon oxide can be deposited using, for example, a PECVD method. Alternatively, silicon oxynitride can be deposited using, for example, a PECVD method.

[0323] Furthermore, for example, silicon oxide deposited using the sputtering method and silicon oxide or silicon oxidnitride deposited using the PECVD method can be used in a layered configuration.

[0324] The insulating film 110bf can also be subjected to heat treatment after it has been formed. By performing heat treatment, water and hydrogen can be removed from the surface and within the insulating film 110bf.

[0325] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate 102, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can also be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a very low content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 110bf as much as possible. Heat treatment can be performed using, for example, an oven or a rapid thermal annealing (RTA) device. Using an RTA device can shorten the heat treatment time.

[0326] After the above heat treatment, a step of supplying oxygen to the insulating film 110bf can also be performed. For example, after the insulating film 110bf is formed, a metal oxide layer can be formed on the insulating film 110bf to supply oxygen to the insulating film 110bf. Alternatively, the heat treatment can be performed after the formation of the metal oxide layer. By performing the heat treatment after the formation of the metal oxide layer, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110bf, and oxygen can be contained in the insulating film 110bf. The oxygen supplied to the insulating film 110bf is then supplied to the semiconductor layer 108_1 and the semiconductor layer 108_2, respectively, in a later step, thereby eliminating oxygen vacancies (V) in the semiconductor layer 108_1 and the semiconductor layer 108_2, respectively. Ｏ ) and V Ｏ H can be reduced.

[0327] After forming the metal oxide layer, or after the aforementioned heat treatment, oxygen can be further supplied to the insulating film 110bf through the metal oxide layer. As a method of supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. As the plasma treatment, a device that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of devices that convert gas into plasma using high-frequency power include plasma etching devices and plasma ashing devices.

[0328] The metal oxide layer may be an insulating layer or a conductive layer. The metal oxide layer may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide, or silicon-containing indium tin oxide.

[0329] It is preferable to use an oxide material containing one or more of the same elements as semiconductor layer 108_1 and semiconductor layer 108_2 as the metal oxide layer. In particular, it is preferable to use an oxide semiconductor material applicable to semiconductor layer 108_1 and semiconductor layer 108_2. This allows the metal oxide layer to be formed using the same sputtering target as semiconductor layer 108_1 and semiconductor layer 108_2, thereby reducing manufacturing costs.

[0330] When using a metal oxide material containing indium and gallium in the metal oxide layer, a material with a higher gallium composition (content) than semiconductor layer 108_1 and semiconductor layer 108_2 can be used. By using a material with a higher gallium composition (content) in the metal oxide layer, the barrier properties against oxygen can be further enhanced. This is preferable because it can suppress the detachment of oxygen contained in the insulating film 110bf to the outside through the metal oxide layer.

[0331] The metal oxide layer is preferably formed in an oxygen-containing atmosphere, for example. In particular, it is preferable to form it by sputtering in an oxygen-containing atmosphere. This allows for a suitable supply of oxygen to the insulating film 110bf during the formation of the metal oxide layer.

[0332] Next, the metal oxide layer is removed. For example, a wet etching method can be suitably used to remove the metal oxide layer.

[0333] The process of supplying oxygen to the insulating film 110bf is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecular ions, etc., can be supplied to the insulating film 110bf by ion doping, ion implantation, plasma treatment, etc. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used. Alternatively, a semiconductor film can be used.

[0334] For the insulating film 110cf, any material that can be used for the insulating layer 110c described above can be used as appropriate.

[0335] For materials and film formation methods that can be used for the insulating film 110cf, refer to the above-mentioned description of materials and film formation methods that can be used for the insulating film 110af.

[0336] Next, a conductive film 112b12f is formed on the insulating film 110cf (Figures 16A to 16C). Any material that can be used for the conductive layer 112b12 described above can be appropriately used for the conductive film 112b12f. Furthermore, for example, a sputtering method can be used to form the conductive film 112b12f.

[0337] Next, the conductive film 112b12f, insulating film 110cf, insulating film 110bf, and insulating film 110af are processed to form conductive layer 112b12, insulating layer 110c, insulating layer 110b, and insulating layer 110a, respectively, whose upper surface shapes are substantially the same (Figures 17A to 17C). This forms an insulating layer 110 having insulating layers 110a, insulating layer 110b, and insulating layer 110c. The insulating layer 110 and the conductive layer 112b12 are formed to have regions that overlap with conductive layers 112a1_1, conductive layer 112a1_2, conductive layer 112a2_1, and conductive layer 112a2_2, respectively. For example, a wet etching method can be used to form the conductive layer 112b12. For example, a dry etching method can be used to form the insulating layer 110.

[0338] The conductive layer 112b12 and the insulating layer 110 can be formed, for example, using the same resist mask. After forming the insulating film (insulating film 110af, insulating film 110bf, and insulating film 110cf) that will become the insulating layer 110, and the conductive film 112b12f, a resist mask is formed on the conductive film 112b12f. Using this resist mask as a mask, the conductive film 112b12f and the insulating film are processed to form the conductive layer 112b12 and the insulating layer 110, respectively. By using the same resist mask for the formation of both the conductive layer 112b12 and the insulating layer 110, productivity can be increased. Furthermore, the top surface shapes of the conductive layer 112b12 and the insulating layer 110 can be made to match or roughly match. Note that different resist masks can also be used for the formation of the conductive layer 112b12 and the insulating layer 110.

[0339] Next, a semiconductor film is formed to cover the conductive layer 112b12, the insulating layer 110, the conductive layer 112a1_1, the conductive layer 112a1_2, the conductive layer 112a2_1, and the conductive layer 112a2_2, which will become semiconductor layers 108_1 and 108_2. Then, a portion of the semiconductor film is removed by etching to form semiconductor layers 108_1 and 108_2, respectively (Figures 18A to 18C). Semiconductor layer 108_1 is provided to have regions that overlap with each of the conductive layers 112a1_1, 112a1_2, and 112b12. Semiconductor layer 108_2 is provided to have regions that overlap with each of the conductive layers 112a2_1, 112a2_2, and 112b12.

[0340] Semiconductor layer 108_1 has regions that are in contact with the upper surface of conductive layer 112a1_1, the upper surface of conductive layer 112a1_2, the side surface of insulating layer 110, the side surface of conductive layer 112b12, and the upper surface of conductive layer 112b12. Semiconductor layer 108_2 has regions that are in contact with the upper surface of conductive layer 112a2_1, the upper surface of conductive layer 112a2_2, the side surface of insulating layer 110, the side surface of conductive layer 112b12, and the upper surface of conductive layer 112b12.

[0341] For the semiconductor films that will become semiconductor layer 108_1 and semiconductor layer 108_2, any materials that can be used for semiconductor layer 108_1 and semiconductor layer 108_2 as described above can be used as appropriate.

[0342] For example, sputtering can be used to form the semiconductor films that will become semiconductor layer 108_1 and semiconductor layer 108_2. For example, when metal oxides are used for semiconductor layer 108_1 and semiconductor layer 108_2, they can be formed by sputtering using a metal oxide target. Using sputtering is preferable because it allows for the relatively easy formation of films with low hydrogen content.

[0343] Furthermore, when using metal oxides for semiconductor layers 108_1 and 108_2, they can also be formed by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

[0344] For example, when forming an In-Ga-Zn oxide, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used. Alternatively, two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can also be used.

[0345] As the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionato)indium, cyclopentadienylindium, indium(III) chloride, etc. can be used.

[0346] Also, as the precursor containing gallium, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionato)gallium, dimethylchlorogallium, diethylchlorogallium, etc. can be used.

[0347] Also, as the precursor containing zinc, dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionato)zinc, zinc chloride, etc. can be used.

[0348] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0349] As a method for controlling the composition of the obtained film, examples include adjusting the flow rate ratio of the source gases, the time for flowing the source gases, the order of flowing the source gases, etc. Also, by adjusting these, a film with a continuously changing composition can be formed. Further, it is also possible to continuously form films with different compositions.

[0350] It is preferable to use the ALD method for forming the semiconductor films that will become the semiconductor layer 108_1 and the semiconductor layer 108_2, because each of the semiconductor layer 108_1 and the semiconductor layer 108_2 can be formed with a uniform thickness on the side surfaces of the insulating layer 110 and the conductive layer 112b12.

[0351] The substrate temperature during the formation of the semiconductor films that will become semiconductor layer 108_1 and semiconductor layer 108_2 is preferably between room temperature (25°C) and 200°C, and more preferably between room temperature and 130°C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when using a large-area glass substrate.

[0352] The higher the substrate temperature (stage temperature) during metal oxide layer formation, the more crystalline the metal oxide layer can be formed. Furthermore, the higher the oxygen flow rate ratio, the more crystalline the metal oxide layer can be formed.

[0353] Furthermore, before forming the semiconductor films that will become semiconductor layer 108_1 and semiconductor layer 108_2, it is preferable to perform at least one of the following: a treatment to desorb water, hydrogen, organic matter, etc. adsorbed on the surface of the insulating layer 110, and a treatment to supply oxygen into the insulating layer 110. For example, a heat treatment can be performed at a temperature of 70°C to 200°C in a reduced-pressure atmosphere. Alternatively, a plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, nitrous oxide (N) can be used. ２ Oxygen can be supplied to the insulating layer 110 by plasma treatment in an atmosphere containing an oxidizing gas such as 0). Plasma treatment containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 110 while supplying oxygen. After such treatment, it is preferable to form semiconductor films that become semiconductor layer 108_1 and semiconductor layer 108_2 continuously without exposing the surface of the insulating layer 110 to the atmosphere.

[0354] Furthermore, when semiconductor layer 108_1 and semiconductor layer 108_2 are each in a stacked structure, it is preferable to form the next semiconductor film continuously after forming the first semiconductor film without exposing its surface to the atmosphere.

[0355] When semiconductor layer 108_1 and semiconductor layer 108_2 are each in a stacked structure, all layers constituting each of semiconductor layer 108_1 and semiconductor layer 108_2 can be deposited using the same method (for example, sputtering or ALD). Alternatively, different deposition methods can be used for each layer. For example, the first semiconductor layer can be deposited by sputtering, and the second semiconductor layer on the first semiconductor layer can be deposited by ALD.

[0356] Furthermore, after forming the semiconductor films that will become semiconductor layer 108_1 and semiconductor layer 108_2, a heat treatment can be performed. The heat treatment reduces the amount of water and hydrogen contained in the semiconductor film and allows oxygen to be supplied to the semiconductor film from the insulating layer 110. Note that the heat treatment can also be performed after processing the semiconductor film.

[0357] Next, an insulating layer 106 is formed by covering semiconductor layer 108_1, semiconductor layer 108_2, conductive layer 112b12, insulating layer 110, conductive layer 112a1_1, conductive layer 112a1_2, conductive layer 112a2_1, conductive layer 112a2_2, and insulating layer 109 (Figures 19A to 19C). The insulating layer 106 has regions that are in contact with the top and side surfaces of semiconductor layer 108_1, semiconductor layer 108_2, conductive layer 112b12, insulating layer 110, conductive layer 112a1_1, conductive layer 112a1_2, conductive layer 112a2_1, conductive layer 112a2_2, and the top surface of insulating layer 109.

[0358] The insulating layer 106 can be made from any of the materials described above as appropriate.

[0359] For example, the ALD method can be used to form the insulating layer 106. The ALD method is preferable because it allows for good coverage of both the semiconductor layer 108_1 and the semiconductor layer 108_2. However, if the semiconductor layer 108_1 and the semiconductor layer 108_2 can be sufficiently covered, methods other than the ALD method can be used to form the insulating layer 106. For example, the PECVD method or sputtering method can be used. This allows for a faster deposition rate of the insulating layer 106 than when using the ALD method, thereby increasing productivity.

[0360] By increasing the temperature during film formation of the insulating layer 106, which functions as a gate insulating layer, an insulating layer with fewer defects can be obtained. However, if the temperature during film formation of the insulating layer 106 is high, oxygen will be detached from the semiconductor layer 108_1 and the semiconductor layer 108_2, respectively, resulting in oxygen deficiencies (V) in the semiconductor layer 108_1 and the semiconductor layer 108_2. Ｏ ) and V Ｏ In some cases, the amount of H may increase. The substrate temperature during the deposition of the insulating layer 106 is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, and more preferably 300°C to 400°C. By setting the substrate temperature during the deposition of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced, and the detachment of oxygen from the semiconductor layer 108_1 and semiconductor layer 108_2 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0361] Before forming the insulating layer 106, plasma treatment can be performed on the surfaces of semiconductor layer 108_1 and semiconductor layer 108_2. This plasma treatment can reduce impurities such as water adsorbed on the surfaces of semiconductor layer 108_1 and semiconductor layer 108_2. As a result, impurities at the interfaces between semiconductor layer 108_1 and insulating layer 106, and between semiconductor layer 108_2 and insulating layer 106 can be reduced, enabling the realization of a highly reliable transistor. This is particularly suitable when the surfaces of semiconductor layer 108_1 and semiconductor layer 108_2 are exposed to the atmosphere between the formation of semiconductor layer 108_1 and semiconductor layer 108_2 and the formation of the insulating layer 106. Plasma treatment can be performed in an atmosphere such as oxygen, ozone, nitrogen, nitrous oxide, or argon. Furthermore, it is preferable that the plasma treatment and the formation of the insulating layer 106 are performed continuously without exposure to the atmosphere.

[0362] Next, conductive films that will become conductive layers 104_1 and 104_2 are formed on the insulating layer 106. The conductive films that will become conductive layers 104_1 and 104_2 can be made from materials that can be used for conductive layers 104_1 and 104_2 as described above. Furthermore, sputtering, CVD, molecular beam epitaxy (MBE), PLD, ALD, etc., can be used to form the conductive films that will become conductive layers 104_1 and 104_2. Here, it is preferable that the conductive films that will become conductive layers 104_1 and 104_2 are formed in contact with the insulating layer 106 such that they have regions facing two sides of the island-shaped insulating layer 110 via the insulating layer 106, semiconductor layer 108_1, and semiconductor layer 108_2. Therefore, it is preferable to use a formation method that provides good coverage or embedding properties for forming the conductive films that will become conductive layer 104_1 and conductive layer 104_2, and it is more preferable to use a CVD method or an ALD method.

[0363] Next, a portion of the conductive film that will become conductive layer 104_1 and conductive layer 104_2 is removed to form conductive layer 104_1 and conductive layer 104_2. Conductive layer 104_1 is formed to have a region that overlaps with semiconductor layer 108_1. Conductive layer 104_2 is formed to have a region that overlaps with semiconductor layer 108_2. In addition, the upper surface of the insulating layer 106 is exposed in the region from which the conductive film that will become conductive layer 104_1 and conductive layer 104_2 has been removed. Either a wet etching method or a dry etching method, or both, can be used to form conductive layer 104_1 and conductive layer 104_2.

[0364] This results in the formation of switch 100A1 having transistors 10A1_1 and 10A1_2, and switch 100A2 having transistors 10A2_1 and 10A2_2, respectively.

[0365] By following the above steps, the semiconductor device 100A can be manufactured (Figures 1A to 1C).

[0366] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0367] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0368] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0369] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0370] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0371] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single-crystal indium oxide.

[0372] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0373] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0374] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10１９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0375] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. It is especially preferable to use elements in which the oxide is conductive or semiconducting.

[0376] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0377] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at the grain boundaries can be suppressed, enabling the realization of a transistor exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by the grain boundaries.

[0378] In addition, compared with microcrystalline films or amorphous films, polycrystalline films can reduce carrier scattering and exhibit high field-effect mobility, which is preferable. When using a polycrystalline film, it is preferable to use a film with as large grain sizes as possible and few grain boundaries. In a transistor to which a polycrystalline film is applied, when there are no grain boundaries in the channel formation region or no grain boundaries are observed, since the channel formation region is located within the single-crystalline region contained in the polycrystalline film, it can be regarded as a transistor to which a single-crystalline film is applied.

[0379] Note that the crystallinity of indium oxide can be analyzed by, for example, XRD, TEM, or electron diffraction (ED: Electron Diffraction). Or, analysis may be performed by combining a plurality of these.

[0380] In addition, in this specification and the like, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one grain, or a semiconductor layer in which the directions of crystal axes are the same in at least two regions within the channel formation region can be regarded as a single-crystalline film.

[0381] Note that the channel formation region refers to a region in the semiconductor layer that overlaps (or faces) the gate electrode through the gate insulating layer and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The grains, grain boundaries, crystal axes, crystal orientations, etc. in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0382] Impurities in the indium oxide film can be a source of carrier scattering, and thus can also be a factor in reducing the field-effect mobility and a factor in inhibiting crystal growth. Examples of impurities in the indium oxide film include boron, silicon, etc. In the channel formation region, the indium oxide film preferably has a lower concentration of these impurities. For example, the concentration of each of the above impurity elements is 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, etc. are elements that may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film more than the above impurities.

[0383] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include group 13 elements of the periodic table such as gallium and aluminum, and group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0384] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0385] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0386] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0387] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0388] Indium oxide has the characteristics that the effective mass of electrons is small and the effective mass of holes is large. Also, the effective mass of electrons in indium oxide has the characteristic of hardly depending on the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and a transistor with high frequency characteristics (also called f characteristics) can be realized. Furthermore, because the effective mass of holes is large, a transistor with an extremely small off-current can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm channel width can be 1 fA (1×10 −１５ A) or less, or 1 aA (1×10 −１８ A) or less in an environment of 125°C, and 1 aA (1×10 −１８ A) or less, or 1 zA (1×10 −２１ A) or less in an environment of room temperature (25°C). Also, since the effective mass of electrons in indium oxide is smaller and the effective mass of holes is larger than those in silicon, there is a possibility of realizing a transistor with higher field-effect mobility and a smaller off-current than a Si transistor.

[0389] It is preferable to provide a seed layer so as to contact at least a part of the crystalline indium oxide film. For the seed layer, it is preferable to use a material containing a crystal with a small difference in lattice constant (also called lattice mismatch) from indium oxide. Thereby, the crystallinity of the indium oxide film can be improved. Note that, as one of the layers contacting at least a part of the crystalline indium oxide film, a substrate (for example, a single crystal substrate) may be used.

[0390] As one method for evaluating the degree of lattice mismatch, there is a method using the value of lattice mismatch shown below. The lattice mismatch degree Δa [%] of the crystal of the formed film (here, the indium oxide film) with respect to the crystal of the seed layer is calculated by Δa = ((L １ - L ２ ) / L ２ ) × 100. Here, L １ is the length of the unit lattice vector or the lattice constant of the crystal of the formed film, and L ２is the length of the unit lattice vector or lattice constant of the crystal possessed by the seed layer.

[0391] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably smaller in absolute value, and most preferably 0. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0392] Here, the crystal of indium oxide has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the YSZ crystal having a cubic crystal structure is within the range of -2% or more and 2% or less, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0393] Note that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not have the same crystal system or crystal orientation. For example, a film having a hexagonal or trigonal crystal structure can also be used under an indium oxide film having a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the lower surface of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of crystals having a hexagonal or trigonal crystal system include wurtzite-type structures, YbFe ２ O ４ type structures, Yb ２ Fe ３ O ７ type structures, and modified structures thereof. Examples of crystals having a YbFe ２ O ４ type structure or a Yb ２ Fe ３ O ７ type structure include IGZO and the like.

[0394] This embodiment can be implemented in appropriate combination with other embodiments described in this specification, at least in part.

[0395] (Embodiment 3) In this embodiment, specific examples of circuit configurations, operating methods, etc. to which the semiconductor device according to one aspect of the present invention described in Embodiment 1 can be applied will be described in detail.

[0396] A semiconductor device according to one aspect of the present invention has the function of suppressing the degradation of the hot carrier of a transistor. This semiconductor device can be used, for example, as an element of a drive circuit for a display device.

[0397] In the following section, an example of a circuit configuration applying a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0398] Figure 20 shows an example of a circuit configuration to which a semiconductor device (here, semiconductor device 100A or semiconductor device 100B) according to one embodiment of the present invention described in Embodiment 1 is applied. The circuit configuration will be explained using Figure 20. The circuit has a switch SW1, a switch SW2, a switch DSW1, and a switch DSW2. Switches SW1 and SW2 are connected to each other. Switches SW1 and DSW1 are connected to each other. Switches SW2 and DSW2 are connected to each other.

[0399] For example, in the circuit shown in Figure 20, semiconductor device 100A or semiconductor device 100B can be applied to switch SW1 and switch DSW1, and to switch SW2 and switch DSW2, respectively.

[0400] Switch SW1 has transistor M1 and transistor M2. Transistors M1 and M2 are connected in series. Specifically, the source of transistor M1 and the drain of transistor M2 are connected to each other. In Figure 20, the node where the source of transistor M1 and the drain of transistor M2 are connected is shown as node N1. Also, the gate of transistor M1 and the gate of transistor M2 are connected to each other.

[0401] Switch SW2 has transistors M3 and M4. Transistors M3 and M4 are connected in series. Specifically, the source of transistor M3 and the drain of transistor M4 are connected to each other. In Figure 20, the node where the source of transistor M3 and the drain of transistor M4 are connected is shown as node N2. Also, the gate of transistor M3 and the gate of transistor M4 are connected to each other.

[0402] Switches SW1 and SW2 are connected to each other. Specifically, the source of transistor M2 on switch SW1 is connected to the drain of transistor M3 on switch SW2. In Figure 20, the node where switches SW1 and SW2 are connected is shown as node ND.

[0403] Furthermore, the drain of transistor M1 on switch SW1 is connected to a high-potential power line, and a high potential (VDD) is supplied to this drain. On the other hand, the source of transistor M4 on switch SW2 is connected to a low-potential power line, and a low potential (VSS) is supplied to this source.

[0404] Switch DSW1 includes transistor DM1 and transistor DM2. Transistors DM1 and DM2 are connected in series. Specifically, the source of transistor DM1 and the drain of transistor DM2 are connected to each other. In Figure 20, the node where the source of transistor DM1 and the drain of transistor DM2 are connected is shown as node DN1. Also, the gate of transistor DM1 and the gate of transistor DM2 are connected to each other.

[0405] Furthermore, the drain of transistor DM1 on switch DSW1 is connected to a high-potential power line, and a high potential (VDD) is supplied to this drain. Also, the source of transistor DM2 on switch DSW1 is connected to a low-potential power line, and a low potential (VSS) is supplied to this source.

[0406] Switch SW1 and Switch DSW1 are connected to each other. Specifically, node N1 on Switch SW1 and node DN1 on Switch DSW1 are connected.

[0407] Switch DSW2 includes transistors DM3 and DM4. Transistors DM3 and DM4 are connected in series. Specifically, the source of transistor DM3 and the drain of transistor DM4 are connected to each other. In Figure 20, the node where the source of transistor DM3 and the drain of transistor DM4 are connected is shown as node DN2. Also, the gate of transistor DM3 and the gate of transistor DM4 are connected to each other.

[0408] Furthermore, the drain of transistor DM3 in switch DSW2 is connected to a high-potential power line, and a high potential (VDD) is supplied to this drain. In addition, the source of transistor DM4 in switch DSW2 is connected to a low-potential power line, and a low potential (VSS) is supplied to this source.

[0409] Switch SW2 and Switch DSW2 are connected to each other. Specifically, node N2 on Switch SW2 is connected to node DN2 on Switch DSW2.

[0410] Although Figure 20 shows a configuration in which each switch has two transistors, this is not limited to this configuration. As described in Embodiment 1, a semiconductor device according to one aspect of the present invention can also be configured in which each switch has three or more transistors. By configuring each switch to have multiple transistors connected in series, the leakage current of each switch can be reduced compared to a configuration with only one transistor. In addition, the breakdown voltage of each switch (specifically, the breakdown voltage between the drain of the first stage transistor and the source of the last stage transistor in each switch) can be increased.

[0411] Furthermore, the number of transistors connected in series in switch SW1 and switch SW2 do not necessarily have to be the same; they can be different. On the other hand, it is preferable that the number of transistors connected in series in switch SW1 and switch DSW1 are the same. This allows all the nodes between transistors in switch SW1 to be connected to the corresponding nodes between transistors in switch DSW1. For the same reason, it is preferable that the number of transistors connected in series in switch SW2 and switch DSW2 are the same.

[0412] As described above, switch SW1 is connected to a high-potential power line and, when conductive, can supply a high potential (VDD) to node ND. Switch SW2 is connected to a low-potential power line and, when conductive, can supply a low potential (VSS) to node ND. One embodiment of the present invention is a semiconductor device that, depending on the operation of the circuit to which it is applied, alternately repeats the operation of conducting switch SW1 and non-conducting switch SW2, and the non-conducting switch SW1 and conducting switch SW2. In other words, the potential of node ND can be either VDD or VSS in a steady state.

[0413] One aspect of the present invention provides a semiconductor device equipped with a switch DSW1 connected to a switch SW1 and a switch DSW2 connected to a switch SW2, thereby suppressing hot carrier degradation of the transistors in each of the switches SW1 and SW2 during operation of the semiconductor device. Before describing an example of operation of one aspect of the present invention having the circuit configuration shown in Figure 20, we will first describe an example of operation of a semiconductor device without switches DSW1 and DSW2 (hereinafter referred to as a "conventional semiconductor device").

[0414] Figures 21A to 21D illustrate an example of operation of a conventional semiconductor device. This semiconductor device has a configuration in which switches DSW1 and DSW2 are omitted from the semiconductor device of one embodiment of the present invention shown in Figure 20.

[0415] Figure 21A shows the potential (V) at which the gates of transistors M1 and M2 turn on. Ｈ A voltage (V) is supplied to the gates of transistors M3 and M4, which is the potential (V) at which each transistor turns off. Ｌ This indicates that a current is being supplied. That is, switch SW1 is in a conductive state and switch SW2 is in a non-conductive state. In the following, we will describe an example of operation of a conventional semiconductor device, with the steady state in which switch SW1 is in a conductive state and switch SW2 is in a non-conductive state being referred to as the first state, and the steady state in which switch SW1 is in a non-conductive state and switch SW2 is in a conductive state being referred to as the second state.

[0416] As mentioned above, in the first state, switch SW1 is conducting and switch SW2 is not conducting, so the potential of node ND is VDD. Also, at this time, the potential of node N1 between transistors M1 and M2 is VDD at switch SW1. At this time, at switch SW2, the potential of node N2 between transistors M3 and M4 is VSS.

[0417] For example, when the state immediately preceding the first state is the second state, and both transistors M3 and M4 are in the ON state, the potentials of both node ND and node N2 are VSS. Therefore, when switching from the second state to the first state (i.e., both transistors M3 and M4 are in the OFF state), node N2 is in a state where VSS is maintained.

[0418] Next, Figure 21B will be used to explain the transition period from the first state to the second state. Figure 21B shows the state immediately after the switch from the first state to the second state, that is, immediately after the switch SW2 becomes conductive.

[0419] First, switch SW1 becomes non-conductive, and then switch SW2 becomes conductive. At this point, a high potential (V) is applied to the gates of transistors M3 and M4. Ｈ When the voltage (V) is supplied, the potential at node ND is VDD and the potential at node N2 is VSS. Therefore, the source-drain voltage of transistor M3 (V) ｄｓ ) becomes VDD-VSS (V of transistor M4) ｄｓ 0V (VSS - VSS). VDD - VSS is the maximum potential difference that can occur in the circuit. Therefore, at the moment switch SW2 becomes conductive, transistor M3 receives V ｄｓ When the current starts flowing from a state where the coefficient is large, hot carriers are more likely to be generated.

[0420] Current flows through switch SW2 until the potential of node ND drops to VSS, after which it enters a steady state. This state is the second state shown in Figure 21C.

[0421] Next, we will explain the transition period when switching from the second state to the first state using Figure 21D. Figure 21D shows the state immediately after switching from the second state to the first state, that is, immediately after switch SW1 becomes conductive.

[0422] First, switch SW2 becomes non-conductive, and then switch SW1 becomes conductive. At this point, a high potential (V) is applied to the gates of transistors M1 and M2. Ｈ When ) is supplied, the potential of node ND is VSS and the potential of node N1 is VDD. Therefore, the source-drain voltage of transistor M2 (V ｄｓ ) becomes VDD-VSS (V of transistor M1) ｄｓ (0V (VDD-VDD)). Therefore, transistor M2 receives V the moment switch SW1 becomes conductive. ｄｓ When the current starts flowing from a state where the coefficient is large, hot carriers are more likely to be generated.

[0423] Current flows through switch SW1 until the potential of node ND rises to VDD, after which it enters a steady state. This state is the first state shown in Figure 21A.

[0424] As described above, one embodiment of the present invention is a semiconductor device that alternately operates by conducting switch SW1 and conducting switch SW2. Therefore, if the semiconductor device is composed only of switch SW1 and switch SW2 (i.e., has the configuration of a conventional semiconductor device), during the operation of the semiconductor device, the hot carriers generated are repeatedly injected into the gate insulating film of transistors M2 and M3, which may cause hot carrier degradation such as the on-current stagnating.

[0425] Figures 22A to 24B illustrate an example of operation of a semiconductor device according to one embodiment of the present invention shown in Figure 20. Similar to the conventional semiconductor device operation examples described above (Figures 21A to 21D), the semiconductor device according to one embodiment of the present invention alternately repeats the conduction of switch SW1 and switch SW2. However, the semiconductor device according to one embodiment of the present invention differs from the conventional semiconductor device in that, in addition to switches SW1 and SW2, it also has switches DSW1 and DSW2. Therefore, in addition to the operation of the conventional semiconductor device described above, the semiconductor device according to one embodiment of the present invention includes a step of operating switches DSW1 and DSW2. By going through this step during operation, the semiconductor device according to one embodiment of the present invention can reduce concerns about hot carrier degradation of transistors M2 and M3. The details of the operation example of the semiconductor device according to one embodiment of the present invention will be described below.

[0426] Figure 22A shows the high potential (V) at which the gates of transistors DM1 and DM2 turn ON. Ｈ A low potential (V) is supplied to the gates of transistors M1 and M2, transistors M3 and M4, and transistors DM3 and DM4, which causes each transistor to be in an off state. ＬThis indicates that a power supply is being provided. That is, switch DSW1 is in a conductive state, and switches SW1, SW2, and DSW2 are in a non-conductive state.

[0427] In the following, a steady state in which switch DSW1 is conducting and switches SW1, SW2, and DSW2 are not conducting will be described as the third state. A steady state in which switch SW1 is conducting and switches SW2, DSW1, and DSW2 are not conducting will be described as the fourth state. A steady state in which switch DSW2 is conducting and switches SW1, SW2, and DSW1 are not conducting will be described as the fifth state. A steady state in which switch SW2 is conducting and switches SW1, DSW1, and DSW2 are not conducting will be described as the sixth state.

[0428] As mentioned above, in the third state, switch DSW1 is in a conducting state, and switches SW1, SW2, and DSW2 are in a non-conducting state. Therefore, at switch DSW1, the potential of node DN1 between transistors DM1 and DM2 is between VDD and VSS (higher than VSS and lower than VDD). In Figure 22A, this potential is V Ｍ It is shown as V Ｍ This is the potential determined by the magnitude of the resistance of transistors DM1 and DM2 when they are turned on. For example, if the magnitudes of the resistances of transistors DM1 and DM2 are equal when they are turned on, the potential V of node DN1 is Ｍ The result is (VDD + VSS) / 2. Also, if the resistance of transistor DM1 when it is ON is greater than the resistance of transistor DM2 when it is ON, then V Ｍ The potential will be lower than (VDD + VSS) / 2 (closer to VSS than VDD). Conversely, if the ON resistance of transistor DM2 is greater than the ON resistance of transistor DM1, then V Ｍ This will result in a potential higher than (VDD + VSS) / 2 (a potential closer to VDD than to VSS).

[0429] In the following, the fact that the potential between nodes is automatically determined by the magnitude of the resistance of each transistor connected in series in each switch when it is turned on is sometimes referred to as "potential division between VDD and VSS."

[0430] Also, the potential of node DN1 of switch DSW1 is V Ｍ As a result, the potential of node N1 of switch SW1 connected to it also becomes V Ｍ This is the result.

[0431] In this case (the third state), the potential of node ND, the potential of node N2 between transistors M3 and M4 in switch SW2, and the potential of node DN2 between transistors DM3 and DM4 in switch DSW2 are all assumed to be VSS.

[0432] For example, when the state immediately preceding the third state is the sixth state, and both transistors M3 and M4 are in the ON state, the potentials of nodes ND, N2, and DN2 are all VSS. Therefore, when switching from the sixth state to the third state (i.e., both transistors M3 and M4 are in the OFF state), nodes ND, N2, and DN2 are in a state where VSS is maintained.

[0433] Next, Figure 22B will be used to explain the transition period from the third state to the fourth state. Figure 22B shows the state immediately after the switch from the third state to the fourth state, that is, immediately after switch SW1 becomes conductive.

[0434] First, switch DSW1 becomes non-conductive, and then switch SW1 becomes conductive. At this point, a high potential (V) is applied to the gates of transistors M1 and M2. Ｈ When ) is supplied, the potential of node ND is VSS and the potential of node N1 is V Ｍ Therefore, the source-drain voltage of transistor M2 (V ｄｓ ) is V Ｍ Therefore, the voltage VSS is generated in transistor M2 the moment switch SW1 becomes conductive.ｄｓ Current begins to flow when the current is relatively small (at least smaller than VDD-VSS). Therefore, compared to the operation of the conventional semiconductor device described above (Figure 21D), hot carriers are less likely to be generated in transistor M2.

[0435] Also, at this time, the source-drain voltage of transistor M1 (V ｄｓ ) is VDD-V Ｍ Therefore, for transistor M1, just like transistor M2, the moment switch SW1 becomes conductive, V ｄｓ Current will begin to flow even when the current is relatively small. Therefore, the generation of hot carriers can also be suppressed in transistor M1.

[0436] Current flows through switch SW1 until the potential of node ND rises to VDD, after which it enters a steady state. At this time, the potentials of nodes N1 and DN1 also reach VDD. This state is the fourth state shown in Figure 23A.

[0437] Next, Figure 23B will be used to explain the transition period from the fourth state to the fifth state. Figure 23B shows the state immediately after the switch from the fourth state to the fifth state, that is, immediately after the switch DSW2 becomes conductive.

[0438] As mentioned above, in the fifth state, switch DSW2 is in a conducting state, and switches SW1, SW2, and DSW1 are in a non-conducting state. Therefore, at switch DSW2, the potential of node DN2 between transistors DM3 and DM4 is the potential between VDD and VSS (higher than VSS and lower than VDD), which is V Ｍ This is the result.

[0439] Also, the potential of node DN2 of switch DSW2 is V Ｍ As a result, the potential of node N2 of switch SW2 connected to it is also V Ｍ This is the result.

[0440] Next, using Figure 24A, we will explain the transition period when switching from the fifth state to the sixth state. Figure 24A shows the state immediately after switching from the fifth state to the sixth state, that is, immediately after switch SW2 becomes conductive.

[0441] First, switch DSW2 becomes non-conductive, and then switch SW2 becomes conductive. At this point, a high potential (V) is applied to the gates of transistors M3 and M4. Ｈ When ) is supplied, the potential at node ND is VDD and the potential at node N2 is V Ｍ Therefore, the source-drain voltage of transistor M3 (V ｄｓ ) is VDD-V Ｍ Therefore, the moment switch SW2 becomes conductive, transistor M3 receives V ｄｓ Current begins to flow when the current is relatively small (at least smaller than VDD-VSS). Therefore, compared to the operation of the conventional semiconductor device described above (Figure 21B), hot carriers are less likely to be generated in transistor M3.

[0442] Also at this time, the source-drain voltage of transistor M4 (V ｄｓ ) is V Ｍ Therefore, for transistor M4, just like transistor M3, the moment switch SW2 becomes conductive, V ｄｓ Current will begin to flow even when the current is relatively low. Therefore, the generation of hot carriers can also be suppressed in transistor M4.

[0443] Current flows through switch SW2 until the potential of node ND drops to VSS, after which it enters a steady state. At this time, the potentials of nodes N2 and DN2 also reach VSS. This state is the sixth state shown in Figure 24B.

[0444] As described above, in one aspect of the present invention, a semiconductor device has a configuration in which switch DSW1 and switch DSW2 are added to a conventional semiconductor device, thereby the source-drain voltage (V) of each transistor in switch SW1 and switch SW2 ｄｓ) can be made smaller than VDD-VSS. Therefore, each transistor can have V ｄｓ Current can begin to flow even when the current is relatively low. In other words, the generation of hot carriers can be suppressed, and the transistor can be prevented from degrading due to hot carriers.

[0445] Next, we will describe an example of a semiconductor device in which each switch has three or more transistors connected in series. Figures 25 to 30 illustrate an example of operation of a semiconductor device in which each switch (switch SW1, switch SW2, switch DSW1, and switch DSW2) has four transistors connected in series.

[0446] For example, in a semiconductor device having the circuit configuration shown in Figures 25 to 30, the semiconductor device 100C or semiconductor device 100D described in Embodiment 1 can be applied to switch SW1 and switch DSW1, and switch SW2 and switch DSW2, respectively.

[0447] As the number of transistors connected in series in a switch increases, the overall channel resistance of the transistors increases, thus reducing the leakage current. Furthermore, the breakdown voltage (specifically, the breakdown voltage between the drain of the first transistor in the switch and the source of the last transistor) can be increased. On the other hand, as the number of transistors connected in series increases, the on-current also decreases; therefore, it is preferable to set the number of transistors connected in series according to the circuit being applied.

[0448] The following description will mainly focus on aspects that differ from the configuration and operation examples of a semiconductor device according to one embodiment of the present invention shown in Figures 20 and 22A to 24B. For other aspects, please refer to the above description relating to the semiconductor device.

[0449] The semiconductor device shown in Figures 25 to 30 as an example of operation has a switch SW1 that has transistors M5 and M6 in addition to transistors M1 and M2. Furthermore, a switch SW2 has transistors M7 and M8 in addition to transistors M3 and M4. Also, a switch DSW1 has transistors DM5 and DM6 in addition to transistors DM1 and DM2. And a switch DSW2 has transistors DM7 and DM8 in addition to transistors DM3 and DM4.

[0450] In switch SW1, the drain of transistor M5 is connected to the source of transistor M2 at node N3. The source of transistor M5 is connected to the drain of transistor M6 at node N4.

[0451] In switch SW2, the source of transistor M4 is connected to the drain of transistor M7 at node N5. The source of transistor M7 is connected to the drain of transistor M8 at node N6. The source of transistor M8 is connected to a low-voltage power line, and a low voltage (VSS) is supplied to this source.

[0452] In switch DSW1, the drain of transistor DM5 is connected to the source of transistor DM2 at node DN3. The source of transistor DM5 is connected to the drain of transistor DM6 at node DN4. The source of transistor DM6 is connected to a low-voltage power line, to which a low voltage (VSS) is supplied.

[0453] In switch DSW2, the source of transistor DM4 is connected to the drain of transistor DM7 at node DN5. The source of transistor DM7 is connected to the drain of transistor DM8 at node DN6. The source of transistor DM8 is connected to a low-voltage power line, to which a low voltage (VSS) is supplied.

[0454] Below, an example of the operation of a semiconductor device having the above configuration will be explained with reference to Figures 25 to 30.

[0455] Figure 25 shows the high potential (V) at which the gates of transistors DM1, DM2, DM5, and DM6 turn ON. Ｈ A low potential (V) is supplied to the gates of transistors M1, M2, M5, and M6, the gates of transistors M3, M4, M7, and M8, and the gates of transistors DM3, DM4, DM7, and DM8, causing each transistor to be in an off state. Ｌ This indicates that a power supply is being provided. That is, switch DSW1 is in a conductive state, and switches SW1, SW2, and DSW2 are in a non-conductive state.

[0456] The third to sixth states used below are the same as the third to sixth states described in Figures 22A to 24B. Specifically, the steady state in which switch DSW1 is conducting and switches SW1, SW2, and DSW2 are not conducting will be described as the third state. The steady state in which switch SW1 is conducting and switches SW2, DSW1, and DSW2 are not conducting will be described as the fourth state. The steady state in which switch DSW2 is conducting and switches SW1, SW2, and DSW1 are not conducting will be described as the fifth state. The steady state in which switch SW2 is conducting and switches SW1, DSW1, and DSW2 are not conducting will be described as the sixth state.

[0457] As mentioned above, in the third state, switch DSW1 is in a conducting state, and switches SW1, SW2, and DSW2 are in a non-conducting state. Therefore, in switch DSW1, potential division occurs between VDD and VSS. Then, each node (node ​​DN1, node DN3, and node DN4) between transistors DM1, DM2, DM5, and DM6 is supplied with a potential corresponding to the magnitude of the resistance of each transistor when it is ON. In Figure 25, the potential supplied to node DN1 between transistors DM1 and DM2 is V Ｍ１ The potential supplied to node DN3 between transistors DM2 and DM5 is V Ｍ２ The potential supplied to node DN4 between transistors DM5 and DM6 is V Ｍ３ This is shown as follows: V Ｍ１ V is at a lower potential than VDD, Ｍ２ is V Ｍ１ It is at a lower potential than V Ｍ３ is V Ｍ２ The potential is lower than VSS. Ｍ３ It is a lower potential than VDD, V Ｍ１ , V Ｍ２ , V Ｍ３ , and VSS is VDD > V Ｍ１ >V Ｍ２ >V Ｍ３ >It has a VSS (Value-Solving System) relationship of magnitude.

[0458] Also, the potential of node DN1 of switch DSW1 is V Ｍ１ As a result, the potential of node N1 of switch SW1 connected to it also becomes V Ｍ１ Similarly, the potential of node DN3 of switch DSW1 is V Ｍ２ As a result, the potential of node N3 of switch SW1 connected to it also becomes V Ｍ２ Therefore, the potential of node DN4 of switch DSW1 is V Ｍ３ As a result, the potential of node N4 of switch SW1 connected to it also becomes V Ｍ３ This is the result.

[0459] In this case (the third state), the potential of node ND, the potential of node N2 between transistors M3 and M4 in switch SW2, the potential of node N5 between transistors M4 and M7 in switch SW2, the potential of node N6 between transistors M7 and M8 in switch SW2, the potential of node DN2 between transistors DM3 and DM4 in switch DSW2, the potential of node DN5 between transistors DM4 and DM7 in switch DSW2, and the potential of node DN6 between transistors DM7 and DM8 in switch DSW2 are all assumed to be VSS.

[0460] Next, we will explain the transition period from the third state to the fourth state using Figure 26. Figure 26 shows the state immediately after the switch from the third state to the fourth state, that is, immediately after switch SW1 becomes conductive.

[0461] First, switch DSW1 becomes non-conductive, and then switch SW1 becomes conductive. At this point, a high potential (V) is applied to the gates of transistors M1, M2, M5, and M6. Ｈ When ) is supplied, the potential of node ND is VSS and the potential of node N1 is V Ｍ１ Therefore, the potential at node N3 is V Ｍ２ Therefore, the potential at node N4 is V Ｍ３ Therefore, the source-drain voltages (V) of transistors M1, M2, M5, and M6 are... ｄｓ ) are, respectively, VDD-V Ｍ１ , V Ｍ１ -V Ｍ２ , V Ｍ２ -V Ｍ３ , V Ｍ３ Therefore, the voltage VSS is -VSS at the moment switch SW1 becomes conductive. ｄｓCurrent will begin to flow when the voltage is relatively small (at least smaller than VDD-VSS). Therefore, hot carriers are less likely to be generated in transistors M1, M2, M5, and M6.

[0462] Current flows through switch SW1 until the potential of node ND rises to VDD, after which it enters a steady state. At this time, the potentials of nodes N1, N3, N4, DN1, DN3, and DN4 also reach VDD. This state is the fourth state shown in Figure 27.

[0463] Next, we will explain the transition period from the fourth state to the fifth state using Figure 28. Figure 28 shows the state immediately after the switch from the fourth state to the fifth state, that is, immediately after the switch DSW2 becomes conductive.

[0464] As mentioned above, in the fifth state, switch DSW2 is in a conducting state, and switches SW1, SW2, and DSW1 are in a non-conducting state. Therefore, in switch DSW2, potential division occurs between VDD and VSS. Then, each node (node ​​DN2, node DN5, and node DN6) between transistors DM3, DM4, DM7, and DM8 is supplied with a potential corresponding to the magnitude of the resistance of each transistor when it is ON. In Figure 28, the potential supplied to node DN2 between transistors DM3 and DM4 is V Ｍ１ The potential supplied to node DN5 between transistors DM4 and DM7 is V Ｍ２ The potential supplied to node DN6 between transistors DM7 and DM8 is V Ｍ３ This is shown as such.

[0465] Also, the potential of node DN2 of switch DSW2 is V Ｍ１ As a result, the potential of node N2 of switch SW2 connected to it is also V Ｍ１ Similarly, the potential of node DN5 of switch DSW2 is V Ｍ２As a result, the potential of node N5 of switch SW2 connected to it also becomes V Ｍ２ Therefore, the potential of node DN6 of switch DSW2 is V Ｍ３ As a result, the potential of node N6 of switch SW2 connected to it also becomes V Ｍ３ This is the result.

[0466] Next, we will explain the transition period from the fifth state to the sixth state using Figure 29. Figure 29 shows the state immediately after the switch from the fifth state to the sixth state, that is, immediately after the switch SW2 becomes conductive.

[0467] First, switch DSW2 becomes non-conductive, and then switch SW2 becomes conductive. At this point, a high potential (V) is applied to the gates of transistors M3, M4, M7, and M8. Ｈ When ) is supplied, the potential at node ND is VDD and the potential at node N2 is V Ｍ１ Therefore, the potential at node N5 is V Ｍ２ Therefore, the potential at node N6 is V Ｍ３ Therefore, the source-drain voltages (V) of transistors M3, M4, M7, and M8 are... ｄｓ ) are, respectively, VDD-V Ｍ１ , V Ｍ１ -V Ｍ２ , V Ｍ２ -V Ｍ３ , V Ｍ３ Therefore, the voltage VSS is -VSS at the moment switch SW2 becomes conductive. ｄｓ Current will begin to flow when the voltage is relatively small (at least smaller than VDD-VSS). Therefore, hot carriers are less likely to be generated in transistors M3, M4, M7, and M8.

[0468] Current flows through switch SW2 until the potential of node ND drops to VSS, after which it enters a steady state. At this time, the potentials of nodes N2, N5, N6, DN2, DN5, and DN6 also reach VSS. This state is the sixth state shown in Figure 30.

[0469] As described above, in one aspect of the present invention, a semiconductor device has a configuration in which switch DSW1 and switch DSW2 are added to a conventional semiconductor device, thereby the source-drain voltage (V) of each transistor in switch SW1 and switch SW2 ｄｓ ) can be made smaller than VDD-VSS. Therefore, each transistor can have V ｄｓ Current can begin to flow even when the current is relatively low. In other words, the generation of hot carriers can be suppressed, and the transistor can be prevented from degrading due to hot carriers.

[0470] Furthermore, by increasing the number of transistors connected in series in each switch from two to three or more, the potential division between the transistors in each switch is subdivided, thus reducing the source-drain voltage (V) when each transistor is ON. ｄｓ This can be made even smaller. Therefore, it can be said that the effect of suppressing the degradation of the transistor's hot carrier is higher when the number of transistors connected in series in each switch is 3 or more than when it is 2.

[0471] Figure 31 is a circuit diagram illustrating an example in which a semiconductor device according to one embodiment of the present invention is used in a shift register circuit. Here, an example is shown in which the shift register circuit SR uses the semiconductor device whose operation example was explained in Figures 25 to 30.

[0472] The shift register circuit SR has switch SW1a as the first switch SW1, and switch SW1b as the second switch SW1. It also has switch SW2a as the first switch SW2, and switch SW2b as the second switch SW2. Furthermore, it has switch DSW1a as the first switch DSW1, and switch DSW1b as the second switch DSW1. Furthermore, it has switch DSW2a as the first switch DSW2, and switch DSW2b as the second switch DSW2. Switch SW1a is connected to switch SW2a at node NC. Switch SW1b is connected to switch SW2b at node NB. Details of the nodes will be described later.

[0473] Furthermore, the shift register circuit SR has switches SW3, SW4, and SW5, each having multiple transistors connected in series. The shift register circuit SR also has two capacitive elements (capacitive element Ca and capacitive element Cb).

[0474] In Figure 31, an example is shown in which four transistors are connected in series to switches SW3 through SW5, similar to the case with switch SW1a, etc. However, the example is not limited to this configuration; one or more transistors are sufficient. By connecting multiple transistors in series, leakage current can be reduced, and circuit operation can be stabilized.

[0475] In the following explanation, for simplicity, each switch will be considered as a single transistor, and the gates of the multiple transistors connected in series in each switch will be referred to as the switch gates. Furthermore, of the multiple transistors connected in series in each switch, the drain of the transistor at the end to which a high potential is supplied will be referred to as the switch drain, and the source of the transistor at the end to which a low potential is supplied will be referred to as the switch source.

[0476] The source of switch SW1a is connected to the drain of switch SW2a and either the source or drain of switch SW3. The gate of switch SW2a is connected to one electrode of the capacitive element Ca, the source of switch SW1b, the drain of switch SW2b, and the gate of switch SW5. The other end of the source or drain of switch SW3 is connected to the gate of switch SW4 and one electrode of the capacitive element Cb. The other end of the source or drain of switch SW4 is connected to the other electrode of the capacitive element Cb and the drain of switch SW5.

[0477] High-potential power lines are connected to the drains of switch SW1a, switch DSW1a, switch DSW2a, switch SW1b, switch DSW1b, switch DSW2b, and the gate of switch SW3. Low-potential power lines are connected to the sources of switch DSW1a, switch SW2a, switch DSW2a, switch DSW1b, switch SW2b, switch DSW2b, switch SW5, and the other electrode of the capacitive element Ca.

[0478] The gates of switch SW1a and SW2b function as signal inputs LIN. The gate of switch SW1b functions as a signal input RIN. The source or drain of switch SW4 functions as a clock signal input CLK. One of the source or drains of switch SW4, the other electrode of the capacitive element Cb, and the drain of switch SW5 function as a signal output SOUT.

[0479] Furthermore, the gates of switch DSW1a and switch DSW2b function as signal input section A. The gate of switch DSW1b functions as signal input section B. The gate of switch DSW2a functions as signal input section C. Here, signal input section A is a signal input section that, when operating a sequential circuit in which multiple shift register circuits SR are connected, inputs signals to the gates of switch SW1a and switch DSW2b before signal input section LIN inputs signals to the gates of switch SW1a and switch SW2b. Furthermore, signal input section B is a signal input section that, when operating the sequential circuit, inputs signals to the gate of switch SW1b before signal input section RIN inputs signals to the gate of switch SW1b. Furthermore, signal input section C is a signal input section that, when operating the sequential circuit, inputs signals to the gate of switch DSW2a before signal input section RIN inputs signals to the gate of switch SW1b. Further details regarding the configuration and operation of the sequential circuit will be explained in Figures 32A to 32C.

[0480] Here, node NA is defined as the node where the other electrode of the source or drain of switch SW3, the gate of switch SW4, and one electrode of the capacitive element Cb are connected. Node NB is defined as the node where the gate of switch SW2a, one electrode of the capacitive element Ca, the source of switch SW1b, the drain of switch SW2b, and the gate of switch SW5 are connected. Node NC is defined as the node where the source of switch SW1a, the drain of switch SW2a, and one of the source or drain of switch SW3 are connected.

[0481] As shown in Figure 32A, the shift register circuit SR can be configured as a sequential circuit by connecting n stages (where n is an integer of 2 or more) in cascade. The signal input LIN of the first stage shift register circuit SR receives a start pulse signal (SSP), and its signal output SOUT[1] is connected to the signal input LIN of the second stage shift register circuit. The signal output SOUT[2] of the second stage shift register circuit SR is connected to the signal input RIN of the first stage shift register circuit SR. The signal input RIN of the nth stage shift register circuit SR receives an end pulse (SEP). A dummy shift register circuit SR that generates the SEP can also be provided.

[0482] This configuration allows for sequential output of pulse signals to signal output units SOUT[1] through SOUT[n], making it usable as a gate driver for selecting pixels in a display device or as a drive circuit for a touch sensor. Furthermore, by combining it with a latch circuit, amplifier circuit, etc., it can also be used as a source driver for supplying data to pixels.

[0483] Next, we will explain the operation when the sequential circuit shown in Figure 32A is applied to a gate driver. Figure 32B is a timing chart illustrating the operation of the shift register circuit SR connected to the k-th row gate line (where k is an odd number less than or equal to n-1). Figure 32C is a timing chart illustrating the operation of the shift register circuit SR connected to the k+1-th row gate line.

[0484] As shown in Figure 32A, the clock signals input to odd-numbered and even-numbered stages are different. However, the basic operation is almost the same, and here we will mainly explain the operation of the shift register circuit SR connected to the gate line of the kth row using Figure 32B.

[0485] Here, the signal input to the signal input unit LIN is referred to as the LIN signal, the signal input to the clock signal input unit CLK is referred to as the CLK signal, the signal input to the signal input unit RIN is referred to as the RIN signal, the signal output from the signal output unit SOUT is referred to as the SOUT signal, the signal input to the signal input unit A is referred to as the A signal, the signal input to the signal input unit B is referred to as the B signal, and the signal input to the signal input unit C is referred to as the C signal.

[0486] During period T1, a high-level A signal is input to the gates of switch DSW1a and switch DSW2b, causing potential division between the transistors of switch DSW1a and switch DSW2b. Consequently, the divided potential is also supplied to the nodes between the transistors of switch SW1a connected to the nodes between the transistors of switch DSW1a, and to the nodes between the transistors of switch SW2b connected to the nodes between the transistors of switch DSW2b.

[0487] Period T2 is a period established to ensure that the operations in period T1 (described above) and the operations in period T3 (described later) do not overlap. If the operations in period T1 and period T3 do not overlap, period T2 can be omitted.

[0488] During period T3, a high-level LIN signal is input to the gate of switch SW1a from SSP or the (n-1)th gate line, causing switch SW1a to conduct and the potential of node NC to become a high-level potential (VDD), and node NA to be precharged. At this time, the nodes between the transistors of switch SW1a are already supplied with the potential divided as described above, so the source-drain voltage (V) of each transistor is reduced. ｄｓ Switch SW1a can be operated when the voltage is relatively low.

[0489] Furthermore, a high-level LIN signal is input to the gate of switch SW2b from SSP or the (n-1)th gate line, causing switch SW2b to conduct and node NB to discharge to a low-level potential. At this time, the nodes between the transistors of switch SW2b are already supplied with the potential divided as described above, so the source-drain voltage (V) of each transistor is reduced. ｄｓ Switch SW2b can be operated when the voltage is relatively low.

[0490] Furthermore, due to the pre-charging of node NA, switch SW4 is in a conducting state, and due to the discharge of node NB, switch SW5 is in a non-conducting state. Since the CLK signal is at a low potential (VSS), the SOUT signal is also at a low potential. In addition, the capacitive element Cb is charged with a charge corresponding to the potential difference between VDD and VSS.

[0491] Furthermore, during period T3, a high-level B signal is input to the gate of switch DSW1b, and potential division occurs between the transistors of switch DSW1b. Consequently, the divided potential is also supplied to the nodes between the transistors of switch DSW1b and the nodes between the transistors of the switches SW1b connected to each of them.

[0492] Similarly, during period T3, a high-level potential C signal is input to the gate of switch DSW2a, and potential division occurs between the transistors of switch DSW2a. Consequently, the divided potential is also supplied to the nodes between the transistors of switch SW2a that are connected to the nodes between the transistors of switch DSW2a.

[0493] During period T4, when the CLK signal switches to a high-level potential (VDD), switch SW4 becomes conductive, switch SW5 becomes non-conductive, and the SOUT signal becomes high-level.

[0494] Furthermore, as the k-th gate line is charged, the potential of node NA rises due to capacitive coupling with the capacitive element Cb, increasing the gate voltage of switch SW4 and compensating for the charging operation of the k-th gate line. At this time, since there is a potential difference of VDD-VSS across the capacitive element Cb, node NA rises to 2 × (VDD-VSS).

[0495] Here, the source potential of switch SW3 becomes higher than the gate potential, resulting in a non-conducting state. Therefore, the potential of node NC does not become higher than VDD. Consequently, the source-drain voltage (V) of the transistor connected to node NC of switch SW2a is... ｄｓ This allows for the suppression of stress on the transistor without unnecessarily increasing the stress on it.

[0496] At this time, the SOUT signal with a high potential is input as the LIN signal to the next stage shift register circuit SR, and in the next stage shift register circuit SR, node NA is pre-charged and node NB is discharged.

[0497] During period T5, the CLK signal switches to a low potential. Also, the high-level SOUT signal from the next stage shift register circuit SR is input to the gate of switch SW1b as the RIN signal, causing switch SW1b to conduct and node NB to be charged to a high potential. At this time, the nodes between the transistors of switch SW1b are already supplied with the potential divided as described above, so the source-drain voltage (V) of each transistor is reduced. ｄｓ Switch SW1b can be operated when the voltage is relatively low.

[0498] Furthermore, when switch SW2a conducts, node NC becomes low-level. At this time, the nodes between the transistors of switch SW2a are already supplied with the potential divided as described above, so the source-drain voltage (V) of each transistor is reduced. ｄｓ Switch SW2a can be operated when the voltage is relatively low.

[0499] When node NC reaches a low potential, switch SW3 conducts, node NA discharges to a low potential, and switch SW4 becomes non-conductive. Switch SW5 also becomes conductive, and the SOUT signal reaches a low potential. In addition, the capacitive element Ca is charged with a charge corresponding to the potential difference between VDD and VSS.

[0500] The above operation completes the operation of the shift register circuit SR connected to the gate line of the kth row. From then on, until the operation is performed again in the next frame, the conduction state of switch SW5 is maintained by the potential difference held in the capacitive element Ca, and the SOUT signal maintains a low potential.

[0501] The above describes a shift register circuit SR using a semiconductor device according to one aspect of the present invention. In the above example of the shift register circuit SR, both switches SW1 and DSW1, and switches SW2 and DSW2 of the semiconductor device are applied, but it is also possible to apply only one of them. For example, it is possible to apply only switches SW1a and DSW1a, and apply only switches SW2a, SW1b, and SW2b to the locations where switches SW2a and DSW2a, SW1b and DSW1b, and SW2b and DSW2b are applied, respectively. By reducing the number of switches applied in the shift register circuit SR, the area occupied by the shift register circuit SR on the substrate surface can be reduced, and the bezel of the display device can be made narrower.

[0502] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0503] (Embodiment 4) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 33A to 35F.

[0504] The electronic device of this embodiment has a display device according to one aspect of the present invention in its display unit. The display device according to one aspect of the present invention is easily made high-definition and high-resolution. Therefore, it can be used in the display units of various electronic devices.

[0505] Examples of electronic devices include television sets, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0506] In particular, a display device according to one aspect of the present invention can be used suitably in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as head-mounted displays for VR (Virtual Reality), glasses-type devices for AR (Augmented Reality), and devices for MR (Mixed Reality).

[0507] A display device according to one aspect of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display device according to one aspect of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display device having either high resolution or high detail, or both, it becomes possible to further enhance the sense of presence and depth. Furthermore, there are no particular limitations on the aspect ratio of the display device according to one embodiment of the present invention. For example, the display device can support various aspect ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0508] The electronic device of this embodiment may have sensors (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0509] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0510] Figures 33A to 33D illustrate an example of a wearable device that can be worn on the head. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, or a function to display MR content. By having an electronic device that has the function to display at least one of the following content types, such as AR, VR, or MR, it is possible to enhance the user's sense of immersion.

[0511] The electronic device 700A shown in Figure 33A and the electronic device 700B shown in Figure 33B each include a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0512] A display device according to one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying extremely high resolution can be created.

[0513] Electronic devices 700A and 700B can project an image displayed on the display panel 751 onto the display area 756 of the optical element 753. Because the optical element 753 is translucent, the user can see the image displayed on the display area superimposed on the transmitted image visible through the optical element 753. Therefore, electronic devices 700A and 700B are electronic devices capable of AR display.

[0514] Electronic devices 700A and 700B may each be equipped with a camera capable of capturing images of the area in front of them as an imaging unit. Furthermore, electronic devices 700A and 700B may each be equipped with an acceleration sensor such as a gyro sensor to detect the orientation of the user's head and display an image corresponding to that orientation in the display area 756.

[0515] The communications unit has a wireless communication device, which can supply video signals and the like. Alternatively, instead of the wireless communication device, or in addition to the wireless communication device, it may be equipped with a connector to which a cable supplying video signals and power potential can be connected.

[0516] Electronic devices 700A and 700B are each equipped with a battery (not shown) which can be charged wirelessly, wired, or both.

[0517] The housing 721 may be equipped with a touch sensor module. The touch sensor module has the function of detecting when the outer surface of the housing 721 is touched. The touch sensor module can detect the user's tap or slide operations and perform various processes. For example, a tap operation can be used to pause or resume the video, and a slide operation can be used to fast forward or rewind. Furthermore, by providing a touch sensor module in each of the two housings 721, the range of operations can be expanded.

[0518] Various types of touch sensors can be applied to the touch sensor module. For example, various methods such as capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical sensors can be used. In particular, it is preferable to apply a capacitive or optical sensor to the touch sensor module.

[0519] When using an optical touch sensor, a photoelectric conversion element can be used as the light-receiving element. The active layer of the photoelectric conversion element can be made of either an inorganic semiconductor or an organic semiconductor, or both.

[0520] The electronic device 800A shown in Figure 33C and the electronic device 800B shown in Figure 33D each include a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0521] A display device according to one embodiment of the present invention can be applied to the display unit 820. Therefore, an electronic device capable of displaying extremely high resolution can be created. This allows the user to experience a high level of immersion.

[0522] The display unit 820 is located inside the housing 821 in a position where it can be viewed through the lens 832. Furthermore, by displaying different images on a pair of display units 820, a three-dimensional display using parallax can also be performed.

[0523] Electronic devices 800A and 800B can each be described as electronic devices for VR. A user wearing electronic device 800A or electronic device 800B can view the image displayed on the display unit 820 through the lens 832.

[0524] It is preferable that electronic devices 800A and 800B each have a mechanism that allows adjustment of the left and right positions of the lens 832 and the display unit 820 so that they are in the optimal position according to the user's eye position. It is also preferable that they have a mechanism that adjusts the focus by changing the distance between the lens 832 and the display unit 820.

[0525] The attachment portion 823 allows the user to attach the electronic device 800A or 800B to their head. While the attachment portion 823 is exemplified in Figure 33C and other figures as resembling the temples of eyeglasses, it is not limited to this. The attachment portion 823 only needs to be wearable by the user; for example, it may be helmet-shaped or band-shaped.

[0526] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras may be provided to accommodate multiple angles of view, such as telephoto and wide-angle.

[0527] Although an example with an imaging unit 825 is shown here, any distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 825 is one form of a detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be acquired, enabling more accurate gesture control.

[0528] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, housing 821, and mounting unit 823. This eliminates the need for separate audio equipment such as headphones, earphones, or speakers, allowing users to enjoy video and audio simply by wearing the electronic device 800A.

[0529] Electronic devices 800A and 800B may each have input terminals. Cables can be connected to the input terminals to supply video signals from video output devices, etc., and power for charging batteries provided in the electronic devices.

[0530] An electronic device according to one aspect of the present invention may have a function for wireless communication with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (for example, voice data) from the electronic device through its wireless communication function. For example, the electronic device 700A shown in Figure 33A has a function for transmitting information to the earphone 750 through its wireless communication function. Also, for example, the electronic device 800A shown in Figure 33C has a function for transmitting information to the earphone 750 through its wireless communication function.

[0531] The electronic device may have an earphone section. The electronic device 700B shown in Figure 33B has an earphone section 727. For example, the earphone section 727 and the control unit can be connected to each other by a wire. Part of the wiring connecting the earphone section 727 and the control unit may be located inside the housing 721 or the mounting section 723.

[0532] Similarly, the electronic device 800B shown in Figure 33D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be connected to each other by a wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be located inside the housing 821 or the mounting unit 823. Also, the earphone unit 827 and the mounting unit 823 may have magnets. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it facilitates storage.

[0533] Furthermore, the electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have an audio input terminal and / or an audio input mechanism. For example, a sound-collecting device such as a microphone can be used as the audio input mechanism. By having an audio input mechanism, the electronic device may be given the function of a so-called headset.

[0534] Thus, as one embodiment of the present invention, both eyeglass-type (electronic device 700A, electronic device 700B, etc.) and goggle-type (electronic device 800A, electronic device 800B, etc.) are preferred as electronic devices.

[0535] An electronic device according to one aspect of the present invention can transmit information to earphones by wire or wireless means.

[0536] The electronic device 6500 shown in Figure 34A is a portable information terminal that can be used as a smartphone.

[0537] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display unit 6502 has a touch panel function.

[0538] A display device according to one embodiment of the present invention can be applied to the display unit 6502.

[0539] Figure 34B is a schematic cross-sectional view of the housing 6501 including the end on the microphone 6506 side.

[0540] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0541] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0542] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and the FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on the printed circuit board 6517.

[0543] A flexible display according to one embodiment of the present invention can be applied to the display panel 6511. This makes it possible to realize an extremely lightweight electronic device. Furthermore, because the display panel 6511 is extremely thin, it is possible to incorporate a large-capacity battery 6518 while keeping the thickness of the electronic device low. In addition, by folding back a part of the display panel 6511 and placing the connection part with the FPC 6515 on the back side of the display unit 6502, an electronic device with a narrow bezel can be realized.

[0544] Figure 34C shows an example of a television system. The television system 7100 has a display unit 7000 incorporated into a housing 7101. Here, the housing 7101 is shown to be supported by a stand 7103.

[0545] A display device according to one embodiment of the present invention can be applied to the display unit 7000.

[0546] The television device 7100 shown in Figure 34C can be operated using the operation switches on the housing 7101 and a separate remote control unit 7111. Alternatively, the display unit 7000 may be equipped with a touch sensor, and the television device 7100 can be operated by touching the display unit 7000 with a finger or the like. The remote control unit 7111 may have a display unit that displays information output from the remote control unit 7111. Channels and volume can be controlled and the image displayed on the display unit 7000 can be controlled using the operation keys or touch panel on the remote control unit 7111.

[0547] The television system 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0548] Figure 34D shows an example of a notebook personal computer. The notebook personal computer 7200 has a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7000 is incorporated into the casing 7211.

[0549] A display device according to one embodiment of the present invention can be applied to the display unit 7000.

[0550] Figures 34E and 34F show examples of digital signage.

[0551] The digital signage 7300 shown in Figure 34E includes a housing 7301, a display unit 7000, a speaker 7303, etc. Furthermore, it may have LED (Light Emitting Diode) lamps, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0552] Figure 34F shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7000 that is provided along the curved surface of the column 7401.

[0553] In Figures 34E and 34F, a display device according to one embodiment of the present invention can be applied to the display unit 7000.

[0554] The larger the display area 7000, the more information can be provided at once. Furthermore, a larger display area 7000 is more eye-catching, which can, for example, enhance the effectiveness of advertising.

[0555] Applying a touch panel to the display unit 7000 is preferable because it not only allows images or videos to be displayed on the display unit 7000, but also enables intuitive operation by the user. Furthermore, when used for purposes such as providing route information or traffic information, intuitive operation can enhance usability.

[0556] As shown in Figures 34E and 34F, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 or information terminal 7411 such as a smartphone owned by the user. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or information terminal 7411. In addition, the display on the display unit 7000 can be switched by operating the information terminal 7311 or information terminal 7411.

[0557] The digital signage 7300 or digital signage 7400 can also be used to run games using the screen of the information terminal 7311 or information terminal 7411 as the control device (controller). This allows an unspecified number of users to participate in and enjoy the game simultaneously.

[0558] Furthermore, a semiconductor device and display device according to one aspect of the present invention can be applied to the area around the driver's seat of a mobile vehicle.

[0559] Figure 35A is a diagram showing the area around the windshield inside the car's interior. Figure 35A shows display panels 9001a, 9001b, and 9001c mounted on the dashboard, as well as display panel 9001d mounted on the pillar.

[0560] Display panels 9001a to 9001c can provide various information by displaying navigation information, speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, and more. Furthermore, the display items and layout shown on the display panels can be changed as needed to suit the user's preferences, enhancing the design. Display panels 9001a to 9001c can also be used as lighting devices.

[0561] The display panel 9001d can compensate for the blind spot (view obstructed by the pillar) by displaying images from an imaging device installed on the vehicle body. In other words, by displaying images from an imaging device installed on the outside of the vehicle, blind spots can be compensated for, and safety can be enhanced. Furthermore, by displaying images that compensate for the parts that are not visible, safety checks can be performed more naturally and without discomfort. The display panel 9001d can also be used as a lighting device.

[0562] Figure 35B is a perspective view showing a wristwatch-type personal information terminal 9200. The personal information terminal 9200 can be used, for example, as a smartwatch (registered trademark). The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless communication headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals and be charged via a connection terminal 9006. Charging may be performed by wireless power supply.

[0563] The portable information terminal 9200 shown in Figure 35B includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switches), connection terminals 9006, sensors 9007 (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0564] Figure 35C is a perspective view showing a foldable portable information terminal 9201. The portable information terminal 9201 has a housing 9000a, a housing 9000b, a display unit 9001, and operation buttons 9056.

[0565] The housing 9000a and housing 9000b are joined by a hinge 9055, which allows them to be folded in half.

[0566] The display unit 9001 of the portable information terminal 9201 is supported by two housings (housing 9000a and housing 9000b) connected by a hinge 9055.

[0567] Figures 35D to 35F are perspective views showing a foldable portable information terminal 9202. Figure 35D shows the portable information terminal 9202 in an unfolded state, Figure 35F shows it in a folded state, and Figure 35E shows a perspective view of the state in between, transitioning from one of Figures 35D or 35F to the other. Thus, the portable information terminal 9202 can be folded into three sections.

[0568] The display unit 9001 of the portable information terminal 9202 is supported by three housings 9000 connected by a hinge 9055.

[0569] In Figures 35C to 35F, a display device according to one embodiment of the present invention can be applied to the display unit 9001. For example, the display unit 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.

[0570] The personal digital assistant 9201 and the personal digital assistant 9202 offer excellent portability when folded and superior readability due to their seamless, wide display area when unfolded.

[0571] Furthermore, by applying a semiconductor device according to one aspect of the present invention to one or more selected from electronic components, large computers, space equipment, data centers, and electronic devices, power consumption can be reduced. Therefore, as energy demand is expected to increase with the performance or integration of semiconductor devices, using a semiconductor device according to one aspect of the present invention can reduce carbon dioxide (CO2) emissions. ２It is also possible to reduce greenhouse gas emissions, such as those represented by [specific examples of greenhouse gas emissions]. Furthermore, because the semiconductor device according to one aspect of the present invention consumes little power, it is also effective as a measure against global warming.

[0572] This embodiment can be combined with other embodiments as appropriate.

[0573] 10A1_1: Transistor, 10A1_2: Transistor, 10A2_1: Transistor, 10A2_2: Transistor, 10B1_1: Transistor, 10B1_2: Transistor, 10B2_1: Transistor, 10B2_2: Transistor, 10C1_1: Transistor, 10C1_2: Transistor, 10C1_3: Transistor, 10C1_4: Transistor, 10C2_1: Transistor, 10C2_2: Transistor, 10C2_3: Transistor, 10C2_4: Transistor, 10D1_1: Transistor, 10D1_2: Transistor 10D1_3: Transistor, 10D1_4: Transistor, 10D2_1: Transistor, 10D2_2: Transistor, 10D2_3: Transistor, 10D2_4: Transistor, 100A: Semiconductor device, 100A1: Switch, 100A2: Switch, 100B: Semiconductor device, 100B1: Switch, 100B2: Switch, 100C: Semiconductor device, 100C1: Switch, 100C2: Switch, 100D: Semiconductor device, 100D1: Switch, 100D2: Switch, 102: Substrate, 104_1: Conductive layer, 104_2: Conductive layer, 106: Insulating layer, 108_1: Semiconductor layer, 108_2: Semiconductor layer, 109: Insulating layer, 110: Insulating layer, 110a: Insulating layer, 110af: Insulating film, 110b: Insulating layer, 110bf: Insulating film, 110c: Insulating layer, 110cf: Insulating film, 112a1_1: Conductive layer, 112a1_2: Conductive layer, 112a12: Conductive layer, 112a2_1: Conductive layer, 112a2_2: Conductive layer, 112a23: Conductive layer, 112a34: Conductive layer, 112b1_1: Conductive layer, 112b1_2: Conductive layer, 112b12: Conductive layer, 112b12f: Conductive film, 112b2_1: Conductive layer, 112b2_2: Conductive Layer, 112b23: conductive layer, 112b34: conductive layer, 700A: electronic device, 700B: electronic device, 721: housing, 723: mounting part, 727: earphone part, 750: earphone, 751: display panel, 753: optical component, 756: display area, 757: frame, 758: nose pad, 800A: electronic device, 800B: electronic device, 820: display part, 821: housing, 822: communication part, 823: mounting part, 824: control unit, 825: imaging unit, 827: earphone part, 832: lens, 6500: electronic device, 6501: housing, 6502: display part, 6503: power button,6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective component, 6511: Display panel, 6512: Optical component, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7000: Display unit, 7100: Television equipment, 7101: Enclosure, 7103: Stand, 7111: Remote control unit, 7200: Notebook personal computer, 7211: Enclosure, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital Digital signage, 7301: enclosure, 7303: speaker, 7311: information terminal, 7400: digital signage, 7401: column, 7411: information terminal, 9000: enclosure, 9000a: enclosure, 9000b: enclosure, 9001: display unit, 9001a: display panel, 9001b: display panel, 9001c: display panel, 9001d: display panel, 9003: speaker, 9005: operation key, 9006: connection terminal, 9007: sensor, 9008: microphone, 9055: hinge, 9056: operation button, 9200: portable information terminal, 9201: portable information terminal, 9202: portable information terminal,

Claims

It comprises a first conductive layer to a seventh conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer and a second insulating layer. The first to fourth conductive layers are each located in different regions on the same plane. The first insulating layer is located in an island-like manner on the first to fourth conductive layers such that it has regions that overlap with each of the first to fourth conductive layers. The fifth conductive layer is located on the first insulating layer, The first semiconductor layer is in contact with the upper surface of the first conductive layer, the upper surface of the second conductive layer, a part of the side surface of the first insulating layer, a part of the side surface of the fifth conductive layer, and a part of the upper surface of the fifth conductive layer. The second semiconductor layer is in contact with the upper surface of the third conductive layer, the upper surface of the fourth conductive layer, the other part of the side surface of the first insulating layer, the other part of the side surface of the fifth conductive layer, and the other part of the upper surface of the fifth conductive layer. The second insulating layer is located on the first semiconductor layer and the second semiconductor layer. The sixth conductive layer is located on the second insulating layer such that it has a region that overlaps with the first semiconductor layer. The seventh conductive layer is located on the second insulating layer such that it has a region that overlaps with the second semiconductor layer. Semiconductor equipment. 　 In claim 1, The first semiconductor layer and the second semiconductor layer are each a metal oxide containing indium. The first insulating layer comprises a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer. The third insulating layer and the fifth insulating layer each contain silicon and nitrogen, The fourth insulating layer comprises silicon and oxygen. Semiconductor equipment. 　 In claim 1 or claim 2, A sixth insulating layer is located beneath the first to fourth conductive layers. The upper surface of the sixth insulating layer is in contact with the first to fourth conductive layers. The sixth insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. Semiconductor equipment. 　 It comprises a first conductive layer to a seventh conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer to a fifth insulating layer. The first insulating layer is located in an island-like manner on a first region of the first conductive layer. The second insulating layer is located in an island-like manner on the second region of the first conductive layer. The third insulating layer is located in an island-like manner on the third region of the first conductive layer. The fourth insulating layer is located in an island-like manner on the fourth region of the first conductive layer. The second conductive layer is located on the first insulating layer, The third conductive layer is located on the second insulating layer, The fourth conductive layer is located on the third insulating layer, The fifth conductive layer is located on the fourth insulating layer, The first semiconductor layer is in contact with a part of the upper surface of the first conductive layer, the side surface of the first insulating layer, the upper and side surfaces of the second conductive layer, the side surfaces of the second insulating layer, and the upper and side surfaces of the third conductive layer. The second semiconductor layer is in contact with another portion of the upper surface of the first conductive layer, the side surface of the third insulating layer, the upper and side surfaces of the fourth conductive layer, the side surfaces of the fourth insulating layer, and the upper and side surfaces of the fifth conductive layer. The fifth insulating layer is located on the first semiconductor layer and the second semiconductor layer. The sixth conductive layer is located on the fifth insulating layer such that it has a region that overlaps with the first semiconductor layer. The seventh conductive layer is located on the fifth insulating layer such that it has a region that overlaps with the second semiconductor layer. Semiconductor equipment. 　 In claim 4, The first semiconductor layer and the second semiconductor layer are each a metal oxide containing indium. The first insulating layer comprises a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer. The second insulating layer comprises a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer. The third insulating layer comprises a twelfth insulating layer, a thirteenth insulating layer on the twelfth insulating layer, and a fourteenth insulating layer on the thirteenth insulating layer. The fourth insulating layer comprises a 15th insulating layer, a 16th insulating layer on the 15th insulating layer, and a 17th insulating layer on the 16th insulating layer. The sixth insulating layer, the eighth insulating layer, the ninth insulating layer, the eleventh insulating layer, the twelfth insulating layer, the fourteenth insulating layer, the fifteenth insulating layer, and the seventeenth insulating layer each contain silicon and nitrogen. The seventh insulating layer, the tenth insulating layer, the thirteenth insulating layer, and the sixteenth insulating layer each contain silicon and oxygen. Semiconductor equipment. 　 In claim 4 or claim 5, An 18th insulating layer is located below the first to fourth insulating layers. The upper surface of the 18th insulating layer is in contact with the first to fourth insulating layers. The 18th insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. Semiconductor equipment. 　 It comprises a first conductive layer to a ninth conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer to a third insulating layer. The first to fifth conductive layers are each located in different regions on the same plane. The first insulating layer is located on the first conductive layer, the third conductive layer, and the first region such that it has a region that overlaps with the first region of the first conductive layer, the third conductive layer, and the fifth conductive layer, respectively. The second insulating layer is located on the second conductive layer, the fourth conductive layer, and the second region, respectively, such that it has a region that overlaps with the second region of the second conductive layer, the fourth conductive layer, and the fifth conductive layer. The sixth conductive layer is located on the first insulating layer, The seventh conductive layer is located on the second insulating layer, The first semiconductor layer is in contact with the upper surface of the first conductive layer, the upper surface of the second conductive layer, a part of the upper surface of the fifth conductive layer, a part of the side surface of the first insulating layer, a part of the side surface of the second insulating layer, a part of the side surface of the sixth conductive layer, a part of the upper surface of the sixth conductive layer, a part of the side surface of the seventh conductive layer, and a part of the upper surface of the seventh conductive layer. The second semiconductor layer is in contact with the upper surface of the third conductive layer, the upper surface of the fourth conductive layer, another part of the upper surface of the fifth conductive layer, another part of the side surface of the first insulating layer, another part of the side surface of the second insulating layer, another part of the side surface of the sixth conductive layer, another part of the upper surface of the sixth conductive layer, another part of the side surface of the seventh conductive layer, and another part of the upper surface of the seventh conductive layer. The third insulating layer is located on the first semiconductor layer and the second semiconductor layer. The eighth conductive layer is located on the third insulating layer such that it has a region that overlaps with the first semiconductor layer. The ninth conductive layer is located on the third insulating layer such that it has a region that overlaps with the second semiconductor layer. Semiconductor equipment. 　 In claim 7, The first semiconductor layer and the second semiconductor layer are each a metal oxide containing indium. The first insulating layer comprises a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. The second insulating layer comprises a seventh insulating layer, an eighth insulating layer on the seventh insulating layer, and a ninth insulating layer on the eighth insulating layer. The fourth insulating layer, the sixth insulating layer, the seventh insulating layer, and the ninth insulating layer each contain silicon and nitrogen. The fifth insulating layer and the eighth insulating layer each contain silicon and oxygen, Semiconductor equipment. 　 In claim 7 or claim 8, A tenth insulating layer is located beneath the first to fifth conductive layers. The upper surface of the tenth insulating layer is in contact with the first to fifth conductive layers. The tenth insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. Semiconductor equipment. 　 It comprises a first conductive layer to a ninth conductive layer, a first semiconductor layer and a second semiconductor layer, and a first insulating layer to a sixth insulating layer. The first conductive layer and the second conductive layer are each located in different regions on the same plane. The first insulating layer is located on a first region of the first conductive layer, The second insulating layer is located on a second region of the first conductive layer, The third insulating layer is located on a third region of the second conductive layer. The fourth insulating layer is located on the fourth region of the second conductive layer, The fifth insulating layer is located on the fifth region of the first conductive layer and on the sixth region of the second conductive layer. The third conductive layer is located on the first insulating layer, The fourth conductive layer is located on the second insulating layer, The fifth conductive layer is located on the third insulating layer, The sixth conductive layer is located on the fourth insulating layer, The seventh conductive layer is located on the fifth insulating layer, The first semiconductor layer is in contact with a portion of the upper surface of the first conductive layer, a portion of the upper surface of the second conductive layer, a side surface of the first insulating layer, a side surface of the third insulating layer, a portion of the side surface of the fifth insulating layer, a side surface of the third conductive layer, the upper surface of the third conductive layer, a side surface of the fifth conductive layer, the upper surface of the fifth conductive layer, a portion of the side surface of the seventh conductive layer, and a portion of the upper surface of the seventh conductive layer. The second semiconductor layer is in contact with the other part of the upper surface of the first conductive layer, the other part of the upper surface of the second conductive layer, the side surface of the second insulating layer, the side surface of the fourth insulating layer, the other part of the side surface of the fifth insulating layer, the side surface of the fourth conductive layer, the upper surface of the fourth conductive layer, the side surface of the sixth conductive layer, the other part of the side surface of the seventh conductive layer, and the other part of the upper surface of the seventh conductive layer. The sixth insulating layer is located on the first semiconductor layer and the second semiconductor layer, The eighth conductive layer is located on the sixth insulating layer such that it has a region that overlaps with the first semiconductor layer. The ninth conductive layer is located on the sixth insulating layer such that it has a region that overlaps with the second semiconductor layer. Semiconductor equipment. 　 In claim 10, The first semiconductor layer and the second semiconductor layer are each a metal oxide containing indium. The first insulating layer comprises a seventh insulating layer, an eighth insulating layer on the seventh insulating layer, and a ninth insulating layer on the eighth insulating layer. The second insulating layer comprises a tenth insulating layer, an eleventh insulating layer on the tenth insulating layer, and a twelfth insulating layer on the eleventh insulating layer. The third insulating layer comprises a thirteenth insulating layer, a fourteenth insulating layer on the thirteenth insulating layer, and a fifteenth insulating layer on the fourteenth insulating layer. The fourth insulating layer comprises a 16th insulating layer, a 17th insulating layer on the 16th insulating layer, and an 18th insulating layer on the 17th insulating layer. The fifth insulating layer comprises a 19th insulating layer, a 20th insulating layer on the 19th insulating layer, and a 21st insulating layer on the 20th insulating layer. The seventh insulating layer, the ninth insulating layer, the tenth insulating layer, the twelfth insulating layer, the thirteenth insulating layer, the fifteenth insulating layer, the sixteenth insulating layer, the eighteenth insulating layer, the nineteenth insulating layer, and the twenty-first insulating layer each contain silicon and nitrogen. The eighth insulating layer, the eleventh insulating layer, the fourteenth insulating layer, the seventeenth insulating layer, and the twentyth insulating layer each contain silicon and oxygen. Semiconductor equipment. 　 In claim 10 or claim 11, A 22nd insulating layer is located beneath the first conductive layer and the second conductive layer. The upper surface of the 22nd insulating layer is in contact with the first conductive layer and the second conductive layer. The 22nd insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. Semiconductor equipment. 　 A first conductive layer to a fourth conductive layer is formed. A first insulating film and a first conductive film are formed in this order on the first conductive layer to the fourth conductive layer. The first conductive film and the first insulating film are processed to have regions that overlap with the first to fourth conductive layers, respectively, to form a fifth conductive layer and a first insulating layer, respectively. A first semiconductor layer is formed in contact with the upper surface of the first conductive layer, the upper surface of the second conductive layer, a part of the side surface of the first insulating layer, a part of the side surface of the fifth conductive layer, and a part of the upper surface of the fifth conductive layer, while a second semiconductor layer is formed in contact with the upper surface of the third conductive layer, the upper surface of the fourth conductive layer, another part of the side surface of the first insulating layer, another part of the side surface of the fifth conductive layer, and another part of the upper surface of the fifth conductive layer. A second insulating layer is formed in contact with the upper surfaces of the first semiconductor layer and the second semiconductor layer, respectively. A sixth conductive layer is formed in contact with the second insulating layer such that it has a region overlapping with the first semiconductor layer, and a seventh conductive layer is formed in contact with the second insulating layer such that it has a region overlapping with the second semiconductor layer. Method for manufacturing semiconductor devices.

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