Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device includes a substrate and a nanosheet transistor formed on the substrate. The nanosheet transistor comprises: a semiconductor layer serving as a channel region formed by a nanosheet; a gate electrode; a source / drain region; and an inner spacer. The semiconductor layer has a widened portion in a region overlapping the gate electrode in a plan view in a stacking direction of the semiconductor layer and the gate electrode, the widened portion having a larger length in a channel width direction than a portion connected to the source / drain region.

Description

Semiconductor device and method for manufacturing a semiconductor device

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Semiconductor devices equipped with Gate All Around Field Effect Transistors (GAA-FETs) using nanosheets are known. Semiconductor devices that enable miniaturization of devices and reduction of power consumption have been proposed using GAA-FETs. Furthermore, there is a need to improve the drive current in semiconductor devices equipped with GAA-FETs. For example, a semiconductor device has been proposed in which the material of the semiconductor layer that forms the channel region is changed to increase the carrier mobility in the channel region and improve the drive current (see Patent Document 1). In this semiconductor device, the SiGe layer is removed from a laminate of a Si layer and a SiGe layer (sacrificial layer), and then SiGe is epitaxially grown from the Si layer to form the channel region.

[0003] U.S. Patent Publication No. 2023 / 0088757

[0004] However, in the semiconductor device described in Patent Document 1 mentioned above, the material of the channel region is limited to the configuration that improves the drive current. With such a limited range of usable materials, the applicable semiconductor device configurations are also limited. For this reason, there is a need for a semiconductor device that can improve the drive current in a wider range of configurations, regardless of the material of the semiconductor layer constituting the channel region.

[0005] To solve the above-mentioned problems, the present invention provides a semiconductor device capable of improving the drive current, and a method for manufacturing a semiconductor device.

[0006] The semiconductor device of the present invention comprises a substrate and a nanosheet transistor formed on the substrate. The nanosheet transistor comprises a semiconductor layer that forms a channel region formed by a nanosheet, a gate electrode stacked on the semiconductor layer, a source / drain region arranged on the side of the stack of the semiconductor layer and the gate electrode and connected to the semiconductor layer, and an inner spacer formed between the gate electrode and the source / drain region between the stacked semiconductor layers. Furthermore, in a plan view in the stacking direction of the semiconductor layer and the gate electrode, the semiconductor layer has a widened portion in the region overlapping with the gate electrode, where the length in the channel width direction is greater than the portion connected to the source / drain region.

[0007] Furthermore, the present invention provides a method for manufacturing a semiconductor device comprising a substrate and a nanosheet transistor formed on the substrate. The method for manufacturing a semiconductor device includes the steps of: forming a laminate on the substrate of a first semiconductor layer which will be a sacrificial layer and a second semiconductor layer which will be a channel region; separating the laminate of the first semiconductor layer and the second semiconductor layer in the channel width direction; forming a sacrificial insulating layer and a dummy gate on the laminate; transferring the pattern of the dummy gate to the sacrificial insulating layer; forming gate spacers on the sides of the sacrificial insulating layer and the dummy gate; replacing a part of the side of the first semiconductor layer with an inner spacer; forming source and drain regions on the side of the second semiconductor layer by epitaxial growth; removing the dummy gate, sacrificial insulating layer and the first semiconductor layer; and forming a gate electrode in the region where the dummy gate, sacrificial insulating layer and the first semiconductor layer have been removed. Furthermore, the method for manufacturing a semiconductor device includes forming a widened portion on the second semiconductor layer in a region that overlaps with the gate electrode, where the length in the channel width direction is greater than the portion connected to the source and drain regions.

[0008] According to the present invention, it is possible to provide a semiconductor device capable of improving the drive current, and a method for manufacturing a semiconductor device.

[0009] This is a schematic diagram of a semiconductor device viewed from the top. This is a schematic diagram of a semiconductor device viewed from the side of the source and drain regions. This is a schematic diagram of a semiconductor device viewed from the top. This is a schematic diagram of a semiconductor device viewed from the side of the source and drain regions. This is an enlarged view of the source and drain regions and the connection portion between the channel region and the source and drain regions, viewed from the top of the semiconductor device. This is a schematic diagram of a semiconductor device of the first embodiment viewed from the top. This is a planar arrangement diagram of the semiconductor layer and gate electrode of the semiconductor device of the first embodiment. This is an X-X cross-sectional view (cross-sectional view in the channel length direction) of the semiconductor device shown in Figure 6. This is a Y-Y cross-sectional view (cross-sectional view in the channel width direction) of the semiconductor device shown in Figure 6. This is a partial enlarged view of the semiconductor device shown in Figure 7. This is a schematic diagram of a semiconductor device viewed from the side of the source and drain regions. This is a planar arrangement of the channel region, connection portion, gate electrode, and inner spacer in the semiconductor layer. This is a planar arrangement of the channel region, connection portion, gate electrode, and inner spacer in the semiconductor layer. This is a planar arrangement of the channel region, connection portion, gate electrode, and inner spacer in the semiconductor layer. This is a plan view of the channel region, inner spacer, and source / drain region of a semiconductor device. This is a graph of the electrical characteristics of a semiconductor device with the configuration shown in Figure 15A. This is a plan view of the channel region, inner spacer, and source / drain region of a semiconductor device with a changing channel width. This is a graph of the electrical characteristics of a semiconductor device with the configuration shown in Figure 16A. This is a manufacturing process diagram of a semiconductor device of the first embodimentThis is a manufacturing process diagram for a semiconductor device of the first embodiment. This is a manufacturing process diagram for a semiconductor device of the first embodiment. This is a manufacturing process diagram for a semiconductor device of the first embodiment. This is a manufacturing process diagram for a semiconductor device of the first embodiment. This is a manufacturing process diagram for a semiconductor device of the second This is a manufacturing process diagram for a semiconductor device of the second embodiment. This is a manufacturing process diagram for a semiconductor device of the second embodiment. This is a manufacturing process diagram for a semiconductor device of the second embodiment. This is a manufacturing process diagram for a semiconductor device of the second embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment.This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment. This is a manufacturing process diagram for a semiconductor device of the third embodiment.

[0010] The following describes examples of embodiments for carrying out the present invention, but the present invention is not limited to these examples. The description will be in the following order: 1. Overview of the semiconductor device and the method for manufacturing the semiconductor device 2. Semiconductor device and method for manufacturing the semiconductor device according to the first embodiment 3. Semiconductor device and method for manufacturing the semiconductor device according to the second embodiment

[0011] <1. Overview of Semiconductor Device and Method for Manufacturing a Semiconductor Device> Before describing embodiments of the present invention, an overview of a conventional semiconductor device and method for manufacturing a semiconductor device will be described. In the figures described below, common components are denoted by the same reference numerals. In addition, in the drawings used in this specification, identical or corresponding components are denoted by the same reference numerals, and repeated descriptions of these components may be omitted. Furthermore, in the following description, only the main components of the present invention will be described and illustrated, and other components such as insulating layers and wiring will not be described or illustrated.

[0012] [Configuration of the wiring layer of the semiconductor device] Figures 1 and 2 show the schematic configuration of the semiconductor device 10. Figure 1 is a schematic diagram of the semiconductor device viewed from the top. Figure 2 is a schematic diagram of the semiconductor device viewed from the side of the source and drain regions.

[0013] The semiconductor device 10 shown in Figure 1 has a gate all-around field-effect transistor (GAA-FET) arranged on a substrate. The semiconductor device 10 comprises semiconductor layers 12 and 13 in which a channel region and a source / drain region are formed, and a gate electrode 11. The semiconductor device is a nanosheet transistor in which the channel region is composed of a nanosheet layer. In the semiconductor device 10, nanosheets also include nanowires. The semiconductor device 10 includes a plurality of P-type GAA-FETs and N-type GAA-FETs arranged on a substrate. For example, in the semiconductor device 10, a P-type GAA-FET is formed on semiconductor layer 12, and an N-type GAA-FET is formed on semiconductor layer 13. Therefore, in the semiconductor device 10, a P-type source / drain region and a channel region of the P-type FET are formed on semiconductor layer 12. Also, in the semiconductor device 10, an N-type source / drain region and a channel region of the N-type FET are formed on semiconductor layer 13. Furthermore, in the semiconductor device 10, the GAA-FET has a gate electrode 11 surrounding the channel region. The gate electrode 11 has a gate metal formed from a metallic material having a work function within a predetermined range.

[0014] As shown in Figure 2, the semiconductor device 10 is arranged on a substrate 15. The gate electrode 11 and semiconductor layers 12 and 13 are arranged on the substrate 15. Also, as shown in Figure 2, the GAA-FET in the semiconductor device 10 has source and drain regions 16 and 17 formed in the semiconductor layers 12 and 13. The semiconductor device 10 has a p-type source and drain region 16 in the semiconductor layer 12 where the p-type GAA-FET is formed, and an n-type source and drain region 17 in the semiconductor layer 13 where the N-type GAA-FET is formed. Furthermore, the semiconductor device 10 has a channel region of a p-type FET connected to the p-type source and drain region 16 in the semiconductor layer 12, and a channel region of an n-type FET connected to the n-type source and drain region 17 in the semiconductor layer 13.

[0015] In a semiconductor device equipped with the conventional GAA-FET configuration described above, a structure in which the semiconductor layers 12 and 13 are expanded in the channel width direction can be considered in order to improve the drive current. In this configuration, the drive current is improved by expanding the channel width.

[0016] Figures 3, 4, and 5 show the schematic configuration of a semiconductor device with a structure expanded in the channel width direction in a GAA-FET. Figure 3 is a schematic diagram viewed from the top of the semiconductor device. Figure 4 is a schematic diagram viewed from the side of the source and drain regions of the semiconductor device. Figure 5 is an enlarged view of the source and drain regions and the connection portion between the channel region and the source and drain regions, viewed from the top of the semiconductor device.

[0017] As shown in Figure 3, the semiconductor device 20 comprises semiconductor layers 22 and 23 in which a channel region and a source / drain region are formed, and a gate electrode 21. In the semiconductor device 20, the gate electrode 21 has the same configuration as the gate electrode 11 of the conventional semiconductor device 10 shown in Figure 1. Also, as shown in Figure 4, the semiconductor device 20 has the gate electrode 21 and the semiconductor layers 22 and 23 arranged on a substrate 25. The semiconductor device 20 has a p-type source / drain region 26 in the semiconductor layer 22 in which a p-type GAA-FET is formed, and an n-type source / drain region 27 in the semiconductor layer 23 in which an N-type GAA-FET is formed.

[0018] The semiconductor device 20 shown in Figure 3 has semiconductor layers 22 and 23 in which the semiconductor layers 12 and 13 of the conventional semiconductor device 10 shown in Figure 1 are expanded in the channel width direction while maintaining the element density. Because the width of the semiconductor layers 22 and 23 is expanded while maintaining the element density in the semiconductor device 20, the spacing between adjacent semiconductor layers 22 and 23 is smaller than that of the semiconductor device 10 shown in Figure 1. Therefore, as shown in Figure 4, the p-type source-drain region 26 and the n-type source-drain region 27 of the semiconductor device 20 interfere with each other. Thus, in a semiconductor device 20 with a configuration in which the width of the semiconductor layers 22 and 23 is expanded while maintaining the element density, if the source-drain regions 26 and 27 are formed using the same method as in the conventional device, adjacent source-drain regions 26 and 27 will interfere with each other. Figure 5 shows the connection portion 29 between the channel region and the source / drain regions 26 and 27 in the semiconductor layers 22 and 23 of the semiconductor device 20 shown in Figures 3 and 4, and the connection portion 28 between the channel region and the source / drain regions 16 and 17 of the semiconductor device 10 shown in Figures 1 and 2. Generally, the source / drain regions 16, 17, 26, and 27 are formed by epitaxial growth from the connection portions 28 and 29 between the channel region and the source / drain regions 16, 17, 26, and 27. Therefore, as shown in Figure 5, the source / drain regions 26 and 27 formed by epitaxial growth from the wider connection portion 29 have a larger length in the channel width direction compared to the source / drain regions 16 and 17 formed from the narrower connection portion 28. For this reason, if the width of the semiconductor layers 22 and 23 is increased while maintaining the density of the elements, the spacing between the semiconductor layers 22 and 23 decreases, and at the same time, the width of the formed source / drain regions 26 and 27 increases. As a result, as shown in Figure 4, in the semiconductor device 20 in which the width of the semiconductor layers 22 and 23 has been expanded, adjacent source and drain regions 26 and 27 interfere with each other.

[0019] As described above, in semiconductor devices 20 with a structure in which adjacent source-drain regions 26 and 27 interfere with each other, it is difficult to obtain the desired characteristics. Generally, n-type source-drain regions 27 and p-type source-drain regions 26 must not be formed simultaneously, but must be manufactured in separate processes. For this reason, in the structure in which adjacent source-drain regions 26 and 27 interfere with each other as shown in Figure 4, for example, if the p-type source-drain region 26 is formed first, the p-type source-drain region 26 will also be formed in the region where the n-type source-drain region 27 is to be formed. Then, when forming the n-type source-drain region 27 in a later process, the formation of the n-type source-drain region 27 is hindered by the p-type source-drain region 26. As a result, it is difficult to manufacture semiconductor devices with the desired characteristics in structures in which adjacent source-drain regions 26 and 27 interfere with each other.

[0020] <2. Semiconductor device of the first embodiment and method for manufacturing a semiconductor device> Hereinafter, an example of a semiconductor device and a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. In the description of the semiconductor device of the first embodiment and the method for manufacturing a semiconductor device, the same reference numerals will be used for components similar to those described in the overview of the semiconductor device and the method for manufacturing a semiconductor device described above, and detailed descriptions will be omitted.

[0021] Figures 6 to 11 show the schematic configuration of the semiconductor device of the first embodiment. Figure 6 is a schematic diagram of the semiconductor device viewed from the top. Figure 7 is a planar arrangement diagram of the semiconductor layer and gate electrode of the semiconductor device. Figure 8 is a cross-sectional view of the semiconductor device shown in Figure 6 along the X-X line (cross-sectional view in the channel length direction). Figure 9 is a cross-sectional view of the semiconductor device shown in Figure 6 along the Y-Y line (cross-sectional view in the channel width direction). Figure 10 is a partially enlarged view of the semiconductor device shown in Figure 7. Figure 11 is a schematic diagram of the semiconductor device viewed from the side direction of the source / drain region.

[0022] [Configuration of Semiconductor Device] (Planar Configuration) The semiconductor device 100 shown in Figure 6 has a gate-all-around field-effect transistor (GAA-FET) arranged on a substrate. The semiconductor device 100 comprises semiconductor layers 102 and 103 in which a channel region and a source / drain region are formed, and a gate electrode 101. The semiconductor device is a nanosheet transistor in which the channel region is formed by a nanosheet layer. In the semiconductor device 100, nanosheets also include nanowires. The semiconductor device 100 includes a plurality of P-type GAA-FETs and N-type GAA-FETs arranged on a substrate. For example, in the semiconductor device 100, a P-type GAA-FET is formed on semiconductor layer 102, and an N-type GAA-FET is formed on semiconductor layer 103. Therefore, in the semiconductor device 100, a P-type source / drain region and a channel region of the P-type FET are formed on semiconductor layer 102. Also, in the semiconductor device 100, an N-type source / drain region and a channel region of the N-type FET are formed on semiconductor layer 103. Furthermore, in the semiconductor device 100, the GAA-FET has a gate electrode 101 surrounding the channel region. The gate electrode 101 has a gate metal formed of a metallic material having a work function within a predetermined range.

[0023] Furthermore, as shown in Figure 7, the semiconductor device 100 has semiconductor layers 102 and 103 that are larger in the channel width direction than the gate-under regions 112 and 113, which overlap with the gate electrodes 101 in a planar arrangement. In other words, the semiconductor device 100 has different widths of semiconductor layers 102 and 103 in the gate-under regions 112 and 113 that overlap with the gate electrodes 101, between gate electrodes 101 outside of the gate-under regions 112 and 113, and in the connection portions between the channel region and the source / drain region.

[0024] (Cross-sectional configuration; channel length direction) Next, Figure 8 shows a cross-sectional view of the semiconductor device 100 in the channel length direction. As shown in Figure 8, in the cross-sectional view in the channel length direction, the semiconductor device 100 has a GAA-FET formed on the substrate 110. The GAA-FET has a gate electrode 101, a semiconductor layer (second semiconductor layer) 102 which forms the channel region, and a source / drain region 106. The semiconductor device 100 has a laminated structure of [gate electrode 101 / semiconductor layer 102 / gate electrode 101 / semiconductor layer 102 / gate electrode 101 / semiconductor layer 102 / gate electrode 101] formed by the stacked structure of the gate electrode 101 and the semiconductor layer 102. The semiconductor device 100 also has a gate spacer 119 on the side surface of the gate electrode 101 which is formed above the uppermost semiconductor layer 102. The gate spacer 119 is formed around the gate electrode 101.

[0025] The semiconductor device 100 includes a source / drain region 106 adjacent to the side surface of a laminate consisting of a gate electrode 101 and a semiconductor layer 102. In the semiconductor device 100, adjacent GAA-FETs in the channel length direction share the source / drain region 106. The semiconductor layer 102 is connected to the source / drain region 106. In the semiconductor device 100, an inner spacer 117 made of an insulating layer is formed between the gate electrode 101 and the source / drain region 106.

[0026] The semiconductor device 100 includes a high dielectric constant material layer (not shown) and a gate insulating film (not shown) at the contact surface between the semiconductor layer 102 and the gate spacer 119 of the gate electrode 101. The metal material constituting the gate electrode 101 is filled on the inner circumference side of the high dielectric constant material layer and the gate insulating film. In the gate electrode 101, the metal material is continuously formed between the stacked semiconductor layers 102 and on the upper part of the semiconductor layers 102.

[0027] The semiconductor device 100 has contact wiring 120 that connects to the source / drain region 106. The contact wiring 120 connects to the source / drain region 106 from the side opposite to the substrate 110 (from above). The contact wiring 120 is positioned between the gate spacers 119 directly above the source / drain region 106.

[0028] Furthermore, in a cross-section (not shown) in the channel width direction, the semiconductor device 100 has a substrate 110 and an STI (Shallow Trench Isolation) formed on the substrate 110 as an element isolation region. The STI is formed in positions other than directly beneath the stack of the gate electrode 101 and the semiconductor layer 102. Also, in the cross-sectional view in the channel width direction, the semiconductor device 100 is covered around the cross-section of the semiconductor layer 102 which forms the channel region by the gate electrode 101 which is continuously formed between the stack of semiconductor layers 102 and on the upper part of the semiconductor layer 102.

[0029] (Channel width direction) In the cross-sectional view in the channel width direction shown in Figure 9, the semiconductor device 100 has an STI (Shallow Trench Isolation) 111 formed on the surface of the substrate 110 as an element isolation region. The STI 111 is made of an insulating film material embedded in the substrate 110. The semiconductor device 100 also has a gate electrode 101 and a semiconductor layer 102 on the substrate 110 and the STI 111. The semiconductor device 100 is constructed by stacking the semiconductor layer 102 and the metal material layer that constitutes the gate electrode 101. The semiconductor device 100 also has the semiconductor layer 102 within a region surrounded by a high dielectric constant material layer (not shown). The semiconductor layer 102 shown in Figure 9 is the gate-under region 112 (Figure 7) located in the region stacked with the gate electrode 101. For this reason, the portion of the semiconductor layer 102 shown in Figure 9 has a greater width in the channel width direction than the connection portion with the source / drain region 106 (Figure 8) (see the connection portion 115 shown in Figure 10). Furthermore, as can be seen from the cross-sectional view in the channel width direction shown in Figure 9, each gate electrode 101 shown in Figure 8 is formed continuously. Therefore, in the cross-sectional view in the channel width direction shown in Figure 9, the semiconductor layer 102 is surrounded by the gate electrodes 101. In other words, the entire cross-section in the channel width direction of the semiconductor layer 102, which forms the channel portion of the semiconductor device 100, is surrounded by the gate electrodes 101, as shown in Figure 9.

[0030] [Planar Configuration; Enlarged View] Figure 10 shows an enlarged view of the channel region, source / drain region, and the connection portion between the channel region and the source / drain region. Figure 10 is an enlarged view of the region indicated by the dashed line in the semiconductor device 100 shown in Figure 6. As shown in Figure 10, the semiconductor layer 102 has a gate-lower region 112, a source / drain region 106, and a connection portion 115 between the gate-lower region 112 and the source / drain region 106. The gate-lower region 112 is formed in the semiconductor layer 102 in the region that overlaps with the gate electrode 101. The connection portion 115 is the region between the gate-lower region 112 and the source / drain region 106. The connection portion 115 is mainly located in the region that overlaps with the inner spacer and gate spacer. The source / drain region 106 is formed at the end of the connection portion 115. The source / drain region 106 is formed by epitaxial growth from the end face of the connection portion 115.

[0031] As shown in Figure 10, the semiconductor layer 102 has a channel width length in the gate-lower region 112 that is greater than the connection portion 115. Due to the larger width of the gate-lower region 112 of the semiconductor layer 102, the channel width under the gate electrode 101 is expanded. As a result, the semiconductor device 100 has a larger channel width length in the gate-lower region 112 of the semiconductor layer 102, which improves the drive current.

[0032] Furthermore, as shown in Figure 10, the semiconductor layer 102 has a channel width length of the connection portion 115 with the source / drain region 106 that is smaller than the gate-under region 112. For this reason, for example, the connection portion 115 in the semiconductor layer 102 can be formed with the same width as a conventional semiconductor device. In this way, since the semiconductor device 100 can have the same width as the connection portion 115, the width of the source / drain region 106, which is epitaxially grown based on the connection portion 115, can also be formed with the same width as a conventional semiconductor device.

[0033] Furthermore, as shown in Figure 11, the semiconductor device 100 is arranged on a substrate 110. The gate electrode 101 and the source / drain regions 106 and 107 are arranged on the substrate 110. Also, as shown in Figure 11, the GAA-FET in the semiconductor device 100 has a pair of source / drain regions 106 and 107 formed in semiconductor layers 102 and 103. The semiconductor device 100 has a p-type source / drain region 106 in the semiconductor layer 102 where the p-type GAA-FET is formed, and an n-type source / drain region 107 in the semiconductor layer 103 where the N-type GAA-FET is formed. Furthermore, the semiconductor device 100 has a channel region of a p-type FET connected to the p-type source / drain region 106 in the semiconductor layer 102, and a channel region of an n-type FET connected to the n-type source / drain region 107 in the semiconductor layer 103.

[0034] As shown in Figure 11, even in the semiconductor layer 102 in which the gate-under region 112 has been enlarged, the width of the connection portion 115 of the semiconductor device 100 has not been enlarged. Therefore, the width of the source and drain regions 106 and 107 of the semiconductor device 100 has not been enlarged. In other words, as shown in Figure 11, the source and drain regions 106 and 107 of the semiconductor device 100 can be formed with the same width as those of a conventional semiconductor device. As a result, the semiconductor device 100 can suppress interference between adjacent source and drain regions 106 and 107 in a configuration in which the width of the gate-under region 112 of the semiconductor layer 102 has been enlarged while maintaining the density of elements.

[0035] [Arrangement of Semiconductor Layers] Next, the arrangement of the gate-under region 112 and connection portion 115 of the semiconductor layer 102 of the semiconductor device 100 and the gate electrode will be described. Figures 12, 13, and 14 show the planar arrangement of the gate-under region 112 and connection portion 115, the gate electrode 101, and the inner spacer 117 in the semiconductor layer 102. In Figures 12, 13, and 14, the upper part of the drawing shows the configuration of the semiconductor layer 102, and the lower part of the drawing shows the planar arrangement in which the gate electrode 101 and the inner spacer 117 are formed on the semiconductor layer 102.

[0036] Figure 12 shows the widened portion 122 of the semiconductor layer 102 where its width is increased, the narrowed portion 125 where its width is not increased, the width of the gate region 121 where the gate electrode 101 is formed (length in the channel length direction), and the width of the spacer region 127 where the inner spacer 117 is formed (length in the channel length direction). As shown in Figure 12, it is preferable that the widened portion 122 of the semiconductor layer 102, where its width is increased, coincides with the gate region 121 where the gate electrode 101 is formed. When the widened portion 122 of the semiconductor layer 102 coincides with the gate region 121 where the gate electrode 101 is formed, the widened portion 122 of the semiconductor layer 102 is not placed in the spacer region 127 where the inner spacer 117 is formed. Then, only the narrowed portion 125 of the semiconductor layer 102, where its width is not increased, is placed in the spacer region 127 where the inner spacer 117 is formed. The region of the semiconductor layer 102 adjacent to the gate electrode 101 is the gate-under region 112. Therefore, the positions of the gate electrode 101 and the widened portion 122 coincide, so that the entire widened portion 122 becomes the gate-under region 112. As a result, the channel width can be increased throughout the gate-under region 112 in the semiconductor device 100. Consequently, the channel width of the semiconductor layer 102 in the gate-under region 112 of the semiconductor device 100 is increased, and the drive current is improved. Furthermore, the semiconductor layer 102 exposed from the spacer region 127 where the inner spacer 117 is formed is only the narrow portion 125. Therefore, the end face of the connection portion 115 is formed only from the narrow portion 125. Consequently, the expansion of the source and drain regions formed by epitaxial growth from the connection portion 115 can be suppressed.

[0037] Next, FIG. 13 shows a configuration in which the widened portion 122 with an increased width in the semiconductor layer 102 is shifted in one direction along the channel length direction. That is, in FIG. 13, the widened portion 122 is disposed only on one source / drain region side, and the narrow portion 125 is disposed on the other source / drain region side. As shown in FIG. 13, when there is a shift between the widened portion 122 and the gate region 121 where the gate electrode 101 is formed, a part of the widened portion 122 of the semiconductor layer 102 is disposed in the spacer region 127 where the inner spacer 117 is formed. Further, not only the widened portion 122 of the semiconductor layer 102 but also a part of the narrow portion 125 is disposed in the gate region 121 where the gate electrode 101 is formed.

[0038] Therefore, in the configuration shown in FIG. 13, in the gate-under region 112 overlapping with the gate electrode 101, the semiconductor layer 102 has the narrow portion 125 with a narrow channel width. The semiconductor device 100 having the configuration shown in FIG. 13 has a narrower channel width in a part of the gate-under region 112 compared to the configuration shown in FIG. 12 described above. For this reason, in the semiconductor device 100, the configuration shown in FIG. 13 has a lower effect of improving the drive current compared to the configuration shown in FIG. 12 described above. On the other hand, in the semiconductor device 100 having the configuration shown in FIG. 13, since the channel width can be increased in the widened portion 122 of the gate-under region 112 of the semiconductor layer 102, the drive current is improved compared to the conventional configuration.

[0039] In addition, it is preferable that the semiconductor device 100 is configured such that the entire widened portion 122 is positioned within the range of the gate region 121 where the gate electrode 101 is formed and the spacer region 127 where the inner spacer 117 is formed. If a part of the widened portion 122 is formed offset from the spacer region 127 in the channel length direction, the widened portion 122 will be exposed outside the inner spacer 117. In this configuration, the widened portion 122 is included in the semiconductor layer 102 exposed from the spacer region 127 where the inner spacer 117 is formed. In this case, the end face of the connection portion 115 is formed by the narrow portion 125 and the widened portion 122. Furthermore, the source and drain regions grow epitaxially not only from the narrow portion 125 but also from the widened portion 122. As a result, the width of the epitaxially grown source and drain regions increases, and it is easy for adjacent source and drain regions to interfere with each other, as shown in Figures 4 and 5 above. Therefore, it is preferable that the widened portion 122 is not positioned outside the gate region 121 where the gate electrode 101 is formed, and the spacer region 127 where the inner spacer 117 is formed.

[0040] Next, Figure 14 shows a configuration in which the widened portion 122, whose width is expanded, is formed in the semiconductor layer 102 by expanding in both directions in the channel length direction. As shown in Figure 14, when the widened portion 122 in the semiconductor layer 102 is larger than the gate region 121 in which the gate electrode 101 is formed, a part of the widened portion 122 of the semiconductor layer 102 is arranged on both sides of the spacer region 127 in which the inner spacer 117 is formed. Also, in the configuration shown in Figure 14, the widened portion 122 is arranged throughout the gate region 121 in the semiconductor layer 102 in which the gate electrode 101 is formed. Therefore, in the region of the semiconductor layer 102 that overlaps with the gate electrode 101, the gate-lower region 112 is entirely composed of the widened portion 122. As a result, in the semiconductor device 100, the channel width can be increased throughout the entire gate-lower region 112 of the semiconductor layer 102. Consequently, the drive current of the semiconductor device 100 is improved.

[0041] Also, in the configuration shown in FIG. 14, the center positions in the channel length direction do not match between the widened portion 122 and the gate region 121 where the gate electrode 101 is formed. Therefore, the widened portion 122 does not have the same amount of expansion in both directions in the channel length direction, and the lengths of the widened portions 122 formed in the spacer region 127 where the inner spacer 117 is formed are different. However, in the semiconductor layer 102, the widened portion 122 is formed only within the range between the gate region 121 where the gate electrode 101 is formed and the spacer region 127 where the inner spacer 117 is formed. For this reason, the widened portion 122 of the semiconductor layer 102 is not exposed from the spacer region 127 where the inner spacer 117 is formed. For this reason, the widened portion 122 is not included in the end face of the connection portion 115 where the source / drain region epitaxially grows. Therefore, the expansion of the source / drain region formed by epitaxial growth from the connection portion 115 can be suppressed.

[0042] [Shape of Channel Region] Next, the shape of the channel region and electrical characteristics will be described. FIGS. 15 and 16 show the relationship between the shape of the channel region and electrical characteristics.

[0043] FIG. 15A is a plan view of the under-gate region 11‚ inner spacer 117‚ and source / drain region 106 of the semiconductor device 100. In FIG. 15A‚ the region of the semiconductor layer 102 disposed below the inner spacer 117 is indicated by a broken line. Also‚ in FIG. 15A‚ the description of the gate electrode is omitted for the sake of explanation‚ but the gate electrode is formed in the region between the inner spacers 117. For this reason‚ in the semiconductor device 100 shown in FIG. 15A‚ the region between the inner spacers 117 becomes the under-gate region 112.

[0044] As shown in Figure 15A, the semiconductor device 100 has a gate-lower region 112 formed only by the widened portion 122 of the semiconductor layer 102. The semiconductor device 100 has a narrowed portion 125 of the semiconductor layer 102 formed only in the region overlapping with the inner spacer 117. As a result, the channel width of the semiconductor device 100 is constant between the source and drain regions 106. In addition, one source and drain region 106 of the semiconductor device 100 is connected to the electrode 126, and the other source and drain region 106 of the semiconductor device 100 is connected to the electrode 128.

[0045] Figure 15B shows the electrical characteristics of the semiconductor device 100 with the configuration shown in Figure 15A. Figure 15B is a graph in which the vertical axis represents potential and the horizontal axis represents the position in the channel length direction in the channel region. Furthermore, in Figure 15B, graph 151 shows the electrical characteristics of the semiconductor device 100 with the configuration shown in Figure 15A when electrode 126 is Vdd and electrode 128 is GND, and graph 152 shows the electrical characteristics when electrode 126 is GND and electrode 128 is Vdd. Specifically, graph 151 shows the change in potential when one source / drain region 106 connected to Vdd by electrode 126 is the drain (D), and the other source / drain region 106 connected to GND by electrode 128 is the source (S). Furthermore, graph 152 shows the change in potential when one source / drain region 106 connected to GND by electrode 126 is designated as the source (S), and the other source / drain region 106 connected to Vdd by electrode 128 is designated as the drain (D).

[0046] As shown in Figure 15B, graphs 151 and 152 follow the same trajectory. In a semiconductor device 100 with a constant channel width between the source and drain regions 106, the potential in the channel region remains the same even when Vdd and GND are swapped. That is, in a semiconductor device 100 with a constant channel width, the potential within the channel region is the same whether one side of the source and drain region 106 is the source (S) and the other side is the drain (D), or whether this is reversed and one side is the drain (D) and the other side is the source (S).

[0047] In contrast, Figure 16A shows the configuration of a semiconductor device 100 in which the channel width changes within the gate-lower region 112. Figure 16A is a plan view of the gate-lower region 112, inner spacer 117, and source / drain region 106 of the semiconductor device 100. In Figure 16A, the region of the semiconductor layer 102 located below the inner spacer 117 is shown by a dashed line. Also, although the gate electrode is omitted in Figure 16A for explanatory purposes, the gate electrode is formed in the region between the inner spacers 117. Therefore, in the semiconductor device 100 shown in Figure 16A, the region between the inner spacers 117 becomes the gate-lower region 112.

[0048] As shown in Figure 16A, the semiconductor device 100 has a gate-subgate region 112 of the semiconductor layer 102 formed by a widened portion 122 and a narrowed portion 125. Furthermore, the semiconductor device 100 has a narrowed portion 125 of the semiconductor layer 102 in a region that overlaps with the inner spacer 117. Therefore, in the channel region, the semiconductor device 100 has a region with a wide channel width where the widened portion 122 is formed, and a region with a narrow channel width where the narrowed portion 125 is formed. In addition, one source / drain region 106 of the semiconductor device 100 is connected to the electrode 126. The other source / drain region 106 of the semiconductor device 100 is connected to the electrode 128.

[0049] Figure 16B shows the electrical characteristics of the semiconductor device 100 with the configuration shown in Figure 16A. Figure 16B is a graph in which the vertical axis represents potential and the horizontal axis represents the position in the channel length direction in the channel region. Furthermore, in Figure 16B, graph 161 shows the electrical characteristics of the semiconductor device 100 with the configuration shown in Figure 16A when electrode 126 is Vdd and electrode 128 is GND, and graph 162 shows the electrical characteristics when electrode 126 is GND and electrode 128 is Vdd. Specifically, graph 161 shows the change in potential when one source / drain region 106 connected to Vdd by electrode 126 is the drain (D), and the other source / drain region 106 connected to GND by electrode 128 is the source (S). Furthermore, graph 162 shows the change in potential when one source / drain region 106 connected to GND by electrode 126 is designated as the source (S), and the other source / drain region 106 connected to Vdd by electrode 128 is designated as the drain (D).

[0050] As shown in Figure 16B, graphs 161 and 162 have different trajectories. Graph 161 shows the potential change when electrode 126 is connected to Vdd and electrode 128 is connected to GND. Under these conditions, because electrode 126 is connected to Vdd, a large amount of current is supplied from the source / drain region 106 to the widened portion 122 of the semiconductor layer 102. Therefore, graph 161 shows that in the channel region, the drain (D) side connected to Vdd by electrode 126 has a high potential. Also, in the channel region, the channel width decreases in the narrow portion 125, and carrier movement is inhibited. Therefore, in graph 161, in the channel region, the potential drops sharply from the position of the narrow portion 125 to the drain (D) side connected to GND by electrode 128. On the other hand, graph 162 shows the potential change when electrode 126 is connected to GND and electrode 128 is connected to Vdd. Under these conditions, since electrode 128 is connected to Vdd, current is supplied from the source / drain region 106 to the narrow portion 125 of the semiconductor layer 102. In the semiconductor layer 102, the narrow portion 125 has a smaller channel width than the widened portion 122, so in graph 162, the current supplied to the channel region is smaller than in graph 161. Furthermore, in graph 162, the potential drops sharply in the portion of the channel region where the narrow portion 125 is formed. Also, in graph 161, the potential drop is more gradual in the channel region because the channel width increases in the widened portion 122.

[0051] As described above, as shown in Figure 15, if the channel width is constant in the channel region, the semiconductor device 100 will have the same current characteristics even if the VDD and GND connected to the source / drain region 106 are swapped. On the other hand, as shown in Figure 16, if the channel width is not constant in the channel region, the semiconductor device 100 will have different current characteristics when the VDD and GND connected to the source / drain region 106 are swapped. For this reason, it is preferable that the channel width is constant in the gate-below region 112 of the semiconductor layer 102 of the semiconductor device 100. Accordingly, it is preferable that the semiconductor device 100 has a configuration in which the gate-below region 112 of the semiconductor layer 102 is entirely formed by the widened portion 122.

[0052] [Manufacturing Method] Next, a method for manufacturing the semiconductor device of the first embodiment will be described. An example of a method for manufacturing the semiconductor device of the first embodiment is shown in Figures 17 to 26. Figures 17A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, and 26A are cross-sectional views along the X-X line (cross-sectional view in the channel length direction) of the semiconductor device shown in Figure 6. Figures 17B, 19B, 20B, 21B, 22B, 23B, 24B, 25B, and 26B are cross-sectional views along the Y-Y line (cross-sectional view in the channel width direction) of the semiconductor device shown in Figure 6. In the following description of the manufacturing method, the same reference numerals are used for the configuration of the semiconductor device of the first embodiment described above and the configuration of a conventional semiconductor device, and detailed explanations are omitted.

[0053] First, in the manufacturing process of the semiconductor device 100, a substrate 110 made of a semiconductor such as Si is prepared, as shown in Figures 17A and 17B. Then, an alternating stacked structure of a first semiconductor layer 171 and a second semiconductor layer 102 is formed on the substrate 110. In Figures 17A and 17B, the first semiconductor layer 171 is formed on the substrate 110 side, and three layers each of the first semiconductor layer 171 and the second semiconductor layer 102 are formed. The second semiconductor layer 102 is the channel region of the GAA-FET and is formed of Si or SiGe with a low Ge concentration. The first semiconductor layer 171 is a sacrificial layer for forming the gate electrode 101 (Figure 8) and is formed of SiGe with a high Ge concentration. Both the first semiconductor layer 171 and the second semiconductor layer 102 are formed by epitaxial growth of nanosheets. The first semiconductor layer 171 and the second semiconductor layer 102 are formed to a thickness of, for example, 5 to 15 nm. For low-Ge concentration SiGe, the Ge content is preferably 15% to 35%, and more preferably 20% to 25%. For high-Ge concentration SiGe, the Ge content is preferably 40% to 75%, and more preferably 50% to 55%.

[0054] Furthermore, as shown in Figure 17B, the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 is separated in the channel width direction, and a fin-shaped laminate of the first semiconductor layer 171 and the second semiconductor layer 102 is formed. Then, an STI (Shallow Trench Isolation) 111 is formed on the substrate 110 exposed by the separation of the first semiconductor layer 171 and the second semiconductor layer 102 from the laminate. The separation of the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 is first performed by pouring SiO onto the laminate. ｘ A hard mask made of or SiN is formed. Then, a photoresist layer is formed on the hard mask. Furthermore, the photoresist layer is exposed and developed by photolithography. A predetermined pattern is formed on the photoresist layer by this photolithography. In this embodiment, a pattern is formed on the photoresist layer in a region that overlaps with the gate electrode in a planar arrangement, with a shape that is larger in the channel width direction than in the region that does not overlap with the gate electrode. Then, the pattern formed on the photoresist layer is transferred to the hard mask using reactive ion etching (RIE) or the like. Furthermore, the pattern formed on the hard mask is transferred to the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 using RIE or the like. Furthermore, trenches are formed in the substrate 110, and SiO is applied to the trenches. ｘ By embedding insulating materials and etching the insulating materials, the sides of the fin-shaped first semiconductor layer 171 and the second semiconductor layer 102 are exposed.

[0055] In this process, when separating the laminate of the first semiconductor layer 171 and the second semiconductor layer 102, as shown in Figures 7 and 10 to 14, the first semiconductor layer 171 and the second semiconductor layer 102 are processed so that the channel width direction is larger in the gate-under region 112 that overlaps with the gate electrode in a planar arrangement than in the region that does not overlap with the gate electrode. An example of a top view of the first semiconductor layer 171 and the second semiconductor layer 102 is shown in Figure 18. Figure 18 is a part of the top view of the laminate of the first semiconductor layer 171 and the second semiconductor layer 102. In Figure 18, the widened portion 122 is the region in which the width of the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 is widened, the narrowed portion 125 is the region in which the width of the laminate is not widened, the width of the gate region 121 in which the gate electrode 101 is formed (length in the channel length direction), and the width of the spacer region 127 in which the inner spacer 117 is formed (length in the channel length direction). As shown in Figure 18, when pattern formation using photolithography is performed to separate the laminate of the first semiconductor layer 171 and the second semiconductor layer 102, the boundary between the widened portion 122 and the narrowed portion 125 is not clearly formed by an acute angle, but rather a gently curved end face is formed. In this embodiment, the widened portion 122 is defined as the region whose width is wider than the narrowed portion 125, which becomes the connection portion 115 with the source and drain regions.

[0056] Next, as shown in Figures 19A and 19B, a sacrificial insulating layer 191, a first hard mask 192, a second hard mask 193, and a third hard mask 194 are laminated on a laminate of a first semiconductor layer 171 and a second semiconductor layer 102 that have been processed into a fin shape. Furthermore, a photoresist layer 195 is patterned on the third hard mask 194 using photolithography in the same shape as the gate electrode of the GAA-FET. The sacrificial insulating layer 191 is made of, for example, SiO ｘ The first hard mask 192 is formed from, for example, polysilicon or amorphous silicon (a-Si). The second hard mask 193 is formed from, for example, SiO ｘThe third hard mask 194 is formed of, for example, SiN. The sacrificial insulating layer 191 is formed on the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 using chemical vapor deposition (CVD) or the like. ｘ These layers are stacked. Then, a-Si is deposited on the sacrificial insulating layer 191 using chemical vapor deposition (CVD) or the like, and then planarized using chemical mechanical polishing (CMP) or the like to form a first hard mask 192. Furthermore, a second hard mask 193 and a third hard mask 194 are formed on the first hard mask 192 using CVD or the like.

[0057] Next, as shown in Figures 20A and 20B, a dummy gate 190 is formed. To form the dummy gate 190, first, the pattern of the photoresist layer 195 is transferred to the second hard mask 193 and the third hard mask 194 and processed to the same pattern as the gate electrode of the GAA-FET. Then, the patterns formed on the second hard mask 193 and the third hard mask 194 are transferred to the first hard mask 192 to form the dummy gate 190. The processing of the first hard mask 192, the second hard mask 193, and the third hard mask 194 is done using reactive ion etching (RIE), etc. Furthermore, as shown in Figures 20A and 20B, the sacrificial insulating layer 191 is removed using the dummy gate 190 as a mask and the pattern of the dummy gate 190 is transferred to the sacrificial insulating layer 191. For removing the sacrificial insulating layer 191, for example, chemical dry etching (CDE) or wet etching can be used.

[0058] Next, as shown in Figures 21A and 21B, gate spacers 119 are formed on the sacrificial insulating layer 191 and on the side surfaces of the dummy gate 190. Furthermore, as shown in Figures 21A and 21B, etching is performed through the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 from the exposed surface between the dummy gates 190 to separate the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 in the channel length direction. For example, gate spacers 119 are formed by using CVD or the like on the entire surface of the laminate of the first semiconductor layer 171 and the second semiconductor layer 102, the sacrificial insulating layer 191, and the dummy gate 190, using SiN, SiOCN, etc. Then, anisotropic etching such as RIE is performed on the formed gate spacers 119 and the fin-shaped laminate of the first semiconductor layer 171 and the second semiconductor layer 102. This process removes the gate spacers 119 from the top surface of the dummy gate 190 and the horizontal surface of the laminate of the first semiconductor layer 171 and the second semiconductor layer 102. The gate spacers 119 remain on the side surfaces of the dummy gate 190 and the side surfaces of the sacrificial insulating layer 191. The top surface of the dummy gate 190 and the top surface of the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 are exposed. Furthermore, anisotropic etching such as RIE is performed on the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 using the dummy gate 190 and the gate spacers 119 as masks. This forms a pillar-shaped laminate of the first semiconductor layer 171 and the second semiconductor layer 102 directly beneath the dummy gate 190 and the gate spacers 119.

[0059] Next, as shown in Figures 22A and 22B, an inner spacer 117 is formed on the side surface of the first semiconductor layer 171 that is exposed in the channel length direction. To form the inner spacer 117, first, the side surface of the first semiconductor layer 171 that is exposed in the channel length direction is selectively etched to remove a portion of the side surface of the first semiconductor layer 171. This creates a recess on the side surface of the first semiconductor layer 171 relative to the side surface of the second semiconductor layer 102. For selective etching of the side surface of the first semiconductor layer 171, isotropic etching such as atomic layer etching (ALE), quasi-ALE, or selective vapor phase etching is used. In this step, a method is used that allows for selective etching of high Ge concentration SiGe and Si and low Ge concentration SiGe. Then, the inner spacer 117 is embedded in the recess on the side surface of the second semiconductor layer 102 that has been formed. The inner spacer 117 is formed by depositing an insulating layer, such as SiN or SiBCN, on the dummy gate 190, the side surface of the gate spacer 119, the side surface of the laminate of the first semiconductor layer 171 and the second semiconductor layer 102, and on the substrate 110. At this time, the insulating layer is also embedded in the recesses formed on the side surface of the laminate of the first semiconductor layer 171 and the second semiconductor layer 102. Then, anisotropic etching such as RIE is performed to remove the inside of the recesses and remove the insulating layer exposed on the dummy gate 190, the side surface of the gate spacer 119, the side surface of the laminate of the first semiconductor layer 171 and the second semiconductor layer 102, and on the substrate 110. Through these steps, the inner spacer 117 is formed with the insulating layer remaining in the recesses.

[0060] Furthermore, as shown in Figures 23A and 23B, source and drain regions 106 are formed on the side surfaces of the laminate of the first semiconductor layer 171 and the second semiconductor layer 102. The source and drain regions 106 are formed, for example, by epitaxial growth of Si from the upper surface of the substrate 110 and the side surfaces of the second semiconductor layer 102. When forming a P-type GAA-FET, the source and drain regions 106 are formed by epitaxial growth of Si while supplying impurities such as B. When forming an N-type GAA-FET, the source and drain regions 106 are formed by epitaxial growth of Si while supplying impurities such as P, As, and Sb.

[0061] Next, as shown in Figures 24A and 24B, an insulating layer 124 is formed on the source / drain region 106, and the dummy gate 190 and sacrificial insulating layer 191 are removed. In this step, first, SiN or SiO is applied to the entire surface of the substrate 110. ｘ An insulating layer 124 is deposited. The insulating layer 124 is deposited to a position higher than the third hard mask 194 of the dummy gate 190. The insulating layer 124 is formed using, for example, CVD. Then, the surface is polished from the top of the insulating layer 124 using CMP or the like to remove the insulating layer 124, the third hard mask 194, and the upper part of the gate spacer 119, exposing the second hard mask 193. Furthermore, the exposed second hard mask 193, the first hard mask 192 below the second hard mask 193, and the sacrificial insulating layer 191 are removed. The removal of the second hard mask 193 is done using, for example, SiO ｘ Wet etching is performed on Si and Si using a chemical such as hydrogen fluoride that can selectively etch SiN. Furthermore, the first hard mask 192 is removed using, for example, plasma etching, which can selectively etch polysilicon and a-Si. The sacrificial insulating layer 191 is removed by etching the Si and low-Ge concentration SiGe constituting the second semiconductor layer 102 with SiO constituting the sacrificial insulating layer 191. ｘ A selective etching method, such as CDE or wet etching, is used.

[0062] Next, as shown in Figures 25A and 25B, the first semiconductor layer 171 is selectively removed. This exposes the interlayer of the second semiconductor layer 102. The removal of the first semiconductor layer 171 can be performed using, for example, dry etching with a mixed gas containing hydrogen fluoride and oxygen, or wet etching with a mixed solution of hydrogen fluoride and hydrogen peroxide, which can selectively etch high-Ge concentration SiGe against Si and low-Ge concentration SiGe. In this step, a step may also be performed to remove a portion of the surface side of the second semiconductor layer 102, as shown in Figure 35, which will be described later, thereby thinning the second semiconductor layer 102.

[0063] Next, as shown in FIGS. 26A and 26B, a gate electrode 101 is formed on the second semiconductor layer 102 and between the layers of the second semiconductor layer 102. To form the gate electrode 101, a gate insulating film (not shown) and a high-k dielectric material layer (not shown) are formed over the entire surface on the substrate 110. The gate insulating film is formed, for example, by thermal oxidation of the exposed surface of the second semiconductor layer 102. The high-k dielectric material layer is formed, for example, using ALD (Atomic Layer Deposition) to form hafnium dioxide (HfO ２ ), hafnium oxynitride (HfON), etc. Then, a metal material (gate metal) is filled over the gate insulating film and the high-k dielectric material layer, and the gate metal above the gate spacer 119 is removed using CMP or RIE. Thereby, the gate electrode 101 is formed. The gate electrode 101 is formed, for example, using CVD or the like with tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium (Nb), tungsten (W), etc.

[0064] Furthermore, as shown in FIGS. 26A and 26B, after removing the insulating layer 124, a contact wiring 120 connected to the source / drain region 106 is formed. The removal of the insulating layer 124 is performed, for example, using RIE or the like. Also, for the formation of the contact wiring 120, for example, a thin film such as TiN is formed over the entire surface on the gate spacer 119, the gate electrode 101, and the source / drain region 106, and then Cu or the like is deposited on this thin film. Then, unnecessary portions such as on the gate electrode 101 and the gate spacer 119 are removed, leaving the contact wiring 120 between the gate spacers 119. Through the above steps, the semiconductor device of the first embodiment can be manufactured.

[0065] In the above-described manufacturing method, in the step of separating the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 to form a fin-shaped laminate, a semiconductor layer (second semiconductor layer) 102 having a widened portion 122 and a narrowed portion 125 is formed using conventional photolithography. Therefore, the above-described manufacturing method can manufacture a semiconductor device having a widened portion 122 and a narrowed portion 125 without adding any steps to the conventional semiconductor device manufacturing process. Furthermore, in the above-described manufacturing method, in the step described with reference to Figure 17, a pattern having a widened portion and a narrowed portion is formed on the semiconductor layer (second semiconductor layer) 102, and the substrate 110 is etched and the STI 111 is embedded according to this pattern. The above-described manufacturing method does not have a step of widening the semiconductor layer 102 in a subsequent step. Therefore, as shown in Figure 26B, in the semiconductor device 100 manufactured by the above-described manufacturing method, the position of the edge of the semiconductor layer 102 which forms the channel region and the interface between the substrate 110 and the STI 111 coincide in the vertical direction in a cross-sectional view in the channel width direction.

[0066] Furthermore, in the above-described manufacturing method, depending on the processing accuracy of the photolithography, the boundary position between the widened portion 122 and the narrowed portion 125 becomes a gentle curve, as shown in Figure 18. In this configuration, the electric field concentration at the corner of the semiconductor layer that forms the channel region is mitigated at the boundary position between the widened portion 122 and the narrowed portion 125. As a result, in semiconductor devices manufactured by the above-described manufacturing method, current flows more easily from the channel region to the source and drain regions, and the channel resistance tends to decrease.

[0067] <3. Semiconductor device of the second embodiment and method for manufacturing a semiconductor device> An example of a method for manufacturing a semiconductor device of the second embodiment will be described below with reference to the drawings. In the description of the method for manufacturing a semiconductor device of the second embodiment, components similar to those described in the overview of the semiconductor device and method for manufacturing a semiconductor device of the first embodiment will be denoted by the same reference numerals and detailed descriptions will be omitted. Furthermore, the semiconductor device manufactured by the method for manufacturing a semiconductor device of the second embodiment has the same configuration as the semiconductor device of the first embodiment described above. For this reason, the components of the semiconductor device manufactured by the method for manufacturing a semiconductor device of the second embodiment will be denoted by the same reference numerals and detailed descriptions will be omitted.

[0068] [Method for Manufacturing a Semiconductor Device] The method for manufacturing a semiconductor device according to the second embodiment will now be described. An example of the method for manufacturing a semiconductor device according to the second embodiment is shown in Figures 27 to 36. Figures 27A, 29A, 30A, 31A, 32A, 33A, 34A, and 35A are planar layouts (top views) of the channel region, inner spacer, and source / drain region of the semiconductor device in the region enclosed by the dashed line shown in Figure 6. Figures 27B, 29B, 30B, 31B, 32B, 33B, 34B, and 35B are cross-sectional views of the semiconductor device shown in Figure 27A along the X-X line (cross-sectional view in the channel length direction). Figures 27C, 29C, 30C, 31C, 32C, 33C, 34C, and 35C are cross-sectional views of the semiconductor device shown in Figure 27A along the Y-Y line (cross-sectional view in the channel width direction). Figure 36A is a cross-sectional view along the X-X line (cross-sectional view in the channel length direction) of the semiconductor device shown in Figure 6. Figure 36B is a cross-sectional view along the Y-Y line (cross-sectional view in the channel width direction) of the semiconductor device shown in Figure 6.

[0069] The steps shown in Figures 27 to 36 correspond to the steps shown in Figures 17 and 19 to 26 in the semiconductor device manufacturing method of the first embodiment. The semiconductor device manufacturing method of the second embodiment can be applied to the same steps as the semiconductor device manufacturing method of the first embodiment described above, except for the steps described below. For this reason, the following description will only explain the steps that differ from the semiconductor device manufacturing method of the first embodiment described above.

[0070] First, in the semiconductor device manufacturing method of the first embodiment described above, the same steps as those described with reference to Figures 17 and 19 to 24 are performed. At this time, in the step shown in Figure 17, the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 is separated in a pattern without widened portions, as in the conventional method, and a fin-shaped laminate of the first semiconductor layer 171 and the second semiconductor layer 102 is formed.

[0071] Figures 27A, 27B, 27C, and 28 show the configuration of the first semiconductor layer 171, second semiconductor layer 102, inner spacer 117, gate spacer 119, and source / drain region 106 of the semiconductor device 100 after the process described using Figure 24 has been performed and the dummy gate and sacrificial insulating layer have been removed. As shown in Figure 27A, the semiconductor device 100 has a second semiconductor layer 102, a gate spacer 119, and a source / drain region 106. As shown in Figure 27A, the second semiconductor layer 102 is positioned between a pair of source / drain regions 106. The second semiconductor layer 102 is formed continuously from the gate lower region 112 to the source / drain region 106. The upper surfaces of both ends of the second semiconductor layer 102 on the source / drain region 106 side are covered by the gate spacer 119. In Figure 27A, the region of the second semiconductor layer 102 positioned below the gate spacer 119 is shown by a dashed line.

[0072] Furthermore, as shown in Figures 27B and 27C, a first semiconductor layer 171 and a second semiconductor layer 102 are stacked on the substrate 110. An inner spacer 117 is placed between the first semiconductor layer 171 and the source / drain region 106. The inner spacer 117 is stacked with the edge region of the second semiconductor layer 102 between the pair of source / drain regions 106.

[0073] Figure 28 is a side view of the semiconductor device shown in Figure 27A, viewed from the channel width direction. As shown in Figure 28, the inner spacer 117, and the first semiconductor layer 171 and second semiconductor layer 102 in the region stacked with the inner spacer 117, have their sides covered by the gate spacer 119. In Figure 28, the regions of the first semiconductor layer 171 and inner spacer 117 whose sides are covered by the gate spacer 119 are shown by dashed lines. The first semiconductor layer 171 and the second semiconductor layer 102 are exposed from the side in the channel width direction of the stack between the gate spacers 119. Furthermore, the uppermost second semiconductor layer 102 has its top surface exposed between the gate spacers 119.

[0074] Next, as shown in Figures 29A, 29B, and 29C, in the laminate of the first semiconductor layer 171 and the second semiconductor layer 102, a portion of the first semiconductor layer 171 exposed on the side surface in the channel width direction is removed. As a result, as shown in Figure 29C, a portion of the side surface of the first semiconductor layer 171 is removed, forming a recess on the side surface of the first semiconductor layer 171 relative to the side surface of the second semiconductor layer 102. Also, in the cross-sectional view shown in Figure 29B, the recess where the first semiconductor layer 171 was removed is positioned between the second semiconductor layers 102. Selective etching of the side surface of the first semiconductor layer 171 can be performed under the same conditions as the process described above using Figure 22.

[0075] Next, as shown in Figures 30A, 30B, and 30C, a first protective layer 129 is formed over the entire surface. This covers the entire surface of the first semiconductor layer 171, the second semiconductor layer 102, the gate spacer 119, and the source / drain region 106 with the first protective layer 129. Also, as shown in Figures 30B and 30C, the first protective layer 129 is embedded in the recess between the second semiconductor layers 102. The first protective layer 129 is formed, for example, using ALD and SiO ｘ This forms the second semiconductor layer 102, gate spacer 119, and source / drain region 106, which are covered by the first protective layer 129, are indicated by dashed lines.

[0076] Next, as shown in Figures 31A, 31B, and 31C, a second protective layer 130 is formed on top of the first protective layer 129. The second protective layer 130 is formed from a material with a lower etching rate than the first protective layer 129. For example, the second protective layer 130 is formed by anisotropic nitriding treatment of the first protective layer 129, nitriding only the upper surface of the first protective layer 129 to form SiN or the like. Alternatively, the second protective layer 130 may be formed by laminating SiN or the like on the first protective layer 129 using CVD or ALD.

[0077] Next, as shown in Figures 32A, 32B, and 32C, the second protective layer 130 and the first protective layer 129 formed on the channel width side of the second semiconductor layer 102 are removed. For example, high selectivity gas etching is performed on the first protective layer 129 and the second protective layer 130 to remove the first semiconductor layer 171 and the first protective layer 129 exposed on the side of the second semiconductor layer 102. Furthermore, RIE is used to remove the second protective layer 130 on the first protective layer 129 and the first protective layer 129 formed on the channel width side of the second semiconductor layer 102. As a result, as shown in Figures 32B and 32C, the channel width side edge of the second semiconductor layer 102 is exposed. In this step, as shown in Figures 32B and 32C, the first protective layer 129 is left in the recess formed on the side of the first semiconductor layer 171. Furthermore, as shown in Figures 32B and 32C, the first protective layer 129 is also left on top of the uppermost second semiconductor layer 102.

[0078] Next, as shown in Figures 33A, 33B, and 33C, epitaxial growth is performed from the side edge in the channel width direction of the exposed second semiconductor layer 102, expanding the second semiconductor layer 102 in the channel width direction. This epitaxial growth of the second semiconductor layer 102 forms a widened portion 122 on the exposed side of the second semiconductor layer 102. Furthermore, during epitaxial growth, the second semiconductor layer 102 grows not only in the width direction but also in the thickness direction (height relative to the substrate surface). Therefore, as shown in Figure 33C, the epitaxially grown portion of the second semiconductor layer 102 is thicker than the portion stacked between the first semiconductor layers 171. In addition, since the first protective layer 129 remains on top of the uppermost second semiconductor layer 102, an increase in the thickness of the second semiconductor layer 102 can be prevented. Furthermore, in the second semiconductor layer 102, the portion stacked between the gate spacer 119 and the inner spacer 117 does not undergo epitaxial growth because its side surface is covered by the gate spacer 119. As a result, in the second semiconductor layer 102, only the region with exposed side edges undergoes epitaxial growth, while the region covered by the gate spacer 119 does not grow. Consequently, as shown in Figure 33A, a widened portion 122 and a narrowed portion 125 are formed in the second semiconductor layer 102.

[0079] Next, as shown in Figures 34A, 34B, and 34C, the first protective layer 129 is removed. This exposes the first semiconductor layer 171, the second semiconductor layer 102, the gate spacer 119, and the source / drain region 106. The first protective layer 129 can be removed using, for example, chemical dry etching or wet etching.

[0080] Next, the same process as described using Figure 25 is performed to selectively remove the first semiconductor layer 171. Then, as shown in Figures 35A, 35B, and 35C, a portion of the surface side of the second semiconductor layer 102 is removed, thinning the second semiconductor layer 102. Due to the thinning, the second semiconductor layer 102 has a portion in the gate-under region 112 where the thickness in the stacking direction is smaller than the connection portion connected to the source-drain region 106. That is, the semiconductor layer 102 has a portion in the widened portion 122 which becomes the gate-under region 112 where the thickness in the stacking direction is smaller than the narrow portion 125 sandwiched between the gate spacer 119 and the inner spacer 117. In Figures 35B and 35C, the portion of the surface side of the second semiconductor layer 102 that has been removed is shown by a dashed line. In this process, along with the thinning of the second semiconductor layer 102, a portion of the exposed surface of the substrate 110 is also removed.

[0081] Next, the same process as described with reference to Figure 26 is performed to form a gate electrode 101 on the second semiconductor layer 102 and between the layers of the second semiconductor layer 102, as shown in Figures 36A and 36B. Furthermore, after removing the insulating layer 124, contact wiring 120 connected to the source / drain region 106 is formed. By performing the above steps, the semiconductor device of the second embodiment can be manufactured.

[0082] In the above-described manufacturing method, the source and drain regions 106 are formed by a second semiconductor layer 102 formed with a normal channel width, and then a widened portion 122 is formed only in the gate-lower region 112 (channel region) of the second semiconductor layer 102. In this manufacturing method, since the source and drain regions 106 are formed before the widened portion 122 is formed, the width of the source and drain regions 106 is not affected by the widening of the second semiconductor layer 102. For this reason, the above-described manufacturing method can apply conventionally known manufacturing methods up to the process of forming the source and drain regions 106, and since the width of the semiconductor layer 102 is not widened when forming the source and drain regions 106, the source and drain regions can be formed with the same size as conventional methods.

[0083] Furthermore, in the manufacturing method described above, in the process explained with reference to Figure 17, a pattern is formed on the laminate of the first semiconductor layer 171 and the second semiconductor layer 102, and the substrate 110 is etched and the STI 111 is embedded according to this pattern. Then, in the process explained with reference to Figure 33, the manufacturing method described above widens the second semiconductor layer 102. As a result, as shown in Figure 36B, in the cross-sectional view in the channel width direction of the semiconductor device 100 manufactured by the manufacturing method described above, the position of the widened portion of the semiconductor layer 102 which becomes the channel region and the position of the interface between the substrate 110 and the STI 111 do not coincide in the vertical direction. In the cross-sectional view in the channel width direction of the semiconductor device 100, the end of the widened portion of the semiconductor layer 102 protrudes toward the STI 111 side relative to the position of the interface between the substrate 110 and the STI 111.

[0084] Furthermore, the above-described manufacturing method allows for self-alignment and widening of the channel region. Therefore, compared to the manufacturing method of a semiconductor device in which the widened portion 122 is formed using the lithography process of the first embodiment described above, misalignment between the widened portion 122 of the semiconductor layer 102 and the gate-under region 112 is less likely to occur. As a result, the above-described manufacturing method allows for the production of semiconductor devices with higher precision.

[0085] <4. Semiconductor device of the third embodiment and method for manufacturing a semiconductor device> An example of a method for manufacturing a semiconductor device of the third embodiment will be described below with reference to the drawings. In the description of the method for manufacturing a semiconductor device of the third embodiment, components similar to those described in the overview of the method for manufacturing a semiconductor device of the first embodiment, the semiconductor device of the second embodiment, and the method for manufacturing a semiconductor device will be denoted by the same reference numerals and detailed descriptions will be omitted. Furthermore, the semiconductor device manufactured by the method for manufacturing a semiconductor device of the third embodiment has the same configuration as the semiconductor device of the first embodiment described above. For this reason, the components of the semiconductor device manufactured by the method for manufacturing a semiconductor device of the third embodiment will be denoted by the same reference numerals and detailed descriptions will be omitted.

[0086] [Method for Manufacturing a Semiconductor Device] The method for manufacturing a semiconductor device according to the third embodiment will now be described. An example of the method for manufacturing a semiconductor device according to the third embodiment is shown in Figures 37 to 49. Figures 37, 45, and 47 are schematic diagrams of the semiconductor device viewed from the top. Figures 38A, 39A, 40A, 41A, 42A, 43A, 44A, 46A, 48A, and 49A are planar arrangement diagrams (top views) of the channel region, inner spacer, and source / drain region of the semiconductor device in the area enclosed by the dashed line shown in Figure 37. Figures 38B, 39B, 40B, 41B, 42B, 43B, 44B, 46B, 48B, and 49B are cross-sectional views along the X-X line (cross-sectional view in the channel length direction) of the semiconductor device shown in Figure 27A. Figures 38C, 39C, 40C, 41C, 42C, 43C, 44C, 46C, 48C, and 49C are Y-Y line cross-sectional views (cross-sectional views in the channel width direction) of the semiconductor device shown in Figure 27A.

[0087] The steps shown in Figures 37 to 49 correspond to the steps shown in Figures 17 and 19 to 26 in the semiconductor device manufacturing method of the first embodiment. The semiconductor device manufacturing method of the third embodiment can be applied to the same steps as the semiconductor device manufacturing method of the first embodiment described above, except for the steps described below. For this reason, the following description will only explain the steps that differ from the semiconductor device manufacturing method of the first embodiment described above.

[0088] First, in the semiconductor device manufacturing method of the first embodiment described above, the same steps as those described with reference to Figure 17 are performed. In this step shown in Figure 17, the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 is separated in a pattern without widened portions, as in the conventional method, and a fin-shaped laminate of the first semiconductor layer 171 and the second semiconductor layer 102 is formed.

[0089] Next, as shown in Figure 37, a first protective layer 137 is formed with a pattern that leaves open only the region where the gate electrode is formed, i.e., the region that becomes the gate-under region 112 of the semiconductor layer 102, and covers the region other than the gate-under region 112. The first protective layer 137 is made of, for example, SiO ｘAfter forming the above over the entire surface, a pattern is formed using photolithography. Figures 38A, 38B, and 38C show a top view, an X-X cross-sectional view, and a Y-Y cross-sectional view of the channel region of the semiconductor device 100 in the state in which the first protective layer 137 has been formed. As shown in Figures 38A, 38B, and 38C, the semiconductor device 100 has a first semiconductor layer 171 and a second semiconductor layer 102 on the substrate 110. As shown in Figure 38B, the first semiconductor layer 171 and the second semiconductor layer 102 are formed continuously in the region covered by the first protective layer 137. In Figure 38B, the regions of the first semiconductor layer 171 and the second semiconductor layer 102 in the position covered by the first protective layer 137 are shown by dashed lines.

[0090] Next, as shown in Figures 39A, 39B, and 39C, in the laminate of the first semiconductor layer 171 and the second semiconductor layer 102, a portion of the first semiconductor layer 171 exposed on the side surface in the channel width direction is removed. As a result, as shown in Figure 39C, a portion of the side surface of the first semiconductor layer 171 is removed, forming a recess on the side surface of the first semiconductor layer 171 relative to the side surface of the second semiconductor layer 102. Also, in the cross-sectional view shown in Figure 39B, the recess where the first semiconductor layer 171 was removed is located between the second semiconductor layers 102. Selective etching of the side surface of the first semiconductor layer 171 can be performed under the same conditions as the process described above using Figure 22.

[0091] Next, as shown in Figures 40A, 40B, and 40C, a second protective layer 140 is formed on the surface of the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 that are exposed from the opening of the first protective layer 137. This covers the entire surface of the first semiconductor layer 171 and the second semiconductor layer 102 with the second protective layer 140. Then, as shown in Figures 40B and 40C, the second protective layer 140 is embedded in the recess between the second semiconductor layers 102. The second protective layer 140 is made of SiO using, for example, ALD. ｘ It forms.

[0092] Next, as shown in Figures 41A, 41B, and 41C, a third protective layer 141 is formed on top of the first protective layer 137 and the second protective layer 140. The third protective layer 141 is formed from a material with a lower etching rate than the first protective layer 137 and the second protective layer 140. For example, the third protective layer 141 is formed by anisotropic nitriding treatment of the first protective layer 137 and the second protective layer 140, nitriding only the upper surfaces of the first protective layer 137 and the second protective layer 140 to form SiN or the like. Alternatively, the third protective layer 141 may be formed by laminating SiN or the like on the second protective layer 140 using CVD or ALD.

[0093] Next, as shown in Figures 42A, 42B, and 42C, the third protective layer 141 and the second protective layer 140 formed on the channel width side of the second semiconductor layer 102 are removed. For example, high selectivity gas etching is performed on the second protective layer 140 and the third protective layer 141 to remove the first semiconductor layer 171 and the second protective layer 140 exposed on the side of the second semiconductor layer 102. Furthermore, RIE is used to remove the third protective layer 141 on the second protective layer 140 and the second protective layer 140 formed on the channel width side of the second semiconductor layer 102. As a result, as shown in Figures 42B and 42C, the channel width side edge of the second semiconductor layer 102 is exposed. In this step, as shown in Figures 42B and 42C, the second protective layer 140 is left in the recess formed on the side of the first semiconductor layer 171. Furthermore, as shown in Figures 42B and 42C, the second protective layer 140 is also left on top of the uppermost second semiconductor layer 102.

[0094] Next, as shown in Figures 43A, 43B, and 43C, epitaxial growth is performed from the side edge in the channel width direction of the exposed second semiconductor layer 102, expanding the second semiconductor layer 102 in the channel width direction. This epitaxial growth of the second semiconductor layer 102 forms a widened portion 122 on the exposed side of the second semiconductor layer 102. Furthermore, during epitaxial growth, the second semiconductor layer 102 grows not only in the width direction but also in the thickness direction (height relative to the substrate surface). Therefore, as shown in Figure 43C, the epitaxially grown portion of the second semiconductor layer 102 is thicker than the portion stacked between the first semiconductor layers 171. In addition, since the second protective layer 140 remains on top of the uppermost second semiconductor layer 102, an increase in the thickness of the second semiconductor layer 102 can be prevented. Furthermore, in the second semiconductor layer 102, the portion covered by the first protective layer 137 does not undergo epitaxial growth. Therefore, in the second semiconductor layer 102, only the region with exposed side edges undergoes epitaxial growth, while the region covered by the first protective layer 137 does not grow. As a result, as shown in Figure 43A, a widened portion 122 and a narrowed portion 125 are formed in the second semiconductor layer 102.

[0095] Next, as shown in Figures 44A, 44B, and 44C, a sacrificial insulating layer 191 is formed on the second semiconductor layer 102 that is exposed through the opening of the first protective layer 137. This covers the entire surface of the second semiconductor layer 102 exposed through the opening of the first protective layer 137 with the second protective layer 140 and the sacrificial insulating layer 191.

[0096] Next, as shown in Figures 45, 46A, 46B, and 46C, a first hard mask 192 is formed on the sacrificial insulating layer 191 exposed from the opening of the first protective layer 137. Then, as shown in Figures 47, 48A, 48B, and 48C, the first protective layer 137 is removed. In Figure 48B, the regions of the first semiconductor layer 171 and the second semiconductor layer 102 in the narrow portion 125 that do not appear in the X-X cross section are shown with dashed lines. Through the above process, the semiconductor device 100 has the same configuration as in the process described using Figure 19, where the sacrificial insulating layer 191 and the first hard mask 192 are formed on a laminate of the fin-shaped first semiconductor layer 171 and the second semiconductor layer 102. In the process described thereafter using Figure 19, a second hard mask 193 and a third hard mask 194 are formed, and a photoresist layer 195 is patterned on the third hard mask 194 in the same shape as the gate electrode of the GAA-FET.

[0097] Next, the same process as described using Figure 20 above is performed to form the dummy gate 190. Then, the same process as described using Figure 21 above is performed to form gate spacers 119 on the sacrificial insulating layer 191 and on the side surface of the first hard mask 192 (dummy gate 190), as shown in Figures 49A, 49B, and 49C. Subsequently, the same process as described using Figures 21 to 26 above and the process described using Figure 35 above is performed to manufacture the semiconductor device 100 with the configuration shown in Figure 36 above.

[0098] In the above-described manufacturing method, before separating the laminate of the first semiconductor layer 171 and the second semiconductor layer 102 in the channel length direction, a widened portion 122 is formed only in the channel region of the second semiconductor layer 102. When forming the widened portion 122, the second semiconductor layer 102 at the connection portion with the source / drain region is covered with a protective layer. As a result, the connection portion is not widened, and the formation width of the source / drain region 106 is not affected by the widening of the second semiconductor layer 102. Therefore, the above-described manufacturing method allows the source / drain region to be formed at the same size as in the conventional method.

[0099] Furthermore, in the manufacturing method described above, in the process explained with reference to Figure 17, a pattern is formed on the laminate of the first semiconductor layer 171 and the second semiconductor layer 102, and the substrate 110 is etched and the STI 111 is embedded according to this pattern. Then, in the manufacturing method described with reference to Figure 43, the second semiconductor layer 102 is widened. For this reason, as shown in Figure 36B, in the cross-sectional view in the channel width direction of the semiconductor device 100 manufactured by the manufacturing method described above, the position of the widened portion of the semiconductor layer 102 which becomes the channel region and the position of the interface between the substrate 110 and the STI 111 do not coincide in the vertical direction. In the cross-sectional view in the channel width direction of the semiconductor device 100, the end of the widened portion of the semiconductor layer 102 protrudes toward the STI 111 side relative to the position of the interface between the substrate 110 and the STI 111.

[0100] Furthermore, the above-described manufacturing method allows for the self-alignment of the gate electrode in the widened channel region. Therefore, compared to the semiconductor device manufacturing method using the lithography process of the first embodiment described above, misalignment between the widened portion 122 of the semiconductor layer 102 and the gate-under region 112 is less likely to occur. As a result, the above-described manufacturing method allows for the production of semiconductor devices with higher precision.

[0101] It should be noted that the present invention is not limited to the configuration described in the above-described embodiments, and various modifications and changes are possible without departing from the configuration of the present invention.

[0102] 10, 20, 100... Semiconductor device, 11, 21, 101... Gate electrode, 12, 13, 22, 23, 103... Semiconductor layer, 15, 25, 110... Substrate, 16, 17, 26, 27, 106, 107... Source / drain region, 28, 29, 115... Connection portion, 102... Semiconductor layer (second semiconductor layer), 111... STI, 112, 113... Gate sub-region, 117... Inner spacer, 119... Gate spacer, 120... Contact wiring, 121... Gate Region, 122... Widened portion, 124... Insulating layer, 125... Narrowed portion, 126, 128... Electrode, 127... Spacer region, 129, 137... First protective layer, 130, 140... Second protective layer, 141... Third protective layer, 151, 152, 161, 162... Graph, 171... First semiconductor layer, 190... Dummy gate, 191... Sacrificial insulating layer, 192... First hard mask, 193... Second hard mask, 194... Third hard mask, 195... Photoresist layer

Claims

1. A semiconductor device comprising a substrate and a nanosheet transistor formed on the substrate, wherein the nanosheet transistor comprises: a semiconductor layer that forms a channel region formed by a nanosheet; a gate electrode laminated on the semiconductor layer; a source / drain region disposed on the side surface of the laminate of the semiconductor layer and the gate electrode and connected to the semiconductor layer; and an inner spacer formed between the gate electrode and the source / drain region between the laminated semiconductor layers, wherein the semiconductor layer has a widened portion in the region overlapping with the gate electrode in a planar arrangement in the stacking direction of the semiconductor layer and the gate electrode, the length in the channel width direction being greater than the portion connected to the source / drain region.

2. The semiconductor device according to claim 1, wherein the semiconductor layer has a constant length in the channel width direction in the region overlapping with the gate electrode.

3. The semiconductor device according to claim 1, wherein the semiconductor layer has a widened portion with a large length in the channel width direction, extending from the region overlapping with the gate electrode to the region overlapping with the inner spacer.

4. The semiconductor device according to claim 1, wherein the semiconductor layer has a curved end face at the end in the channel length direction of the side end in the channel width direction in the widened portion where the length in the channel width direction is large.

5. The semiconductor device according to claim 1, wherein the semiconductor layer, in the region overlapping with the gate electrode, has a thickness in the stacking direction that is smaller than the portion connected to the source and drain regions.

6. A method for manufacturing a semiconductor device comprising a substrate and a nanosheet transistor formed on the substrate, comprising: forming a laminate on the substrate of a first semiconductor layer which will be a sacrificial layer and a second semiconductor layer which will be a channel region; separating the laminate of the first semiconductor layer and the second semiconductor layer in the channel width direction; forming a sacrificial insulating layer and a dummy gate on the laminate; transferring the pattern of the dummy gate to the sacrificial insulating layer; forming gate spacers on the side surfaces of the sacrificial insulating layer and the dummy gate; replacing a part of the side surface of the first semiconductor layer with an inner spacer; forming source and drain regions on the side surface of the second semiconductor layer by epitaxial growth; removing the dummy gate, the sacrificial insulating layer and the first semiconductor layer; and forming a gate electrode in the region where the dummy gate, the sacrificial insulating layer and the first semiconductor layer have been removed. A method for manufacturing a semiconductor device, comprising forming a widened portion in the second semiconductor layer, in a region overlapping the gate electrode, where the widened portion has a longer length in the channel width direction than the portion connected to the source and drain regions.

7. The method for manufacturing a semiconductor device according to claim 6, wherein, in the step of separating the laminate of the first semiconductor layer and the second semiconductor layer in the channel width direction, the widened portion is patterned in the region that overlaps with the gate electrode in a planar arrangement by photolithography.

8. A method for manufacturing a semiconductor device according to claim 6, further comprising the step of removing the dummy gate, the sacrificial insulating layer, and the first semiconductor layer, and then growing the second semiconductor layer exposed from the side surface in the channel width direction of the laminate between the gate spacers to form the widened portion.

9. A method for manufacturing a semiconductor device according to claim 6, further comprising the step of separating the laminate of the first semiconductor layer and the second semiconductor layer in the channel width direction, and then growing the second semiconductor layer exposed from the side surface of the laminate in the channel width direction to form the widened portion.

10. The method for manufacturing a semiconductor device according to claim 6, further comprising the step of removing a portion of the surface side of the second semiconductor layer on which the widened portion is formed, thereby thinning the second semiconductor layer.

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