Semiconductor device

Abstract

A semiconductor device includes a block, a light-emitting element physically and electrically coupled to the block with a solder layer, and an insulating film disposed between the block and the light-emitting element such that the insulating film is disposed adjacent to the solder layer on a plane substantially defined by the solder layer, wherein the insulating film has a raised step portion.

Description

SEMICONDUCTOR DEVICECROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority of U.S. Provisional Patent Application No. 63 / 739,347 filed December 27, 2024 the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device.

[0003] For example, PTL 1 discloses a semiconductor laser light source in which a barrier layer is provided between a semiconductor laser and a submount. The barrier layer includes a wall part at a part excluding a part corresponding to an output end side of the semiconductor laser.

[0004] [PTL 1] Japanese Unexamined Patent Application Publication No. 2015-173218Summary

[0005] Incidentally, it is desired to improve a manufacturing yield of a semiconductor device.

[0006] It is desirable to provide a semiconductor device that makes it possible to improve a manufacturing yield.

[0007] A semiconductor device according to example embodiments of the present disclosure includes a block, a light-emitting element physically and electrically coupled to the block with a solder layer, and an insulating film disposed between the block and the light-emitting element such that the insulating film is disposed adjacent to the solder layer on a plane substantially defined by the solder layer, wherein the insulating film has a raised step portion.

[0008] In the semiconductor device according to the embodiment of the present disclosure, the insulating film including the step part on the upper surface of the insulating film is provided on the bonding surface, of the bonding object, to which the semiconductor light-emitting element is bonded. The coupling pad and the conductor layer are further provided on the bonding surface of the bonding object. The conductor layer is provided on the coupling pad and bonds the semiconductor light-emitting element and the bonding object to each other. The insulating film is provided to so extend on both the bonding surface and the peripheral part of the coupling pad as to surround the conductor layer. This prevents excessive wetting and spreading of the conductor layer.

[0009] Fig. 1 is a perspective diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present disclosure.Fig. 2 is an exploded perspective view of the semiconductor device illustrated in Fig. 1.Fig. 3 is a schematic diagram illustrating a front configuration example of the semiconductor device illustrated in Fig. 1.Fig. 4 includes an upper surface diagram (A) and cross-sectional diagrams (B) and (C) each illustrating a configuration example of a submount illustrated in Fig. 1.Fig. 5 is a schematic cross-sectional diagram illustrating an example of bonding between a semiconductor laser element and the submount in the semiconductor device illustrated in Fig. 1.Fig. 6 is a schematic cross-sectional diagram illustrating a process of bonding the semiconductor laser element and the submount to each other in the semiconductor device illustrated in Fig. 1.Fig. 7 is a schematic cross-sectional diagram illustrating another example of the bonding between the semiconductor laser element and the submount in the semiconductor device.Fig. 8 is a schematic cross-sectional diagram illustrating a configuration example of a submount according to Modification example 1 of the present disclosure.Fig. 9 is a schematic cross-sectional diagram illustrating a process of bonding the semiconductor laser element and a submount illustrated in Fig. 8 to each other.Fig. 10 is a schematic cross-sectional diagram illustrating an example of bonding between the semiconductor laser element and the submount illustrated in Fig. 8.Fig. 11 is a schematic cross-sectional diagram illustrating an example of a configuration of a semiconductor device according to Modification example 2 of the present disclosure.Fig. 12 is a schematic cross-sectional diagram illustrating another example of the configuration of the semiconductor device according to Modification example 2 of the present disclosure.Fig. 13 is a perspective diagram illustrating a configuration example of a semiconductor device according to Modification example 3 of the present disclosure.Fig. 14 is a perspective diagram illustrating a configuration example of a semiconductor device according to Modification example 4 of the present disclosure.

[0010] Hereinafter, a description is given in detail of embodiments of the present disclosure with reference to the drawings.

[0011] The drawings to be referred to in the following description are intended to describe embodiments of the present disclosure and facilitate understanding thereof; shapes, dimensions, ratios, and the like illustrated in the drawings may differ from actual ones, in some cases, for better understanding. Further, the design of the semiconductor device illustrated in the drawings can be modified as appropriate by taking into consideration the following description and publicly known techniques. In addition, in the description using the cross-sectional view of the semiconductor device, the up / down direction of the stacked structure of the semiconductor device corresponds to a relative direction in a case where an external electrode to be wire-bonded is defined as being the top. The up / down direction may differ, in some cases, from an up / down direction that is compliant with the actual gravitational acceleration.

[0012] In the following description, expressions regarding a size and a shape do not only mean the same values as a numerical value defined mathematically or a shape defined geometrically. The expressions regarding a size and a shape also include a shape in a case of having an industrially acceptable difference in a process of manufacturing the semiconductor device, a shape similar thereto, and the like.

[0013] In the description of the semiconductor device, unless otherwise specified, "coupling" means electrical coupling between a plurality of components. Additionally, "coupling" in the following description includes not only a case of coupling a plurality of components directly and electrically, but also a case of coupling the plurality of components indirectly and electrically via another component. It is to be noted that the description is given in the following order. 1. Embodiment (An example of a semiconductor device in which an insulating film including a step part on an upper surface thereof is so provided on a bonding surface of a submount as to surround a solder layer bonding a semiconductor laser element and the submount to each other) 2. Modification Examples 2-1. Modification Example 1 (Another example of the configuration of the insulating film) 2-2. Modification Example 2 (Another example of the configuration of the insulating film) 2-3. Modification Example 3 (Another example of the configuration of the semiconductor device) 2-4. Modification Example 4 (Another example of the configuration of the semiconductor device) <1. Embodiment>

[0014] Fig. 1 is a perspective diagram illustrating a configuration example of a semiconductor device 1 according to an embodiment of the present disclosure. Fig. 2 is an exploded perspective view of the semiconductor device 1 illustrated in Fig. 1. Fig. 3 schematically illustrates a front configuration of the semiconductor device 1 illustrated in Fig. 1. The semiconductor device 1 is used as, for example, a light source or a heat source of an electronic apparatus.

[0015] The semiconductor device 1 includes, for example, a submount 20 and a semiconductor laser element 10 that is mounted on a mounting surface Sb1 of the submount 20. The submount 20 includes, on the mounting surface Sb1, a coupling electrode Ec to which the semiconductor laser element 10 is bonded. A solder layer 30 is provided on the coupling electrode Ec. The semiconductor laser element 10 and the submount 20 are bonded to each other by the solder layer 30. The mounting surface Sb1 is further provided with an insulating film 23. The insulating film 23 is provided to so extend on both the mounting surface Sb1 and a peripheral part of the coupling electrode Ec as to surround the solder layer 30. A step part X is provided on an upper surface 23S1 (see Fig. 5) of the insulating film 23.

[0016] Here, the semiconductor laser element corresponds to a specific example of a "semiconductor light-emitting element" according to one embodiment of the present disclosure. The submount 20 corresponds to a specific example of a "bonding object" according to one embodiment of the present disclosure. The mounting surface Sb1 corresponds to a specific example of a "bonding surface" according to one embodiment of the present disclosure. The coupling electrode Ec corresponds to a specific example of a "coupling pad" according to one embodiment of the present disclosure. The solder layer 30 corresponds to a specific example of a "conductive layer" according to one embodiment of the present disclosure. The insulating film 23 corresponds to a specific example of an "insulating film" according to one embodiment of the present disclosure, and the step part X corresponds to a specific example of a "step part" according to one embodiment of the present disclosure. { Configuration of Semiconductor Device }

[0017] The semiconductor device 1 includes the semiconductor laser element 10, the submount 20, the solder layer 30, external electrodes Ea and Eb, and the coupling electrode Ec.

[0018] The semiconductor laser element 10 is, for example, a type of edge-emitting semiconductor laser element, and includes a pair of end surfaces (resonator end surfaces Sa1 and Sa2) opposed to each other in a resonator direction. The resonator end surface Sa1 is, for example, a light output surface through which a laser beam is outputted to an outside. The semiconductor laser element 10 further includes: a ridge part 11 extending in a direction in which the resonator end surfaces Sa1 and Sa2 are opposed to each other (here, a Y-axis direction); and a pair of trenches 12 that allows the ridge part 11 to be provided. The resonator end surfaces Sa1 and Sa2 are surfaces formed by cleaving. The resonator end surfaces Sa1 and Sa2 serve as resonator mirrors, and the ridge part 11 serves as an optical waveguide. The semiconductor laser element 10 further includes a pair of side surfaces Sa3 and Sa4 opposed to each other in a direction orthogonal to an extending direction of the ridge part 11.

[0019] As illustrated in Fig. 3, the semiconductor laser element 10 includes, for example, a semiconductor stack section 110 in which a substrate 111, a buffer layer 112, a lower clad layer 113, an active layer 114, an upper clad layer 115, and a contact layer 116 are stacked in this order. The semiconductor stack section 110 corresponds to a specific example of a "semiconductor layer" of the present disclosure. An upper surface of the semiconductor stack section 110 (an upper surface of the contact layer 116) is referred to as an upper surface 10S1 of the semiconductor laser element 10, and a lower surface of the semiconductor stack section 110 (a surface, of the substrate 111, opposite to a surface on which the above-described semiconductor layers are provided) is referred to as a lower surface 10S2. The ridge part 11 is provided on the upper surface 10S1 of the semiconductor laser element 10. For example, each of the pair of trenches 12 that allows the ridge part 11 to be provided penetrates the contact layer 116, and includes a bottom surface within the upper clad layer 115. The semiconductor laser element 10 further includes an upper electrode 117 on the contact layer 116 of the ridge part 11, and further includes a lower electrode 118 on a back surface of the substrate 111. The semiconductor laser element 10 further includes a dielectric film 13. The dielectric film 13 is provided on side surfaces and the bottom surfaces of the pair of trenches 12 as well as the contact layer 116 positioned outside the pair of trenches 12.

[0020] The semiconductor stack section 110 includes, for example, a group III-V compound semiconductor such as gallium arsenide (GaAs). Here, the term "group III-V semiconductor" refers to a semiconductor including: at least one out of group 3B elements (at least one element out of Ga, Al, In, and B) in the short-form periodic table; and at least As out of group 5B elements in the short-form periodic table. Examples of the group III-V compound semiconductor include gallium arsenide-based compounds each including gallium (Ga) and arsenic (As). Examples of the gallium arsenide-based compounds include gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), and the like. The group III-V compound semiconductor is doped with an n-type impurity of a group IV or group VI element such as silicon (Si), germanium (Ge), oxygen (O), or selenium (Se), or with a p-type impurity of a group II or group IV element such as magnesium (Mg), zinc (Zn), or carbon (C), as necessary.

[0021] For example, the substrate 111 may be a group III-V compound semiconductor substrate such as a GaAs substrate. The substrate 111 may be an aluminum nitride (AlN) substrate, a sapphire substrate, a silicon carbide (SiC) substrate, a Si substrate, or a zirconium oxide (ZrO) substrate.

[0022] The buffer layer 112 is adapted to mitigate a lattice mismatch between the substrate 111 and the lower clad layer 113. In a case where the substrate 111 and the lower clad layer 113 have different lattice constants, the buffer layer 112 is controlled in the lattice constant to have a more favorable crystalline state. This makes it possible to suppress a crystal defect and further prevent warping of the substrate 111. The buffer layer 112 is provided on, for example, a main surface of the substrate 111, and includes, for example, a semiconductor layer (an n-type semiconductor layer) having n-type conductivity. The buffer layer 112 includes, for example, a GaAs layer, an AlGaAs layer, or both. The buffer layer 112 includes, for example, Si as a dopant adapted to provide n-type conductivity.

[0023] The lower clad layer 113 corresponds to a specific example of a "first-conductivity-type layer" according to one embodiment of the present disclosure. The lower clad layer 113 is provided on, for example, the buffer layer 112, and includes, for example, a semiconductor layer (an n-type semiconductor layer) having n-type conductivity. The lower clad layer 113 includes, for example, an AlGaAs layer. The lower clad layer 113 includes, for example, Si as a dopant adapted to provide n-type conductivity.

[0024] The active layer 114 corresponds to a specific example of an "active layer" according to one embodiment of the present disclosure. The active layer 114 is provided on, for example, the lower clad layer 113. The active layer 114 is provided between the lower clad layer 113 and the upper clad layer 115. The active layer 114 has, for example, a multi-well structure in which barrier layers and well layers are alternately stacked. The active layer 114 may have a multi-quantum well structure.

[0025] Each of the well layers includes Ga and a group III-V compound semiconductor. Each of the well layers includes a non-doped semiconductor layer. Each of the well layers generates a photon having a wavelength of 780 nm to 1700 nm, for example.

[0026] Each of the barrier layers includes a group III-V compound semiconductor. Each of the barrier layers includes a non-doped semiconductor layer. Each of the barrier layers has a bandgap having a value greater than or equal to, for example, a maximum bandgap of each of the well layers.

[0027] The upper clad layer 115 corresponds to a specific example of a "second-conductivity-type layer" according to one embodiment of the present disclosure. The upper clad layer 115 is provided on the active layer 114. The upper clad layer 115 includes, for example, a semiconductor layer (a p-type semiconductor layer) having p-type conductivity. The upper clad layer 115 includes, for example, an AlGaAs layer. The upper clad layer 115 includes, for example, C as a dopant adapted to provide p-type conductivity.

[0028] The contact layer 116 is provided on, for example, the upper clad layer 115, and includes, for example, a semiconductor layer (a p-type semiconductor layer) having p-type conductivity. The contact layer 116 includes, for example, a GaAs layer, an AlGaAs layer, or both. The contact layer 116 includes, for example, C as a dopant adapted to provide p-type conductivity.

[0029] The pair of trenches 12 allows the ridge part 11 to be provided in an upper part of the semiconductor stack section 110, specifically, in the contact layer 116 and a part of the upper clad layer 115. The ridge part 11 extends in one direction (the resonator direction) in a stacking plane of the semiconductor stack section 110. In other words, the ridge part 11 extends in the direction in which the resonator end surfaces Sa1 and Sa2 are opposed to each other (here, the Y-axis direction), as described above. Further, in other words, the ridge part 11 is sandwiched between the pair of resonator end surfaces Sa1 and Sa2 of the semiconductor stack section 110. The ridge part 11 is formed by, for example, performing etching removal from the upper surface of the contact layer 116 to the middle of the upper clad layer 115.

[0030] The upper electrode 117 is provided on the contact layer 116 and in contact with an upper surface of the ridge part 11. The upper electrode 117 has, for example, a configuration in which a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer are stacked in this order from a side closer to the contact layer 116. It is sufficient for the upper electrode 117 to be electrically coupled to the contact layer 116, and a layer configuration of the upper electrode 117 is not limited to the configuration described above. Further, the upper electrode 117 may be in contact with the entirety of the upper surface of the contact layer 116, or may be in contact with only a part of the upper surface of the contact layer 116.

[0031] For example, the lower electrode 118 is provided in contact with a lower surface of the substrate 111. The lower electrode 118 applies a voltage to the active layer 114 from a side closer to the lower clad layer 113. The lower electrode 118 has, for example, a configuration in which an AuGe layer, an Ni layer, and an Au layer are stacked in this order from a side closer to the substrate 111. It is sufficient for the lower electrode 118 to be electrically coupled to the substrate 111, and a layer configuration of the lower electrode 118 is not limited to the configuration described above. Further, the lower electrode 118 may be in contact with the entirety of the lower surface of the substrate 111, or may be in contact with only a part of the lower surface of the substrate 111.

[0032] The dielectric film 13 covers the side surfaces and the bottom surfaces of the pair of trenches 12, as well as a part, of the upper surface 10S1 of the semiconductor stack section 110, positioned outside the pair of trenches 12 that allows the ridge part 11 to be provided. The dielectric film 13 includes, for example, silicon oxide (SiO2).

[0033] The resonator end surfaces Sa1 and Sa2 may each be provided with an end surface coating film. The end surface coating film is, for example, a multilayer reflective film or an antireflection film. The multilayer reflective film includes, for example, a dielectric such as SiO2, titanium oxide (TiO2), tantalum oxide (Ta2O5), or silicon nitride (SiN). The multilayer reflective film is provided on the resonator end surface Sa1 serving as the light output surface. The antireflection film includes, for example, a dielectric (e.g., SiO2, TiO2, Ta2O5, SiN, or the like) and Si. The antireflection film is provided on the resonator end surface Sa2.

[0034] In the semiconductor laser element 10 of the present embodiment, when a predetermined voltage is applied between the upper electrode 117 and the lower electrode 118, a current is injected into the active layer 114, which causes light emission to occur owing to recombination of electrons and holes. The light is repeatedly reflected by the pair of resonator end surfaces Sa1 and Sa2 and then outputted from one of the end surfaces (the resonator end surface Sa1) as a laser beam of a predetermined wavelength. In this way, laser oscillation is performed.

[0035] The external electrode Ea is provided on the upper surface 10S1 of the semiconductor laser element 10. The external electrode Ea is, for example, a metal layer to which a bonding wire is bonded. The external electrode Ea includes, for example, Ti and Au in this order from a side closer to the upper electrode 117 and the dielectric film 13. The external electrode Ea is electrically coupled to the upper surface of the ridge part 11 via the upper electrode 117. The external electrode Ea may be provided collectively with the upper electrode 117.

[0036] The submount 20 includes a block 21. The block 21 includes the mounting surface Sb1 on which the semiconductor laser element 10 is mounted and a bonding end surface Sb2 having a normal line that intersects a normal line of the mounting surface Sb1. The block 21 further includes, as surfaces thereof, a non-bonding end surface Sb3 and a pair of side surfaces Sb4 and Sb5. The non-bonding end surface Sb3 is opposed to the bonding end surface Sb2. The side surfaces Sb4 and Sb5 each have a normal line that intersects each of the normal line of the mounting surface Sb1 and the normal line of the bonding end surface Sb2. The block 21 includes an insulating material having a high heat dissipation property. The block 21 includes, for example, AlN, Si, SiC, copper (Cu), tungsten (W), molybdenum (Mo), aluminum (Al), diamond, a composite material including any of these materials, or the like. Examples of such a composite material include Cu-W, Al-SiC, and the like.

[0037] The bonding end surface Sb2, the non-bonding end surface Sb3, and the side surfaces Sb4 and Sb5 are side surfaces of the block 21. The block 21 is larger in size than the semiconductor laser element 10. Specifically, the mounting surface Sb1 of the block 21 is larger in size than the lower electrode 118 of the semiconductor laser element 10. The semiconductor laser element 10 is so bonded to the mounting surface Sb1 that, for example, the ridge part 11 is at a position opposed to a center position, of the mounting surface Sb1, in a width direction of the ridge part 11. For example, the resonator end surface Sa1 is disposed at a position close to the bonding end surface Sb2. For example, the resonator end surface Sa2 is disposed at a position distant from the non-bonding end surface Sb3, as compared with a distance between the resonator end surface Sa1 and the bonding end surface Sb2. For example, the side surface Sa3 is disposed at a position close to the side surface Sb4. For example, the side surface Sa4 is disposed at a position distant from the side surface Sb5, as compared with a distance between the side surface Sa3 and the side surface Sb4. The position of the semiconductor laser element 10 on the mounting surface Sb1 is not limited to the position described above.

[0038] The bonding end surface Sb2 is, for example, a bonding surface to be bonded to an external component. The semiconductor laser element 10 is bonded to the external component via the submount 20.

[0039] The bonding end surface Sb2 is provided with a bonding metal layer 22. The bonding metal layer 22 is bonded to the external component via, for example, solder. The bonding metal layer 22 includes, for example, Ti, Pt, and Au in this order from a side closer to the bonding end surface Sb2. It is sufficient for the bonding metal layer 22 to be able to be in close contact with the bonding end surface Sb2, and a layer configuration of the bonding metal layer 22 is not limited to the configuration described above.

[0040] The mounting surface Sb1 is provided with the external electrode Eb and the coupling electrode Ec. The external electrode Eb is, for example, a metal layer to which the bonding wire is bonded. The lower electrode 118 of the semiconductor laser element 10 is bonded to the coupling electrode Ec via the solder layer 30. The external electrode Eb and the coupling electrode Ec each include, for example, Ti, Pt, and Au in this order from a side closer to the block 21. It is sufficient for each of the external electrode Eb and the coupling electrode Ec to be able to be in close contact with the mounting surface Sb1 of the block 21, and a layer configuration of each of the external electrode Eb and the coupling electrode Ec is not limited to the configuration described above. Each of the external electrode Eb and the coupling electrode Ec may be, for example, a single-layer film including Au. Each of the external electrode Eb and the coupling electrode Ec may be, for example, a stacked film that includes Au and an aluminum-silicon alloy (AlSi) in this order from a side closer to the bonding end surface Sb2.

[0041] The solder layer 30 is adapted to bond the semiconductor laser element 10 and the submount 20 to each other. The solder layer 30 is, for example, so provided between the lower electrode 118 and the coupling electrode Ec as to bond the lower surface 10S2 of the semiconductor laser element 10 and the mounting surface Sb1 of the submount 20 to each other. The solder layer 30 includes, for example, AuSn (gold-tin). That is, the semiconductor laser element 10 and the submount 20 are eutectically bonded to each other by, for example, AuSn. The semiconductor laser element 10 and the submount 20 may be bonded to each other by a silver (Ag) paste, sintered gold (Au), sintered silver (Ag), or the like.

[0042] Fig. 4 schematically illustrates each of a configuration of an upper surface of the submount 20 in (A) and configurations of cross-sections of the submount 20 in (B) and (C). Note that (B) and (C) of Fig. 4 each illustrate the cross-section corresponding to that taken along line I-I' line illustrated in (A) of Fig. 4. (B) of Fig. 4 illustrates a state in which a solder paste 30A is applied on the coupling electrode Ec. (C) of Fig. 4 illustrates a state in which the solder paste 30A applied on the coupling electrode Ec is melted. Fig. 5 schematically illustrates a bonding state of the semiconductor laser element 10 and the submount 20 corresponding to the cross-section taken along the line I-I'.

[0043] The mounting surface Sb1 is provided with the insulating film 23, as described above. The insulating film 23 is adapted to prevent excessive wetting and spreading of the molten solder paste 30A on the mounting surface Sb1 when the semiconductor laser element 10 is bonded to the submount 20 via the solder layer 30. The insulating film 23 is also adapted to prevent the coupling electrode Ec from falling off from the mounting surface Sb1. The insulating film 23 is also adapted to suppress, for example, turning and inclining of the semiconductor laser element 10 after the semiconductor laser element 10 is bonded to the submount 20 via the solder layer 30. As will be described later, the insulating film 23 is so provided as to surround the solder paste 30A. Therefore, it is possible to suppress, for example, turning and inclining of the semiconductor laser element 10 after the semiconductor laser element 10 is bonded to the submount 20 via the solder layer 30 by pressing the semiconductor laser element 10 against the insulating film 23 from the upper surface 10S1 side when the semiconductor laser element 10 is bonded to the submount 20 via the solder layer 30. This reduces a coupling failure between the lower electrode 118 of the semiconductor laser element 10 and the coupling electrode Ec.

[0044] For example, as illustrated in (A) to (C) of Fig. 4, the insulating film 23 is provided to so extend on both the mounting surface Sb1 and the peripheral part of the coupling electrode Ec as to surround the solder paste 30A. The insulating film 23 includes, for example, at least one of silicon nitride (SiN), silicon oxide (SiO2), or aluminum oxide (Al2O3). The insulating film 23 may be a single-layer film, or may be a stacked film. The insulating film 23 has a film thickness of, for example, greater than or equal to 100 nm and less than or equal to 2000 nm.

[0045] The upper surface 23S1 of the insulating film 23 is provided with the step part X. For example, as illustrated in (A) of Fig. 4, the step part X is provided in the vicinity of a border between the mounting surface Sb1 and the peripheral part of the coupling electrode Ec. The step part X has, for example, a height difference (a height h in (B) of Fig. 4) of greater than or equal to 100 nm and less than or equal to 2000 nm. The step part X is formed to reflect, for example, a level difference between the mounting surface Sb1 and the coupling electrode Ec at a time when the insulating film 23 is formed. For example, the step part X may be formed on the upper surface 23S1 of the insulating film 23 by, for example, etching using a photolithography method.

[0046] Fig. 6 schematically illustrates a process of bonding the semiconductor laser element 10 and the submount 20 to each other. Fig. 7 schematically illustrates the bonding state of the semiconductor laser element 10 and the submount 20. In the present embodiment, as described above, the step part X is provided on the upper surface 23S1 of the insulating film 23. Therefore, even if the molten solder paste 30A flows out onto the insulating film 23 when the semiconductor laser element 10 and the submount 20 are bonded to each other, it is possible to suppress excessive flowing out of the solder paste 30A, because a gap between the step part X and the lower electrode 118 serves as a pocket structure A, as illustrated in Fig. 7, for example.

[0047] Note that although (A) of Fig. 4 illustrates the example in which the insulating film 23 is continuously provided to extend on both the mounting surface Sb1 and the peripheral part of the coupling electrode Ec, this is non-limiting. For example, the insulating film 23 may be partially divided. That is, as long as it is possible to prevent excessive wetting and spreading of the molten solder paste 30A on the mounting surface Sb1, the insulating film 23 may be provided discontinuously. {Workings and Effects}

[0048] In the semiconductor device 1 of the present embodiment, the insulating film 23 is provided on the mounting surface Sb1 of the submount 20. The insulating film 23 is provided to so extend on both the mounting surface Sb1 and the peripheral part of the coupling electrode Ec as to surround the solder layer 30 provided on the coupling electrode Ec to which the semiconductor laser element 10 is bonded. The step part X is provided on the upper surface 23S1 of the insulating film 23. This prevents excessive wetting and spreading of the solder layer 30. This will be described below.

[0049] As described above, as a method of suppressing wetting and spreading of solder upon mounting a semiconductor laser on a submount using solder, a method has been reported in which a barrier layer having a wall part at a part excluding a part corresponding to an output end side of the semiconductor laser is provided between the semiconductor laser and the submount. This method reduces the variation in amount of solder below the semiconductor laser after the mounting, and thus achieves an effect of improving laser performance and reliability. On the other hand, this method leads to an issue that a solder ball is formed on the output end side of the semiconductor laser due to a structure in which the solder wets and spreads on only the output end side of the semiconductor laser.

[0050] Further, for example, a semiconductor element such as a semiconductor laser includes a structure in which a plurality of semiconductor layers that differ in expansion coefficient is stacked. Therefore, in a case where a semiconductor element having a long shape is bonded to a submount, a bonding failure due to warping of the semiconductor element can occur, which is known as an issue. To address this issue, a technique has been reported that one or more spacer layers each having a smaller plane area than the bonding layer including a eutectic solder material are provided between the submount and the bonding layer. The one or more spacer layers each include a metal material having a melting point higher than that of the bonding layer. In a case where the semiconductor element has a downward convex warp, the one or more spacer layers are provided in the vicinity of an end surface of the semiconductor element. In a case where the semiconductor element has an upward convex warp, the one or more spacer layers are provided in a middle part of the semiconductor element. It is thus possible to reduce bonding failure by variously changing the thickness, the shape, the formation position, and the like of the spacer layer. On the other hand, this can lead to an issue that voids are generated at locations other than the spacer layer.

[0051] In contrast, in the present embodiment, provided on the mounting surface Sb1 of the submount 20 is the insulating film 23 that so extends on both the mounting surface Sb1 and the peripheral part of the coupling electrode Ec as to surround the solder layer 30 provided on the coupling electrode Ec to which the semiconductor laser element 10 is bonded, and that includes the step part X on the upper surface 23S1, as described above. This prevents excessive wetting and spreading of the solder layer 30 (the molten solder paste 30A). In addition, for example, as illustrated in Fig. 7, even if the molten solder paste 30A flows out onto the insulating film 23, the gap between the step part X and the lower electrode 118 serves as the pocket structure A, which suppresses excessive flowing out of the solder paste 30A.

[0052] It is thus possible for the semiconductor device 1 of the present embodiment to improve a manufacturing yield.

[0053] Further, in the present embodiment, the insulating film 23 including the step part X on the upper surface 23S1 is so provided as to extend on both the mounting surface Sb1 and the coupling electrode Ec to which the semiconductor laser element 10 is bonded. Therefore, it is possible to suppress, for example, turning and inclining of the semiconductor laser element 10 after bonding, by pressing the semiconductor laser element 10 against the insulating film 23 from the upper surface 10S1 side. It is thus possible to reduce a coupling failure between the lower electrode 118 of the semiconductor laser element 10 and the coupling electrode Ec without generating voids.

[0054] Accordingly, it is possible for the semiconductor device 1 of the present embodiment to further improve a manufacturing yield.

[0055] Next, Modification examples 1 to 4 of the present disclosure will be described. Note that components corresponding to those of the semiconductor device 1 of the above-described embodiment are denoted with the same reference numerals, and descriptions thereof are omitted. <2. Modification Examples> (2-1. Modification Example 1)

[0056] Fig. 8 schematically illustrates a configuration example of the submount 20 according to Modification example 1 of the present disclosure. Fig. 9 schematically illustrates a process of bonding the semiconductor laser element 10 and the submount 20 illustrated in Fig. 8 to each other. Fig. 10 schematically illustrates a bonding state of the semiconductor laser element 10 and the submount 20 illustrated in Fig. 8. Note that Figs. 8 to 10 each illustrate a cross-section corresponding to that taken along the line I-I' illustrated in (A) of Fig. 4.

[0057] In the above-described embodiment, the example has been described in which the step part X having a stair shape is provided on the upper surface 23S1 of the insulating film 23; however, this is non-limiting. For example, as illustrated in Fig. 8, the submount 20 of the present modification example includes an insulating film 43 that includes a step part Y having a recessed shape on an upper surface 43S1 of the insulating film 43. The insulating film 43 is so provided as to extend on both the mounting surface Sb1 and the coupling electrode Ec to which the semiconductor laser element 10 is bonded. Except for this point, the insulating film 43 and the submount 20 including the insulating film 43 of the present modification example have configurations substantially similar to the configurations of the insulating film 23 and the submount 20 including the insulating film 23 of the above-described embodiment.

[0058] As with the insulating film 23, the insulating film 43 includes, for example, at least one of silicon nitride (SiN), silicon oxide (SiO2), or aluminum oxide (Al2O3). The insulating film 43 may be a single-layer film, or may be a stacked film. The insulating film 43 has a film thickness of, for example, greater than or equal to 200 nm and less than or equal to 4000 nm.

[0059] For example, as illustrated in Fig. 8, the insulating film 43 has a configuration in which a first layer 43A and a second layer 43B are stacked in this order from a side closer to the mounting surface Sb1. As with the insulating film 23, the first layer 43A is provided to extend on both the mounting surface Sb1 and the coupling electrode Ec, and a stair-shaped step reflecting the level difference between the mounting surface Sb1 and the coupling electrode Ec is provided on an upper surface of the first layer 43A. The second layer 43B is provided on the first layer 43A, outside the above-described stair-shaped step. As a result, the step part Y having the recessed shape is provided on the upper surface 43S1 of the insulating film 43. The first layer 43A and the second layer 43B include respective materials that differ from each other in etching rate.

[0060] As described above, in the submount 20 of the present modification example, provided is the insulating film 43 that extends on both the mounting surface Sb1 and the coupling electrode Ec to which the semiconductor laser element 10 is bonded and that includes the step part Y having the recessed shape on the upper surface 43S1. This makes it possible to further suppress excessive flowing out of the solder paste 30A when the molten solder paste 30A flows out onto the insulating film 43, as compared with the above-described embodiment. Therefore, the semiconductor device 1A of the present modification example makes it possible to further improve a manufacturing yield. (2-2. Modification Example 2)

[0061] Fig. 11 schematically illustrates an example of a cross-sectional configuration of a semiconductor device 1B according to Modification example 2 of the present disclosure. Fig. 12 schematically illustrates another example of the cross-sectional configuration of the semiconductor device 1B according to Modification example 2 of the present disclosure.

[0062] In the embodiment and Modification example 1 described above, the example has been described in which the step part X of the insulating film 23 includes a side surface perpendicular to the upper surface 23S1, and the step part Y of the insulating film 43 includes a side surface perpendicular to the upper surface 43S1; however, this is non-limiting. As illustrated in Figs. 11 and 12, in the semiconductor device 1B of the present modification example, the step part X of the insulating film 23 includes a side surface 23S3 having a tapered shape, and the step part Y of the insulating film 43 includes a side surface 43S3 having a tapered shape. Except for this point, the semiconductor device 1B of the present modification example has a configuration substantially similar to that of the semiconductor device 1 of the embodiment and that of the semiconductor device 1A of Modification example 1 described above.

[0063] The semiconductor device 1B of the present modification example having such a configuration also makes it possible to achieve effects similar to those of the above-described embodiment. (2-3. Modification Example 3)

[0064] Fig. 13 schematically illustrates a front configuration of a semiconductor device 1C according to Modification example 3 of the present disclosure.

[0065] The semiconductor device 1C of the present modification example further includes an under barrier metal (UBM) layer 31 that is provided between the coupling electrode Ec and the solder layer 30. Except for this point, the semiconductor device 1C of the present modification example has a configuration substantially similar to that of the semiconductor device 1 of the above-described embodiment.

[0066] For example, as illustrated in Fig. 13, the UBM layer 31 is provided between the coupling electrode Ec and the solder layer 30, and so extends as to cover a side surface 23S2 and the upper surface 23S1 of the insulating film 23. The UBM layer 31 has, for example, a configuration in which a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer are stacked in this order from a side closer to the submount 20.

[0067] The semiconductor device 1C of the present modification example having such a configuration also makes it possible to achieve effects similar to those of the above-described embodiment. (2-4. Modification Example 4)

[0068] Fig. 14 is a perspective diagram illustrating a configuration example of a semiconductor device 1D according to Modification example 4 of the present disclosure.

[0069] In the above-described embodiment, the example has been described in which the semiconductor laser element 10 is mounted on the submount 20; however, this is non-limiting. In the semiconductor device 1D of the present modification example, the semiconductor laser element 10 is mounted on a heat sink 50 instead of the submount 20. Except for this point, the semiconductor device 1D has a configuration substantially similar to that of the semiconductor device 1 of the above-described embodiment.

[0070] The heat sink 50 corresponds to a specific example of the "bonding object" according to one embodiment of the present disclosure. As with the submount 20, the heat sink 50 includes, for example, a block including, as surfaces, the mounting surface Sb1, the bonding end surface Sb2, the non-bonding end surface Sb3, and the side surfaces Sb4 and Sb5, as illustrated in Fig. 14. In the block of the heat sink 50, the mounting surface Sb1 is provided with the coupling electrode Ec and the external electrode Eb. In the block of the heat sink 50, the bonding end surface Sb2 is provided with the bonding metal layer 22. The block of the heat sink 50 includes, for example, Cu, Fe, Al, Au, W, Mo, a composite material including any of these materials, or the like. Examples of such a composite material include Cu-W, Cu-Mo, and the like.

[0071] The semiconductor device 1D of the present modification example having such a configuration also makes it possible to achieve effects similar to those of the above-described embodiment.

[0072] Although the present disclosure has been described above with reference to the embodiment and Modification examples 1 to 4, the present disclosure is not limited to the embodiment and the like described above, and various modifications may be made. For example, any two or more of the respective configurations of the embodiment and Modification examples 1 to 4 described above may be appropriately combined with each other.

[0073] For example, the semiconductor device and the semiconductor laser element of the present disclosure do not necessarily have to include all of the components described in the embodiment and the like above, and conversely, may include any other layer. In one example, the semiconductor laser element 10 may further include, for example, a spacer layer adapted to adjust optical confinement in a stacking direction. In one example, the semiconductor laser element 10 may further include, for example, a stopper layer adapted to stop etching within the upper clad layer 115 in the process of forming the pair of trenches 12.

[0074] Furthermore, not all of the configurations and the operations described in the embodiment and the like above are necessarily essential as the configurations and the operations of the present disclosure. For example, among the components in the embodiment and the like described above, the components not recited in the independent claim representing the broadest concept of the present disclosure should be understood as optional components.

[0075] The terms used throughout this specification and the appended claims are to be interpreted as "non-limiting" terms. For example, the terms "include" or "be included" are to be interpreted as "not limited to the example described as being included". For example, the term "have" is to be interpreted as "not limited to the example described as having".

[0076] The terms in this specification are used merely for convenience of description, and include terms that are not used to limit the configurations and the operations. For example, the terms "right", "left", "up", "down", and the like merely indicate the directions in the drawing to which reference is made. Further, the terms "inner" and "outer" merely indicate a direction toward the center of the component of interest and a direction away from the center of the component of interest, respectively. This similarly applies to terms similar to the above-described terms, terms having meanings similar to those of the above-described terms, and the like.

[0077] It is to be noted that the effects described in this specification are mere examples and the descriptions thereof are non-limiting. Any other effect may also be achieved.

[0078] It is to be noted that the present disclosure may have any of the following configurations. According to the present technology having any of the following configurations, it is possible to improve a manufacturing yield. (1) A semiconductor device, including a block, a light-emitting element physically and electrically coupled to the block with a solder layer, and an insulating film disposed between the block and the light-emitting element such that the insulating film is disposed adjacent to the solder layer on a plane substantially defined by the solder layer, wherein the insulating film has a raised step portion. (2) The semiconductor according to (1), wherein a portion of the solder layer is disposed outside of the raised step portion of the insulating film. (3) The semiconductor device according to (1) or (2), wherein the raised step portion of the insulating film has a substantially rectangular profile in a cross-sectional view. (4) The semiconductor device according to (1) or (2), wherein the raised step portion of the insulating film has a substantially tapered profile in a cross-sectional view. (5) The semiconductor device according to (1) to (4), wherein the insulating film includes a second raised step portion such that a recessed channel is formed substantially parallel to a perimeter of the solder layer. (6) The semiconductor device according to (5), wherein a portion of the solder layer is disposed within the recessed channel. (7) The semiconductor device according to (1) to (6), wherein the block is a heat sink. (8) The semiconductor device according to (1) to (7), wherein the raised step portion is formed by a photolithography method. (9) The semiconductor device according to (1) to (8), wherein the insulating film comprises a first layer which has a first etching rate and a second layer which has a second etching rate. (10) The semiconductor device according to (1) to (9), wherein the insulating film has a thickness between 200 nanometers (nm) and 4000 nm. (11) The semiconductor device according to (1) to (9), wherein the insulating film has a thickness between 100 nanometers (nm) and 2000 nm. (12) The semiconductor device according to (1) to (11), wherein the insulating film includes at least one of silicon nitride, silicon oxide, or aluminum oxide. (13) The semiconductor device according to (1) to (12), wherein the solder layer includes at least one of silver paste, sintered gold, or sintered silver. (14) The semiconductor device according to (1) to (13), wherein the block includes at least one of aluminum nitride, silicon, silicon carbide, copper, tungsten, molybdenum, aluminum, or diamond. (15) The semiconductor device according to (1) to (14), wherein the raised step portion of the insulating film has a protrusion distance between 100 nanometers (nm) and 2000 nm. (16) The semiconductor device according to (1) to (15), wherein the insulating film has at least one discontinuity along a perimeter of the solder layer. (17) The semiconductor device according to (1) to (16), further comprising a barrier layer disposed between the block and the solder layer, the insulating film and the solder layer, and the insulating film and the light-emitting element. (18) The semiconductor device according to (17), wherein the barrier layer has a discontinuity corresponding with an output end side of the light-emitting element. (19) The semiconductor device according to (1), (17), or (18), wherein the barrier layer is a metal layer. (20) The semiconductor device according to (1) to (19), wherein the raised step portion mechanically supports the light-emitting element at a predefined distance from and attitude relative to the block during coupling of the block and the light-emitting element. (21) A semiconductor device including: a semiconductor light-emitting element; a bonding object including a bonding surface to which the semiconductor light-emitting element is bonded; a coupling pad provided in a bonding region, of the bonding surface, to which the semiconductor light-emitting element is bonded; a conductor layer that is provided on the coupling pad and bonds the semiconductor light-emitting element and the bonding object to each other; and an insulating film that is provided to extend on both the bonding surface and a peripheral part of the coupling pad and to surround the coupling pad, and includes a step part on an upper surface of the insulating film. (22) The semiconductor device according to (21), in which the step part is provided in the vicinity of a border between the bonding surface and the peripheral part of the coupling pad. (23) The semiconductor device according to (21) or (22), in which the step part has a recessed shape. (24) The semiconductor device according to any one of (21) to (23), in which the step part has a side surface having a tapered shape. (25) The semiconductor device according to any one of (21) to (24), in which the step part has a height difference that is greater than or equal to 100 nanometers and less than or equal to 2000 nanometers. (26) The semiconductor device according to any one of (21) to (25), in which the bonding object includes a submount or a heat sink. (27) The semiconductor device according to any one of (21) to (26), in which the coupling pad includes an Au film. (28) The semiconductor device according to (27), in which the coupling pad further includes an AlSi film. (29) The semiconductor device according to any one of (21) to (28), in which the insulating film is provided continuously or discontinuously to surround the coupling pad. (30) The semiconductor device according to any one of (21) to (29), in which the insulating film includes a single-layer film or a stacked film. (31) The semiconductor device according to any one of (21) to (30), in which the insulating film includes at least one of silicon nitride, silicon oxide, or aluminum oxide. (32) The semiconductor device according to any one of (21) to (31), in which the semiconductor light-emitting element includes a semiconductor layer including a first-conductivity-type layer, an active layer, and a second-conductivity-type layer, the second-conductivity-type layer being stacked on the first-conductivity-type layer with the active layer interposed between the second-conductivity-type layer and the first-conductivity-type layer, the second-conductivity-type layer including a ridge part that has a band shape. (33) The semiconductor device according to (32), in which the semiconductor layer includes a pair of resonator end surfaces that are opposed to each other in an extending direction of the ridge part.

[0079] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.Reference Numerals List

[0080] 1, 1A, 1B, 1C, 1D semiconductor device 10 semiconductor laser element 11 ridge part 12 trench 13 dielectric film 20 submount 21 block 22 bonding metal layer 23, 43 insulating film 30 solder layer 30A solder paste 31 UBM layer 43A first layer 43B second layer 50 heat sink 110 semiconductor stack section 111 substrate 112 lower buffer layer 113 lower clad layer 114 active layer 115 upper clad layer 116 contact layer 117 upper electrode 118 lower electrode 10S1, 23S1, 43S1 upper surface 10S2 lower surface 23S2, 23S3, 43S3, Sa3, Sa4, Sb4, Sb5 side surface A pocket structure Ea, Eb external electrode Ec coupling electrode Sa1, Sa2 resonator end surface Sb1 mounting surface Sb2 bonding end surface Sb3 non-bonding end surface X, Y step part h height

Claims

1. A semiconductor device, including: a block; a light-emitting element physically and electrically coupled to the block with a solder layer; and an insulating film disposed between the block and the light-emitting element such that the insulating film is disposed adjacent to the solder layer on a plane substantially defined by the solder layer, wherein the insulating film has a raised step portion.

2. The semiconductor device of claim 1, wherein a portion of the solder layer is disposed outside of the raised step portion of the insulating film.

3. The semiconductor device of claim 1, wherein the raised step portion of the insulating film has a substantially rectangular profile in a cross-sectional view.

4. The semiconductor device of claim 1, wherein the raised step portion of the insulating film has a substantially tapered profile in a cross-sectional view.

5. The semiconductor device of claim 1, wherein the insulating film includes a second raised step portion such that a recessed channel is formed substantially parallel to a perimeter of the solder layer.

6. The semiconductor device of claim 5, wherein a portion of the solder layer is disposed within the recessed channel.

7. The semiconductor device of claim 1, wherein the block is a heat sink.

8. The semiconductor device of claim 1, wherein the raised step portion is formed by a photolithography method.

9. The semiconductor device of claim 1, wherein the insulating film comprises a first layer which has a first etching rate and a second layer which has a second etching rate.

10. The semiconductor device of claim 1, wherein the insulating film has a thickness between 200 nanometers (nm) and 4000 nm.

11. The semiconductor device of claim 1, wherein the insulating film has a thickness between 100 nanometers (nm) and 2000 nm.

12. The semiconductor device of claim 1, wherein the insulating film includes at least one of silicon nitride, silicon oxide, or aluminum oxide.

13. The semiconductor device of claim 1, wherein the solder layer includes at least one of silver paste, sintered gold, or sintered silver.

14. The semiconductor device of claim 1, wherein the block includes at least one of aluminum nitride, silicon, silicon carbide, copper, tungsten, molybdenum, aluminum, or diamond.

15. The semiconductor device of claim 1, wherein the raised step portion of the insulating film has a protrusion distance between 100 nanometers (nm) and 2000 nm.

16. The semiconductor device of claim 1, wherein the insulating film has at least one discontinuity along a perimeter of the solder layer.

17. The semiconductor device of claim 1, further comprising a barrier layer disposed between the block and the solder layer, the insulating film and the solder layer, and the insulating film and the light-emitting element.

18. The semiconductor device of claim 17, wherein the barrier layer has a discontinuity corresponding with an output end side of the light-emitting element.

19. The semiconductor device of claim 17, wherein the barrier layer is a metal layer.

20. The semiconductor device of claim 1, wherein the raised step portion mechanically supports the light-emitting element at a predefined distance from and attitude relative to the block during coupling of the block and the light-emitting element.

Images