Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device comprising a first substrate and a second substrate stacked on the first substrate. The second substrate includes a semiconductor substrate, a chip bonded above the semiconductor substrate, and an embedding layer in which the chip is embedded. A first mark for measurement and a second mark for stress relaxation are provided on a first bonding surface of the first substrate, said surface being bonded to the embedding layer. Furthermore, a third mark for measurement is provided on the second substrate.

Description

Semiconductor device and method for manufacturing a semiconductor device

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Flip-chip packaging technology is known for electrically and physically joining semiconductor chips to semiconductor wafers, or semiconductor wafers to each other, or semiconductor chips to each other. Flip-chip packaging technology is suitable for increasing the density and miniaturization of semiconductor devices. An example of such a joining structure is the semiconductor device disclosed in Patent Document 1 below.

[0003] International Publication No. 2024 / 111532

[0004] During bonding, film deposition, etc., heat applied can cause distortion in the stacked structure consisting of semiconductor chips and semiconductor wafers, or between semiconductor wafers, or between semiconductor chips. As a result of such distortion, elements such as transistors provided within the semiconductor wafer or semiconductor chip may exhibit characteristics different from those desired. Therefore, various countermeasures to mitigate distortion have been proposed in the conventional technology, but these countermeasures have not been sufficient to eliminate the distortion in the final stacked structure.

[0005] Therefore, this disclosure proposes a semiconductor device and a method for manufacturing a semiconductor device that enable accurate measurement of strain and suitable strain relief measures based on the measurement results.

[0006] According to this disclosure, a semiconductor device is provided, comprising a first substrate and a second substrate laminated on the first substrate, wherein the second substrate includes a semiconductor substrate, a chip bonded above the semiconductor substrate, and an embedded layer in which the chip is embedded, the first bonding surface of the first substrate that is bonded to the embedded layer is provided with a first mark for measurement and a second mark for stress relief, and the second substrate is provided with a third mark for measurement.

[0007] Furthermore, the present disclosure provides a method for manufacturing a semiconductor device, which includes bonding a semiconductor substrate, a chip bonded above the semiconductor substrate, and a embedding layer in which the chip is embedded to a first substrate on which a first mark for measurement and a second mark for stress relaxation are provided, such that the embedding layer is in contact with the first substrate; measuring the strain occurring in the laminated structure of the first substrate and the second substrate using the first mark and a third mark provided on the second substrate; and, according to the measurement results, changing at least one of the shape, position, density, and size of the second mark to produce the next second mark on the first substrate.

[0008] This is a block diagram showing a schematic of the basic configuration of the imaging device. This is a circuit diagram showing an example of the circuit configuration of pixel 2. This is a cross-sectional view of the basic stacked structure of the imaging device according to an embodiment of this disclosure. This is a cross-sectional view showing the cross-sectional structure in each step of the manufacturing method of the imaging device according to a comparative example. This is a cross-sectional view (1) showing the cross-sectional structure in each step of the manufacturing method of the imaging device according to the first embodiment of this disclosure. This is a cross-sectional view (2) showing the cross-sectional structure in each step of the manufacturing method of the imaging device according to the first embodiment of this disclosure. This is an explanatory diagram (1) for explaining the mark according to the second embodiment of this disclosure. This is an explanatory diagram (2) for explaining the mark according to the second embodiment of this disclosure. This is an explanatory diagram (3) for explaining the mark according to the second embodiment of this disclosure. This is an explanatory diagram (1) for explaining the mark according to the third embodiment of this disclosure. This is an explanatory diagram (2) for explaining the mark according to the third embodiment of this disclosure. This is an explanatory diagram (3) for explaining the mark according to the third embodiment of this disclosure. This is an explanatory diagram (1) for explaining the mark according to the fourth embodiment of this disclosure. This is an explanatory diagram (2) for explaining the mark according to the fourth embodiment of this disclosure. This is an explanatory diagram (3) for explaining the mark according to the fourth embodiment of this disclosure. This is an explanatory diagram (part 4) illustrating the mark according to the fourth embodiment of this disclosure. This is an explanatory diagram (part 1) illustrating the mark according to the fifth embodiment of this disclosure. This is an explanatory diagram (part 2) illustrating the mark according to the fifth embodiment of this disclosure. This is an explanatory diagram illustrating the mark according to the sixth embodiment of this disclosure. This is a cross-sectional view of the imaging device according to the seventh embodiment of this disclosure. This is a cross-sectional view (part 1) showing the cross-sectional structure in each step of the manufacturing method of the imaging device according to the seventh embodiment of this disclosure. This is a cross-sectional view (part 2) showing the cross-sectional structure in each step of the manufacturing method of the imaging device according to the seventh embodiment of this disclosure. This is a cross-sectional view (part 3) showing the cross-sectional structure in each step of the manufacturing method of the imaging device according to the seventh embodiment of this disclosure.

[0009] Preferred embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configuration will be denoted by the same reference numeral to avoid redundant explanation. In addition, in this specification and drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding a different alphabet after the same reference numeral. However, if there is no particular need to distinguish each of multiple components having substantially the same or similar functional configurations, only the same reference numeral will be used.

[0010] Furthermore, the drawings referenced in the following description are intended to illustrate and facilitate understanding of one embodiment of this disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from those of the actual product. In addition, the apparatus shown in the drawings may be modified in design as appropriate, taking into consideration the following description and known technology.

[0011] The explanation will proceed in the following order: 1. Background 1.1 Example of Functional Configuration of Imaging Device 1.2 Example of Pixel Circuit Configuration 1.3 Example of Stacked Structure 1.4 Background Leading to the Creation 2. First Embodiment 3. Second Embodiment 4. Third Embodiment 5. Fourth Embodiment 6. Fifth Embodiment 7. Sixth Embodiment 8. Seventh Embodiment 8.1 Example of Stacked Structure 8.2 Manufacturing Method 9. Summary 10. Supplementary Information

[0012] <<1. Background>> <1.1 Example of Functional Configuration of Imaging Device> First, before describing the embodiments of this disclosure, the present inventor will explain the background that led to the creation of the embodiments of this disclosure. First, the general configuration of the imaging device 1 to which the technology of this disclosure can be applied will be described in order. Note that the imaging device 1 is an example of a semiconductor device to which the technology proposed in this disclosure can be applied, and the technology proposed in this disclosure is not limited to the application of the imaging device 1.

[0013] First, referring to FIG. 1, an overview of an example of the functional configuration of an imaging device 1 to which the technology of the present disclosure is applicable will be described. Here, as the imaging device 1, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is a type of imaging device using the X-Y address method, will be described as an example. A CMOS image sensor is an image sensor manufactured by applying or partially using a CMOS process. FIG. 1 is a block diagram showing an outline of the basic configuration of a CMOS image sensor (imaging device 1), which is an example of an imaging device applicable to each embodiment of the present disclosure.

[0014] The imaging device 1 shown in FIG. 1 includes a pixel array unit (cell array) 11 in which pixels (cells) 2 including a photoelectric conversion unit are two-dimensionally arranged in the row direction and the column direction, that is, in a matrix arrangement, and a peripheral circuit unit of the pixel array unit 11. Here, the row direction refers to the arrangement direction (horizontal direction) of the pixels 2 in the pixel row, and the column direction refers to the arrangement direction (vertical direction) of the pixels 2 in the pixel column. The pixel 2 generates and accumulates charges corresponding to the amount of received light by performing photoelectric conversion.

[0015] In the example of FIG. 1, as the peripheral circuit unit of the pixel array unit 11, for example, a row selection unit 12, a constant current source unit 13, an analog-digital conversion unit 14, a horizontal transfer scanning unit 15, a signal processing unit 16, a timing control unit 17, and the like can be mentioned.

[0016] In the pixel array unit 11, for the matrix pixel arrangement, control lines 32 ｎ , １ ~32 ｎ are wired along the row direction. Also, vertical signal lines 31 １ ~31 ｍ are wired along the column direction. Note that when there is no need to particularly distinguish the vertical signal lines 31 １ ~31 ｍ , the vertical signal lines 31 １ ~31 ｍ will be described as the vertical signal line 31 as appropriate. Similarly, when there is no need to particularly distinguish the control lines 32 １ ~32 ｎ , the control lines 32 １ ~32ｎ This will be explained as control line 32 as appropriate.

[0017] The control line 32 transmits drive signals for driving the pixels when reading signals from the pixels 2. In Figure 1, the control line 32 is shown as a single wire, but the control line 32 is not limited to one wire and can include multiple wires. One end of the control line 32 is connected to the output terminal corresponding to each row of the row selection unit 12.

[0018] Next, we will describe each circuit portion of the peripheral circuit section of the pixel array section 11, namely the row selection section 12, the constant current source section 13, the analog-to-digital conversion section 14, the horizontal transfer scanning section 15, the signal processing section 16, and the timing control section 17.

[0019] The row selection unit 12 is composed of a shift register, an address decoder, and the like, and controls the scanning of pixel rows and the address of pixel rows when selecting each pixel 2 included in the pixel array unit 11. The specific configuration of the row selection unit 12 is not shown in the diagram, but generally it has a configuration that has two scanning systems: a read scanning system and a sweep scanning system.

[0020] The readout scanning system sequentially selects and scans the pixels 2 of the pixel array section 11 row by row in order to read out the pixel signal from the pixels 2. The pixel signal read out from the pixels 2 is an analog signal. The sweep scanning system performs a sweep scan for each row being scanned by the readout scanning system, preceding the scan by the shutter speed.

[0021] This sweep scanning system resets the photoelectric converter by sweeping away unwanted charges from the photoelectric converter of pixel 2 in the readout row. By sweeping away (resetting) unwanted charges in this sweep scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to the operation of discarding the charge in the photoelectric converter and starting a new exposure (starting charge accumulation).

[0022] The constant current source unit 13 has a vertical signal line 31 for each pixel row. １ ~31 ｍEach of the constant current sources I is connected to a plurality of current sources I, for example, consisting of MOS (Metal Oxide Semiconductor) transistors. The constant current source unit 13 supplies a vertical signal line 31 to each pixel 2 of the pixel row selected and scanned by the row selection unit 12. １ ~31 ｍ A bias current is supplied through each of them.

[0023] The analog-to-digital conversion unit 14 includes a plurality of analog-to-digital converters provided corresponding to the pixel rows of the pixel array unit 11, for example, one converter provided for each pixel row. The analog-to-digital conversion unit 14 provides a vertical signal line 31 for each pixel row. １ ~31 ｍ This is a column-parallel type analog-to-digital conversion unit that converts the pixel signals, which are analog signals output through each of the components, into N-bit digital signals. Hereinafter, the analog-to-digital conversion unit 14 will be referred to as the column-parallel analog-to-digital conversion unit 14.

[0024] As the analog-to-digital converter included in the column-parallel analog-to-digital conversion unit 14, for example, a single-slope type analog-to-digital converter, which is an example of a reference signal comparison type analog-to-digital converter, can be used. However, this disclosure is not limited to such examples, and as the analog-to-digital converter included in the column-parallel analog-to-digital conversion unit 14, successive approximation type analog-to-digital converters, delta-sigma modulation type (ΔΣ modulation type) analog-to-digital converters, etc., can be used.

[0025] The horizontal transfer scanning unit 15 is composed of a shift register, an address decoder, etc., and controls the scanning of the pixel column and the address of the pixel column when reading the signal of each pixel 2 in the pixel array unit 11. Under the control of this horizontal transfer scanning unit 15, the pixel signals converted into digital signals by the column-parallel analog-to-digital conversion unit 14 are read out on a 2N-bit wide horizontal transfer line 18 on a pixel column basis.

[0026] The signal processing unit 16 performs predetermined signal processing on the digital pixel signals supplied through the horizontal transfer line 18 to generate two-dimensional image data. For example, the signal processing unit 16 can perform various signal processes such as correction of vertical line defects and dot defects, and clamping of signals on the supplied pixel signals. In addition, the signal processing unit 16 can perform signal processes such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation on the supplied pixel signals. The signal processing unit 16 outputs the generated image data to a subsequent device as an output signal of the imaging device 1.

[0027] The timing control unit 17 generates various timing signals, clock signals, control signals, etc., and based on these generated signals, performs drive control on the row selection unit 12, constant current source unit 13, column parallel analog-digital conversion unit 14, horizontal transfer scanning unit 15, signal processing unit 16, etc.

[0028] <1.2 Circuit Configuration Example of Pixel> Next, referring to FIG. 2, a circuit configuration example of pixel 2 will be described. FIG. 2 is a circuit diagram showing an example of the circuit configuration of pixel 2 applicable to each embodiment of the present disclosure. Pixel 2 has, for example, an imaging element (photodiode) 21 as a photoelectric conversion unit. In addition to the imaging element 21, pixel 2 has a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25. These transistors are also referred to as pixel transistors for driving the imaging element 21.

[0029] In the example of FIG. 2, the four transistors, namely the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, are formed from, for example, N-channel metal-oxide-semiconductor field-effect transistors (FETs). Hereinafter, an N-channel metal-oxide-semiconductor field-effect transistor is referred to as an NMOS transistor. By configuring the pixel 2 only with NMOS transistors, optimization from the viewpoints of area efficiency and process reduction can be achieved. Note that the combination of the conductivity types of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 shown in FIG. 2 is merely an example, and these combinations are not limited.

[0030] For the pixel 2, as the control line 32 described above, a plurality of control lines are commonly wired to each pixel 2 in the same pixel row. These plurality of control lines are connected in pixel row units to the output terminals corresponding to each pixel row of the row selection unit 12. The row selection unit 12 appropriately outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the plurality of control lines.

[0031] The imaging device 21 has an anode electrode connected to a low-potential side power supply (for example, a ground potential), photoelectrically converts the received light into charges (here, photoelectrons) having a charge amount corresponding to the light amount, and accumulates the charges. The cathode electrode of the imaging device 21 is electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistor 22. Here, the region to which the gate electrode of the amplification transistor 24 is electrically connected is the floating diffusion region FD. The floating diffusion region FD is a charge-voltage conversion unit that converts charges into a voltage.

[0032] A transfer signal TRG that becomes active at a high (High) level (for example, VDD level) is supplied from the row selection unit 12 to the gate electrode of the transfer transistor 22. The transfer transistor 22 becomes conductive in response to the transfer signal TRG, and transfers the charges photoelectrically converted by the imaging device 21 and accumulated in the imaging device 21 to the floating diffusion region FD.

[0033] The reset transistor 23 is connected between the node of the power supply VDD, which supplies the high-potential power supply voltage, and the floating diffusion region FD. A reset signal RST, which becomes active at a high level, is supplied to the gate electrode of the reset transistor 23 from the row selection unit 12. In response to the reset signal RST, the reset transistor 23 becomes conductive and resets the floating diffusion region FD by discarding the charge in the floating diffusion region FD to the node of the power supply VDD.

[0034] The gate electrode of the amplification transistor 24 is connected to the floating diffusion region FD, and the drain electrode is connected to the node of the power supply VDD. The amplification transistor 24 serves as the input to a source follower that reads out the signal obtained by photoelectric conversion at the image sensor 21. Specifically, the source electrode of the amplification transistor 24 is connected to the vertical signal line 31 via the selection transistor 25. The amplification transistor 24 and the current source I connected to one end of the vertical signal line 31 constitute a source follower that converts the voltage of the floating diffusion region FD to the voltage of the vertical signal line 31.

[0035] The drain electrode of the selection transistor 25 is connected to the source electrode of the amplification transistor 24, and the source electrode is connected to the vertical signal line 31. A selection signal SEL, which becomes active when high level, is supplied to the gate electrode of the selection transistor 25 from the row selection unit 12. In response to the selection signal SEL, the selection transistor 25 becomes conductive, thereby selecting pixel 2 and transmitting the signal output from the amplification transistor 24 to the vertical signal line 31.

[0036] Furthermore, a circuit configuration in which the selection transistor 25 is connected between the node of the power supply VDD and the drain electrode of the amplification transistor 24 can also be applied. Also, in the example in Figure 2, the pixel circuit of pixel 2 is given as an example of a 4Tr configuration consisting of a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25, i.e., a 4Tr configuration consisting of 4 transistors (Tr), but it is not limited to this. For the circuit configuration of pixel 2, for example, the selection transistor 25 can be omitted and the amplification transistor 24 can be given the function of the selection transistor 25, resulting in a 3Tr configuration, or the number of transistors can be increased to 5Tr or more as needed.

[0037] <1.3 Example of Laminated Structure> Next, an example of the basic laminated structure of the imaging device 1 will be described with reference to Figure 3. Figure 3 is a cross-sectional view of the basic laminated structure of the imaging device 1 according to the embodiment of this disclosure. As described above, the imaging device 1 has various functional blocks. Therefore, in the imaging device 1, multiple substrates and semiconductor chips provided with different functional blocks are laminated and bonded together using flip-chip mounting technology.

[0038] In detail, as shown in Figure 3, the imaging device 1 has a support substrate (first substrate) 302 and a substrate (second substrate) 600 bonded to the support substrate 302. The substrate 600 has a semiconductor substrate 108, a wiring layer 260 provided on the semiconductor substrate 108, semiconductor chips 400 and 500 bonded on the wiring layer 260, and an embedded layer 306 in which the semiconductor chip 400 is embedded. By configuring the imaging device 1 in this stacked structure of the support substrate 302, the substrate 600, and the semiconductor chips 400 and 500, it becomes possible to manufacture each substrate and each semiconductor chip, each equipped with different functional blocks, using a manufacturing method suitable for each. Furthermore, by configuring the imaging device 1 in this stacked structure, the imaging device 1 can be made more compact.

[0039] In detail, the semiconductor substrate 108 is a sensor substrate on which an image sensor is mounted that generates and outputs a pixel signal corresponding to the amount of incident light, and specifically, a pixel array section 11 including a plurality of image sensors 21 is provided.

[0040] Furthermore, the semiconductor chips 400 and 500 bonded to the wiring layer 260 may include, for example, circuits containing multiple transistors or circuits containing multiple memory elements.

[0041] Furthermore, semiconductor chips 400 and 500 are embedded in the embedding layer 306. As shown in Figure 3, the semiconductor chips 400 and 500 are arranged adjacent to each other in the horizontal direction.

[0042] In this specification, "semiconductor chip" refers to a chip obtained by cutting out a semiconductor wafer. In this specification, "substrate" refers to a semiconductor wafer such as a silicon wafer, silicon germanium wafer, or silicon carbide wafer, or a semiconductor chip obtained by cutting them out.

[0043] In this embodiment, the imaging device 1 is not limited to the stacked structure shown in Figure 3, but can be modified in various ways.

[0044] <1.4 Background to the Creation> Next, with reference to Figure 4, the background to the invention of the embodiments of the present invention will be explained. Figure 4 is a cross-sectional view showing the cross-sectional structure of each step in the manufacturing method of the imaging device 1 according to a comparative example. Here, the comparative example refers to the manufacturing method of the imaging device 1 that the present inventors had been studying before creating the embodiments of the present invention.

[0045] First, a schematic example of the manufacturing method of the imaging device 1 according to the comparative example will be described. As shown on the left side of Figure 4, semiconductor chips 400 and 500 are created and bonded to a substrate 600 (chip bonding). The substrate 600 has a semiconductor substrate 108 and a wiring layer 260 formed on the semiconductor substrate 108. Next, as shown in the center of Figure 4, an embedding layer 306 is formed to cover the bonded semiconductor chips 400 and 500. At this time, the embedding layer 306 is formed to fill the space between the bonded semiconductor chips 400 and 500, and then the upper surface of the embedding layer 306 is flattened (embedding flattening). Then, as shown on the right side of Figure 4, the upper and lower surfaces of the substrate 600 are flipped over and the substrate 600 is bonded to the support substrate 302 so that the embedding layer 306 is in contact with the support substrate 302 (support substrate bonding).

[0046] In the manufacturing method of the imaging device 1 according to this comparative example, heat is applied when forming each layer and when bonding the support substrate 302, substrate 600, and semiconductor chips 400 and 500. Due to the differences in internal stress caused by the applied heat, distortion occurs in the support substrate 302, substrate 600, and semiconductor chips 400 and 500. As a result of such distortion, the characteristics of various elements (e.g., transistors) provided in the support substrate 302, substrate 600, and semiconductor chips 400 and 500 may differ from the desired characteristics. In other words, distortion can cause defects and failures in the imaging device 1.

[0047] More specifically, as shown on the left side of Figure 4, when semiconductor chips 400 and 500 are bonded to the substrate 600, distortion may occur in the laminated structure of the substrate 600 and the semiconductor chips 400 and 500 due to differences in internal stress generated by the applied heat. In particular, when semiconductor chips 400 and 500 are bonded to a wafer (for example, when the semiconductor substrate 108 is a silicon wafer), the resulting distortion tends to be greater than when a wafer is bonded to another wafer. Then, as shown in the center of Figure 4, by forming a filling layer 306 to fill the space between the bonded semiconductor chips 400 and 500, new stress is added, and the state of distortion in the laminated structure changes. Next, as shown on the right side of Figure 4, when the substrate 600 is bonded to the support substrate 302, further stress is added, and the state of distortion in the laminated structure of the support substrate 302, the substrate 600, and the semiconductor chips 400 and 500 changes even further.

[0048] Therefore, as a conventional technique, it has been proposed to provide a layer with a difference in density at the bonding site where semiconductor chips are joined in order to mitigate the strain generated within the device. In the above proposal, by providing a layer with a difference in density, internal stress is absorbed and the strain caused by the bonding of semiconductor chips is eliminated. However, it is difficult to eliminate the strain caused by the deposition of the embedding layer performed after the provision of the layer with a difference in density according to the above proposal, and ultimately, strain remains within the device. Furthermore, in the above proposal, in order to create a layer with a suitable difference in density, it is necessary to accurately measure the strain generated when semiconductor chips are bonded. However, when semiconductor chips are made smaller in order to reduce manufacturing costs, it becomes impossible to make measurement marks on the semiconductor chips, making it difficult to accurately measure the strain generated when semiconductor chips are bonded.

[0049] Therefore, in light of these circumstances, the inventors have created an embodiment of the present disclosure that takes into account the occurrence of strain at each stage of manufacturing, accurately measures strain, and enables appropriate strain mitigation measures based on the measurement results. The details of the embodiment of the present disclosure created by the inventors will be described below.

[0050] <<2. First Embodiment>> First, a method for manufacturing the imaging device 1 according to the first embodiment of this disclosure will be described with reference to Figures 5A and 5B. Figures 5A and 5B are cross-sectional views showing the cross-sectional structure in each step of the manufacturing method of the imaging device 1 according to this embodiment.

[0051] First, in this embodiment, as shown in the upper left of Figure 5A, strain measurement marks 700 (third marks for measurement) are formed on a semiconductor substrate 108 made of, for example, silicon, silicon carbide, silicon germanium, etc. The strain measurement marks 700 are markers for measuring strain by their position and can also be used as markers for aligning the substrate or semiconductor chip. For example, trenches are formed in the semiconductor substrate 108, and various metal materials (for example, copper (Cu), aluminum (Al), etc.), various oxide materials, nitride materials (for example, silicon oxide (Si)) are used in the formed trenches. ｘ O ｙ ), silicon nitride (Si ｘ N ｙ It can be manufactured by embedding (etc.). Details of the strain measurement mark 700 according to this embodiment will be described later. The semiconductor substrate 108 is, for example, a sensor substrate on which an image sensor is mounted, and specifically, a pixel array section 11 including a plurality of image sensors 21 is provided.

[0052] Next, as shown in the upper left of Figure 5A, a wiring layer 260 is formed on the semiconductor substrate 108. More specifically, the wiring layer 206 has an insulating film (not shown) made of, for example, silicon oxide or silicon nitride, and a plurality of wirings or through electrodes (not shown) provided within or on the surface of the insulating film.

[0053] Next, as shown in the lower left of Figure 5A, semiconductor chips 400 and 500 are bonded to the wiring layer 206 (chip bonding). The semiconductor chips 400 and 500 are, for example, equipped with circuits including multiple transistors or circuits including multiple memory elements. Specifically, one of the semiconductor chips 400 and 500 is a logic chip equipped with a logic circuit that performs predetermined signal processing using an image signal, and is provided with the signal processing unit 16 described above. Furthermore, the other of the semiconductor chips 400 and 500 is a memory chip equipped with a memory circuit that stores an image signal. The semiconductor chips 400 and 500 have, for example, a semiconductor substrate made of silicon and a wiring layer provided on the semiconductor substrates 440 and 540. The semiconductor substrate is provided with, for example, transistors. When bonding the semiconductor chips 400 and 500, the semiconductor chips 400 and 500 may be aligned using strain measurement marks 700. As explained earlier, when bonding the semiconductor chips 400 and 500, strain may occur due to the applied heat.

[0054] Furthermore, strain measurement marks (third marks for measurement) 800 are formed near the bonding surfaces of the semiconductor chips 400 and 500, in other words, at the interface between the wiring layer 260 and the embedding layer 306. The strain measurement marks 800 serve as markers for measuring strain depending on their position, and can also be used as markers for aligning the substrate and semiconductor chips. It is also preferable that the strain measurement marks 800 are placed in a position that does not overlap with the semiconductor chips 400 and 500 that will be bonded later. The strain measurement marks 800 can be manufactured, for example, by forming a trench on the wiring layer 206 and embedding various metal materials, various oxide materials, or nitride materials into the formed trench. Details of the strain measurement marks 800 according to this embodiment will be described later.

[0055] Then, as shown in the lower right of Figure 5A, a filling layer 306 is stacked to fill the space between the bonded semiconductor chips 400 and 500. In this way, a substrate (second substrate) 600 consisting of a semiconductor substrate 108, a wiring layer 206, semiconductor chips 400 and 500, and a filling layer 306 is created. The filling layer 306 is made of, for example, silicon oxide, silicon nitride, etc. Furthermore, the upper surface of the filling layer 306 is flattened by polishing, for example, CMP (Chemical Mechanical Polishing) (embedded flattening). Then, due to the stacking and flattening of the filling layer 306, new stress is applied and the state of strain changes.

[0056] Furthermore, as shown in the upper left of Figure 5B, a mark 900 is formed on the support substrate (first substrate) 302. In detail, the mark 900 includes a strain measurement mark (first mark for measurement) and a stress relaxation mark (second mark for stress relaxation). The strain measurement mark, as before, is a marker for measuring strain based on its position and can also be used as a marker for aligning the substrate. The stress relaxation mark can alleviate the surrounding strain. For example, if the stress relaxation mark is formed of a high-stress film, the strain is relieved by applying stress to the surrounding area. Also, for example, if the stress relaxation mark is formed of a sparse film, the strain is relieved by absorbing the surrounding strain. Furthermore, for example, if the stress relaxation mark is formed of the same material as the surrounding layer, the difference in internal stress generated by the applied heat becomes smaller, making it less likely for strain to occur. Specifically, the mark 900 can be manufactured, for example, by forming a trench in the support substrate 302 and embedding various metal materials, various oxide materials, or nitride materials into the formed trench. The material embedded in the trench may also be a high-stress film containing high stress. Details of the mark 900 according to this embodiment will be described later.

[0057] Next, as shown in the lower left of Figure 5B, the top and bottom surfaces of the substrate 600 are flipped over, and the substrate 600 is joined to the support substrate 302 so that the embedded layer 306 is in contact with the support substrate 302 (support substrate joining). At this time, alignment can be performed using the strain measurement marks 700, 800 and the strain measurement marks included in mark 900.

[0058] Then, as shown in the lower center of Figure 5B, when the substrate 600 is joined to the support substrate 302, further stress is applied, and the state of strain changes further. In this embodiment, the strain can be measured accurately by comparing the positions of the strain measurement marks included in strain measurement marks 700, 800 and 900 with each other. In this embodiment, the strain can be measured in the state after chip joining, embedding and planarization, and support substrate joining by the strain measurement marks included in strain measurement marks 700, 800 and 900.

[0059] Next, as shown in the lower right of Figure 5B, the upper surface of the semiconductor substrate 108 is thinned by polishing, for example, using CMP (thinning). The state of strain changes further during the thinning of the semiconductor substrate 108. In this embodiment, the strain can be accurately measured by comparing the positions of the strain measurement marks included in strain measurement marks 700, 800 and 900 with each other. In this embodiment, the strain can be accurately measured in the state after chip bonding, embedding and planarization, support substrate bonding, and thinning using the strain measurement marks included in strain measurement marks 700, 800 and 900. Furthermore, in this embodiment, information can be obtained to estimate the state of strain in each layer and which process is likely to cause significant strain using the strain measurement marks included in strain measurement marks 700, 800 and 900 provided on different layers.

[0060] Furthermore, in this embodiment, the measured strain results are fed back into the process of creating and modifying the stress relief marks included in the mark 900. Specifically, based on the measured strain results, the shape, position, density, size, etc., of the stress relief marks are changed to create and modify the stress relief marks. In this embodiment, based on the accurately measured strain results, it is possible to create and modify stress relief marks that have a form that suitably relieves the strain. In addition, in this embodiment, by using a direct drawing machine, a digital exposure device, or a method of overlapping exposures using an exposure device, it becomes easy to create and modify stress relief marks that immediately reflect the measured results.

[0061] In this embodiment, as shown in the lower right of Figure 5B, the imaging device (semiconductor device) 1 has a support substrate (first substrate) 302 and a substrate (second substrate) 600 laminated on the support substrate 302. The substrate 600 has a semiconductor substrate 108, a wiring layer 260 laminated on the semiconductor substrate 108, semiconductor chips 400 and 500 bonded on the wiring layer 206, and an embedded layer 306 in which the semiconductor chips 400 and 500 are embedded. Furthermore, the bonding surface (first bonding surface) of the support substrate 302 that is bonded to the embedded layer 306 is provided with marks 900 including strain measurement marks (first marks) and stress relaxation marks (second marks). The substrate 600 is also provided with strain measurement marks (third marks) 700 and 800.

[0062] In this specification, the imaging device (semiconductor device) 1 shown in Figure 5B is not limited to being a final product, but may also be a stacked structure before being pieced into individual components as a final product. Furthermore, the stacked structure may be a stacked structure of wafers, or a stacked structure of semiconductor chips.

[0063] As described above, in this embodiment, the strain measured by the strain measurement marks 700, 800 and 900 allows for accurate measurement of strain in the state after chip bonding, embedding and planarization, support substrate bonding, thinning, etc. Furthermore, in this embodiment, the strain is relieved by the stress relaxation mark included in 900, and since this stress relaxation mark is manufactured and modified based on the results of accurately measured strain, the strain can be effectively eliminated.

[0064] In this embodiment, the imaging device 1 is not limited to being manufactured by the manufacturing method shown in Figures 5A and 5B, nor is it limited to the form shown in the lower right of Figure 5B.

[0065] <<3. Second Embodiment>> Next, as a second embodiment of the present disclosure, the details of the strain measurement mark 700 (third mark) created on the semiconductor substrate 108 side will be described with reference to Figures 6A to 6C. Figures 6A to 6C are explanatory diagrams for illustrating the strain measurement mark 700 according to this embodiment.

[0066] In this embodiment, as shown in Figure 6A, the strain measurement mark 700 forms a trench in the semiconductor substrate 108, and fills the formed trench with various metal materials (for example, copper (Cu), aluminum (Al), etc.), various oxide materials, nitride materials (for example, silicon oxide (Si)). ｘ O ｙ ), silicon nitride (Si ｘ N ｙIt can be manufactured by embedding (etc.). As explained earlier, the strain measurement marks 700 are markers for measuring strain depending on their position, and can also be used as markers for aligning substrates and semiconductor chips. Therefore, the shape, position, density, and size of the strain measurement marks 700 are fixed. In other words, the shape, position, density, and size of the strain measurement marks 700 are not changed by the measured strain. In this embodiment, even if the wafer from which the semiconductor substrate 108 is cut is different, or even if the position of the semiconductor substrate 108 within the wafer is different, the shape, position, density, and size of the strain measurement marks 700 will not be changed.

[0067] Furthermore, in this embodiment, as shown in Figure 6B, the strain measurement mark 712 may be provided within the wiring layer 260. More specifically, the strain measurement mark 712 may be provided within the wiring layer 260 or on the upper surface of the wiring layer 260. In this case, the strain measurement mark 712 may be formed from the same metal material as the wiring or through electrode 724, or it may be formed from a different material than the wiring or through electrode 724.

[0068] Furthermore, in this embodiment, as shown in Figure 6C, the strain measurement marks 720 can be made by forming trenches in the stress relaxation layer (first stress relaxation layer) 722 provided on the wiring layer 260 and embedding various materials in the formed trenches. In addition, in this embodiment, wiring or through electrodes 724 may be provided in the stress relaxation layer (first stress relaxation layer) 722. The stress relaxation layer can be formed from, for example, a high-stress film or a sparse film.

[0069] In this embodiment, the strain measurement mark 700 is not limited to the form shown in Figures 6A to 6C.

[0070] <<4. Third Embodiment>> Next, as a third embodiment of the present disclosure, the details of the strain measurement mark 800 (third mark) created on the interface side between the wiring layer 206 and the embedded layer 306 will be described with reference to Figures 7A to 7C. Figures 7A to 7C are explanatory diagrams for illustrating the strain measurement mark 800 according to this embodiment.

[0071] In this embodiment, as shown in Figure 7A, the strain measurement mark 800 is made of various metal materials (for example, copper (Cu), aluminum (Al), etc.), various oxide materials, nitride materials (for example, silicon oxide (Si)) at the joint surface (second joint surface) between the wiring layer 260 and the embedded layer 306. ｘ O ｙ ), silicon nitride (Si ｘ N ｙ It can be manufactured by (etc.). As explained earlier, the strain measurement marks 800 are markers for measuring strain based on their position, and can also be used as markers for aligning substrates and semiconductor chips. Therefore, the shape, position, density, and size of the strain measurement marks 800 are fixed. In other words, the shape, position, density, and size of the strain measurement marks 800 are not changed by the measured strain. In this embodiment, even if the wafer from which the semiconductor substrate 108 on which the wiring layer 260 is stacked is cut is different, and even if the position of the semiconductor substrate 108 within the wafer is different, the shape, position, density, and size of the strain measurement marks 800 will not be changed.

[0072] Furthermore, in this embodiment, strain measurement marks 814 may be provided within the embedded layer 306, as shown in Figure 7B. More specifically, the strain measurement marks 814 may be provided within a stress relaxation layer (second stress relaxation layer) 812 provided within the embedded layer 306. In this case, it is preferable that the strain measurement marks 814 are provided at the same height as the bonding surface of the semiconductor chips 400 and 500. In this embodiment, the strain measurement marks 814 can be provided within the embedded layer 306 by using lithography, etching, or the like.

[0073] Furthermore, in this embodiment, as shown in Figure 7C, strain measurement marks 800 may be omitted, and only strain measurement marks 814 may be provided.

[0074] In this embodiment, the strain measurement mark 800 is not limited to the form shown in Figures 7A to 7C.

[0075] <<5. Fourth Embodiment>> Next, as a fourth embodiment of the present disclosure, the details of the mark 900 created on the support substrate 302 side will be described with reference to Figures 8A to 8D. Figures 8A to 8D are explanatory diagrams for illustrating the mark 900 according to this embodiment.

[0076] As explained earlier, in this embodiment, the marks 900 provided on the support substrate 302 include strain measurement marks (first marks) and stress relaxation marks (second marks). In detail, as explained earlier, the strain measurement marks are markers for measuring strain based on their position, and can also be used as markers for aligning substrates and semiconductor chips. Therefore, the shape, position, density, and size of the strain measurement marks are fixed. In other words, the shape, position, density, and size of the strain measurement marks are not changed by the measured strain. In this embodiment, even if the wafer from which the support substrate 302 is cut is different, or even if the position of the support substrate 302 within the wafer is different, the shape, position, density, and size of the strain measurement marks will not change.

[0077] On the other hand, stress relief marks can alleviate surrounding strain by adjusting their shape, size, material, density, and position. For example, if the stress relief marks are formed from a high-stress film, the strain is relieved by applying stress to the surrounding area. Also, if the stress relief marks are formed from a sparse film, the strain is relieved by absorbing the surrounding strain. Furthermore, if the stress relief marks are formed from the same material as the surrounding layers, the difference in internal stress caused by the applied heat becomes smaller, making it less likely for strain to occur. Therefore, in this embodiment, the shape, position, density, and size of the stress relief marks can be changed according to the state of strain. In this embodiment, if the wafer from which the support substrate 302 is cut is different, or if the position of the support substrate 302 within the wafer is different, the shape, position, density, and size of the stress relief marks may differ. Furthermore, in this embodiment, if the position of the stress relief marks within the support substrate 302 is different, the shape, density, and size of the stress relief marks may differ.

[0078] Furthermore, in this embodiment, the mark 900 can be manufactured, for example, by forming a trench in the support substrate 302 and embedding various metal materials, various oxide materials, or nitride materials into the formed trench. The material embedded in the trench may also be a high-stress film containing high stress.

[0079] In this embodiment, as shown in Figure 8A, the mark 900 may include strain measurement marks 902. The strain measurement marks 902 are created, for example, as a grid pattern within a unit structure (shot 960) on the wafer from which the support substrate 302 is cut. The strain measurement marks 902 can be used to measure the strain of the support substrate 302 or the wafer from which the support substrate 302 is cut. The strain measurement marks 902 can also be used for alignment with the substrate 600. In this specification, shot 960 refers to the area irradiated in a single exposure and is not necessarily the same size as the support substrate 302.

[0080] Furthermore, in this embodiment, as shown in Figure 8B, the mark 900 may include stress relaxation marks 904 together with the strain measurement marks 902. Based on the measured strain, the stress relaxation marks 904 are formed within the shot 960. In the example shown in Figure 8B, multiple shots 960 are provided with stress relaxation marks 904 of the same form. Also, in this embodiment, within a single shot 960, the shape, position, and density of the stress relaxation marks 904 may be varied depending on their location within the shot 960 (in the example shown in Figure 8B, the densities are different). In this embodiment, since the stress relaxation marks 904 are provided according to the strain distributed within the shot 960, the strain within the shot 960 can be suitably relaxed. Note that in this embodiment, the strain measurement marks 902 and the stress relaxation marks 904 may be formed from the same material.

[0081] Furthermore, in this embodiment, as shown in Figure 8C, stress relaxation marks 904 having different shapes may be provided for each shot 960 based on the measured strain. In this embodiment, since stress relaxation marks 904 are provided according to the strain distribution within the wafer, the strain within the wafer can be suitably relaxed.

[0082] Furthermore, in this embodiment, as shown in Figure 8D, the strain measurement mark 902 and the stress relaxation mark 904 may be formed from different materials.

[0083] In this embodiment, the mark 900 is not limited to the form shown in Figures 8A to 8D.

[0084] <<6. Fifth Embodiment>> Next, as a fifth embodiment of the present disclosure, the difference between the strain measurement mark 902 and the stress relaxation mark 904 included in the mark 900 will be described with reference to Figures 9 and 10. Figures 9 and 10 are explanatory diagrams for illustrating the mark 900 according to this embodiment.

[0085] As shown on the right and left sides of Figure 9, in this embodiment, even if the shots 960 are different, the shape, position, density, and size of the strain measurement marks 902 remain fixed.

[0086] On the other hand, as shown on the right and left sides of Figure 9, in this embodiment, if the shots 960 are different, the stress relief marks 904 may change their shape, position, density, and size for each shot 960 in order to relieve different strains for each shot 960. Furthermore, in this embodiment, as shown on the right side of Figure 9, even within the same shot 960, the stress relief marks 904 may change their shape density and size according to their position in order to relieve different strains depending on their position within the shot 960.

[0087] Furthermore, in this embodiment, as shown in Figure 10, when a semiconductor chip 950 or the like is mounted on the support substrate 302, the strain measurement marks 902 are used for alignment and for measuring strain, so it is preferable that they are provided so as not to overlap with the semiconductor chip 950. On the other hand, the stress relaxation marks 904 may be provided so as to overlap with the semiconductor chip 950.

[0088] More specifically, in this embodiment, it is preferable that the stress relaxation mark 904 is smaller in size than the strain measurement mark 902. For example, the strain measurement mark 902 is several tens of micrometers. ２ From several hundred μm ２ The stress relaxation mark 904 is of a certain size, and is several micrometers in size. ２ It has the following dimensions. In addition, in this embodiment, the density of stress relaxation marks 904 is greater than that of strain measurement marks 902.

[0089] Furthermore, in this embodiment, the shape of the strain measurement mark 902 is composed of a set consisting of a pattern for the X direction and a pattern for the Y direction in order to perform alignment and measurement of strain in the X and Y directions on the plane of each substrate. On the other hand, the stress relaxation mark 904 is not particularly limited in shape, and may be rectangular, polygonal, circular, or a repetition of these simple shapes, or it may be a grid, honeycomb structure, or stripe shape.

[0090] In this embodiment, the mark 900 is not limited to the form shown in Figures 9 and 10.

[0091] <<7. Sixth Embodiment>> Next, as a sixth embodiment of the present disclosure, examples of the shapes of strain measurement marks 700, 800, 902 and stress relaxation marks 904 will be described with reference to Figure 11. Figure 11 is an explanatory diagram for illustrating the marks according to this embodiment.

[0092] In this embodiment, the strain measurement marks 700, 800, and 902 may be the "XY separate measurement type" shown in Figure 11 (1) or the "XY simultaneous measurement type" shown in Figure 11 (2) in order to align the X and Y directions on the plane of each substrate and measure the strain.

[0093] Furthermore, the strain measurement marks 700, 800, and 902 can be of the following shapes for alignment and strain measurement: the "Bar in Box type" shown in (a) of Figure 11, the "Bar in Bar type" shown in (b), the "Windmill type" shown in (c), the "Cross type" shown in (d), the "Circle type" shown in (e), the "Clover type" shown in (f), the "Four Box type" shown in (g), the "Asterisk type" shown in (h), etc.

[0094] Furthermore, the strain measurement marks 700, 800, and 902 may be of the "line / space type" as shown in Figure 11(i) for alignment and strain measurement. Figure 11(i) shows various examples of "line / space type" with different pitch lengths. Note that the "line / space type" marks can also be used as stress relaxation marks 904.

[0095] Furthermore, the distortion measurement marks 700, 800, and 902 may be various "alignment mark types for exposure machines" as shown in Figure 11(j) for measuring distortion.

[0096] Furthermore, the strain measurement marks 700, 800, and 902 may be of the "dummy mark type" shown in Figure 11(k) for alignment and strain measurement. In detail, the dummy mark type has the basic structure of the "Bar in Bar type" described above, but a part of it is composed of a minute rectangular dummy pattern. Note that the marks of the "dummy mark type" can also be used as stress relaxation marks 904.

[0097] Furthermore, in this embodiment, the stress relaxation mark 904 may be configured in the same way as wiring and through electrodes, as shown in Figure 11(l), or it may be rectangular, polygonal, circular, or a repeat of these simple shapes.

[0098] In this embodiment, the shapes of the strain measurement marks 700, 800, 902 and the stress relaxation mark 904 are not limited to the forms shown in Figure 11.

[0099] <<8. Seventh Embodiment>> <8.1 Example of Laminated Structure> The imaging device 1 described so far has been a laminated structure of mainly two substrates, a support substrate 302 and a substrate 600. However, in this embodiment, the imaging device 1 is not limited to this form and may be a laminated structure of three substrates. With reference to Figure 12, the detailed configuration of the imaging device 1a according to the seventh embodiment of this disclosure, which has a laminated structure of three substrates, will be described. Figure 12 is a cross-sectional view of the imaging device 1a according to this embodiment.

[0100] As shown in Figure 12, the imaging device 1a according to this embodiment has a stacked structure of three substrates 100, 200, and 300.

[0101] The substrate 100 bonded to the substrate 200 is, for example, a sensor substrate equipped with an image sensor that generates and outputs a pixel signal corresponding to the amount of incident light, and specifically, a pixel array section 11 including a plurality of image sensors 21 is provided.

[0102] In detail, the substrate 100 includes, for example, a semiconductor substrate 108 on which an image sensor 21 is provided, a transparent insulating film 106 laminated on the semiconductor substrate 108, a color filter 104 laminated on the transparent insulating film 106, and an on-chip lens 102 provided on the color filter 104. Furthermore, the substrate 100 has a wiring layer 110 consisting of an insulating film and wiring, provided on the surface of the semiconductor substrate 108 opposite to the transparent insulating film 106.

[0103] Furthermore, the substrate 100 is electrically and physically connected to the substrate 200 via electrodes 130 provided on the outermost surface of the wiring layer 110. The substrate 100 also has an opening 120 that penetrates the transparent insulating film 106, the semiconductor substrate 108, and the wiring layer 110 from the transparent insulating film 106 side, exposing electrodes 202 provided on the substrate 200.

[0104] Furthermore, in this embodiment, for example, strain measurement marks 700 are provided on the semiconductor substrate 108.

[0105] Furthermore, the substrate 200 bonded to the substrate 300 has a circuit including one or more transistors 242. More specifically, the substrate 200 is a logic chip equipped with a logic circuit that performs predetermined signal processing using an image signal, and specifically includes the signal processing unit 16 described above.

[0106] In detail, the substrate 200 has a semiconductor substrate 240 on which a transistor 242 is provided, and a wiring layer 210 consisting of an insulating film and wiring laminated on the semiconductor substrate 240. An electrode 204 is provided on the outermost surface of the wiring layer 210 for electrically and physically connecting to the substrate 100. That is, the electrode 204 is joined to the electrode 130 described above, thereby electrically and physically connecting the substrate 100 and the substrate 200. The substrate 200 also has through vias 230 that penetrate the semiconductor substrate 240, and an insulating film 250 provided on the surface of the semiconductor substrate 240 opposite to the wiring layer 210. An electrode 254 is provided on the outermost surface of the insulating film 250 for electrically and physically connecting to the substrate 300.

[0107] Furthermore, although not shown in the illustration, strain measurement marks 800 are provided within the substrate 200 in this embodiment.

[0108] Furthermore, the substrate 300 includes a support substrate 302, an insulating film 304 laminated on the support substrate 302, and an embedded layer 306 provided on the insulating film 304. In addition, semiconductor chips 400 and 500 are embedded in the embedded layer 306 via an insulating film 308. More specifically, as shown in Figure 12, the semiconductor chips 400 and 500 are arranged adjacent to each other in the horizontal direction on the substrate 300.

[0109] Furthermore, the semiconductor chips 400 and 500 have semiconductor substrates 440 and 540 made of, for example, silicon. Transistors 442 and 542 are provided on the semiconductor substrates 440 and 540. Wiring layers 410 and 510, consisting of an insulating film and wiring, are laminated on the semiconductor substrates 440 and 540. Electrodes 404 and 504 are provided on the outermost surface of the wiring layers 410 and 510 for electrical and physical connection to the substrate 200. That is, by joining the electrodes 404 and 504 with the aforementioned electrode 254, the substrate 200 and the substrate 300 are electrically and physically connected.

[0110] Furthermore, in this embodiment, for example, a mark 900 is provided on the support substrate 302.

[0111] <8.2 Manufacturing Method> Next, the manufacturing method of the imaging device 1a according to this embodiment will be described with reference to Figures 13A to 13C. Figures 13A to 13C are cross-sectional views showing the cross-sectional structure at each step of the manufacturing method of the imaging device 1a according to this embodiment.

[0112] First, in this embodiment, strain measurement marks 700 are formed on the semiconductor substrate 108, as shown on the left side of Figure 13A. Next, a wiring layer 110 is formed on the semiconductor substrate 108. Furthermore, a wiring layer 110 is formed on the semiconductor substrate 240. Then, by joining the semiconductor substrates 108 and 240 so that the wiring layers 110 face each other, the configuration shown second from the left in Figure 13A can be obtained.

[0113] Next, as shown in the third image from the left in Figure 13A, the semiconductor substrate 240 is thinned, and an insulating film 250 is deposited on the thinned semiconductor substrate 240. Furthermore, through electrodes that penetrate the insulating film 250 and the semiconductor substrate 240 are formed. Next, as shown in the fourth image from the left in Figure 13A, pads are formed on the through electrodes, and further, as shown on the right side of Figure 13A, copper wiring and copper pads are formed.

[0114] Next, semiconductor chips 400 and 500 are created. As shown in the upper left of Figure 13B, transistors, wiring layers 462, etc. are formed on the semiconductor substrate 460. Then, as shown in the second image from the left in the upper row of Figure 13B, the semiconductor substrate 460 is thinned. Furthermore, as shown in the third and fourth images from the left in the upper row of Figure 13B, the semiconductor substrate 460 is attached to a laminate film and cut to create individual semiconductor chips 400 and 500.

[0115] Next, as shown in the upper right of Figure 13B, the surfaces of the semiconductor chips 400 and 500 are cleaned. Then, as shown in the lower left of Figure 13B, the surfaces of the semiconductor chips 400 and 500 are activated. Furthermore, as shown in the second image from the left in the lower row of Figure 13B, the semiconductor chips 400 and 500 are cleaned. Next, as shown in the third and fourth images from the left in the lower row of Figure 13B, the semiconductor chips 400 and 500 are bonded to the laminated structure of the semiconductor substrates 108 and 240.

[0116] Then, as shown in the upper left of Figure 13C, an embedding layer 306 is stacked to fill the space between the bonded semiconductor chips 400 and 500. Furthermore, as shown second from the left in the upper part of Figure 13C, a mark 900 is formed on the support substrate 302. Next, as shown in the upper right of Figure 13C, the laminated structure of semiconductor substrates 108 and 240 is bonded to the support substrate 302.

[0117] Next, as shown in the lower left of Figure 13C, the semiconductor substrate 108 is thinned by polishing with CMP. Then, as shown second from the left in the lower part of Figure 13C, a color filter 104 and an on-chip lens 102 are formed, and as shown in the lower right of Figure 13C, the substrate is separated into individual pieces.

[0118] In this embodiment, the imaging device 1a is not limited to the form shown in Figure 12, nor is it limited to being manufactured by the manufacturing method shown in Figures 13A to 13C.

[0119] <<9. Summary>> As described above, the technology proposed in this disclosure allows for accurate measurement of strain in the state after chip bonding, embedding and planarization, support substrate bonding, thinning, etc., using the strain measurement marks included in strain measurement marks 700, 800, and 900. Furthermore, according to the technology proposed in this disclosure, the stress relaxation marks included in mark 900 are manufactured and modified based on the results of accurately measured strain, thereby effectively eliminating strain.

[0120] Furthermore, although the embodiments of this disclosure described above have been applied to an imaging device 1, the embodiments of this disclosure are not limited to being applied to an imaging device 1. The embodiments of this disclosure can be applied, for example, to semiconductor devices in which another semiconductor chip is flip-chip bonded to a semiconductor wafer or semiconductor chip.

[0121] Furthermore, in this disclosure, each embodiment and each variation of the disclosure described above can be implemented in combination with each other.

[0122] Furthermore, the imaging device 1 according to the embodiment of this disclosure can be manufactured using methods, apparatus, and conditions commonly used in the manufacture of semiconductor devices. In other words, the imaging device 1 according to this embodiment can be manufactured using existing semiconductor device manufacturing processes.

[0123] Examples of the methods mentioned above include the PVD (Physical Vapor Deposition) method, the CVD (Chemical Vapor Deposition) method, and the ALD (Atomic Layer Deposition) method. Examples of PVD methods include vacuum deposition, electron beam (EB) deposition, various sputtering methods (magnetron sputtering, RF (Radio Frequency)-DC (Direct Current) coupled bias sputtering, ECR (Electron Cyclotron Resonance) sputtering, counter-target sputtering, high-frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE (Molecular Beam Epitaxy)), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal-organic (MO) CVD, and optical CVD. Furthermore, other methods include electrolytic plating, electroless plating, spin coating, immersion, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, as well as stamping, spraying, air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calender coater. In addition, patterning methods include chemical etching such as shadow masking, laser transfer, and photolithography, as well as physical etching using ultraviolet light or lasers. Furthermore, planarization techniques include CMP, laser planarization, and reflow.

[0124] <<10. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the attached drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person with ordinary skill in the art of the present disclosure may conceive of various modifications or alterations within the scope of the technical ideas described in the claims, and these will naturally also fall within the technical scope of the present disclosure.

[0125] Furthermore, the effects described herein are merely descriptive or illustrative and not limiting. In other words, the technology relating to this disclosure may produce other effects that will be apparent to those skilled in the art from the description herein, in addition to or in lieu of the effects described herein.

[0126] Furthermore, this technology can also take the following configurations: (1) A semiconductor device comprising a first substrate and a second substrate laminated on the first substrate, wherein the second substrate includes a semiconductor substrate, a chip bonded above the semiconductor substrate, and an embedded layer in which the chip is embedded, the first bonding surface of the first substrate that is bonded to the embedded layer is provided with a first mark for measurement and a second mark for stress relief, and the second substrate is provided with a third mark for measurement. (2) The semiconductor device according to (1) above, wherein at least one of the shape, position, density, and size of the second mark is variable according to the measured strain of the laminated structure of the first substrate and the second substrate. (3) The semiconductor device according to (2) above, wherein at least one of the shape, position, density, and size of the second mark changes according to the wafer from which the first substrate is cut, the position of the first substrate within the wafer, or the position of the second mark within the first bonding surface. (4) The semiconductor device according to any one of (1) to (3) above, wherein the first mark and the second mark are formed from different materials. (5) The semiconductor device according to any one of (1) to (4) above, wherein the size of the second mark is smaller than that of the first mark. (6) The semiconductor device according to any one of (1) to (5) above, wherein the density of the second mark is greater than that of the first mark. (7) The semiconductor device according to any one of (1) to (6) above, wherein the second substrate further includes a wiring layer laminated on the semiconductor substrate, and the chip is bonded on the wiring layer. (8) The semiconductor device according to (7) above, wherein the semiconductor substrate is provided with the third mark. (9) The semiconductor device according to (7) above, wherein the wiring layer is provided with the third mark. (10) The semiconductor device according to (7) above, wherein the second substrate further includes a first stress relaxation layer provided between the wiring layer and the chip, and the first stress relaxation layer is provided with the third mark. (11) The semiconductor device according to (7), wherein the third mark is provided on the second bonding surface to which the embedded layer is bonded to the wiring layer.(12) The semiconductor device according to (7) above, wherein the third mark is provided in the embedded layer. (13) The semiconductor device according to (12) above, wherein the second substrate further includes a second stress relaxation layer provided in the embedded layer, and the third mark is provided in the second stress relaxation layer. (14) The semiconductor device according to any one of (1) to (13) above, wherein the third mark is provided so as not to overlap with the chip. (15) The semiconductor device according to any one of (1) to (14) above, wherein the semiconductor substrate includes a plurality of image sensors. (16) A method for manufacturing a semiconductor device, comprising: bonding a semiconductor substrate, a chip bonded above the semiconductor substrate, and a embedding layer in which the chip is embedded onto a first substrate having a first mark for measurement and a second mark for stress relaxation, such that the embedding layer is in contact with the first substrate; measuring the strain occurring in the laminated structure of the first substrate and the second substrate using the first mark and a third mark provided on the second substrate; and producing the next second mark on the first substrate by changing at least one of the shape, position, density, and size of the second mark according to the measurement results.

[0127] 1, 1a Imaging device 2 Pixel 11 Pixel array (cell array) 12 Row selection unit 13 Constant current source unit 14 Analog-to-digital conversion unit 15 Horizontal transfer scanning unit 16 Signal processing unit 17 Timing control unit 18 Horizontal transfer line 21 Image sensor (photodiode) 22 Transfer transistor 23 Reset transistor 24 Amplifier transistor 25 Selection transistor 31, 31 ｍ , 31 １ Vertical signal lines 32, 32 ｎ , 32 １Control lines 100, 200, 300, 600 Substrate 102 On-chip lens 104 Color filter 106 Transparent insulating film 108, 240, 440, 460, 540 Semiconductor substrate 110, 206, 210, 260, 410, 462, 510 Wiring layer 120 Aperture 130, 202, 204, 254, 404, 504 Electrode 230 Through-via 242, 442, 542 Transistor 250, 304, 308 Insulating film 302 Support substrate 306 Embedding layer 400, 500, 950 Semiconductor chip 700, 712, 720, 800, 814, 902 Strain measurement mark 722, 812 Stress relaxation layer 724 Through-electrode 900 Mark 904 Stress relaxation mark 960 Shot

Claims

1. A semiconductor device comprising a first substrate and a second substrate laminated on the first substrate, wherein the second substrate includes a semiconductor substrate, a chip bonded above the semiconductor substrate, and an embedded layer in which the chip is embedded, the first bonding surface of the first substrate that is bonded to the embedded layer is provided with a first mark for measurement and a second mark for stress relief, and the second substrate is provided with a third mark for measurement.

2. The semiconductor device according to claim 1, wherein at least one of the shape, position, density, and size of the second mark is variable in accordance with the measured strain of the laminated structure of the first and second substrates.

3. The semiconductor device according to claim 2, wherein at least one of the shape, position, density, and size of the second mark changes depending on the wafer from which the first substrate is cut, the position of the first substrate within the wafer, or the position of the second mark within the first bonding surface.

4. The semiconductor device according to claim 1, wherein the first mark and the second mark are formed from different materials.

5. The semiconductor device according to claim 1, wherein the size of the second mark is smaller than that of the first mark.

6. The semiconductor device according to claim 1, wherein the density of the second marks is greater than that of the first marks.

7. The semiconductor device according to claim 1, wherein the second substrate further includes a wiring layer laminated on the semiconductor substrate, and the chip is bonded on the wiring layer.

8. The semiconductor device according to claim 7, wherein the semiconductor substrate is provided with the third mark.

9. The semiconductor device according to claim 7, wherein the third mark is provided within the wiring layer.

10. The semiconductor device according to claim 7, wherein the second substrate further includes a first stress-relieving layer provided between the wiring layer and the chip, and the third mark is provided within the first stress-relieving layer.

11. The semiconductor device according to claim 7, wherein the third mark is provided on the second bonding surface to which the embedded layer is bonded to the wiring layer.

12. The semiconductor device according to claim 7, wherein the third mark is provided within the embedding layer.

13. The semiconductor device according to claim 12, wherein the second substrate further includes a second stress-relieving layer provided within the embedding layer, and the third mark is provided within the second stress-relieving layer.

14. The semiconductor device according to claim 1, wherein the third mark is provided so as not to overlap with the chip.

15. The semiconductor device according to claim 1, wherein the semiconductor substrate includes a plurality of image sensors.

16. A method for manufacturing a semiconductor device, comprising: bonding a semiconductor substrate, a chip bonded above the semiconductor substrate, and a embedding layer in which the chip is embedded onto a first substrate having a first mark for measurement and a second mark for stress relief, such that the embedding layer is in contact with the first substrate; measuring the strain occurring in the laminated structure of the first and second substrates using the first mark and a third mark provided on the second substrate; and creating the next second mark on the first substrate by changing at least one of the shape, position, density, and size of the second mark according to the measurement results.

Images