Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device (1) according to an embodiment of the present disclosure includes a semiconductor light-emitting element (10) and a block to which the light-emitting element is mounted, wherein the block has a bonding end surface (Sb2) with a normal line that intersects with a normal line of a mounting surface of the light-emitting element, and wherein the bonding end surface is provided with asperities having a repeating pattern.

Description

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICECROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority of U.S. Provisional Patent Application No. 63 / 739,324 filed December 27, 2024, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device, and to a method of manufacturing a semiconductor device.

[0003] When assembling precision equipment, it is important that no dust or the like adheres to a surface to be bonded (hereinafter referred to as a "target surface"), that is, cleanliness of the target surface is important. Examples of a method of inspecting the cleanliness of the target surface include a method of inspecting whether or not there is a defect in quality and characteristic such as dust or chipping on the target surface by using image data obtained by imaging the target surface.

[0004] For example. PTL 1 discloses inspection of the target surface.

[0005] PTL 1: Japanese Unexamined Patent Application Publication No. 2010-210451Summary

[0006] Incidentally, inspection of a target surface is desired to precisely detect a defect in quality and characteristic such as dust or chipping. It is desirable to provide a semiconductor device including a target surface on which a defect in quality and characteristic such as dust or chipping is detectable precisely, and a method of manufacturing such a semiconductor device.

[0007] A semiconductor device according to a first embodiment of the present disclosure includes a semiconductor light-emitting element and a block to which the light-emitting element is mounted, wherein the block has a bonding end surface with a normal line that intersects with a normal line of a mounting surface of the light-emitting element, and wherein the bonding end surface is provided with asperities having a repeating pattern.

[0008] A method of manufacturing a semiconductor device according to a second embodiment of the present disclosure includes the following five processes: (1) forming a bar-shaped substrate; (2) polishing a surface of the bar-shaped substrate to remove random asperities and create repeating asperities; (3) imaging the surface with an imaging device to create initial image data; (4) performing a fast Fourier transform (FFT) on the initial image data to filter the repeating asperities from the initial image data and create transformed image data without the repeating asperities; and (5) detecting particulate contamination on the surface as irregularities in the transformed image data.

[0009] Fig. 1 is a diagram illustrating an example of a perspective configuration of a light-emitting device according to an embodiment of the present disclosure.Fig. 2 is a diagram illustrating an example of a developed perspective configuration of the light-emitting device of Fig. 1.Fig. 3 is a diagram illustrating an example of a front configuration of the light-emitting device of Fig. 1.Fig. 4 is a diagram illustrating an example of a cross-sectional configuration at a location where a bonding metal layer is not provided of a bonding end surface of a submount of Fig. 1.Fig. 5 is a diagram illustrating an example of a cross-sectional configuration at a location where the bonding metal layer is provided of the bonding end surface of the submount of Fig. 1.(A) of Fig. 6 is a diagram illustrating an example of a manufacturing process of the submount of Fig. 1. (B) of Fig. 6 is a diagram illustrating an example of a manufacturing process subsequent to (A) of Fig. 6. (C) of Fig. 6 is a diagram illustrating an example of a manufacturing process subsequent to (B) of Fig. 6. (D) of Fig. 6 is a diagram illustrating an example of a planar configuration of a side surface of a bar-shaped substrate of (C) of Fig. 6.(A) of Fig. 7 is a diagram illustrating an example of a manufacturing process subsequent to (C) of Fig. 6. (B) of Fig. 7 is a diagram illustrating an example of a manufacturing process subsequent to (A) of Fig. 7. (C) of Fig. 7 is a diagram illustrating an example of a manufacturing process subsequent to (B) of Fig. 7. (D) of Fig. 7 is a diagram illustrating an example of a manufacturing process subsequent to (C) of Fig. 7.Fig. 8 is a diagram illustrating a modification example of a planar configuration of a bonding end surface of the submount of Fig. 1.Fig. 9 is a diagram illustrating a modification example of the planar configuration of the bonding end surface of the submount of Fig. 1.Fig. 10 is a diagram illustrating a modification example of the perspective configuration of the light-emitting device of Fig. 1.

[0010] <Background> A semiconductor light-emitting element such as a semiconductor laser element is usable as a light source or a heat source of an electronic apparatus. The semiconductor light-emitting element is fixed to, for example, a block such as a submount or a heat sink, and thereafter is bonded to a predetermined location in the electronic apparatus via the block. At this time, at the predetermined location, a surface (a simulated datum feature) is provided that is to be a reference for measurement of an attitude and a position of the block by coming into contact with a datum feature of the block.

[0011] It is important that no dust or the like adheres to the datum feature (hereinafter referred to as a "target surface") of the block, that is, cleanliness of the target surface is important. In a case where dust or the like adheres to the target surface, there is a possibility that the block is inclined and bonded to a predetermined location due to the dust or the like. It is therefore desirable to inspect whether or not dust or the like adheres to the target surface of the block before bonding the block to the predetermined location.

[0012] As a method of inspecting cleanliness of the target surface, a method is considered of inspecting whether or not dust or the like adheres to the target surface by using image data obtained by imaging the target surface. However, in a case where the image data includes noise different from the dust or the like, it is difficult to detect the dust or the like from the image data. It is desirable to provide a semiconductor device including a target surface to which adhesion of dust or the like is detectable precisely, and a method of manufacturing such a semiconductor device.

[0013] Incidentally, it is conceivable to reduce noise included in the image data by mirror-finishing the target surface. However, a mirror surface has a small surface area, and has low adhesiveness after bonding. It is more desirable to provide a semiconductor device including a target surface that has higher adhesiveness than that of the mirror surface and to which adhesion of dust or the like is detectable precisely, and a method of manufacturing such a semiconductor device.

[0014] Hereinafter, embodiments of the present disclosure are described in detail with reference to the drawings. In the present specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0015] The drawings to be referred to in the following description are intended to describe an embodiment of the present disclosure and facilitate understanding thereof; shapes, dimensions, ratios, and the like illustrated in the drawings may differ from actual ones, in some cases, for better understanding. Further, the design of a light-emitting device illustrated in the drawings can be modified as appropriate by taking into consideration the following description and known techniques. In addition, in the description using the cross-sectional view of the light-emitting device, the up / down direction of the stacked structure of the light-emitting device corresponds to a relative direction in a case where an external electrode to be wire-bonded is defined as being the top. The up / down direction may differ, in some cases, from an up / down direction that is compliant with the actual gravitational acceleration.

[0016] In the following description, expressions regarding a size and a shape do not only mean the same values as a numerical value defined mathematically or a shape defined geometrically. The expressions regarding a size and a shape also include a shape in a case of having an industrially acceptable difference in a step of manufacturing the light-emitting device or even a shape similar thereto.

[0017] In the description of the light-emitting device, unless otherwise specified, the term "coupling" means electrical coupling between a plurality of elements. Additionally, the term "coupling" in the following description includes not only a case of coupling a plurality of elements directly and electrically, but also a case of coupling the plurality of elements indirectly and electrically via another element. It is to be noted that the description is given in the following order. 1. Embodiment (Figs. 1 to 7) 2. Modification Examples (Figs. 8 to 10) 1. Embodiment <Configuration>

[0018] A description is given of a light-emitting device 1 according to an embodiment of the present disclosure. Fig. 1 illustrates a perspective configuration example of the light-emitting device 1. Fig. 2 illustrates a developed perspective configuration example of the light-emitting device of Fig. 1. Fig. 3 illustrates a front configuration example of the light-emitting device 1 of Fig. 1.

[0019] The light-emitting device 1 includes, for example, a semiconductor light-emitting element 10 provided with a ridge part R, and a submount 20, as illustrated in Figs. 1 to 3. The semiconductor light-emitting element 10 corresponds to a specific example of a "semiconductor light-emitting element " according to an embodiment of the present disclosure. The submount 20 corresponds to a specific example of a "submount" according to an embodiment of the present disclosure.

[0020] The semiconductor light-emitting element 10 is mounted on a top surface (a mounting surface Sb1) of the submount 20, with a surface, which is opposite to a surface on which the ridge part R is provided, being closer to the submount 20. The mounting surface Sb1 of the submount 20 is provided with a coupling electrode Ec and an external electrode Eb. The external electrode Eb is coupled to the coupling electrode Ec. A lower electrode 19 provided on a back surface of the semiconductor light-emitting element 10 is bonded to the coupling electrode Ec via solder 30. The solder 30 is configured by, for example, a Sn-based solder material. The mounting surface Sb1 corresponds to a specific example of a "mounting surface" and a "first main surface" according to an embodiment of the present disclosure. The lower electrode 19 corresponds to a specific example of a "first electrode" according to an embodiment of the present disclosure. The coupling electrode Ec corresponds to a specific example of a "coupling electrode" according to an embodiment of the present disclosure.

[0021] The semiconductor light-emitting element 10 includes a substrate 11 and a semiconductor layer 12. The semiconductor layer 12 is provided on the substrate 11. The semiconductor layer 12 is a stacked body formed by subjecting the substrate 11 as a crystal growth substrate to epitaxial crystal growth. The semiconductor layer 12 includes, for example, a lower clad layer 13, an active layer 14, an upper clad layer 15, and a contact layer 16 in this order from a side closer to the substrate 11. It is to be noted that the semiconductor layer 12 may further include another layer in addition to those described above. The semiconductor layer 12 may further include, for example, a buffer layer or a spacer layer. The buffer layer is to adjust lattice mismatch between the substrate 11 and the lower clad layer 13. The spacer layer is to adjust an optical confinement property in a stacking direction.

[0022] The substrate 11 and the semiconductor layer 12 are each provided with a pair of resonator end surfaces Sa1 and Sa2 opposed to each other in an extending direction of the ridge part R. The substrate 11 and the semiconductor layer 12 are each further provided with a pair of side surfaces Sa3 and Sa4 opposed to each other in a direction orthogonal to the extending direction of the ridge part R. Hereinafter, the direction orthogonal to the extending direction of the ridge part R is referred to as a "width direction of the ridge part R". Respective end surfaces of at least the substrate 11, the lower clad layer 13, the active layer 14, and the upper clad layer 15 are exposed to the resonator end surfaces Sa1 and Sa2 and the side surfaces Sa3 and Sa4.

[0023] The resonator end surface Sa1 and Sa2 are each a cleaved surface. The side surfaces Sa3 and Sa4 are each a cleaved surface or a dicing surface. The resonator end surface Sa1 is a light emission surface through which laser light is emitted to the outside. Accordingly, the semiconductor light-emitting element 10 is one kind of what is called an edge-emitting semiconductor laser. The resonator end surfaces Sa1 and Sa2 each function as a resonator mirror, and the ridge part R functions as an optical waveguide. The resonator end surface Sa1 may be provided with a multilayer reflective film that is configured so as to allow a reflectance at the resonator end surface Sa1 to be about 15%, for example. The resonator end surface Sa2 may be provided with a multilayer reflective film that is configured so as to allow a reflectance at the resonator end surface Sa2 to be about 95%, for example.

[0024] The semiconductor layer 12 is provided with the ridge part R having a raised shape. The ridge part R is provided between the resonator end surface Sa1 and the resonator end surface Sa2 in the semiconductor layer 12. The ridge part R has a band-like shape extending from the resonator end surface Sa1 to the resonator end surface Sa2. The ridge part R is provided on, for example, the contact layer 16 and the upper clad layer 15 of the semiconductor layer 12.

[0025] The substrate 11 is, for example, a Si-doped n-type GaAs substrate. The substrate 11 may be configured by a material system different from that of the semiconductor layer 12. In this case, the buffer layer described above may be provided in the semiconductor layer 12. The semiconductor layer 12 is configured by, for example, an AlxGa1-xAs-based (0 ≦ x < 1) semiconductor material. The lower clad layer 13 is configured by, for example, Si-doped n-type Alx1Ga1-x1As (0 < x1 < 1). The active layer 14 has, for example, a multiple-quantum well structure. The multiple-quantum well structure is, for example, a structure in which a barrier layer and a well layer are alternately stacked. The barrier layer is configured by, for example, Alx2Ga1-x2As (0 < x2 < 1). The well layer is configured by, for example, Alx3Ga1-x3As (0 < x3 < 1, and x3 > x2). In the active layer 14, a dopant in the multiple-quantum well structure of the active layer 14, and a doping concentration of the dopant are adjusted so as to allow an average electric characteristic of the active layer 14 to be of a p-type. The upper clad layer 15 is configured by, for example, C-doped p-type Alx4Ga1-x4As (0 < x4 < 1). The contact layer 16 is configured by, for example, C-doped p-type GaAs. The materials of the substrate 11 and the semiconductor layer 12 are not limited the materials described above.

[0026] The semiconductor light-emitting element 10 includes the upper electrode 18 on a top surface of the semiconductor layer 12. The semiconductor light-emitting element 10 includes the lower electrode 19 on a back surface of the substrate 11.

[0027] The upper electrode 18 is a metal layer to inject a current supplied from the outside into the ridge part R. The upper electrode 18 is provided in contact with a top surface of the ridge part R. The upper electrode 18 is in contact with the contact layer 16 provided on an upper part of the ridge part R, for example. The upper electrode 18 includes, for example, Ti Pt, and Au in this order from a side closer to the ridge part R. It is sufficient for the upper electrode 18 to be electrically coupled to the top surface of the ridge part R, and a layer configuration of the upper electrode 18 is not limited to the configuration described above.

[0028] The lower electrode 19 is provided in contact with the back surface of the substrate 11, for example. The lower electrode 19 includes, for example, at least two or more of Ti, Al, vanadium (V), Pt, or Au. The lower electrode 19 is electrically coupled to the back surface of the substrate 11. The lower electrode 19 may be in contact with the entire back surface of the substrate 11, or may be in contact with only a portion of the back surface of the substrate 11.

[0029] The semiconductor light-emitting element 10 includes an insulating film 17 that is in contact with both side surfaces and the foot of the ridge part R. The insulating film 17 is a film to regulate a region where a current supplied from the outside is to be injected into the ridge part R. The insulating film 17 has an opening at a location opposed to the top surface of the ridge part R. The upper electrode 18 is provided in the opening of the insulating film 17. The upper electrode 18 is in contact with the top surface of the ridge part R via the opening of the insulating film 17.

[0030] The semiconductor light-emitting element 10 includes an external electrode Ea on top surfaces of the upper electrode 18 and the insulating film 17. The external electrode Ea is, for example, a metal layer to which a bonding wire is bonded. The external electrode Ea includes, for example, Ti and Au in this order from a side closer to the upper electrode 18 and the insulating film 17. The external electrode Ea is electrically coupled to the top surface of the ridge part R via the upper electrode 18. The external electrode Ea may be formed collectively with the upper electrode 18.

[0031] The submount 20 includes a block 21. The block 21 includes the mounting surface Sb1 and a bonding end surface Sb2 on a surface. The semiconductor light-emitting element 10 is mounted on the mounting surface Sb1. The bonding end surface Sb2 has a normal line that intersects with a normal line of the mounting surface Sb1. The block 21 further includes a non-bonding end surface Sb3 and a pair of side surfaces Sb4 and Sb5 on the surface. The non-bonding end surface Sb3 is opposed to the bonding end surface Sb2. The pair of side surfaces Sb4 and Sb5 each has a normal line that intersects with the normal lines of the mounting surface Sb1 and the bonding end surface Sb2.

[0032] The block 21 corresponds to a specific example of a "block" according to an embodiment of the present disclosure. The bonding end surface Sb2 corresponds to a specific example of a "first end surface" according to an embodiment of the present disclosure. The block 21 is configured by an insulating material having a high heat dissipation property. The block 21 is configured by, for example, AlN, Si, SiC, Cu, W, Mo, Al, diamond, or a composite material including these materials such as Cu-W or Al-SiC.

[0033] The mounting surface Sb1 is provided with the coupling electrode Ec and the external electrode Eb. The lower electrode 19 of the semiconductor light-emitting element 10 is bonded to the coupling electrode Ec via the solder 30. The external electrode Eb is, for example, a metal layer to which a bonding wire is bonded. The coupling electrode Ec and the external electrode Eb each include, for example, Ti, Pt, and Au in this order from a side closer to the block 21. It is sufficient for the coupling electrode Ec and the external electrode Eb to be able to be in close contact with the mounting surface Sb1 of the block 21, and a layer configuration thereof is not limited the configuration described above.

[0034] The bonding end surface Sb2, the non-bonding end surface Sb3, and the side surfaces Sb4 and Sb5 are side surfaces of the block 21. The block 21 has a size larger than a size of the semiconductor light-emitting element 10. Specifically, the mounting surface Sb1 of the block 21 has a size larger than a size of the lower electrode 19 of the semiconductor light-emitting element 10. For example, the semiconductor light-emitting element 10 is bonded to the mounting surface Sb1 so as to allow the ridge part R to be positioned opposed to a center position of the mounting surface Sb1 in the width direction of the ridge part R, for example. The resonator end surface Sa1 is disposed, for example, at a position close to the bonding end surface Sb2. The resonator end surface Sa2 is disposed, for example, at a position away from the non-bonding end surface Sb3 by a distance longer than a distance between the resonator end surface Sa1 and the bonding end surface Sb2. The side surface Sa3 is disposed, for example, at a position close to the side surface Sb4. The side surface Sa4 is disposed, for example, at a position away from the side surface Sb5 by a distance longer than a distance between the side surface Sa3 and the side surface Sb4. The position of the semiconductor light-emitting element 10 on the mounting surface Sb1 is not limited to the position described above.

[0035] Incidentally, the bonding end surface Sb2 is a bonding surface to be bonded to an external component. The semiconductor light-emitting element 10 is bonded to the external component via the submount 20. At this time, the bonding end surface Sb2 serves as a datum feature. A datum indicates a theoretically exact geometric reference that is set to define an attitude or a position of a feature. Meanwhile, a surface of the external component, to which the bonding end surface Sb2 (the datum feature) of the submount 20 is to be bonded, is a surface (a simulated datum feature) that is to be a reference for measurement of an attitude and a position of the submount 20 by coming into contact with the bonding end surface Sb2 (the datum feature) of the submount 20.

[0036] For example, as illustrated in Figs. 1 to 4, the entire bonding end surface Sb2 is provided with asperities 21A having a monotonous and periodic geometric pattern. The asperities 21A correspond to a specific embodiment of "asperities" according to an embodiment of the present disclosure. Here, the term "monotonous" means that there is only one type of asperities. The term "monotonous" is a concept excluding asperities in which a plurality of types of asperities is superimposed on each other. The term "monotonous" is, for example, a concept excluding asperities in which first asperities having a periodic geometric pattern and second asperities different from the first asperities are superimposed on each other. The second asperities may be asperities having a periodic geometric pattern different from that of the first asperities.

[0037] For example, it is assumed that illumination light is incident perpendicularly on a surface (the bonding end surface Sb2) provided with the asperities 21A, and reflected light on the bonding end surface Sb2 is imaged by an imaging device to thereby obtain image data. Hereinafter, the image data thus obtained is referred to as "first image data". At this time, the asperities 21A are configured with a periodic geometric pattern that makes it possible to distinguish the asperities 21A and dust or the like present on the bonding end surface Sb2 from each other in the first image data by performing image processing such as FFT on the first image data. The asperities 21A are configured with a periodic geometric pattern that makes it possible to remove the asperities 21A in the first image data by performing image processing such as FFT on the first image data. The illumination light is, for example, coaxial light. An incident direction of the illumination light is, for example, a direction parallel to an extending direction of the asperities 21A.

[0038] For example, as illustrated in Figs. 1 to 4, the asperities 21A include a plurality of linear recesses extending in a predetermined direction when the bonding end surface Sb2 is viewed in plan view. The extending direction of the plurality of linear recesses is not particularly limited. The extending direction of the plurality of linear recesses corresponds to a specific example of a "first direction" according to an embodiment of the present disclosure. At this time, an asperity pitch of the asperities 21A is, for example, from about 1 μm to about 50 μm. An asperity height of the asperities 21A is, for example, from about 0.1 μm to about 1.0 μm.

[0039] The bonding end surface Sb2 is provided with a bonding metal layer 22. The bonding metal layer 22 is bonded to an external component via solder, for example. The bonding metal layer 22 includes, for example, Ti, Pt and Au in this order from a side closer to the bonding end surface Sb2. It is sufficient for the bonding metal layer 22 to be able to be in close contact with the bonding end surface Sb2, and a layer configuration of the bonding metal layer 22 is not limited to the configuration described above. For example, as illustrated in Figs. 1 to 3 and 5, the entire bonding metal layer 22 is provided with asperities 22A having a monotonous and periodic geometric pattern. The asperities 22A have an asperity shape corresponding to that of the asperities 21A. As illustrated in Figs. 1 to 3 and 5, the asperities 22A includes, for example, a plurality of linear recesses extending in the same direction as the extending direction of the asperities 21A when the bonding end surface Sb2 is viewed in plan view. An asperity pitch of the asperities 22A is, for example, from about 1 μm to about 50 μm. An asperity height of the asperities 22A is, for example, from about 0.1 μm to about 1.0 μm. <Operations>

[0040] In the light-emitting device 1 having such a configuration, when a predetermined voltage is applied between the upper electrode 18 and the lower electrode 19, a current is injected into the active layer 14 through the ridge part R, which causes light to be emitted due to recombination of electrons and holes. The light is reflected by the pair of resonator end surfaces Sa1 and Sa2, and is confined by the lower clad layer 13 and the upper clad layer 15, thereby causing generation of laser oscillation at a predetermined oscillation wavelength. At this time, an optical waveguide region where oscillated laser light is to be guided is formed in the semiconductor layer 12. The optical waveguide region is generated in a region directly below the ridge part R, with the active layer 14 being centered. Thereafter, laser light of a predetermined oscillation wavelength is emitted from one resonator end surface Sa1 to the outside. <Manufacturing Method>

[0041] A description is given next of a method of manufacturing the submount 20. (A) of Fig. 6 illustrates an example of a manufacturing process of the submount 20. (B) of Fig. 6 illustrates an example of a manufacturing process subsequent to (A) of Fig. 6. (C) of Fig. 6 illustrates an example of a manufacturing process subsequent to (B) of Fig. 6. (D) of Fig. 6 illustrates a planar configuration example of a side surface of a bar-shaped substrate 300 of (C) of Fig. 6. (A) of Fig. 7 illustrates an example of a manufacturing process subsequent to (C) of Fig. 6. (B) of Fig. 7 illustrates an example of a manufacturing process subsequent to (A) of Fig. 7. (C) of Fig. 7 illustrates an example of a manufacturing process subsequent to (B) of Fig. 7. (D) of Fig. 7 illustrates an example of a manufacturing process subsequent to (C) of Fig. 7.

[0042] First, a substrate 100 including the same material as the material of the block 21 is prepared. Thereafter, the external electrodes Eb and the coupling electrodes Ec are formed at predetermined intervals on the substrate 100 (see (A) of Fig. 6). Thus, a surface of the substrate 100 serves as a mounting surface 110. Thereafter, for example, the substrate 100 is diced using a dicing blade 200, for example, (see (A) of Fig. 6). Thus, the bar-shaped substrate 300 is formed in which a pair of dicing surfaces is formed (see (B) of Fig. 6).

[0043] At this time, a top surface of the bar-shaped substrate 300 serves as a mounting surface 310 on which a plurality of external electrodes Eb and a plurality of coupling electrodes Ec are formed side by side in one line. In addition, one dicing surface of the pair of dicing surfaces of the bar-shaped substrate 300 is referred to as a "side surface 320". At this time, the side surface 320 is a surface that is not subjected to polishing in a next process. Accordingly, the side surface 320 at this time is referred to as a "pre-polished surface 320a".

[0044] Thereafter, the pre-polished side surface 320a is polished using a polishing wheel 400, for example, (see (C) of Fig. 6). Thus, the asperities 21A having a monotonous and periodic geometric pattern are formed on the entire polished pre-polished side surface 320a. It is possible to form the asperities 21A including a plurality of linear recesses, for example, by adjusting a way of polishing using the polishing wheel 400. At this time, the side surface 320 on which the asperities 21A are formed is referred to as a "polished side surface 320b". The pre-polished side surface 320a has random asperities 21B formed by dicing, as illustrated in a drawing on the right of (D) of Fig. 6. In contrast, the polished side surface 320b does not has the random asperities 21B, and has only the asperities 21A having a monotonous and periodic geometric pattern, as illustrated in the drawing on the left of (D) of Fig. 6.

[0045] Thereafter, a plurality of bonding metal layers 22 is formed at predetermined locations of the polished side surface 320b (see (A) of Fig. 7). Thereafter, the bar-shaped substrate 300 is diced using the dicing blade 200, for example (see (B) of Fig. 7). Thus, the block 21 including the bonding end surface Sb2 and the mounting surface Sb1 is formed (see (C) of Fig. 7). The bonding end surface Sb2 is a part of the polished dicing surface (the polished side surface 320b) and serves as a datum feature. The mounting surface Sb1 is a part of the mounting surface 310. Thereafter, the semiconductor light-emitting element 10 is mounted on the mounting surface Sb1 of the block 21 by using a mounter, for example (see (D) of Fig. 7). As a result, the light-emitting device 1 is formed in which the semiconductor light-emitting element 10 is mounted on the submount 20. <Effects>

[0046] A description is given next of effects of the light-emitting device 1.

[0047] In the present embodiment, the entire bonding end surface Sb2 that is a datum feature is provided with the asperities 21A having a monotonous and periodic geometric pattern. Accordingly, it is possible to make asperities included in the first image data described above less noticeable or remove the asperities, for example, by performing image processing such as FFT on the first image data. As a result, it is possible to easily detect dust or the like adhering to the bonding end surface Sb2 from the first image data. It is to be noted that in a case where, for example, random asperities due to dicing are formed on a bonding end surface, even if image processing such as FFT is performed on image data (hereinafter referred to as "second image data") obtained by imaging the entire bonding end surface, it is difficult to distinguish asperities included in the second image data and the dust or the like present on the bonding end surface from each other. This makes it difficult to easily detect dust or the like adhering to the bonding end surface from the second image data. As described above, in the present embodiment, it is possible to more precisely detect presence of dust or the like adhering to the bonding end surface Sb2. This makes it possible to provide the submount 20 including the bonding end surface Sb2 to which adhesion of dust or the like is detectable precisely, and a method of manufacturing such a submount 20.

[0048] In the present embodiment, the entire bonding end surface Sb2 is provided with the plurality of linear recesses extending in the predetermined direction when the bonding end surface Sb2 is viewed in plan view. Accordingly, it is possible to make asperities included in the first image data less noticeable or remove the asperities, for example, by performing image processing such as FFT on the first image data. As a result, it is possible to easily detect dust or the like adhering to the bonding end surface Sb2 from the first image data. This makes it possible to provide the submount 20 including the bonding end surface Sb2 to which adhesion of dust or the like is detectable precisely, and a method of manufacturing such a submount 20.

[0049] In the present embodiment, the mounting surface Sb1 of the submount 20 is provided with the coupling electrode Ec, and the lower electrode 19 of the semiconductor light-emitting element 10 is bonded to the coupling electrode Ec. For example, this makes it possible to bond the semiconductor light-emitting element 10 to an external component via the submount 20. As a result, it is possible to precisely bond the semiconductor light-emitting element 10 to the external component.

[0050] In the present embodiment, the entire bonding end surface Sb2 is provided with the asperities 21A. This makes it possible to increase a surface area of the bonding end surface Sb2 and enhance adhesiveness between the bonding end surface Sb2 and the external component, as compared with a case where the entire bonding end surface is a mirror surface. <2. Modification Examples>

[0051] A description is given next of modification examples of the light-emitting device 1 according to the embodiment described above. <Modification Example A>

[0052] In the embodiment described above, for example, as illustrated in Fig. 8, the asperities 21A may include a plurality of dashed linear recesses extending in a predetermined direction when the bonding end surface Sb2 is viewed in plan view. It is possible to form the asperities 21A including the plurality of dashed linear recesses, for example, by adjusting the way of polishing using the polishing wheel 400. In such a case also, it is possible to make asperities included in the first image data less noticeable or remove the asperities, for example, by performing image processing such as FFT on the first image data. As a result, it is possible to easily detect dust or the like adhering to the bonding end surface Sb2 from the first image data. This makes it possible to provide the submount 20 including the bonding end surface Sb2 to which adhesion of dust or the like is detectable precisely, and a method of manufacturing such a submount 20. <Modification Example B>

[0053] In the embodiment described above, for example, as illustrated in Fig. 9, the asperities 21A may include a plurality of dotted recesses regularly arranged in a first direction and a second direction intersecting with the first direction when the bonding end surface Sb2 is viewed in plan view. It is possible to form the asperities 21A including the plurality of dotted recesses, for example, by adjusting the way of polishing using the polishing wheel 400. In such a case also, it is possible to make asperities included in the first image data less noticeable or remove the asperities, for example, by performing image processing such as FFT on the first image data. As a result, it is possible to easily detect dust or the like adhering to the bonding end surface Sb2 from the first image data. Tis makes it possible to provide the submount 20 including the bonding end surface Sb2 to which adhesion of dust or the like is detectable precisely, and a method of manufacturing such a submount 20. <Modification Example C>

[0054] In the embodiment described above and Modification Examples A and B, for example, as illustrated in Fig. 10, a heat sink 40 may be provided instead of the submount 20. The heat sink 40 corresponds to a specific example of a "heat sink" according to an embodiment of the present disclosure.

[0055] As with the submount 20, for example, as illustrated in Fig. 10, the heat sink 40 includes a block including the mounting surface Sb1, the bonding end surface Sb2, the non-bonding end surface Sb3, and the side surfaces Sb4 and Sb5 on a surface. The block of the heat sink 40 corresponds to a specific example of a "block" according to an embodiment of the present disclosure. In the block of the heat sink 40, the mounting surface Sb1 is provided with the coupling electrode Ec and an the external electrode Eb. In the block of the heat sink 40, the bonding end surface Sb2 is provided with the bonding metal layer 22. The block of the heat sink 40 is configured by, for example, Cu, Fe, Al, Au, W, Mo, or a composite material including these materials such as Cu-W or Cu-Mo.

[0056] As described above, in the present modification example, the entire bonding end surface Sb2 of the heat sink 40 is provided with the asperities 21A having a monotonous and periodic geometric pattern. In such a case, it is possible to provide the heat sink 40 including the bonding end surface Sb2 to which adhesion of dust or the like is detectable precisely, and a method of manufacturing such a heat sink 40.

[0057] In the present modification example, the entire bonding end surface Sb2 of the heat sink 40 is provided with the asperities 21A. Accordingly, it is possible to increase the surface area of the bonding end surface Sb2 and enhance adhesiveness between the bonding end surface Sb2 and the external component, as compared with the case where the entire bonding end surface is a mirror surface. <Modification Example D>

[0058] In the embodiment described above and Modification Examples A to C, the semiconductor light-emitting element 10 may be mounted on the top surface (the mounting surface Sb1) of the submount 20, with the surface, on which the ridge part R is provided, being closer to the submount 20. At this time, the external electrode Ea is bonded to the coupling electrode Ec via the solder 30. In addition, the lower electrode 19 serves as an external electrode to be wire-bonded. In such a case also, it is possible to achieve effects similar to those of the embodiment described above and Modification Examples A to C.

[0059] Although the present disclosure has been described above with reference to the embodiment, the modification examples thereof, and the application example thereof, the present disclosure is not limited to the embodiment and the like described above, and may be modified in a wide variety of ways. It is to be noted that the effects described herein is merely exemplary. The effects of the present disclosure are not limited to the effects described herein. The present disclosure may have effects other than the effects described herein.

[0060] In addition, for example, the present disclosure may also have the following configurations. (1) A semiconductor device including: a block including, on a surface, a mounting surface on which a semiconductor light-emitting element is to be mounted, and a first end surface that has a normal line intersecting with a normal line of the mounting surface, in which the entire first end surface is provided with monotonous and periodic asperities. (2) The semiconductor device according to (1), in which the entire first end surface is provided with a plurality of linear recesses, as the asperities, extending in a first direction. (3) The semiconductor device according to (1), in which the entire first end surface is provided with a plurality of dashed linear recesses, as the asperities, extending in a first direction. (4) The semiconductor device according to (1), in which the entire first end surface is provided with a plurality of dotted recesses, as the asperities, regularly arranged in a first direction and a second direction intersecting with the first direction. (5) The semiconductor device according to any one of (1) to (4), in which the block includes a submount or a heat sink. (6) The semiconductor device according to (5), further including the semiconductor light-emitting element, in which the semiconductor light-emitting element includes a first electrode, and the mounting surface is provided with a coupling electrode that is bonded to the first electrode. (7) The semiconductor device according to (6), in which the first end surface includes a bonding surface to an external component. (8) The semiconductor device according to (1), in which the first end surface serves as a datum feature. (9) A method of manufacturing a semiconductor device, the method including: forming a bar-shaped substrate, in which a pair of dicing surfaces is formed, by dicing a substrate including a mounting surface on which a semiconductor light-emitting element is to be mounted; performing polishing on one of the dicing surfaces to thereby form monotonous and periodic asperities on the entire polished dicing surface; and forming a block including a first end surface and a first main surface by dicing the bar-shaped substrate, the first end surface being a part of the polished dicing surface, the first main surface being a part of the mounting surface. (10) The method of manufacturing the semiconductor device according to (9), in which a plurality of linear recesses extending in a first direction is formed as the asperities by performing the polishing. (11) The method of manufacturing the semiconductor device according to (9), in which a plurality of dashed linear recesses extending in a first direction is formed as the asperities by performing the polishing. (12) The method of manufacturing the semiconductor device according to (9), in which a plurality of dotted recesses arranged in a first direction and a second direction intersecting with the first direction is formed as the asperities by performing the polishing. (13) A semiconductor device, comprising a semiconductor light-emitting element and a block to which the light-emitting element is mounted, wherein the block has a bonding end surface with a normal line that intersects with a normal line of a mounting surface of the light-emitting element, and wherein the bonding end surface is provided with asperities having a repeating pattern. (14) The semiconductor device according to (13), wherein the asperities have a regular pattern. (15) The semiconductor device according to (14), wherein the geometric pattern is regular in a first direction and semi-regular in a second direction which intersects the first direction, and the first direction and the second direction are tangential to a plane of the bonding end surface. (16) The semiconductor device according to (13) to (15), wherein a resonator end surface of the light-emitting element is disposed at a position closer to the bonding end surface than a surface longitudinally opposed to the bonding end surface. (17) The semiconductor device according to (13) to (16), wherein the asperities are provided across the entire bonding end surface. (18) The semiconductor device according to (13) to (17), wherein at least one portion of the bonding end surface includes an increased or decreased pitch between adjacent pairs of asperities where the pattern is locally irregular. (19) The semiconductor device according to (13) to (18), wherein the asperities include a plurality of substantially linear recesses extending in a common direction tangential to a plane of the bonding end surface. (20) The semiconductor device according to (13) to (19), wherein the asperities include a plurality of dotted recesses regularly or semi-regularly arranged in a first direction and a second direction intersecting with the first direction, wherein the first direction and the second direction are tangential to a plane of the bonding end surface. (21) The semiconductor according to (13) to (20), wherein the bonding end surface is provided with a bonding metal layer. (22) The semiconductor device according to (13) to (21), wherein the block is a submount or a heatsink. (23) The semiconductor device according to (13) to (22), wherein the asperities have a pitch in a first direction between 1 μm to 50 μm and a height between 0.1 μm to about 1.0 μm. (24) The semiconductor device according to (23), wherein the asperities have a pitch in a second direction different from the pitch in the first direction and the second direction intersects the first direction. (25) The semiconductor device according to (13) to (24), wherein the block includes AlN, Si, SiC, Cu, W, Mo, Al, diamond, or composites thereof. (26) A method of manufacturing a semiconductor device, comprising forming a bar-shaped substrate, polishing a surface of the bar-shaped substrate to remove random asperities and create repeating asperities, imaging the surface with an imaging device to create initial image data, performing a fast Fourier transform (FFT) on the initial image data to filter the repeating asperities from the initial image data and create transformed image data without the repeating asperities, and detecting particulate contamination on the surface as irregularities in the transformed image data. (27) The method according to (26), wherein the initial image data is collected with illumination light incident substantially perpendicularly to the surface. (28) The method according to (27), wherein the illumination light is coaxial light. (29) The method according to (26) to (28), further comprising dicing the bar-shaped semiconductor substrate on a dicing plane substantially normal to a plane of the surface and substantially normal to a plane of an element mounting surface. (30) The method according to (29), further comprising mounting a semiconductor light-emitting element to the element mounting surface. (31) The method according to (30), wherein at least one surface of the substrate substantially parallel to the dicing plane is unpolished. (32) The method according to (26) to (31), wherein the repeating asperities have a regular pattern. (33) The method according to (26) to (31), further comprising depositing a bonding metal layer upon the surface.

[0061] In a semiconductor device according to a first embodiment of the present disclosure and a method of manufacturing a semiconductor device according to a second embodiment of the present disclosure, an entire first end surface is provided with monotonous and periodic asperities. Accordingly, for example, FFT processing is performed on image data (hereinafter referred to as "first image data") obtained by imaging the entire first end surface, which makes it possible to remove asperities included in the first image data. As a result, it is possible to easily detect a defect in quality and characteristic such as dust or chipping on the first end surface from the first image data. It is to be noted that in a case where, for example, random asperities due to dicing are formed on the first end surface, even if the FFT processing is performed on image data (hereinafter referred to as "second image data") obtained by imaging the entire first end surface, it is difficult to remove the asperities included in the second image data. This makes it difficult to easily detect a defect in quality and characteristic such as dust or chipping on the first end surface from the second image data. As described above, in the present disclosure, it is possible to precisely detect a defect in quality and characteristic such as dust or chipping on the first end surface. This makes it possible to provide a semiconductor device including a target surface on which a defect in quality and characteristic such as dust or chipping is detectable precisely, and a method of manufacturing such a semiconductor device.

[0062] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.Reference Numerals List

[0063] 1 light-emitting device 10 semiconductor light-emitting element 11 substrate 12 semiconductor layer 13 lower clad layer 14 active layer 15 upper clad layer 6 contact layer 17 insulating film 18 upper electrode 19 lower electrode 20 submount 21 block 21A, 22A asperities 22 bonding metal layer 30 solder 40 heat sink 100 substrate 110 mounting surface 200 dicing blade 300 bar-shaped substrate 310 mounting surface 320 side surface 320a pre-polished side surface 320b polished side surface 400 polishing wheel Ea, Eb external electrode Ec coupling electrode R ridge part Sa1, Sa2 resonator end surface Sa3, Sa4 side surface Sb1 mounting surface Sb2 bonding end surface Sb3 non-bonding end surface Sb4, Sb5 side surface

Claims

1. A semiconductor device, comprising: a semiconductor light-emitting element; and a block to which the light-emitting element is mounted, wherein the block has a bonding end surface with a normal line that intersects with a normal line of a mounting surface of the light-emitting element, and wherein the bonding end surface is provided with asperities having a repeating pattern.

2. The semiconductor device of claim 1, wherein the asperities have a regular pattern.

3. The semiconductor device of claim 2, wherein the geometric pattern is regular in a first direction and semi-regular in a second direction which intersects the first direction, and the first direction and the second direction are tangential to a plane of the bonding end surface.

4. The semiconductor device of claim 1, wherein a resonator end surface of the light-emitting element is disposed at a position closer to the bonding end surface than a surface longitudinally opposed to the bonding end surface.

5. The semiconductor device of claim 1, wherein the asperities are provided across the entire bonding end surface.

6. The semiconductor device of claim 1, wherein at least one portion of the bonding end surface includes an increased or decreased pitch between adjacent pairs of asperities where the pattern is locally irregular.

7. The semiconductor device of claim 1, wherein the asperities include a plurality of substantially linear recesses extending in a common direction tangential to a plane of the bonding end surface.

8. The semiconductor device of claim 1, wherein the asperities include a plurality of dotted recesses regularly or semi-regularly arranged in a first direction and a second direction intersecting with the first direction, wherein the first direction and the second direction are tangential to a plane of the bonding end surface.

9. The semiconductor device of claim 1, wherein the bonding end surface is provided with a bonding metal layer.

10. The semiconductor device of claim 1, wherein the block is a submount or a heatsink.

11. The semiconductor device of claim 1, wherein the asperities have a pitch in a first direction between 1 μm to 50 μm and a height between 0.1 μm to about 1.0 μm.

12. The semiconductor device of claim 11, wherein the asperities have a pitch in a second direction different from the pitch in the first direction and the second direction intersects the first direction.

13. The semiconductor device of claim 1, wherein the block includes AlN, Si, SiC, Cu, W, Mo, Al, diamond, or composites thereof.

14. A method of manufacturing a semiconductor device, comprising: forming a bar-shaped substrate; polishing a surface of the bar-shaped substrate to remove random asperities and create repeating asperities; imaging the surface with an imaging device to create initial image data; performing a fast Fourier transform (FFT) on the initial image data to filter the repeating asperities from the initial image data and create transformed image data without the repeating asperities; and detecting particulate contamination on the surface as irregularities in the transformed image data.

15. The method of claim 14, wherein the initial image data is collected with illumination light incident substantially perpendicularly to the surface.

16. The method of claim 15, wherein the illumination light is coaxial light.

17. The method of claim 14, further comprising dicing the bar-shaped semiconductor substrate on a dicing plane substantially normal to a plane of the surface and substantially normal to a plane of an element mounting surface.

18. The method of claim 17, further comprising mounting a semiconductor light-emitting element to the element mounting surface.

19. The method of claim 18, wherein at least one surface of the substrate substantially parallel to the dicing plane is unpolished.

20. The method of claim 14, wherein the repeating asperities have a regular pattern.

21. The method of claim 14, further comprising depositing a bonding metal layer upon the surface.

Images