Semiconductor device

Abstract

In the present invention, a plurality of trenches are recessed from a first substrate surface toward a second substrate surface. A dielectric layer covers the first substrate surface and the inner surfaces of the plurality of trenches. A first conductive layer is provided on the dielectric layer. A first external electrode is provided so as to cover a portion of the first conductive layer. A second external electrode is disposed apart from the first external electrode when viewed from the Z-axis direction, and is in contact with the first substrate surface. A second conductive layer is provided on the second substrate surface. The dielectric layer includes a plurality of inner surface dielectric layers provided on the inner surfaces of the plurality of trenches. The first conductive layer includes a plurality of internal electrodes provided so as to fill at least a part of an internal region surrounded by the plurality of inner surface dielectric layers. A semiconductor substrate and the plurality of internal electrodes face each other with the plurality of inner surface dielectric layers interposed therebetween, and thereby constitute a capacitor.

Description

Semiconductor equipment

[0001] This disclosure relates to semiconductor devices.

[0002] Conventionally, capacitors are used in various circuits. Some capacitors use a semiconductor substrate as one of their electrodes (see, for example, Patent Document 1). One electrode of the capacitor is mounted on a substrate for constructing the circuit, and the other electrode of the capacitor is connected to a pad on the substrate by a wire.

[0003] Japanese Patent Publication No. 2022-134391

[0004] [Overview] Incidentally, there are times when it is necessary to reduce the inductance in circuits that use capacitors. For this reason, semiconductor devices that include capacitors are required to reduce their inductance.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface; a plurality of trenches recessed from the first substrate surface toward the second substrate surface; a dielectric layer covering the inner surfaces of the plurality of trenches and the first substrate surface; a first conductive layer provided on the dielectric layer; a first external electrode provided so as to cover a part of the first conductive layer; a second external electrode arranged at a distance from the first external electrode when viewed from the thickness direction of the semiconductor substrate and in contact with the first substrate surface; and a second conductive layer provided on the second substrate surface. The dielectric layer includes a plurality of inner dielectric layers provided on the inner surfaces of the plurality of trenches, and a surface dielectric layer covering the first substrate surface. The first conductive layer includes a plurality of internal electrodes provided so as to fill at least a part of the internal region surrounded by the plurality of inner dielectric layers; and a surface electrode provided on the surface dielectric layer that electrically connects the plurality of internal electrodes. The semiconductor substrate and the plurality of internal electrodes face each other across the plurality of inner dielectric layers to constitute a capacitor.

[0006] Figure 1 is a schematic perspective view of an exemplary semiconductor device according to one embodiment. Figure 2 is a schematic plan view of the semiconductor device of Figure 1. Figure 3 is a schematic plan view showing the semiconductor substrate and trench of the semiconductor device of Figure 1. Figure 4 is a schematic cross-sectional view of the semiconductor device along the line F4-F4 in Figure 2. Figure 5 is a schematic perspective view of the semiconductor device of Figure 4. Figure 6 is a schematic cross-sectional view showing the mounted state of the semiconductor device of Figure 4. Figure 7 is a schematic cross-sectional view showing the mounted state of a comparative example semiconductor device. Figure 8 is an explanatory diagram showing the frequency characteristics of the impedance in a circuit using the semiconductor device of Figure 6 and the comparative example semiconductor device of Figure 7. Figure 9 is an explanatory diagram showing the resistance component in the semiconductor device of Figure 4. Figure 10 is an explanatory diagram showing the resistance component in the comparative example semiconductor device. Figure 11 is a schematic cross-sectional view showing a modified semiconductor device. Figure 12 is a schematic plan view showing a modified semiconductor device. Figure 13 is a schematic cross-sectional view of the semiconductor device along the line F13-F13 in Figure 12. Figure 14 is a schematic cross-sectional view showing a modified semiconductor device. Figure 15 is a schematic plan view showing a modified semiconductor device. Figure 16 is a schematic cross-sectional view of the semiconductor device along the line F16-F16 in Figure 15. Figure 17 is an explanatory diagram showing the resistance components of the semiconductor device in Figure 15. Figure 18 is a schematic plan view showing a modified semiconductor device. Figure 19 is a schematic cross-sectional view showing a modified semiconductor device. Figure 20 is a schematic plan view showing a modified semiconductor device. Figure 21 is a schematic cross-sectional view of the semiconductor device along the line F21-F21 in Figure 20. Figure 22 is a schematic plan view showing a modified semiconductor device. Figure 23 is a schematic cross-sectional view of the semiconductor device along the line F23-F23 in Figure 22. Figure 24 is a schematic cross-sectional view showing a modified semiconductor device.

[0007] [Detailed Description] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the attached drawings. For simplicity and clarity, the components shown in the drawings are not necessarily drawn to a consistent scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The attached drawings are merely illustrative of embodiments of the present disclosure and should not be considered limiting. The terms "first," "second," "third," etc., used in this disclosure are used simply to distinguish objects and do not rank them.

[0008] <Embodiment> An embodiment of the semiconductor device 10 will be described with reference to Figures 1 to 5. Figure 1 is a schematic perspective view of an exemplary semiconductor device according to one embodiment. Figure 2 is a schematic plan view of the semiconductor device of Figure 1. Figure 3 is a schematic plan view showing the semiconductor substrate 20 and trench 23 of the semiconductor device 10 of Figure 1. Figure 4 is a schematic cross-sectional view of the semiconductor device along the line F4-F4 in Figure 2. Figure 5 is a schematic perspective view of the semiconductor device of Figure 4. In Figure 5, the components on the first substrate surface 20S of the semiconductor substrate 20 (dielectric layer 30, first conductive layer 40, and first external electrode 50) are shown by dashed lines.

[0009] As shown in Figures 1 and 2, the semiconductor device 10 has a roughly rectangular parallelepiped shape. The semiconductor device 10 includes a semiconductor substrate 20. The semiconductor substrate 20 has a rectangular parallelepiped shape. In one example, the semiconductor substrate 20 may have a rectangular shape in plan view.

[0010] (Semiconductor Substrate) The semiconductor substrate 20 includes a plurality of sides 20A, 20B, 20C, 20D that intersect with the first substrate surface 20S and the second substrate surface 20R. Here, for the sake of explanation, two directions that are orthogonal to each other within the first substrate surface 20S of the semiconductor substrate 20 are called the X-axis direction and the Y-axis direction, and the direction that is orthogonal to the X-axis direction and the Y-axis direction is called the Z-axis direction. The Z-axis direction may be perpendicular to the first substrate surface 20S. Viewing a component in question from the Z-axis direction is called a plan view. The Z-axis direction corresponds to the thickness direction of the semiconductor substrate 20. The X-axis direction corresponds to the "second direction", and the Y-axis direction corresponds to the "first direction". In one example, the first side surface 20A and the second side surface 20B extend along the Y-axis direction and face opposite each other. In one example, the third side surface 20C and the fourth side surface 20D extend along the X-axis direction and face opposite each other. The semiconductor substrate 20 may have a rounded shape with chamfered corners in a plan view. The area between the sides 20A to 20D of the semiconductor substrate 20 may be curved so as to be convex outwards. The sides of the semiconductor substrate 20 do not necessarily have to be clearly demarcated into the first to fourth sides 20A to 20D.

[0011] The semiconductor substrate 20 may be made of a material containing Si (silicon). In one example, the semiconductor substrate 20 may be a silicon substrate. The semiconductor substrate 20 may contain impurities. The impurities may be impurities of a first conductivity type. In one example, it may be a silicon substrate containing impurities of a first conductivity type. The first conductivity type may be, for example, n-type. The resistivity of the semiconductor substrate 20 may be 1 mΩ·cm or more and 100 mΩ·cm or less due to the introduction of n-type impurities. The resistivity of the semiconductor substrate 20 may be 1 mΩ·cm or less. The thickness T11 of the semiconductor substrate 20 may be 50 μm or more and 200 μm or less. In one example, the thickness T11 of the semiconductor substrate 20 is 180 μm.

[0012] (Dielectric layer) The semiconductor device 10 may include a dielectric layer 30. The dielectric layer 30 may be provided over the entire first substrate surface 20S of the semiconductor substrate 20. The dielectric layer 30 includes an upper surface 30S and a lower surface 30R opposite to the upper surface 30S. The lower surface 30R of the dielectric layer 30 is in contact with the first substrate surface 20S of the semiconductor substrate 20. The dielectric layer 30 includes a plurality of side surfaces 30A, 30B, 30C, 30D connecting the upper surface 30S and the lower surface 30R. The side surfaces 30A to 30D of the dielectric layer 30 may be flush with the side surfaces 20A to 20D of the semiconductor substrate 20. In a plan view, the dielectric layer 30 may have a rounded shape with chamfered corners. The area between the side surfaces 30A to 30D of the dielectric layer 30 may be curved so as to be convex outwards from the dielectric layer 30. The side surfaces of the dielectric layer 30 do not necessarily have to be clearly demarcated into the first to fourth side surfaces 30A to 30D.

[0013] The dielectric layer 30 is made of an insulating material. ２ (Silicon oxide), SiN (Silicon nitride), SiON (Silicon oxynitride), Al ２ O ３ The dielectric layer 30 may be made of a material containing at least one of (aluminum oxide). The dielectric layer 30 may also be made of a high-dielectric material (High-k material). The resistivity of the dielectric layer 30 is 1e １３ It may be greater than or equal to Ω·cm. For example, the dielectric layer 30 is SiO ２ It is composed of materials including the above. The dielectric layer 30 may have a structure in which multiple insulating films are stacked.

[0014] (First conductive layer) The semiconductor device 10 may include a first conductive layer 40. The first conductive layer 40 is disposed on a semiconductor substrate 20. The first conductive layer 40 may partially cover the upper surface 30S of the dielectric layer 30. The first conductive layer 40 includes an upper surface 40S and a lower surface 40R opposite to the upper surface 40S. The lower surface 40R of the first conductive layer 40 is in contact with the upper surface 30S of the dielectric layer 30.

[0015] The first conductive layer 40 is formed in a region that is spaced inward from the sides 20A to 20D of the semiconductor substrate 20. In a plan view, the first conductive layer 40 is located in the central region of the semiconductor substrate 20 in the Y-axis direction. In a plan view, the first conductive layer 40 is located closer to the side 20A of the semiconductor substrate 20 in the X-axis direction. In a plan view, the first conductive layer 40 can be said to be surrounded by the dielectric layer 30 on the first substrate surface 20S of the semiconductor substrate 20. The first conductive layer 40 can be said to be separated from the periphery of the first substrate surface 20S of the semiconductor substrate 20.

[0016] The first conductive layer 40 includes a plurality of side surfaces 40A, 40B, 40C, and 40D that connect the upper surface 40S and the lower surface 40R. The side surfaces 40A to 40D of the first conductive layer 40 are spaced inward from the side surfaces 20A to 20D of the semiconductor substrate 20. The first conductive layer 40 can be said to include the side surfaces 40A to 40D that are spaced inward from the side surfaces 20A to 20D of the semiconductor substrate 20. The side surfaces 40A to 40D of the first conductive layer 40 may also be called the edges or end faces of the first conductive layer 40. The region between the side surfaces 40A to 40D of the first conductive layer 40 and the side surfaces 20A to 20D of the semiconductor substrate 20 may be an insulating region where the dielectric layer 30 on the first substrate surface 20S of the semiconductor substrate 20 is exposed. In plan view, the first conductive layer 40 may have a rounded shape with chamfered corners. The area between the sides 40A to 40D of the first conductive layer 40 may be curved so as to be convex toward the outside of the first conductive layer 40. The side surface of the first conductive layer 40 does not have to be clearly demarcated into the first to fourth side surfaces 40A to 40D.

[0017] The first conductive layer 40 is made of a conductive material. The first conductive layer 40 may be made of a material containing at least one of polysilicon, W (tungsten), Cu (copper), and Al (aluminum). In one example, the first conductive layer 40 is made of polysilicon.

[0018] (First external electrode) The semiconductor device 10 may include a first external electrode 50. The first external electrode 50 is disposed on a semiconductor substrate 20. The first external electrode 50 is disposed on a first conductive layer 40. The first external electrode 50 may cover at least a portion of the first conductive layer 40. In one example, the first external electrode 50 covers the entire first conductive layer 40.

[0019] The first external electrode 50 includes an upper surface 50S and a lower surface 50R opposite to the upper surface 50S. The lower surface 50R of the first external electrode 50 is in contact with the upper surface 40S of the first conductive layer 40. The first external electrode 50 is formed in a region spaced inward from the sides 20A to 20D of the semiconductor substrate 20. In a plan view, the first external electrode 50 is located in the central region of the semiconductor substrate 20 in the Y-axis direction. In a plan view, the first external electrode 50 is located closer to the side surface 20A of the semiconductor substrate 20 in the X-axis direction. In a plan view, the first external electrode 50 can be said to be surrounded by the dielectric layer 30 on the first substrate surface 20S of the semiconductor substrate 20. The first external electrode 50 can be said to be separated from the periphery of the first substrate surface 20S of the semiconductor substrate 20.

[0020] The first external electrode 50 includes a plurality of side surfaces 50A, 50B, 50C, and 50D that connect the upper surface 50S and the lower surface 50R. The side surfaces 50A to 50D of the first external electrode 50 are spaced inward from the side surfaces 20A to 20D of the semiconductor substrate 20. The side surfaces 50A to 50D of the first external electrode 50 may be flush with the side surfaces 40A to 40D of the first conductive layer 40. The first external electrode 50 can be said to include side surfaces 50A to 50D that are spaced inward from the side surfaces 20A to 20D of the semiconductor substrate 20. The side surfaces 50A to 50D of the first external electrode 50 may also be called the edges or end faces of the first external electrode 50. The region between the side surfaces 50A to 50D of the first external electrode 50 and the side surfaces 20A to 20D of the semiconductor substrate 20 may be an insulating region where the dielectric layer 30 on the first substrate surface 20S of the semiconductor substrate 20 is exposed. The first external electrode 50 may have a rounded shape with chamfered corners in a plan view. The area between the side surfaces 50A to 50D of the first external electrode 50 may be curved so as to be convex outward from the first external electrode 50. The side surfaces of the first external electrode 50 do not necessarily have to be clearly demarcated into first to fourth side surfaces 50A to 50D.

[0021] The first external electrode 50 may be made of one or more metallic materials such as Cu, Al, Ni (nickel), Pd (palladium), and Au (gold). In one example, the first external electrode 50 may be made of a material containing Al. The thickness T1 of the first external electrode 50 may be expressed as the distance from the upper surface 40S of the first conductive layer 40 to the upper surface 50S of the first external electrode 50 in the Z-axis direction. The thickness T1 of the first external electrode 50 may be 1 μm or more and 3 μm or less.

[0022] (Second external electrode) The second external electrode 60 is positioned on the semiconductor substrate 20. The second external electrode 60 is positioned at a distance from the first external electrode 50 when viewed from the thickness direction Z of the semiconductor substrate 20. The second external electrode 60 is positioned at a distance from the first external electrode 50 in the X-axis direction. The second external electrode 60 is positioned closer to the side surface 20B of the semiconductor substrate 20. The second external electrode 60 extends along the side surface 20B. In one example, the second external electrode 60 has a rectangular shape that is elongated in the Y-axis direction when viewed from above.

[0023] The second external electrode 60 includes an upper surface 60S and a lower surface 60R opposite to the upper surface 60S. The lower surface 60R of the second external electrode 60 includes a portion in contact with the first substrate surface 20S of the semiconductor substrate 20 and a portion in contact with the dielectric layer 30. The second external electrode 60 is formed in a region spaced inward from the sides 20A to 20D of the semiconductor substrate 20. In a plan view, the second external electrode 60 is located in the central region of the semiconductor substrate 20 in the Y-axis direction. In a plan view, the second external electrode 60 is located closer to the side surface 20B of the semiconductor substrate 20 in the X-axis direction. In a plan view, the second external electrode 60 can be said to be surrounded by the dielectric layer 30 on the first substrate surface 20S of the semiconductor substrate 20. The second external electrode 60 can be said to be separated from the periphery of the first substrate surface 20S of the semiconductor substrate 20.

[0024] The second external electrode 60 includes a plurality of sides 60A, 60B, 60C, and 60D that connect the upper surface 60S and the lower surface 60R. The sides 60A to 60D of the second external electrode 60 are spaced inward from the sides 20A to 20D of the semiconductor substrate 20. The sides 60A to 60D of the second external electrode 60 may be flush with the sides 40A to 40D of the first conductive layer 40. The second external electrode 60 can be said to include sides 60A to 60D that are spaced inward from the sides 20A to 20D of the semiconductor substrate 20. The first side 60A of the second external electrode 60 faces the second side 50B of the first external electrode 50. The first side 60A of the second external electrode 60 faces the second side 40B of the first conductive layer 40. The sides 60A to 60D of the second external electrode 60 may also be called the edge or end face of the second external electrode 60. The region between the second external electrode 60 and the first external electrode 50, and the region between the sides 60B to 60D of the second external electrode 60 and the sides 20B to 20D of the semiconductor substrate 20 may be an insulating region where the dielectric layer 30 on the first substrate surface 20S of the semiconductor substrate 20 is exposed. In plan view, the second external electrode 60 may have a rounded shape with chamfered corners. The area between the sides 60A to 60D of the second external electrode 60 may be curved so as to be convex outward from the second external electrode 60. The sides of the second external electrode 60 do not necessarily have to be clearly demarcated into first to fourth sides 60A to 60D.

[0025] The thickness T2 of the second external electrode 60 may be expressed as the distance from the first substrate surface 20S of the semiconductor substrate 20 to the upper surface 60S of the second external electrode 60 in the Z-axis direction. The thickness T2 of the second external electrode 60 may be 1 μm or more and 3 μm or less. The thickness T2 of the second external electrode 60 may be equal to the distance L11 from the first substrate surface 20S of the semiconductor substrate 20 to the upper surface 50S of the first external electrode 50.

[0026] The second external electrode 60 is electrically connected to the semiconductor substrate 20. The second external electrode 60 is positioned to cover the contact opening 35 of the dielectric layer 30 when viewed from the Z-axis direction. The contact opening 35 is provided at a distance from the first external electrode 50. The contact opening 35 is provided between the first external electrode 50 and the side surface 20D of the semiconductor substrate 20. The contact opening 35 exposes the first substrate surface 20S of the semiconductor substrate 20. The dielectric layer 30 can be said to include the contact opening 35 that exposes a part of the first substrate surface 20S of the semiconductor substrate 20. The second external electrode 60 is larger than the contact opening 35 when viewed from the Z-axis direction. The second external electrode 60 is in contact with the first substrate surface 20S of the semiconductor substrate 20 through the contact opening 35 of the dielectric layer 30.

[0027] The second external electrode 60 may include a contact portion 63 and an extension portion 64. The contact portion 63 is the portion that contacts the semiconductor substrate 20 through the contact opening 35 of the dielectric layer 30 in a plan view. The extension portion 64 is the portion surrounding the contact portion 63, extending from the contact portion 63 to the upper surface 30S of the dielectric layer 30. The second external electrode 60 can be said to include a contact portion 63 that contacts the first substrate surface 20S of the semiconductor substrate 20 through the contact opening 35, and an extension portion 64 that is arranged on the peripheral edge of the contact opening 35 in the dielectric layer 30.

[0028] The second external electrode 60 may include a conductive film 61 and a metal film 62. The conductive film 61 covers the first substrate surface 20S of the semiconductor substrate 20 exposed by the contact opening 35 and the upper surface 30S of the dielectric layer 30 surrounding the contact opening 35. The conductive film 61 is made of a conductive material. The conductive film 61 may be made of a material containing at least one of polysilicon, W (tungsten), Cu (copper), and Al (aluminum). In one example, the conductive film 61 may be made of the same material as the first conductive layer 40.

[0029] The metal film 62 may be composed of one or more metallic materials such as Cu, Al, Ni, Pd, and Au. In one example, the metal film 62 may be composed of the same material as the first external electrode 50.

[0030] (Second conductive layer) The semiconductor device 10 may include a second conductive layer 70. The second conductive layer 70 is disposed on the second substrate surface 20R of the semiconductor substrate 20. The second conductive layer 70 may cover the second substrate surface 20R of the semiconductor substrate 20. The second conductive layer 70 includes an upper surface 70S and a lower surface 70R opposite to the upper surface 70S. The upper surface 70S of the second conductive layer 70 is in contact with the second substrate surface 20R of the semiconductor substrate 20. The second conductive layer 70 includes a plurality of side surfaces 70A, 70B, 70C, 70D that connect the upper surface 70S and the lower surface 70R. The side surfaces 70A to 70D of the second conductive layer 70 may be flush with the side surfaces 20A to 20D of the semiconductor substrate 20. In plan view, the second conductive layer 70 may have a rounded shape with chamfered corners. The sides 70A to 70D of the second conductive layer 70 may be curved so as to be convex toward the outside of the second conductive layer 70. The sides of the second conductive layer 70 do not necessarily have to be clearly demarcated into the first to fourth sides 70A to 70D.

[0031] The second conductive layer 70 is made of a conductive material. The second conductive layer 70 is electrically connected to the semiconductor substrate 20. The second conductive layer 70 may be made of a material containing at least one of Ti (titanium), Cu, Ni, Pd, and Au. In one example, the second conductive layer 70 may be made of a material containing Ti. The thickness T3 of the second conductive layer 70 in the Z-axis direction may be 1 μm or more and 3 μm or less.

[0032] As shown in Figure 4, the second conductive layer 70 includes a first portion 71, a second portion 72, and a third portion 73. The first portion 71 overlaps with the first external electrode 50 when viewed from the Z-axis direction. The second portion 72 overlaps with the second external electrode 60 when viewed from the Z-axis direction. The third portion 73 is located between the first portion 71 and the second portion 72 when viewed from the Z-axis direction and electrically connects the first portion 71 and the second portion 72. The second conductive layer 70 can be said to include a first portion 71 that overlaps with the first external electrode 50 when viewed from the Z-axis direction, a second portion 72 that overlaps with the second external electrode 60, and a third portion that connects the first portion 71 and the second portion 72.

[0033] (Internal structure of the semiconductor device) As shown in Figures 2 to 5, the semiconductor device 10 includes a plurality of trenches 23 provided in the semiconductor substrate 20. The plurality of trenches 23 are recessed from the first substrate surface 20S toward the second substrate surface 20R of the semiconductor substrate 20.

[0034] Multiple trenches 23 are arranged with spacing between them in a plan view. In one example, multiple trenches 23 are arranged such that, in a plan view, one trench 23 is located at each of the three vertices of an equilateral triangle DS. In this case, the multiple trenches 23 can be said to be arranged in a close-packing pattern in a plan view, with the maximum number of trenches 23 within a given area. Alternatively, multiple trenches 23 can be said to be arranged in a staggered pattern with spacing between them in a plan view.

[0035] The plurality of trenches 23 open to the first substrate surface 20S of the semiconductor substrate 20. The plurality of trenches 23 may be described as bottomed recesses having openings 24 in the first substrate surface 20S of the semiconductor substrate 20. The openings of the plurality of trenches 23 may have a circular shape in plan view. That is, the plurality of trenches 23 may have a cylindrical shape. The plurality of trenches 23 may be formed, for example, by removing a part of the semiconductor substrate 20 from the first substrate surface 20S by dry etching.

[0036] As shown in FIGS. 4 and 5, the inner surface 25 of the plurality of trenches 23 includes a bottom surface 26 and an inner side surface 27 between the bottom surface 26 and the opening 24. In one example, the inner side surface 27 extends in the Z-axis direction, that is, the thickness direction of the semiconductor substrate 20. The inner side surface 27 may be inclined or curved such that the size (inner diameter) of the trench 23 at the portion closer to the bottom surface 26 is smaller than the size (inner diameter) of the trench 23 at the opening 24 in plan view.

[0037] The inner surface 25 of the plurality of trenches 23 is constituted by a plurality of partition wall portions 21 that partition the plurality of trenches 23. It can be said that the semiconductor substrate 20 includes a plurality of partition wall portions 21 that partition the plurality of trenches 23. The plurality of partition wall portions 21 are constituted by the semiconductor substrate 20. Therefore, it can be said that the plurality of partition wall portions 21 are electrically connected to each other. The inner side surface 27 and the bottom surface 26 may be curved so as to protrude toward the inside of the semiconductor substrate 20. The inner surface 25 of the trench 23 may not be clearly defined by the inner side surface 27 and the bottom surface 26.

[0038] The size of the plurality of trenches 23 may be indicated by the size of the openings in the first substrate surface 20S. In one example, the plurality of trenches 23 have circular openings 24 in plan view. Therefore, the size of the plurality of trenches 23 may be indicated by the diameter D1 of the opening 24. The diameter D1 of the opening 24 may be referred to as the opening diameter. The opening diameter D1 of the plurality of trenches 23 may be 5 μm or more and 9 μm or less. In one example, the opening diameter of the plurality of trenches 23 may be 6 μm.

[0039] The depth T12 of the multiple trenches 23 may be indicated by the distance from the first substrate surface 20S of the semiconductor substrate 20 to the bottom surface 26 of the multiple trenches 23 in the Z-axis direction. In one example, the depth T12 of the multiple trenches 23 may be 5 to 20 times the opening diameter D1 of the multiple trenches 23. The aspect ratio of the multiple trenches 23 may be the ratio of the depth T12 to the opening diameter D1, and the aspect ratio may be 5 to 20. Preferably, the aspect ratio is 15 or less. In one example, if the opening diameter D1 of the multiple trenches 23 is 6 μm, the depth T12 of the multiple trenches 23 may be 30 μm to 120 μm.

[0040] As shown in Figures 3 to 5, in a plan view, adjacent trenches 23 are arranged with a gap L1 between them. The gap L1 between adjacent trenches 23 may be 2 μm or more and 5 μm or less. In one example, the gap L1 between adjacent trenches 23 may be 2 μm. The arrangement pitch L2 of the multiple trenches 23 arranged along the first substrate surface 20S of the semiconductor substrate 20 may be 7 μm or more and 14 μm or less. In one example, the arrangement pitch L2 may be 8 μm.

[0041] The dielectric layer 30 covers the inner surfaces 25 of the plurality of trenches 23 and the first substrate surface 20S of the semiconductor substrate 20. The dielectric layer 30 includes a plurality of inner dielectric layers 31 provided on the inner surfaces of the plurality of trenches 23, and a surface dielectric layer 33 covering the first substrate surface 20S. The surface dielectric layer 33 includes a plurality of side surfaces 30A, 30B, 30C, and 30D which are the side surfaces of the dielectric layer 30. The dielectric layer 30 may be provided, for example, by a CVD method, so as to cover the first substrate surface 20S of the semiconductor substrate 20 and the inner surfaces 25 of the trenches 23.

[0042] The multiple inner dielectric layers 31 include a first covering portion 32A that covers the inner surfaces 27 of the multiple trenches 23 and a second covering portion 32B that covers the bottom surfaces 26 of the multiple trenches 23. The thickness of the first covering portion 32A and the thickness of the second covering portion 32B may be equal. The thickness of the surface dielectric layer 33 may be equal to the thickness of the inner dielectric layer 31. The thickness T21 of the inner dielectric layer 31 is smaller than the opening diameter D1 of the multiple trenches 23. The thickness T21 of the inner dielectric layer 31 may be the distance between the inner surface 27 of the trench 23 and the internal electrode 41 of the first conductive layer 40 on a straight line passing through the center of the trench 23. The thickness T21 of the inner dielectric layer 31 may be said to be the thickness T21 of the dielectric layer 30 within the trench 23. The thickness T21 of the multiple inner dielectric layers 31 may be 0.15 μm or more and 1.5 μm or less when converted to an equivalent oxide film thickness. In one example, the thickness T21 of the inner dielectric layer 31 may be 0.4 μm.

[0043] The inner dielectric layer 31 covering the inner surface 25 of the multiple trenches 23 constitutes an internal region 36 that is recessed from the upper surface 30S of the dielectric layer 30 toward the bottom surface 26 of the multiple trenches 23. The internal region 36 can be said to be recessed from the upper surface 30S of the dielectric layer 30 toward the second substrate surface 20R of the semiconductor substrate 20. The semiconductor device 10 can be said to include an internal region 36 surrounded by the multiple inner dielectric layers 31 within the multiple trenches 23.

[0044] The first conductive layer 40 is provided on top of the dielectric layer 30. The first conductive layer 40 includes a plurality of internal electrodes 41 provided to fill at least a portion of an internal region 36 surrounded by a plurality of internal dielectric layers 31, and a surface electrode 42 provided on top of the surface dielectric layer 33 that electrically connects the plurality of internal electrodes 41. In one example, the plurality of internal electrodes 41 fill the internal region 36. The plurality of internal electrodes 41 may have a cylindrical shape that is long in the Z-axis direction. The plurality of internal electrodes 41 may have a shape in which the ends closer to the bottom surface 26 of the trench 23 are chamfered. It is preferable that the plurality of internal electrodes 41 do not contain any voids inside.

[0045] Multiple internal electrodes 41 face multiple partition walls 21 with multiple inner dielectric layers 31 in between. The multiple partition walls 21 and the multiple internal electrodes 41 face each other with the multiple inner dielectric layers 31 in between, thereby forming a capacitor C1A. Also, the multiple partition walls 21 face each other with a surface dielectric layer 33 in between, thereby forming a surface electrode 42. The multiple partition walls 21 and the surface electrode 42 face each other with the surface dielectric layer 33 in between, thereby forming a capacitor C1B. Therefore, the semiconductor device 10 includes a capacitor C1 (= C1A + C1B) composed of multiple partition walls 21 facing each other with the dielectric layer 30 in between and a first conductive layer 40.

[0046] The multiple inner dielectric layers 31 include a surface 31S opposite to the semiconductor substrate 20. The surface electrode 42 includes a surface opposite to the semiconductor substrate 20. The upper surface 30S of the dielectric layer 30 includes the surface 31S of the inner dielectric layer 31 and the surface 33S of the surface dielectric layer 33. Each of the multiple internal electrodes 41 may cover at least a portion of the surface 31S of the multiple inner dielectric layers 31. Each of the multiple internal electrodes 41 may cover the entire surface 31S of the multiple inner dielectric layers 31. The surface electrode 42 may cover at least a portion of the surface 33S of the surface dielectric layer 33. The surface electrode 42 may cover the region of the surface 33S of the surface dielectric layer 33 in which the multiple trenches 23 are arranged.

[0047] The first conductive layer 40 may be provided so as to fill at least the opening 36A of each of the plurality of internal regions 36. The first conductive layer 40 may be provided so as to close the opening 36A of the plurality of internal regions 36. The first conductive layer 40 may also be provided so as to cover at least a part of the surface 31S of the plurality of inner dielectric layers 31 that constitute the plurality of internal regions 36, and also so as to cover the plurality of internal regions 36. The semiconductor device 10 may include at least one void inside at least one of the plurality of internal electrodes 41 provided in the plurality of internal regions 36.

[0048] The first conductive layer 40 may be made of polysilicon containing impurities. For example, the impurities are n-type impurities. An example of an n-type impurity is phosphorus (P). The impurity concentration of n-type impurities in the first conductive layer 40 is 1 × 10⁻⁶.１８ cm －３ The above is sufficient. The impurities may be p-type impurities. The first conductive layer 40 may be made of a material containing Cu or Al, and may be formed by forming a conductive film on the dielectric layer 30, for example by CVD, and then selectively etching the conductive film.

[0049] The thickness T31 of the first conductive layer 40 is smaller than the opening diameter D1 of the multiple trenches 23. The thickness T31 of the first conductive layer 40 may be, for example, the thickness of the portion of the surface electrode 42 in the Z-axis direction. The size of the internal electrode 41 may be indicated by the diameter D21 of the internal electrode 41 on a straight line passing through the center of the trench 23.

[0050] (Operation of the Embodiment) Next, several comparative examples of the semiconductor device 10 of the embodiment and the operation of the embodiment in relation to the comparative examples will be described. In the description of the comparative examples, the same names and reference numerals are used for components that are the same as those of the semiconductor device 10 of the embodiment.

[0051] (Semiconductor device of the first comparative example) Figure 7 shows the cross-sectional structure and mounting state of the semiconductor device 10X1 of the first comparative example. In the semiconductor device 10X1 of the first comparative example, the second external electrode 60X is provided on the second substrate surface 20R of the semiconductor substrate 20, and the first external electrode 50 is provided on the first substrate surface 20S of the semiconductor substrate 20. The second external electrode 60X is electrically connected to the pad P2 of the mounting substrate PB by a conductive bonding material SD such as solder. The first external electrode 50 is provided on the first substrate surface 20S of the semiconductor substrate 20 and is located on the opposite side of the mounting substrate PB from the second external electrode 60X. The first external electrode 50 of the semiconductor device 10X1 of the first comparative example is electrically connected to the pad P1 of the mounting substrate PB by a wire W1. Multiple circuit elements, including the semiconductor device 10X1 of the first comparative example, are mounted on the mounting substrate PB. The multiple circuit elements constitute a circuit that utilizes the capacitor C1X of the semiconductor device 10X1 of the first comparative example, for example, a high-frequency circuit.

[0052] (Semiconductor device of the embodiment) Figure 6 shows the mounting state of the semiconductor device 10 of the embodiment. The semiconductor device 10 has a first external electrode 50 and a second external electrode 60 provided on the first substrate surface 20S of the semiconductor substrate 20 (bottom in Figure 6). The semiconductor device 10 is positioned with respect to the mounting substrate PB, with the first external electrode 50 and the second external electrode 60 facing the mounting substrate PB. The first external electrode 50 and the second external electrode 60 are electrically connected to pads P1 and P2 of the mounting substrate PB by a conductive bonding material SD such as solder. The semiconductor device 10 of the embodiment is a circuit element in which the first external electrode 50 and the second external electrode 60 are flip-chip bonded to the mounting substrate PB, in other words, an electronic component that is flip-chip mounted with the first substrate surface 20S facing the mounting substrate PB.

[0053] The semiconductor device 10 of the embodiment does not require the connection wire W1 shown in Figure 7. In other words, the electrical path of the semiconductor device 10 of the embodiment to the mounting substrate PB is shorter than that of the semiconductor device 10X1 of the first comparative example. The electrical path has equivalent series inductance (ESL) in the circuit it constitutes. Because the electrical path of the semiconductor device 10 of the embodiment is shorter than that of the semiconductor device 10X1 of the first comparative example, the equivalent series inductance can be reduced.

[0054] Figure 8 shows the simulation results of the inductance frequency characteristics in a circuit constructed using the mounting board PB shown in Figures 6 and 7. In Figure 8, the solid line LT1 shows the frequency characteristics of a circuit including the semiconductor device 10 of the embodiment shown in Figure 6, and the dashed line LT2 shows the frequency characteristics of a circuit including the semiconductor device 10X1 of the first comparative example shown in Figure 7. Equivalent series inductance affects the resonant frequency in a high-frequency circuit. The resonant frequency in the circuit using the semiconductor device 10 of the embodiment is higher than that of the semiconductor device 10X1 of the first comparative example. In other words, the semiconductor device 10 of the embodiment can reduce the inductance in the circuit compared to the semiconductor device 10X1 of the first comparative example, and can be applied to higher frequencies.

[0055] (Semiconductor device of the second comparative example) Figure 10 shows the cross-sectional structure of the semiconductor device 10X2 of the second comparative example. The semiconductor device 10X2 of the second comparative example does not include the second conductive layer 70 compared to the configuration of the semiconductor device 10 of the embodiment.

[0056] As shown in Figure 10, the semiconductor device 10X2 of the second comparative example has a configuration in which a first external electrode 50 and a second external electrode 60 are arranged on the first substrate surface 20S of the semiconductor substrate 20. Therefore, this semiconductor device 10X2 of the second comparative example is configured to be flip-chip bondable as shown in Figure 6, similar to the semiconductor device 10 of the embodiment.

[0057] The semiconductor device 10X2 of the second comparative example includes a resistive component between the first external electrode 50 and the second external electrode 60. This resistive component is called the equivalent series resistance (ESR). The resistive component in the semiconductor device 10X2 of the second comparative example mainly includes the resistive component of the semiconductor substrate 20. The resistive component of the semiconductor substrate 20 can be viewed as a resistive component R1 along the XY plane and a resistive component R2 in the X-axis direction. In this case, the semiconductor substrate 20 can also be viewed as including a first portion 20H having resistive component R1 and a second portion 20V having resistive component R2. The resistive component RX in the semiconductor device 10X2 of the second comparative example can be the combined resistance value of resistive component R1 and resistive component R2 (RX = R1 + R2). In Figure 10, for the sake of explanation, the resistive component R1 is shown as being along the back surface 20R of the semiconductor substrate 20.

[0058] (Semiconductor device of the embodiment) Figure 9 shows the resistive components in the semiconductor device 10 of the embodiment. The semiconductor device 10 of the embodiment includes resistive components R1 and R2 in the semiconductor substrate 20, similar to the semiconductor device 10X2 of the second comparative example shown in Figure 10. Furthermore, the semiconductor device 10 of the embodiment includes a second conductive layer 70 provided on the second substrate surface 20R of the semiconductor substrate 20. Therefore, the resistive component RA in the semiconductor device 10 of the embodiment includes the resistive component R3 of the second conductive layer 70. The second conductive layer 70 is electrically connected to the second substrate surface 20R of the semiconductor substrate 20. Therefore, the resistive component R3 of the second conductive layer 70 is connected in parallel with the resistive component R1 of the semiconductor substrate 20. Therefore, the resistive component RA in the semiconductor device 10 of the embodiment is the combined resistance value of the parallel-connected resistive components R1 and R3 and the resistive component R2 (RA = R2 + {R1・R3 / (R1 + R3)}).

[0059] In the semiconductor device 10 of the embodiment, the second conductive layer 70 is made of a material containing at least one of Ti, Cu, Ni, Pd, and Au. The resistivity of the materials constituting the second conductive layer 70 is 50 μΩ·cm or less. The resistivity of the second conductive layer 70 is lower than the resistivity of the semiconductor substrate 20. The resistivity of the second conductive layer 70 may be 20 μΩ·cm or less. For example, when the second conductive layer 70 is made of Au, the resistivity of the second conductive layer 70 is about 2.2 μΩ·cm, which is about 1 / 1000 of the resistivity of the semiconductor substrate 20. Therefore, the resistive component R3 of the second conductive layer 70 is about 1 / 100 to 1 / 1000 of the resistive component R1 of the semiconductor substrate 20. The resistive component RA of the semiconductor device 10 of the embodiment is smaller than the resistive component RX of the semiconductor device 10X2 of the second comparative example. Thus, the semiconductor device 10 of this embodiment can reduce the equivalent series resistance RA between the first external electrode 50 and the second external electrode 60.

[0060] (Operation of the semiconductor device of the embodiment with components not compared to the comparative example) In the semiconductor device 10 of the embodiment, the plurality of trenches 23 have a circular shape when viewed from the Z-axis direction of the semiconductor substrate 20. The plurality of trenches 23 are arranged at intervals L1 of 5 μm or less. The opening diameter D1 of the plurality of trenches 23 is 9 μm or less, and the depth T12 of the plurality of trenches 23 is 5 times or more and 20 times or less of the opening diameter D1.

[0061] The capacitance density per unit area of ​​a trench 23 with respect to its opening diameter D1 increases as the opening diameter D1 increases, provided the distance between the trenches 23 remains constant. On the other hand, if the opening diameter D1 remains constant, the capacitance density decreases as the distance L1 between the trenches 23 increases.

[0062] In the semiconductor device 10, the capacitance value of the capacitor formed by the trenches 23 is small, so there is a risk that the semiconductor device 10 will become larger in order to obtain the required capacitance value. For this reason, the spacing L1 between the multiple trenches 23 is preferably 2 μm or more and 5 μm or less.

[0063] The semiconductor device 10 of this embodiment has a plurality of circular trenches 23, and the plurality of trenches 23 are arranged at intervals L1 of 5 μm or less. The opening diameter D1 of the plurality of trenches 23 is 9 μm or less, and the depth T12 of the plurality of trenches 23 is 5 times or more and 20 times or less the opening diameter D1. This makes it possible to increase the capacitance value of the semiconductor device 10.

[0064] The opening diameter D1 of the multiple trenches 23 affects the formation and manufacturing process of the capacitor. If the opening diameter D1 of the trenches 23 is less than, for example, 3 μm, it becomes difficult to deposit the dielectric layer 30 and the first conductive layer 40 inside the trenches 23. If the dielectric layer 30 is not deposited on a part of the inner surface 25 of the trenches 23, for example, the bottom surface 26, it becomes impossible to form a capacitor C1. If the opening diameter D1 of the trenches 23 exceeds, for example, 9 μm, it becomes difficult to cover the openings 24 of the trenches 23 with the dielectric layer 30 and the first conductive layer 40, and openings may be formed in the first conductive layer 40 that connect to voids inside the trenches 23. Such openings may affect the manufacturing process, for example, the formation of an etching mask. For this reason, it is preferable that the opening diameter D1 of the multiple trenches 23 is between 5 μm and 9 μm.

[0065] By setting the opening diameter D1 and spacing L1 of the multiple trenches 23 within the above range, a desired capacitance value can be obtained for the semiconductor device 10. In other words, a semiconductor device 10 having a desired capacitance value can be obtained. Furthermore, by setting the opening diameter D1 and spacing L1 of the multiple trenches 23 within the above range, a desired withstand voltage can be achieved for the semiconductor device 10. As a result, a semiconductor device 10 having a desired withstand voltage and capacitance value can be obtained.

[0066] In a plan view, if the trench on the inner surface 25 includes corners, these corners can be a factor that leads to a decrease in the withstand voltage. In the semiconductor device 10 of this embodiment, the plurality of trenches 23 have a circular shape in a plan view. Therefore, the semiconductor device 10 of this embodiment can suppress the influence on the withstand voltage.

[0067] The depth T12 of the multiple trenches 23 affects the opposing area between the partition walls 21 constituting the multiple trenches 23 and the first conductive layer 40. If the multiple trenches 23 are shallow, the capacitance value of the capacitor formed by each trench 23 will be small, which may cause the semiconductor device 10 to become larger in order to obtain the required capacitance value. If the multiple trenches 23 are deep, it becomes difficult to form the multiple trenches 23 and to fill the inside of the multiple trenches 23. For this reason, it is preferable that the depth T12 of the multiple trenches 23 be 5 times or more and 20 times or less the opening diameter D1 of the multiple trenches 23. This makes it possible to obtain a semiconductor device 10 having the desired breakdown voltage and capacitance value.

[0068] The thickness T21 of the dielectric layer 30 within the trench 23 affects the capacitance value and breakdown voltage of the capacitor C1. Increasing the thickness of the dielectric layer 30 lowers the capacitance value of the capacitor C1 and increases the breakdown voltage of the capacitor C1. Therefore, the thickness T21 of the dielectric layer 30 is preferably 0.15 μm or more and 1.5 μm or less. This makes it possible to obtain a semiconductor device 10 with desired breakdown voltage and capacitance values.

[0069] The multiple trenches 23 are arranged such that, in a plan view, one trench 23 is located at each of the three vertices of the equilateral triangle DS. By arranging the multiple trenches 23 in this way, more trenches 23 can be formed on the semiconductor substrate 20 compared to, for example, arranging the trenches 23 along the X-axis and Y-axis. This makes it possible to obtain a semiconductor device 10 having the desired breakdown voltage and capacitance value. Furthermore, compared to, for example, arranging the trenches 23 along the X-axis and Y-axis, the area of ​​the region where the multiple trenches 23 are formed, i.e., the size of the semiconductor device 10 can be reduced.

[0070] <Effects of the Embodiment> As described above, the semiconductor device 10 of the embodiment provides the following effects: (1) The semiconductor device 10 includes a semiconductor substrate 20, a plurality of trenches 23, a dielectric layer 30, a first conductive layer 40, a first external electrode 50, a second external electrode 60, and a second conductive layer 70. The semiconductor substrate 20 includes a first substrate surface 20S and a second substrate surface 20R opposite to the first substrate surface 20S. The plurality of trenches 23 are recessed from the first substrate surface 20S toward the second substrate surface 20R. The dielectric layer 30 covers the inner surfaces 25 of the plurality of trenches 23 and the first substrate surface 20S. The first conductive layer 40 is provided on top of the dielectric layer 30. The first external electrode 50 is provided so as to cover a part of the first conductive layer 40. The second external electrode 60 is arranged spaced apart from the first external electrode 50 when viewed from the Z-axis direction and is in contact with the first substrate surface 20S. The second conductive layer 70 is provided on the second substrate surface 20R. The dielectric layer 30 includes a plurality of internal dielectric layers 31 provided on the inner surfaces 25 of the plurality of trenches 23, and a surface dielectric layer 33 covering the first substrate surface 20S. The first conductive layer 40 includes a plurality of internal electrodes 41 provided to fill at least a portion of the internal region 36 surrounded by the plurality of internal dielectric layers 31, and a surface electrode 42 provided on the surface dielectric layer 33 that electrically connects the plurality of internal electrodes 41. The semiconductor substrate 20 and the plurality of internal electrodes 41 face each other with the plurality of internal dielectric layers 31 in between to form a capacitor C1.

[0071] The semiconductor device 10 has a first external electrode 50 and a second external electrode 60 provided on the first substrate surface 20S of the semiconductor substrate 20. The semiconductor device 10 is positioned with respect to the mounting substrate PB, with the first external electrode 50 and the second external electrode 60 facing the mounting substrate PB. The semiconductor device 10 of this embodiment is an electronic component that is flip-chip mounted with the first substrate surface 20S facing the mounting substrate PB. Therefore, compared to cases where connections are made using wires or the like, the inductance in the semiconductor device 10 can be reduced.

[0072] (2) The semiconductor device 10 includes a second conductive layer 70 provided on the second substrate surface 20R of the semiconductor substrate 20. The second conductive layer 70 is made of a conductive material and is electrically connected to the semiconductor substrate 20. The resistivity of the second conductive layer 70 is smaller than the resistivity of the semiconductor substrate 20. Therefore, the resistive component (equivalent series resistance) between the first external electrode 50 and the second external electrode 60 of the semiconductor device 10 can be reduced.

[0073] (3) When viewed from the Z-axis direction of the semiconductor substrate 20, the plurality of trenches 23 have a circular shape. The plurality of trenches 23 are arranged at intervals L1 of 5 μm or less. The opening diameter D1 of the plurality of trenches 23 is 9 μm or less, and the depth T12 of the plurality of trenches 23 is 5 times or more and 20 times or less the opening diameter D1. As a result, the capacitance value of the semiconductor device 10 can be increased.

[0074] (4) By setting the opening diameter D1 and spacing L1 of the multiple trenches 23 within the above range, a desired capacitance value can be obtained for the semiconductor device 10. Furthermore, by setting the opening diameter D1 and spacing L1 of the multiple trenches 23 within the above range, a desired withstand voltage can be achieved for the semiconductor device 10. As a result, a semiconductor device 10 having the desired withstand voltage and capacitance value can be obtained.

[0075] (5) In a plan view, if the trench on the inner surface 25 includes corners, the corners can be a factor that causes a decrease in withstand voltage. In the semiconductor device 10 of the embodiment, the plurality of trenches 23 have a circular shape in a plan view. Therefore, the semiconductor device 10 of the embodiment can suppress the influence on withstand voltage.

[0076] (6) The depth T12 of the multiple trenches 23 affects the opposing area between the partition wall portion 21 constituting the multiple trenches 23 and the first conductive layer 40. If the multiple trenches 23 are shallow, the capacitance value of the capacitor formed by each trench 23 is small, which may cause the semiconductor device 10 to become larger in order to obtain the required capacitance value. If the multiple trenches 23 are deep, it becomes difficult to form the multiple trenches 23 and to fill the inside of the multiple trenches 23. For this reason, the depth T12 of the multiple trenches 23 may be 5 times or more and 20 times or less the opening diameter D1 of the multiple trenches 23. This makes it possible to obtain a semiconductor device 10 having the desired breakdown voltage and capacitance value.

[0077] (7) The thickness T21 of the dielectric layer 30 in the trench 23 affects the capacitance value and breakdown voltage of the capacitor C1. Increasing the thickness of the dielectric layer 30 lowers the capacitance value of the capacitor C1 and increases the breakdown voltage of the capacitor C1. Therefore, the thickness T21 of the dielectric layer 30 may be 0.15 μm or more and 1.5 μm or less when converted to equivalent oxide film thickness. This makes it possible to obtain a semiconductor device 10 with desired breakdown voltage and capacitance values.

[0078] (8) The first conductive layer 40 covers the upper surface 30S of the dielectric layer 30. The first conductive layer 40 covers the surface 31S of the inner dielectric layer 31 and the surface 33S of the outer dielectric layer 33 of the dielectric layer 30. The first conductive layer 40 may be made of polysilicon containing impurities. The first conductive layer 40 fills the internal region 36 of the dielectric layer 30. Therefore, the inside of the trench 23 can be reliably filled with the dielectric layer 30 and the first conductive layer 40.

[0079] (9) The multiple trenches 23 are arranged such that, in a plan view, one trench 23 is located at each of the three vertices of the equilateral triangle DS. By arranging the multiple trenches 23 in this way, more trenches 23 can be formed on the semiconductor substrate 20 compared to, for example, when the trenches 23 are arranged along the X-axis and Y-axis directions. This makes it possible to obtain a semiconductor device 10 having the desired breakdown voltage and capacitance value. Furthermore, compared to, for example, when the trenches 23 are arranged along the X-axis and Y-axis directions, the area of ​​the region where the multiple trenches 23 are formed, i.e., the size of the semiconductor device 10 can be reduced.

[0080] <Examples of Modifications> The above embodiment can be modified as follows, for example. The above embodiment and the following examples of modifications can be combined with each other as long as no technical inconsistencies arise. In the following examples of modifications, parts common to the above embodiment are denoted by the same reference numerals as in the above embodiment, and their descriptions are omitted.

[0081] Figure 11 is a schematic cross-sectional view showing a modified semiconductor device 110. The modified semiconductor device 110 includes a second external electrode 160. The second external electrode 160 is composed of a single metal layer. The second external electrode 160 may be composed of one or more metal materials such as Cu, Al, Ni, Pd, and Au. In one example, the second external electrode 160 may be composed of a material containing Al. The thickness T2 of the second external electrode 160 in the Z-axis direction may be 1 μm or more and 3 μm or less. In the Z-axis direction, the thickness T2 of the second external electrode 160 may be equal to the distance L11 from the first substrate surface 20S of the semiconductor substrate 20 to the upper surface 50S of the first external electrode 50, or it may be less than the distance L11. In one example, the thickness T2 of the second external electrode 160 may be equal to the thickness T1 of the first external electrode 50.

[0082] Figure 12 is a schematic plan view showing a modified semiconductor device 210. Figure 13 is a schematic cross-sectional view of the semiconductor device 210 along the line F13-F13 in Figure 12. In the modified semiconductor device 210, the first conductive layer 40 may cover the dielectric layer 30 up to the sides 30A, 30C, and 30D of the dielectric layer 30. The first external electrode 50 may cover the upper surface 40S of the first conductive layer 40. The second external electrode 60 may cover the dielectric layer 30 up to the sides 30B, 30C, and 30D of the dielectric layer 30.

[0083] Figure 14 is a schematic cross-sectional view showing a modified semiconductor device 310. In the modified semiconductor device 310, the second conductive layer 70 may expose a portion of the second substrate surface 20R of the semiconductor substrate 20. For example, the second conductive layer 70 may include, in plan view, a first portion 71 the same size as the first external electrode 50 and a second portion 72 the same size as the second external electrode 60. In other words, each side surface 70A, 70B of the second conductive layer 70 may be located closer to the center of the semiconductor substrate 20 than each side surface 20A to 20D of the semiconductor substrate 20. The same applies to side surfaces 70C, 70D, although they are not shown.

[0084] Figure 15 is a schematic plan view showing a modified semiconductor device 410. Figure 16 is a schematic cross-sectional view of the semiconductor device 410 along the line F16-F16 in Figure 15. Figure 17 is an explanatory diagram showing the resistive components in the semiconductor substrate 20 of the semiconductor device 410 in Figure 15.

[0085] The modified semiconductor device 410 includes two second external electrodes 60, 460. The two second external electrodes 60, 460 have the same configuration as each other. In a plan view, the two second external electrodes 60, 460 are arranged spaced apart from the first external electrode 50. In one example, the two second external electrodes 60, 460 are arranged so as to sandwich the first external electrode 50 in the X-axis direction. The second external electrode 460 includes an upper surface 60S, a lower surface 60R, and side surfaces 60A to 60D. The side surface 60B of the second external electrode 460 faces the side surface 50A of the first external electrode 50 and the side surface 40A of the first conductive layer 40.

[0086] As shown in Figure 17, in the modified semiconductor device 410, the resistance component RA between the first external electrode 50 and the second external electrodes 60, 460 can be considered as a first resistance component RA1 between the central portion of the first external electrode 50 and the second external electrode 60, and a second resistance component RA2 between the central portion of the first external electrode 50 and the second external electrode 460. The first resistance component RA1 and the second resistance component RA2 are smaller than the resistance component RA in the semiconductor device 410 of the embodiment that includes one second external electrode 60. Therefore, the equivalent series resistance can be further reduced in the modified semiconductor device 410.

[0087] Figure 18 is a schematic plan view showing a modified semiconductor device 510. The modified semiconductor device 510 includes a second external electrode 560 arranged to surround the first external electrode 50. In one example, the second external electrode 560 has an annular shape in plan view that surrounds the first external electrode 50. The second external electrode 560 includes electrode portions 560A, 560B, 560C, and 560D that extend along the sides 20A, 20B, 20C, and 20D of the semiconductor substrate 20. The dielectric layer 530 includes a contact opening 535 that exposes the first substrate surface 20S of the semiconductor substrate 20. The contact opening 535 includes opening portions 535A, 535B, 535C, and 535D that extend along the sides 20A, 20B, 20C, and 20D of the semiconductor substrate 20. The electrode portions 560A to 560D of the second external electrode 560 are in contact with the first substrate surface 20S of the semiconductor substrate 20 through the openings 535A to 535D of the contact opening 535.

[0088] The term "ring-shaped" as used in this disclosure refers not only to any structure that forms a continuous shape without ends, i.e., a loop, but also to generally loop-shaped structures that have a break (gap), such as a C-shape. For example, in Figure 18, the second external electrode 560 may have a configuration in which one of the electrode portions 560A to 560D, for example electrode portion 560A, is omitted. Also, in at least one portion of each electrode portion 560A to 560D, the electrode portions may be spaced apart when adjacent along the sides 20A to 20D of the semiconductor substrate 20. For example, electrode portion 560A and electrode portion 560D may be spaced apart from each other. Also, electrode portion 560A and electrode portion 560D may be spaced apart from each other, and electrode portion 560B and electrode portion 560D may be spaced apart from each other. Furthermore, at least one of each electrode portion 560A to 560D may be composed of multiple electrode portions that are spaced apart from each other.

[0089] Furthermore, the contact opening 535 may have a configuration in which one of the openings 535A to 535D is omitted. Also, in at least a portion of each of the openings 535A to 535D, the openings may be spaced apart when adjacent along the sides 20A to 20D of the semiconductor substrate 20. For example, opening 535A and opening 535D may be spaced apart from each other. Alternatively, opening 535A and opening 535D may be spaced apart from each other, and opening 535B and opening 535D may also be spaced apart from each other. Furthermore, at least one of each of the openings 535A to 535D may be composed of multiple openings that are spaced apart from each other.

[0090] Figure 19 is a schematic cross-sectional view showing a modified semiconductor device 610. The modified semiconductor device 610 includes a dielectric layer 630. The dielectric layer 630 may include a first dielectric layer 631 and a second dielectric layer 632. The first dielectric layer 631 and the second dielectric layer 632 may be made of different materials. In one example, the first dielectric layer 631 is SiO ２The second dielectric layer 632 is composed of a material containing SiN, and the material contains. In one example, the second dielectric layer 632 is disposed on the semiconductor substrate 20, and the first dielectric layer 631 is disposed on the second dielectric layer 632. In this case, the dielectric layer 630 contains SiO ２ The first dielectric layer 631 containing can be referred to as an ON film composed of the first dielectric layer 631 containing and the second dielectric layer 632 containing SiN. Note that the first dielectric layer 631 may be disposed on the semiconductor substrate 20, and the second dielectric layer 632 may be disposed on the first dielectric layer 631. The dielectric layer 630 may have a configuration including a plurality of at least one of the first dielectric layer 631 and the second dielectric layer 632. For example, the dielectric layer 630 may be an ONO film in which the second dielectric layer 632 is disposed between two first dielectric layers 631. In the case of this dielectric layer 630, the total value of the film thicknesses of the plurality of dielectric layers may be the thickness T21.

[0091] The semiconductor device 610 of the modified example includes a first external electrode 650. The first external electrode 650 may include a first metal film 651 and a second metal film 652. The first metal film 651 and the second metal film 652 may be composed of one or more metal materials such as Cu, Al, Ni, Pd, Au, etc. The first metal film 651 and the second metal film 652 may be composed of the same material as each other, or may be composed of different materials from each other. The first external electrode 650 may be composed of three or more metal films.

[0092] The semiconductor device 610 of the modified example includes a second external electrode 660. The second external electrode 660 includes a conductive film 61 and a metal film 662. The metal film 662 may include a first metal film 663 and a second metal film 66,4. The first metal film 663 and the second metal film 664 may be composed of one or more metal materials such as Cu, Al, Ni, Pd, Au, etc. The first metal film 663 and the second metal film 664 may be composed of the same material as each other, or may be composed of different materials from each other. The metal film 662 may be composed of three or more metal films.

[0093] The modified semiconductor device 610 includes a second conductive layer 670. The second conductive layer 670 may include a first metal film 671 and a second metal film 672. The first metal film 671 and the second metal film 672 may be made of a material containing at least one of Ti, Cu, Ni, Pd, and Au. The first metal film 671 and the second metal film 672 may be made of the same material or of different materials. The second external electrode 660 may be made of three or more metal films.

[0094] Figure 20 is a schematic plan view showing a modified semiconductor device 710. Figure 21 is a schematic cross-sectional view of the semiconductor device 710 along the line F21-F21 in Figure 20. The modified semiconductor device 710 may include a passivation layer 720. The passivation layer 720 may cover a part of the first external electrode 50 and a part of the second external electrode 60. The passivation layer 720 may cover the side surface of the first conductive layer 40. The passivation layer 720 may cover the side surface of the first external electrode 50. The passivation layer 720 may cover the side surface of the second external electrode 60. In addition, the passivation layer 720 may cover the upper surface 30S of the dielectric layer 30 that is exposed from the first conductive layer 40 and the second external electrode 60. Furthermore, the passivation layer 720 may include a first opening 721 that exposes a portion of the upper surface 50S of the first external electrode 50, and a second opening 722 that exposes a portion of the upper surface 60S of the second external electrode 60. In a plan view, the passivation layer 720 covers the peripheral edges of the first external electrode 50 and the peripheral edges of the second external electrode 60. The passivation layer 720 may be made of, for example, SiO ２ , SiN, SiON, Al ２ O ３ The passivation layer 720 may be made of a material containing at least one of the following. ２ The passivation layer 720 may be made of a material containing at least one of or SiN. The passivation layer 720 may also be made of a resin material such as polyimide resin or epoxy resin.

[0095] Figure 22 is a schematic plan view showing a modified semiconductor device 810. Figure 23 is a schematic cross-sectional view of the semiconductor device 810 along the line F23-F23 in Figure 22. The modified semiconductor device 810 includes a resin layer 820. The resin layer 820 may cover at least the second conductive layer 70. The resin layer 820 may cover at least a portion of the sides 20A to 20D of the semiconductor substrate 20.

[0096] The resin layer 820 in this modified example includes a back surface covering portion 821 covering the second conductive layer 70, side surface covering portions 822A, 822B, 822C, 822D covering the sides 20A, 20B, 20C, 20D of the semiconductor substrate 20, and a surface covering portion 823 on the first substrate surface 20S of the semiconductor substrate 20. The back surface covering portion 821 and the side surface covering portions 822A to 822D may be connected or separated from each other. Each of the side surface covering portions 822A to 822D may be connected or separated from each other. The side surface covering portions 822A to 822D and the surface covering portion 823 may be connected or separated from each other.

[0097] The resin layer 820 may include at least one of the back coating portion 821, the side coating portions 822A to 822D, and the surface coating portion 823. For example, the resin layer 820 may include only the back coating portion 821. Alternatively, the resin layer 820 may include the back coating portion 821 and the side coating portions 822A to 822D. Alternatively, the resin layer 820 may include the back coating portion 821 and the surface coating portion 823.

[0098] As shown in Figure 23, the surface coating portion 823 covers the upper surface 30S of the dielectric layer 30. The surface coating portion 823 includes an annular coating portion 824 that covers the outer peripheral edge of the dielectric layer 30, and a coating portion 825 that covers the upper surface 30S of the dielectric layer 30 between the first external electrode 50 and the second external electrode 60. In one example, the upper surface 823S of the surface coating portion 823 is located closer to the semiconductor substrate 20 than the upper surface 50S of the first external electrode 50 and the upper surface 60S of the second external electrode 60. In other words, the first external electrode 50 and the second external electrode 60 protrude beyond the upper surface 823S of the surface coating portion 823. Note that the upper surface 50S of the first external electrode 50 and the upper surface 60S of the second external electrode 60 may be flush with the upper surface 823S of the surface coating portion 823. Furthermore, the upper surface 50S of the first external electrode 50 and the upper surface 60S of the second external electrode 60 may be located closer to the semiconductor substrate 20 than the upper surface 823S of the surface coating portion 823.

[0099] The resin layer 820 may be made of an insulating material. The resin layer 820 may be made of a resin material such as epoxy resin, polyimide resin, acrylic resin, or phenolic resin. The resin layer 820 may be colored to a predetermined color, and may be transparent or translucent.

[0100] Figure 24 is a schematic cross-sectional view showing a modified semiconductor device 910. In the modified semiconductor device 910, the dielectric layer 30 may expose the first substrate surface 20S of the semiconductor substrate 20 over the entire region corresponding to the second external electrode 60. In one example, the side surface 30B of the dielectric layer 30 may be located between the first external electrode 50 and the second external electrode 60 in a plan view. In other words, the contact opening 35 of the dielectric layer 30 can be said to expose the first substrate surface 20S from the side surface 20B of the semiconductor substrate 20 to the space between the first external electrode 50 and the second external electrode 60. The entire lower surface 60R of the second external electrode 60 is in contact with the first substrate surface 20S of the semiconductor substrate 20.

[0101] The term “on” as used in this disclosure includes both meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, the expression “the first layer is formed on the second layer” is intended to mean that in one embodiment the first layer may be in contact with the second layer and directly placed on the second layer, while in other embodiments the first layer may be placed above the second layer without contact with the second layer. In other words, the term “on” does not preclude structures in which another layer is formed between the first and second layers.

[0102] The Z-axis direction used in this disclosure does not necessarily have to be vertical, nor does it have to perfectly coincide with the vertical. Therefore, the various structures according to this disclosure (for example, the structure shown in Figure 1) are not limited to the Z-axis direction "up" and "down" being described herein being vertical "up" and "down". For example, the X-axis direction may be vertical, or the Y-axis direction may be vertical.

[0103] <Note> The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in this note are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each note should not be limited to those indicated by the reference numerals.

[0104] [Note 1] A semiconductor substrate (20) including a first substrate surface (20S) and a second substrate surface (20R) opposite to the first substrate surface (20S); a plurality of trenches (23) recessed from the first substrate surface (20S) toward the second substrate surface (20R); a dielectric layer (30) covering the inner surface (25) of the plurality of trenches (23) and the first substrate surface (20S); a first conductive layer (40) provided on the dielectric layer (30); a first external electrode (50) provided so as to cover a part of the first conductive layer (40); a second external electrode (60) positioned at a distance from the first external electrode (50) when viewed from the thickness direction (Z) of the semiconductor substrate (20) and in contact with the first substrate surface (20S); and a second conductive layer (70) provided on the second substrate surface (20R), The dielectric layer (30) includes a plurality of internal dielectric layers (31) provided on the inner surfaces (25) of the plurality of trenches (23), and a surface dielectric layer (33) covering the first substrate surface (20S). The first conductive layer (40) includes a plurality of internal electrodes (41) provided to fill at least a portion of the internal region (36) surrounded by the plurality of internal dielectric layers (31), and a surface electrode provided on the surface dielectric layer (33) to electrically connect the plurality of internal electrodes (41). The semiconductor device constitutes a capacitor (C1) when the semiconductor substrate (20) and the plurality of internal electrodes (41) face each other with the plurality of internal dielectric layers (31) in between.

[0105] [Note 2] The semiconductor device according to Note 1, wherein the second conductive layer (70) includes, when viewed from the thickness direction (Z), a first portion (71) that overlaps with the first external electrode (50), a second portion (72) that overlaps with at least a part of the second external electrode (60), and a connecting portion (73) that connects the first portion and the second portion.

[0106] [Note 3] The semiconductor device according to Note 1 or Note 2, wherein the resistivity of the second conductive layer (70) is lower than the resistivity of the semiconductor substrate (20).

[0107] [Note 4] The resistivity of the second conductive layer (70) is 50 μΩ·cm or less, as described in any one of Notes 1 to 3.

[0108] [Note 5] The semiconductor device according to any one of Notes 1 to 4, wherein the second conductive layer (70) is made of a material containing at least one of Ti, Cu, Ni, Pd, and Au.

[0109] [Note 6] The semiconductor device according to any one of Notes 1 to 5, wherein the thickness of the second conductive layer (70) in the thickness direction (Z) is 1 μm or more and 3 μm or less.

[0110] [Note 7] The semiconductor device according to any one of Notes 1 to 6, wherein the second conductive layer (70) covers the entire second substrate surface (20R).

[0111] [Note 8] The semiconductor device (610) according to any one of Notes 1 to 7, wherein the second conductive layer (670) is composed of a plurality of metal films (671, 672).

[0112] [Note 9] The semiconductor device according to any one of Notes 1 to 8, wherein the first external electrode (50) covers at least a portion of the area in which the plurality of trenches (23) are arranged in a plan view.

[0113] [Note 10] The semiconductor device according to any one of Notes 1 to 9, wherein the first external electrode (50) and the second external electrode (60) are made of a material containing at least one of Ti, Cu, Ni, Pd, Au, and Al.

[0114] [Note 11] The semiconductor device according to any one of Notes 1 to 10, wherein the thickness of the first external electrode (50) and the second external electrode (60) in the thickness direction (Z) is 1 μm or more and 3 μm or less.

[0115] [Note 12] The semiconductor device according to any one of Notes 1 to 11, wherein the distance from the first substrate surface (20S) to the upper surface of the first external electrode (50) is equal to the distance from the first substrate surface (20S) to the upper surface of the second external electrode (60).

[0116] [Note 13] The semiconductor device (610) according to any one of Notes 1 to 12, wherein the first external electrode (650) and the second external electrode (660) are composed of a plurality of metal films (651, 652, 663, 664).

[0117] [Note 14] The semiconductor device according to any one of Notes 1 to 13, wherein the second external electrode (60) is in contact with the first substrate surface (20S) and comprises a conductive film (61) made of a material containing polysilicon, and a metal film (62) disposed on the conductive film.

[0118] [Note 15] The semiconductor device according to any one of Notes 1 to 14, wherein the dielectric layer (30) includes a contact opening (35) that exposes a part of the first substrate surface (20S), and the second external electrode (60) includes a contact portion (63) that contacts the first substrate surface (20S) by the contact opening (35) of the dielectric layer (30), and an extended portion (64) disposed on the peripheral edge of the contact opening in the dielectric layer (30).

[0119] [Note 16] The resistivity of the dielectric layer (30) is 1e １３ A semiconductor device described in any one of the appendices 1 to 15, having a capacitance of Ω·cm or greater.

[0120] [Note 17] The semiconductor device according to any one of Notes 1 to 16, wherein the thickness of the inner dielectric layer (31) is 0.15 μm or more and 1.5 μm or less when converted to an equivalent oxide film thickness.

[0121] [Note 18] The dielectric layer (30) is SiO ２ A semiconductor device according to any one of Appendix 1 to Appendix 17, comprising a material containing at least one of and SiN.

[0122] [Note 19] The dielectric layer (630) is SiO ２ A semiconductor device (610) according to any one of Appendix 1 to Appendix 17, comprising both a first dielectric layer (631) made of a material containing and a second dielectric layer (632) made of a material containing SiN.

[0123] [Note 20] The semiconductor device according to any one of Notes 1 to 19, wherein the first conductive layer (40) is made of polysilicon containing impurities.

[0124] [Note 21] The aforementioned impurity is an n-type impurity, and the impurity concentration is 1 × 10⁻⁶ １８ cm －３ The semiconductor device described in Appendix 20 is as described above.

[0125] [Note 22] The semiconductor device according to any one of Notes 1 to 21, wherein the semiconductor substrate (20) is made of a material containing Si.

[0126] [Note 23] The semiconductor device according to any one of Notes 1 to 22, wherein the resistivity of the semiconductor substrate (20) is 100 mΩ·cm or less.

[0127] [Note 24] The semiconductor device according to any one of Notes 1 to 23, wherein the thickness of the semiconductor substrate (20) is 50 μm or more and 200 μm or less.

[0128] [Note 25] The plurality of trenches (23) have a circular shape when viewed from the thickness direction (Z), the plurality of trenches (23) are arranged at intervals of 5 μm or less, the opening diameter of the plurality of trenches (23) is 9 μm or less, and the depth of the plurality of trenches (23) is 5 times or more and 20 times or less the opening diameter, the semiconductor device according to any one of Notes 1 to 24.

[0129] [Note 26] The semiconductor device according to Note 25, wherein the depth of the plurality of trenches (23) is 10 times or more the diameter of the opening.

[0130] [Note 27] The semiconductor device according to any one of Notes 1 to 26, wherein the plurality of trenches (23) are arranged such that, when viewed from the thickness direction (Z), one trench (23) is located at each of the three vertices of an equilateral triangle (DS).

[0131] [Note 28] The semiconductor device described in Note 27, wherein the length of one side of the equilateral triangle (DS) is 5 μm or more and 14 μm or less.

[0132] [Note 29] The semiconductor device according to any one of Notes 1 to 28, wherein the plurality of trenches (23) are arranged in a staggered pattern with spacing between them in a plan view.

[0133] [Note 30] A semiconductor device (710) according to any one of Notes 1 to 29, comprising a passivation layer (720) covering the upper surface (30S) of the dielectric layer (30), a part of the first external electrode (50), and a part of the second external electrode (60).

[0134] [Note 31] The semiconductor device according to Note 30, wherein the passivation layer (720) includes a first opening (721) that exposes a part of the upper surface of the first external electrode (50) and a second opening (722) that exposes a part of the upper surface of the second external electrode (60).

[0135] [Note 32] The semiconductor device according to Note 30 or Note 31, wherein the passivation layer (720) is made of resin.

[0136] [Note 33] The passivation layer (720) is SiO ２ A semiconductor device according to Appendix 30 or Appendix 31, comprising a material containing at least one of and SiN.

[0137] [Note 34] A semiconductor device (810) according to any one of Notes 1 to 29, comprising a resin layer (820) covering the second conductive layer (70).

[0138] [Note 35] The semiconductor device according to Note 34, wherein the semiconductor substrate (20) includes side surfaces (20A to 20D) connecting the first substrate surface (20S) and the second substrate surface (20R), and the resin layer (820) covers at least a portion of the side surfaces (20A to 20D).

[0139] [Note 36] The semiconductor device according to Note 34 or Note 35, wherein the resin layer (820) includes a surface coating portion (823) on the first substrate surface (20S), and the first external electrode (50) and the second external electrode (60) protrude from the upper surface (823S) of the surface coating portion (823).

[0140] [Note 37] The semiconductor device according to any one of Notes 1 to 36, wherein the first conductive layer (40) is made of polysilicon or tungsten.

[0141] The above description is for illustrative purposes only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond those enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims.

[0142] 10... Semiconductor device, 20... Semiconductor substrate, 20A-20D... Side surface, 20S... First substrate surface, 20R... Second substrate surface, 21... Partition wall, 23... Trench, 24... Opening, 25... Inner surface, 26... Bottom surface, 27... Inner surface, 30... Dielectric layer, 30A-30D... Side surface, 30R... Bottom surface, 30S... Top surface, 31... Inner dielectric layer, 31S... Surface, 32A, 32B... First and second covering portions, 33... Surface dielectric layer, 33S... Surface, 34... Inner surface, 35... Contact opening, 36... Internal region, 36A... Opening portion, 40... First conductive layer, 40A-40D... Side surface, 40R... Bottom surface, 40S... Top surface, 4 1...Internal electrode, 42...Surface electrode, 50...First external electrode, 50A-50D...Side, 50R...Bottom, 50S...Top, 60...Second external electrode, 60A-60D...Side, 60R...Bottom, 60S...Top, 61...Conductive film, 62...Metal film, 63...Contact portion, 64...Extended portion, 70...Second conductive layer, 70A-70D...Side, 70R...Bottom, 70S...Top, 71-73...First to third portions, 80...Second conductive layer, 80A-80D...Side, 110...Semiconductor device, 160...Second external electrode, 210...Semiconductor device, 310...Semiconductor device, 353A-353D...Opening portion, 4 10...Semiconductor device, 460...Second external electrode, 510...Semiconductor device, 530...Dielectric layer, 535...Contact opening, 535A-535D...Opening portion, 560...Second external electrode, 560A-560D...Electrode portion, 610...Semiconductor device, 630...Dielectric layer, 631, 632...First and second dielectric layers, 650...First external electrode, 651, 652...First and second metal films, 660...Second external electrode, 662...Metal film, 663, 664...First and second metal films, 670...Second conductive layer, 671, 672...First and second metal films, 710...Semiconductor device, 720...Passivation layer, 72 1,722...First and second openings, 810...Semiconductor device, 820...Resin layer, 821...Back surface covering, 822A to 822D...Side covering, 823...Front covering, 823S...Top surface, 824, 825...Covering portion, 910...Semiconductor device, C1, C1A, C1B...Capacitors, D1...Opening diameter, D1...Diameter, D21...Diameter, DS...Equilateral triangle, L1...Spacing, L1...Distance, L2...Pitch, L11...Distance, R1 to R3...Resistance component, RA...Equivalent series resistance, Resistance component, RA1...First resistance component, RA2...Second resistance component, T1 to T3...Thickness, T11, T21, T31...Thickness.

Claims

1. A semiconductor device comprising: a semiconductor substrate including a first substrate surface and a second substrate surface opposite to the first substrate surface; a plurality of trenches recessed from the first substrate surface toward the second substrate surface; a dielectric layer covering the inner surfaces of the plurality of trenches and the first substrate surface; a first conductive layer provided on the dielectric layer; a first external electrode provided so as to cover a part of the first conductive layer; a second external electrode positioned spaced apart from the first external electrode when viewed from the thickness direction of the semiconductor substrate and in contact with the first substrate surface; and a second conductive layer provided on the second substrate surface, wherein the dielectric layer comprises a plurality of inner dielectric layers provided on the inner surfaces of the plurality of trenches and a surface dielectric layer covering the first substrate surface; the first conductive layer comprises a plurality of internal electrodes provided so as to fill at least a part of the internal region surrounded by the plurality of inner dielectric layers, and a surface electrode provided on the surface dielectric layer that electrically connects the plurality of internal electrodes, and the semiconductor substrate and the plurality of internal electrodes facing each other across the plurality of inner dielectric layers constitute a capacitor.

2. The semiconductor device according to claim 1, wherein the second conductive layer includes, viewed from the thickness direction, a first portion that overlaps with the first external electrode, a second portion that overlaps with at least a portion of the second external electrode, and a connecting portion that connects the first portion and the second portion.

3. The semiconductor device according to claim 1 or 2, wherein the resistivity of the second conductive layer is lower than the resistivity of the semiconductor substrate.

4. The semiconductor device according to any one of claims 1 to 3, wherein the resistivity of the second conductive layer is 50 μΩ·cm or less.

5. The semiconductor device according to any one of claims 1 to 4, wherein the second conductive layer is made of a material containing at least one of Ti, Cu, Ni, Pd, and Au.

6. The semiconductor device according to any one of claims 1 to 5, wherein the thickness of the second conductive layer in the thickness direction is 1 μm or more and 3 μm or less.

7. The semiconductor device according to any one of claims 1 to 6, wherein the first external electrode covers at least a portion of the area in which the plurality of trenches are arranged in a plan view.

8. The semiconductor device according to any one of claims 1 to 7, wherein the dielectric layer includes a contact opening that exposes a part of the first substrate surface, and the second external electrode includes a contact portion that contacts the first substrate surface through the contact opening of the dielectric layer, and an extended portion disposed on the peripheral edge of the contact opening in the dielectric layer.

9. The resistivity of the dielectric layer is 1e １３ A semiconductor device according to any one of claims 1 to 8, wherein the impedance is Ω·cm or greater.

10. The semiconductor device according to any one of claims 1 to 9, wherein the thickness of the inner dielectric layer is 0.15 μm or more and 1.5 μm or less when converted to an equivalent oxide film thickness.

11. The dielectric layer is SiO ２ A semiconductor device according to any one of claims 1 to 10, comprising a material containing at least one of and SiN.

12. The dielectric layer is SiO ２ A semiconductor device according to any one of claims 1 to 10, comprising both a first dielectric layer made of a material containing and a second dielectric layer made of a material containing SiN.

13. The semiconductor device according to any one of claims 1 to 12, wherein the first conductive layer is made of polysilicon containing impurities.

14. The aforementioned impurity is an n-type impurity, and its impurity concentration is 1 × 10⁻⁶. １８ cm －３ The semiconductor device according to claim 13.

15. The semiconductor device according to any one of claims 1 to 14, wherein the semiconductor substrate is made of a material containing Si.

16. The semiconductor device according to any one of claims 1 to 15, wherein the resistivity of the semiconductor substrate is 100 mΩ·cm or less.

17. The semiconductor device according to any one of claims 1 to 16, wherein the thickness of the semiconductor substrate is 50 μm or more and 200 μm or less.

18. The semiconductor device according to any one of claims 1 to 17, wherein the plurality of trenches have a circular shape when viewed from the thickness direction, the plurality of trenches are arranged at intervals of 5 μm or less, the opening diameter of the plurality of trenches is 9 μm or less, and the depth of the plurality of trenches is 5 times or more and 20 times or less the opening diameter.

19. A semiconductor device according to any one of claims 1 to 18, comprising a passivation layer covering the upper surface of the dielectric layer, a portion of the first external electrode, and a portion of the second external electrode.

20. A semiconductor device according to any one of claims 1 to 18, comprising a resin layer covering the second conductive layer.

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