Gate drive device

Abstract

This gate drive device for driving a gate of a power transistor performs at least one of raising and lowering the gate voltage while changing the gate current a plurality of times at timings of the changes in the gate current of the power transistor. Thus, the gate of the power transistor can be more appropriately driven.

Description

Gate driving device

[0001] The present disclosure relates to a gate driving device.

[0002] Conventionally, as this type of gate driving device, a device for driving the gate of a power transistor (SiC MOSFET) has been proposed (see, for example, Non-Patent Document 1). This device detects the drain current using the voltage change between the power source terminal and the Kelvin source terminal of the power transistor, and adjusts the gate-source voltage based on the amount of time change of the detected drain current.

[0003] "Active Gate Driver for Improving Current Sharing Performance of Paralleled High-Power Sic MOSFET Modules", Yan Wen, Yuan Yang, and Yong Gao, IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL.36, NO.2, FEBRUARY 2021, pp. 1491-1505.

[0004] However, the above-mentioned gate driving device can be applied to a power transistor having a Kelvin source terminal, but cannot be applied to a power transistor not having a Kelvin source terminal. Generally, power transistors for high-power applications have a Kelvin source terminal, while power transistors for low-power applications have only a power source terminal without a Kelvin source terminal. Therefore, a gate driving device that can properly drive the gate regardless of whether the power transistor has a Kelvin source terminal or not is desired.

[0005] The main purpose of the gate driving device of the present disclosure is to more properly drive the gate of the power transistor regardless of whether the power transistor has a Kelvin source terminal or not.

[0006] The gate driving device of the present disclosure has taken the following means to achieve the above main purpose.

[0007] The gate drive device of this disclosure is a gate drive device for driving the gate of a power transistor, and its gist is to perform at least one of raising and lowering the gate voltage while changing the gate current multiple times at the timing of changes in the gate current of the power transistor.

[0008] In the gate drive device of this disclosure, at least one of raising and lowering the gate voltage is performed while changing the gate current multiple times in accordance with the timing of the change in the gate current of the power transistor. Since the gate drive device of this disclosure can accurately grasp the timing of the change in gate current even when the gate capacitance changes, the gate of the power transistor can be driven more appropriately regardless of whether the power transistor has a Kelvin source terminal or not.

[0009] In such a gate drive device of the present disclosure, the gate drive device may include a detection resistor connected to the gate, and a gate current adjustment circuit that sets the timing of the change in the voltage drop amount between the gate current and the detection resistor as the timing of the change in the gate current, and performs at least one of raising and lowering the gate voltage while changing the gate current multiple times at the timing of the change in the voltage drop amount. In this way, the gate drive device of the present disclosure can change the gate current using the timing of the change in the voltage drop amount.

[0010] In a gate drive device of the present disclosure in which the timing of the change in gate current is determined by the timing of the change in the gate voltage drop, the gate current adjustment circuit may change the gate current multiple times when the voltage drop crosses multiple reference voltages. In this way, the gate drive device of the present disclosure can change the gate current at a more appropriate timing. As a result, the gate drive device of the present disclosure can drive the gate of the power transistor more appropriately.

[0011] In a gate drive device of the present disclosure, which changes the gate current multiple times when the voltage drop crosses multiple reference voltages, the gate drive device includes a detection circuit that compares the voltage drop with the multiple reference voltages and outputs a result signal indicating the comparison result, and the gate current adjustment circuit may change the gate current multiple times in accordance with the output of the result signal. In this way, the gate drive device of the present disclosure can change the gate current at a more appropriate timing. As a result, the gate drive device of the present disclosure can drive the gate of the power transistor more appropriately.

[0012] In a gate drive device of the present disclosure equipped with a detection circuit, the plurality of reference voltages include a first reference voltage which is a positive voltage and a second reference voltage which is a positive voltage lower than the first reference voltage, the detection circuit outputs a first result signal when the voltage drop is less than or equal to the first reference voltage, and outputs a second result signal when the voltage drop is less than or equal to the second reference voltage, and the gate current adjustment circuit may set the gate current as a first current when raising the gate voltage, reduce the gate current to less than the first current in response to the input of the first result signal after setting the gate current to the first current, and increase the gate current in response to the input of the second result signal after reducing the gate current. In this way, the gate drive device of the present disclosure can raise the gate voltage more appropriately. As a result, the gate drive device of the present disclosure can drive the gate of a power transistor more appropriately.

[0013] In a gate drive device of the present disclosure equipped with a detection circuit, the plurality of reference voltages include a third reference voltage which is a negative voltage and a fourth reference voltage which is a negative voltage and higher than the third reference voltage, the detection circuit outputs a third result signal when the voltage drop is equal to or greater than the third reference voltage, and outputs a fourth result signal when the voltage drop is equal to or greater than the fourth reference voltage, the gate current adjustment circuit may set the gate current to a negative second current when the gate voltage is turned down, increase the gate current to the second current in response to the input of the third result signal, and decrease the gate current in response to the input of the fourth result signal after the gate current has been increased. In this way, the gate drive device of the present disclosure can raise the gate voltage more appropriately. As a result, the gate drive device of the present disclosure can drive the gate of a power transistor more appropriately.

[0014] In a gate drive device of the present disclosure that includes a gate current adjustment circuit, the gate current adjustment circuit may include a pull-up circuit having n P-type transistors connected in parallel between a power supply and the gate of the power transistor, and a first adjustment circuit that adjusts which of the n P-type transistors in the pull-up circuit is turned on when the gate voltage is raised. In this way, the gate current can be adjusted using the pull-up circuit in the gate drive device of the present disclosure.

[0015] Furthermore, in a gate drive device of the present disclosure that includes a gate current adjustment circuit, the gate current adjustment circuit may include a pull-down circuit having m N-type transistors connected in parallel between the gate of the power transistor and ground, and a second adjustment circuit that adjusts which of the m N-type transistors in the pull-down circuit is turned on when the gate voltage is turned down. In this way, the gate current can be adjusted using the pull-down circuit in the gate drive device of the present disclosure.

[0016] Furthermore, the gate drive device of this disclosure may be mounted on a single semiconductor substrate. This would allow for miniaturization of the gate drive device of this disclosure.

[0017] This is a schematic diagram showing the configuration of the gate drive device according to an embodiment of the present disclosure. This is a timing chart for explaining the operation of the gate drive device. This is an explanatory diagram showing the measurement results of the time change of the gate voltage when the load current is changed when the IGBT temperature is 25°C, in the case of raising the gate voltage. This is an explanatory diagram showing the measurement results of the time change of the detection voltage when the load current is changed when the temperature is 25°C, in the case of raising the gate voltage. This is an explanatory diagram showing the measurement results of the time change of the collector current when the load current is changed when the IGBT temperature is 25°C, in the case of raising the gate voltage. This is an explanatory diagram showing the measurement results of the relationship between time and load current at different temperatures. This is an explanatory diagram showing the measurement results of the relationship between the collector current IC overshoot amount and the energy loss ELOSS due to switching of IGBT 12.

[0018] Embodiments of this disclosure will be described with reference to the drawings. Figure 1 is a schematic diagram showing the configuration of the gate drive device 20 of an embodiment of this disclosure. The gate drive device 20 is configured as a device for driving the gate G of an insulated gate bipolar transistor (IGBT) 12.

[0019] Here, IGBT 12 will be described. The collector of IGBT 12 is connected to the power supply VDC (e.g., 600V) via the load 10, and the emitter is connected to a power terminal e to which ground potential is supplied. The load 10 comprises a reactor L, a diode D1, and IGBT 14 connected in parallel to each other.

[0020] The gate drive device 20 includes a detection resistor RG, a pull-up circuit 22, a pull-down circuit 24, a detection circuit 30, pull-up and pull-down serial in-parallel out registers (hereinafter referred to as "SIPO") 40 and 42, and pull-up and pull-down parallel in-serial out registers (hereinafter referred to as "PISO") 44 and 46. The "gate current adjustment circuit" corresponds to the pull-up circuit 22, the pull-down circuit 24, the level shifter 48, the SIPO 40 and 42, and the PISO 44 and 46. The "first adjustment circuit" corresponds to the level shifter 48, the SIPO 40, and the PISO 44. The "second adjustment circuit" corresponds to the SIPO 42 and the PISO 46.

[0021] The detection resistor RG is connected to the gate G of the IGBT 12. As will be described later, the detection resistor RG is input to comparators Comp1 to 4 in order to detect the gate current IG flowing through the gate G. Therefore, the resistance value is set to a level that allows the gate current IG to be detected without excessively hindering the operation of the IGBT 12.

[0022] The pull-up circuit 22 includes P-channel metal-oxide-semiconductor (PMOS) transistors P1 to P6 connected in parallel between the power supply VDRIVE and the gate G of the IGBT 12. The PMOS transistors P1 to P6 are configured as transistors with the same gate length but different gate widths. The gate widths of the PMOS transistors P2 to P6 are adjusted to be 2, 4, 8, 16, and 32 times the gate width of the PMOS transistor P1. In this embodiment, the power supply VDRIVE is supplied with a voltage of 10V to 18V, preferably 15V.

[0023] The pull-down circuit 24 includes N-channel (N-type) metal-oxide-semiconductor (NMOS) transistors N1 to N6 connected in parallel between the gate G of the IGBT 12 and ground. The NMOS transistors N1 to N6 are configured as transistors with the same gate length but different gate widths. The gate widths of the NMOS transistors N2 to N6 are adjusted to be 2 times, 4 times, 8 times, 16 times, and 32 times the gate width of the NMOS transistor N1.

[0024] The detection circuit 30 includes comparators Comp1 to Comp4. Comparators Comp1 and Comp2 receive the following inputs: the voltage across the detection resistor RG of the gate G, i.e., the detection voltage VRG as the voltage drop across the gate G due to the gate current IG and the detection resistor RG; the turn-on side reference voltages (first and second reference voltages) VREF1 and VREF2; and the reference input voltage IN. The detection voltage VRG is the voltage drop across the gate G due to the gate current IG and the detection resistor RG. The reference voltages VREF1 and VREF2 are predetermined voltages that are positive voltages lower than the maximum value of the detection voltage VRG. Reference voltage VREF2 is a voltage smaller than reference voltage VREF1. The reference input voltage IN is a pulse signal, which rises (becomes logic high) when the gate G of IGBT 12 is pulled up, and falls (becomes logic low) when the gate G of IGBT 12 is pulled down. Comparator Comp1 outputs a pulse signal (first result signal) to PISO 44 via level shifter 48, which changes the amplitude of the signal, when the reference input voltage IN is rising and the detection voltage VRG goes from a voltage higher than the reference voltage VREF1 to a voltage lower than or equal to the reference voltage VREF1. Comparator Comp2 outputs a pulse signal (second result signal) to PISO 44 via level shifter 48, when the reference input voltage IN is rising and the detection voltage VRG goes from a voltage higher than the reference voltage VREF2 to a voltage lower than or equal to the reference voltage VREF2. Comparators Comp3 and Comp4 receive a detection voltage VRG, reference voltages (third and fourth reference voltages) VREF3 and VREF4, and a reference input voltage IN. Reference voltages VREF3 and VREF4 are predetermined negative voltages lower than 0V. Reference voltage VREF4 is set to be higher (smaller in absolute value) than reference voltage VREF3. Comparator Comp3 outputs a pulse signal (third result signal) to PISO46 when the reference input voltage IN is falling and the detection voltage VRG rises from a voltage lower than reference voltage VREF3 to a voltage equal to or greater than reference voltage VREF3.Comparator Comp4 outputs a pulse signal (fourth result signal) to PISO46 when the reference input voltage IN is falling and the detection voltage VRG rises from a voltage lower than the reference voltage VREF4 to a voltage higher than or equal to the reference voltage VREF4.

[0025] SIPO 40 receives a scan-in input SIn and a clock signal, the scan clock SCLK, via a level shifter 48. SIPO 42 receives a scan-in input SIn and the scan clock SCLK. The scan-in input SIn is a serial signal that indicates a predetermined pattern Pp, which is a combination of transistors to be turned on from among the PMOS transistors P1 to P6, and a pattern Pn, which is a combination of transistors to be turned on from among the NMOS transistors N1 to N6. Pattern Pp is predetermined such that when the current flowing when the PMOS transistor P1 is turned on is Iop (positive current), the gate current IG changes in the order of n1・Iop, n2・Iop, n3・Iop. In this embodiment, "n1" is set to value 63, "n2" to value 1, and "n3" to value 63. Pattern Pn is predetermined such that when the current flowing when the NMOS transistor N1 is turned on is Ion (negative current), the gate current IG changes in the order of n4・Ion, n5・Ion, and n6・Ion. In this embodiment, "n4" is set to value 63, "n5" to value 1, and "n6" to value 63. SIPO40 receives the scan-in input SIn in synchronization with the scan clock SCLK and outputs a parallel signal indicating pattern Pp to PISO44. SIPO42 receives the scan-in input SIn in synchronization with the scan clock SCLK and outputs a parallel signal indicating pattern Pn to PISO46.

[0026] PISO44 receives a pattern Pp of transistor combinations to be turned on from SIPO40, as well as a reference input voltage IN and a pulse signal from the detection circuit 30 via the level shifter 48. PISO44 drives the PMOS transistors P1 to P6 of the pull-up circuit 22 based on the reference input voltage IN and the pulse signal from the detection circuit 30 input via the level shifter 48, and the pattern Pp. When the reference input voltage IN rises, PISO44 controls the PMOS transistors P1 to P6 of the pull-up circuit 22 according to the pattern Pp so that the gate current IG becomes n1・Iop. Next, when the pulse signal is input from the detection circuit 30, PISO44 controls the PMOS transistors P1 to P6 of the pull-up circuit 22 according to the pattern Pp so that the gate current IG becomes n2・Iop. Subsequently, when PISO44 receives a pulse signal from the detection circuit 30, it controls the PMOS transistors P1 to P6 of the pull-up circuit 22 according to pattern Pp so that the gate current IG becomes n3・Iop. In this way, when the reference input voltage IN rises, PISO44 sequentially switches which transistors among the PMOS transistors P1 to P6 of the pull-up circuit 22 to turn on according to pattern Pp in response to the pulse signal input from the detection circuit 30. When the reference input voltage IN falls, PISO44 turns off all of the PMOS transistors P1 to P6 of the pull-up circuit 22.

[0027] PISO46 receives a pattern Pn of the combination of transistors to be turned on from SIPO42, a reference input voltage IN, and a pulse signal from the detection circuit 30. PISO46 drives the NMOS transistors N1 to N6 of the pull-down circuit 24 based on the reference input voltage IN, the pulse signal from the detection circuit 30, and pattern Pn. When the reference input voltage IN falls, PISO46 controls the NMOS transistors N1 to N6 of the pull-down circuit 24 according to pattern Pn so that the gate current IG is n4·Ion. Next, when a pulse signal is input from the detection circuit 30, PISO46 controls the NMOS transistors N1 to N6 of the pull-down circuit 24 according to pattern Pn so that the gate current IG is n5·Ion. Subsequently, when a pulse signal is input from the detection circuit 30, PISO47 controls the NMOS transistors N1 to N6 of the pull-down circuit 24 according to pattern Pn so that the gate current IG is n6·Ion. In this way, PISO46 sequentially switches the transistors that turn on among the NMOS transistors N1 to N6 of the pull-down circuit 24 according to pattern Pn, in response to the falling edge of the reference input voltage IN and the input of a pulse signal from the detection circuit 30. When the reference input voltage IN rises, PISO46 turns off all of the NMOS transistors N1 to N of the pull-down circuit 24.

[0028] SIPO40 and PISO44 are supplied with a power supply voltage VDD1, such as 5V. SIPO42, PISO46, and the detection circuit 30 are supplied with a power supply voltage VDD2, such as 5V.

[0029] In the gate drive device 20 of this embodiment, the entire gate drive device 20 can be integrated onto a single semiconductor substrate, thereby enabling miniaturization of the entire device.

[0030] Next, the operation of the gate drive device 20 of the embodiment configured in this way will be described. Figure 2 is a timing chart for illustrating the operation of the gate drive device 20.

[0031] In the gate drive device 20, when the reference input voltage IN rises (time t00), PISO 44 controls the PMOS transistors P1 to P6 of the pull-up circuit 22 according to pattern Pp so that the gate current IG becomes n1・Iop (first current). As a result, the gate voltage VGE, which is the voltage between the gate and emitter, increases. With the increase in the gate voltage VGE, the gate current IG, which is the charging current of the gate G, decreases.

[0032] When the gate voltage VGE increases and reaches the threshold voltage of the IGBT 12 (time t10), the collector current IC increases from a value of 0. In the gate drive device 20 of this embodiment, the timing at which the collector current IC increases from a value of 0 is detected by comparing the continuously decreasing detection voltage VRG with the reference voltage VREF1. Specifically, the timing at which the detection voltage VRG falls below the reference voltage VREF1 is detected. The comparator Comp1 of the detection circuit 30 outputs a pulse signal to PISO 44 via the level shifter 48 when the detection voltage VRG decreases to below the reference voltage VREF1. The PMOS transistors P1 to P6 of the pull-up circuit 22 are controlled according to the pattern Pp at which the pulse signal is input to PISO 44 so that the gate current IG becomes n2・Iop. As a result, the gate current IG changes from n1・Iop to n2・Iop. In this embodiment, since "n1" is value 63 and "n2" is value 1, the gate current IG decreases. At this time, the gate voltage VGE decreases instantaneously and then rises and is maintained at the Miller plateau voltage. By reducing the gate current IG in this way, the amount of collector current IC overshoot can be reduced. Thus, the gate drive device 20 detects the timing when the collector current IC has increased when the detection voltage VRG falls below the reference voltage VREF1 and reduces the gate current IG. The gate current IG, which is the charging current of the gate G, continues to decrease for a period of time t2.

[0033] At time t20, the collector current IC overshoots and reaches its peak. In the gate drive device 20 of this embodiment, the timing at which the collector current IC overshoots and reaches its peak is detected by comparing the continuously decreasing detection voltage VRG with the reference voltage VREF2. Specifically, the timing at which the detection voltage VRG falls below the reference voltage VREF2 is detected. The comparator Comp2 of the detection circuit 30 outputs a pulse signal to PISO44 via the level shifter 48 at the timing when the detection voltage VRG becomes less than or equal to the reference voltage VREF2. Upon receiving the pulse signal, PISO44 controls the PMOS transistors P1 to P6 of the pull-up circuit 22 according to pattern Pp so that the gate current IG becomes n3・Iop. As a result, the gate current IG changes from n2・Iop to n3・Iop. In this embodiment, since "n2" is a value of 1 and "n3" is a value of 63, the gate current IG increases. At this time, the gate voltage VGE rises and is maintained at a voltage corresponding to the gate current IG. In this way, the gate drive device 20 detects the timing when the collector current IC overshoots and reaches its peak when the detection voltage VRG falls below the reference voltage VREF2, and increases the gate current IG. Through this operation, when the reference input voltage IN rises, the gate drive device 20 raises the gate voltage VGE while adjusting the gate current IG in accordance with the timing of the change in the detection voltage VRG, i.e., the gate current IG. As a result, the gate drive device 20 can drive the gate G while suppressing excessive overshoot of the collector current IC.

[0034] In the gate drive device 20, when the reference input voltage IN falls (time t30), PISO 46 controls the NMOS transistors N1 to N6 of the pull-down circuit 24 according to pattern Pn so that the gate current IG becomes n4・Ion (negative current, second current). As a result, when the reference input voltage IN falls, the absolute value of the gate current IG, which is the discharge current of the gate G, decreases as the gate voltage VGE decreases. When the gate voltage VGE decreases, the IGBT 12 turns off, so the collector voltage VCE, which is the voltage between the collector and emitter, rises and the collector current IC decreases.

[0035] At time t40, the collector current IC begins to decrease. In the gate drive device 20 of this embodiment, the timing at which the collector current IC begins to decrease is detected by comparing a detection voltage VRG, whose absolute value decreases in accordance with the decrease in the absolute value of the gate current IG, with a reference voltage VREF3 (negative voltage). Specifically, the timing at which the detection voltage VRG (negative voltage) increases to be greater than or equal to the reference voltage VREF3 (negative voltage) is detected. The comparator Comp3 of the detection circuit 30 outputs a pulse signal to PISO46 at the timing when the detection voltage VRG becomes greater than or equal to the reference voltage VREF3. Upon receiving the pulse signal, PISO46 controls the NMOS transistors N1 to N6 of the pull-down circuit 24 according to pattern Pn so that the gate current IG becomes n5・Ion. As a result, the gate current IG changes from n4・Ion to n5・Ion. In this embodiment, since "n4" is value 63 and "n5" is value 1, the gate current IG increases (the absolute value of the gate current IG decreases). At this time, the gate voltage VGE rises instantaneously and then falls to the Miller plateau voltage. This suppresses the increase in the collector voltage VCE and reduces the amount of overshoot in the collector voltage VCE. In this way, the gate drive device 20 detects the timing when the collector current IC decreases by the timing when the detection voltage VRG increases and increases the gate current IG (decreases the absolute value of the gate current IG). The absolute value of the gate current IG, which is the discharge current of the gate G, continues to decrease for a period of time t5.

[0036] At time t50, the collector current IC becomes 0. In the gate drive device 20 of this embodiment, the timing at which the collector current IC becomes 0 is detected by comparing a detection voltage VRG, whose absolute value decreases in accordance with the decrease in the absolute value of the gate current IG, with a reference voltage VREF4 (negative voltage). Specifically, the timing at which the detection voltage VRG (negative voltage) increases to be greater than or equal to the reference voltage VREF4 (negative voltage) is detected. The comparator Comp4 of the detection circuit 30 outputs a pulse signal to PISO46 at the timing when the detection voltage VRG becomes greater than or equal to the reference voltage VREF4. Upon receiving the pulse signal, PISO46 controls the NMOS transistors N1 to N6 of the pull-down circuit 24 according to pattern Pn so that the gate current IG becomes n6・Ion. As a result, the gate current IG changes from n5・Ion to n6・Ion. In this embodiment, "n5" is value 1 and "n6" is value 63, and the current Ion is a negative current, so the gate current IG decreases (the absolute value of the gate current IG increases). At this time, the gate voltage VGE decreases to a negative voltage (-VDD2). In this way, the gate drive device 20 detects the timing when the collector current IC decreases at the timing when the detection voltage VRG increases (decreases in absolute value). Through this operation, when the reference input voltage IN falls, the gate drive device 20 lowers the gate voltage VGE while adjusting the gate current IG in accordance with the timing of the change in the detection voltage VRG, i.e., the gate current IG. As a result, the gate drive device 20 can drive the gate G while suppressing excessive overshoot of the collector voltage VCE.

[0037] Figure 3 is an explanatory diagram showing the measurement results of the time change of the gate voltage VGE when the load current IL is changed while the temperature Tj of the IGBT 12 is 25°C, in the case of raising the gate voltage VGE. Figure 4 is an explanatory diagram showing the measurement results of the time change of the detection voltage VRG when the load current IL is changed while the temperature Tj is 25°C, in the case of raising the gate voltage VGE. Figure 5 is an explanatory diagram showing the measurement results of the time change of the collector current IC when the load current IL is changed while the temperature Tj of the IGBT 12 is 25°C, in the case of raising the gate voltage VGE. Figure 6 is an explanatory diagram showing the measurement results of the relationship between time t2 and load current IL at different temperatures Tj. Figure 7 is an explanatory diagram showing the measurement results of the relationship between the amount of overshoot of the collector current IC and the energy loss ELOSS due to switching of the IGBT 12. In Figure 7, the black circles indicate the relationship between the amount of overshoot of the collector current IC and the energy loss ELOSS of the IGBT 12 in a comparative gate drive device where time t2 is constant. The black star indicates the relationship between the collector current IC overshoot amount and the IGBT 12 energy loss ELOSS in the gate drive device 20 of the embodiment.

[0038] As shown in Figures 3 to 6, time t2 is longer when the load current IL is large compared to when it is small. This is because, as shown in Figure 5, as the load current IL increases, the timing at which the collector current IC reaches its peak is delayed. As shown in Figure 6, time t2 is longer when the temperature Tj is high compared to when it is low. This is because, when the temperature Tj is high, the peak value of the collector current IC is larger compared to when it is low, and the timing at which the collector current IC reaches its peak is delayed. As shown in Figure 7, in the gate drive device 20 of the embodiment, the energy loss ELOSS of the IGBT 12 is smaller compared to the comparative embodiment. Thus, in the gate drive device 20 of the embodiment, the energy loss ELOSS can be suppressed compared to the comparative embodiment.

[0039] According to the gate drive device 20 of this embodiment described above, the gate G of the IGBT 12 can be driven more appropriately by changing the gate current IG multiple times at the timing of the change in the gate current IG of the IGBT 12 while raising and lowering the gate voltage VGE.

[0040] Furthermore, in the gate drive device 20 of this embodiment, a detection resistor RG connected to the gate G, and SIPO 40, 42, PISO 44, 46, level shifter 48, pull-up circuit 22, pull-down circuit 24 are provided, which set the timing of the change in the detection voltage VRG as the timing of the change in the gate current IG, and raise and lower the gate voltage VGE while changing the gate current IG multiple times at the timing of the change in the detection voltage VRG, thereby making it possible to change the gate current IG using the timing of the change in the detection voltage VRG.

[0041] Furthermore, in the gate drive device 20 of this embodiment, when the detection voltage VRG crosses the reference voltages VREF1 to VREF4, the gate current IG is changed multiple times, thereby enabling more appropriate driving of the gate G of the IGBT 12.

[0042] Furthermore, the gate drive device 20 of this embodiment is equipped with comparators Comp1 to Comp4 that compare a detection voltage VRG with reference voltages VREF1 to VREF4 and output a pulse signal. SIPO 40, 42, PISO 44, 46, level shifter 48, pull-up circuit 22, and pull-down circuit 24 change the gate current IG multiple times in accordance with the output of the pulse signal, thereby enabling more appropriate driving of the gate G of the IGBT 12.

[0043] Also, in the gate drive device 20 of the present embodiment, when the detection voltage VRG is less than or equal to the reference voltage VREF1, the comparator Comp1 outputs a pulse signal to the PISO44 via the level shifter 48. When the detection voltage VRG is less than or equal to the reference voltage VREF2, the comparator Comp2 outputs a pulse signal to the PISO44 via the level shifter 48. The PISO44 controls the PMOS transistors P1 to P6 of the pull-up circuit 22 so that the gate current IG becomes n1·Iop, and then controls the PMOS transistors P1 to P6 of the pull-up circuit 22 so that the gate current IG becomes n2·Iop in response to the input of the pulse signal. After controlling the PMOS transistors P1 to P6 of the pull-up circuit 22 so that the gate current IG becomes n2·Iop, the PMOS transistors P1 to P6 of the pull-up circuit 22 are controlled so that the gate current IG becomes n3·Iop in response to the input of the pulse signal, thereby enabling more appropriate driving of the gate G of the IGBT12.

[0044] Further, in the gate drive device 20 of the present embodiment, when the detection voltage VRG is greater than or equal to the reference voltage VREF3, the comparator Comp3 outputs a pulse signal to the PISO46. When the detection voltage VRG is greater than or equal to the reference voltage VREF4, the comparator Comp4 outputs a pulse signal to the PISO46. The PISO46 controls the NMOS transistors N1 to N6 of the pull-down circuit 24 so that the gate current IG becomes n4·Ion, and then controls the NMOS transistors N1 to N6 of the pull-down circuit 24 so that the gate current IG becomes n5·Ion in response to the input of the pulse signal. After controlling the NMOS transistors N1 to N6 of the pull-down circuit 24 so that the gate current IG becomes n5·Ion, the NMOS transistors N1 to N6 of the pull-down circuit 24 are controlled so that the gate current IG becomes n6·Ion in response to the input of the pulse signal, thereby enabling more appropriate driving of the gate G of the IGBT12.

[0045] And in the gate drive device 20 of the present embodiment, since it has a pull-up circuit 22, and a SIP040 and a PISO44 that adjust transistors that turn on among the PMOS transistors P1 to P6 of the pull-up circuit 22 when raising the gate voltage VGE, the gate current IG can be adjusted using the pull-up circuit 22.

[0046] Also, in the gate drive device 20 of the present embodiment, since it has a pull-down circuit 24, and a SIP042 and a PISO446 that adjust transistors that turn on among the NMOS transistors N1 to N6 of the pull-down circuit 24 when lowering the gate voltage VGE, the gate current IG can be adjusted using the pull-down circuit 24.

[0047] Further, since the gate drive device 20 of the present embodiment is mounted on one semiconductor substrate, the size of the device can be reduced.

[0048] In the above-described embodiment, the gate current IG is changed at the timing of the change in the gate current IG of the IGBT12 when the gate voltage VGE is rising and falling. However, when at least one of the rising and falling of the gate voltage VGE is performed, the gate current IG may be changed at the timing of the change in the gate current IG of the IGBT12. For example, when the gate voltage VGE is rising, the gate current IG is changed at the timing of the change in the gate current IG of the IGBT12, and when the gate voltage VGE is falling, the gate current IG may be changed at a predetermined timing without considering the timing of the change in the gate current IG of the IGBT12.

[0049] In the above-described embodiment, the gate current IG is changed three times at the timing of the change in the gate current IG of the IGBT12 when the gate voltage VGE is rising and falling. However, the number of times the gate current IG is changed is not limited to three times, and it may be two times or four times or more.

[0050] In the embodiment described above, the gate drive device 20 compares the detection voltage VRG with two reference voltages (reference voltages VREF1 and VREF2) when the gate voltage VGE is raised, but it may also compare the detection voltage VRG with three or more reference voltages.

[0051] In the embodiment described above, the gate drive device 20 compares the detection voltage VRG with two reference voltages (reference voltages VREF3, VREF4) when the gate voltage VGE falls, but it may also compare the detection voltage VRG with three or more reference voltages.

[0052] In the embodiment described above, the pull-up circuit 22 comprises PMOS transistors P1 to P6 with the same gate length but different gate widths. However, at least one of the PMOS transistors P1 to P6 may have the same gate width, or their gate lengths may be different. Furthermore, the number of PMOS transistors included in the pull-up circuit 22 is not limited to six, but may be appropriately changed according to the required gate current IG.

[0053] In the embodiment described above, the pull-down circuit 24 includes NMOS transistors N1 to N6 with the same gate length but different gate widths. However, at least one of the NMOS transistors N1 to N6 may have the same gate width, or they may have different gate lengths. Furthermore, the number of NMOS transistors included in the pull-down circuit 24 is not limited to six, but may be appropriately changed according to the required gate current IG.

[0054] In the embodiment described above, the gate drive device 20 drives the gate G of the IGBT 12. However, the object whose gate is driven can be any power transistor equipped with a gate, for example, a power MOSFET (metal-oxide-semiconductor field-effect transistor).

[0055] In the embodiment described above, the timing of the change in the detection voltage VRG is used as the timing of the change in the gate current IG. However, instead of providing a detection resistor RG, the gate current IG supplied from the gate drive device 20 to the gate G may be detected by a current sensor, and the timing of the change in the detected value may be used as the timing of the change in the gate current IG.

[0056] In the embodiments described above, the gate drive device 20 of this disclosure is mounted on one semiconductor substrate, but it may be mounted on two or more semiconductor substrates.

[0057] The correspondence between the main elements of the embodiment and the main elements of the invention described in the section on means for solving the problem will be explained. In the embodiment, the IGBT 12 corresponds to a "power transistor," and the gate drive device 20 corresponds to a "gate drive device."

[0058] Furthermore, the correspondence between the main elements of the embodiment and the main elements of the invention described in the section on means for solving the problem is merely an example to specifically explain the form in which the embodiment implements the invention described in the section on means for solving the problem, and does not limit the elements of the invention described in the section on means for solving the problem. In other words, the interpretation of the invention described in the section on means for solving the problem should be based on the description in that section, and the embodiment is merely one specific example of the invention described in the section on means for solving the problem.

[0059] Although the embodiments for implementing this disclosure have been described above, this disclosure is not limited in any way to these embodiments, and can of course be implemented in various forms without departing from the gist of this disclosure.

[0060] This disclosure can be used in industries such as the manufacturing of gate drive devices.

Claims

1. A gate drive device for driving the gate of a power transistor, wherein the gate drive device performs at least one of raising and lowering the gate voltage while changing the gate current multiple times at the timing of changes in the gate current of the power transistor.

2. A gate drive device according to claim 1, comprising: a detection resistor connected to the gate; and a gate current adjustment circuit that sets the timing of the change in the voltage drop amount between the gate current and the detection resistor as the timing of the change in the gate current, and performs at least one of raising and lowering the gate voltage while changing the gate current multiple times at the timing of the change in the voltage drop amount.

3. A gate drive device according to claim 2, wherein the gate current adjustment circuit changes the gate current multiple times when the voltage drop amount crosses multiple reference voltages.

4. A gate drive device according to claim 3, comprising a detection circuit that compares the voltage drop amount with a plurality of reference voltages and outputs a result signal indicating the comparison result, wherein the gate current adjustment circuit changes the gate current multiple times in accordance with the output of the result signal.

5. A gate drive device according to claim 4, wherein the plurality of reference voltages include a first reference voltage which is a positive voltage and a second reference voltage which is a positive voltage and lower than the first reference voltage, the detection circuit outputs a first result signal when the voltage drop is less than or equal to the first reference voltage, and outputs a second result signal when the voltage drop is less than or equal to the second reference voltage, and the gate current adjustment circuit sets the gate current as a first current when raising the gate voltage, reduces the gate current to less than the first current in response to the input of the first result signal after the gate current has been set to the first current, and increases the gate current in response to the input of the second result signal after the gate current has been reduced.

6. A gate drive device according to claim 4, wherein the plurality of reference voltages include a third reference voltage which is a negative voltage and a fourth reference voltage which is a negative voltage and is higher than the third reference voltage, the detection circuit outputs a third result signal when the voltage drop is greater than or equal to the third reference voltage, and outputs a fourth result signal when the voltage drop is greater than or equal to the fourth reference voltage, and the gate current adjustment circuit sets the gate current to a negative second current when the gate voltage is turned down, increases the gate current to be greater than the second current in response to the input of the third result signal after the gate current has been set to the second current, and decreases the gate current in response to the input of the fourth result signal after the gate current has been increased.

7. A gate drive device according to claim 2, wherein the gate current adjustment circuit comprises: a pull-up circuit having n P-type transistors connected in parallel between a power supply and the gate of the power transistor; and a first adjustment circuit that adjusts which of the n P-type transistors in the pull-up circuit is turned on when the gate voltage is raised.

8. A gate drive device according to claim 2, wherein the gate current adjustment circuit comprises: a pull-down circuit having m N-type transistors connected in parallel between the gate of the power transistor and ground; and a second adjustment circuit that adjusts which of the m N-type transistors in the pull-down circuit is turned on when the gate voltage is turned down.

9. A gate drive device according to claim 1 or 2, wherein the gate drive device is mounted on a single semiconductor substrate.

Images