Display panel and electronic device

Abstract

A driving circuit according to embodiments of the present invention comprises a plurality of stages, wherein the plurality of stages are disposed on a plurality of island portions, at least one signal line connected to the stages includes at least one first conductive line disposed on first bridge portions and at least one second conductive line disposed on second bridge portions, and the at least one second conductive line can extend across a plurality of island portions.

Description

Display panels and electronic devices

[0001] Embodiments of the present invention relate to a display device, more specifically a stretchable display device and an electronic device including the same.

[0002] As display devices that visually display electrical signals advance, various display devices with excellent characteristics such as thinness, lightness, and low power consumption are being introduced. For example, flexible display devices that can be folded or rolled into a roll shape are being introduced. Recently, research and development on stretchable display devices capable of changing into various shapes is actively underway.

[0003] Embodiments of the present invention may provide a display device with improved display quality. However, these objectives are exemplary and do not limit the scope of the present invention.

[0004] A display panel according to one embodiment of the present invention includes a non-display area defined with a plurality of island portions and a plurality of bridge portions connecting the island portions, and a driving circuit including a plurality of stages is provided in the non-display area, at least one of the plurality of stages is disposed in each of the plurality of island portions, and at least one signal line connected to the plurality of stages is disposed in the plurality of bridge portions, the plurality of bridge portions include first bridge portions extended along a first direction and second bridge portions extended along a second direction perpendicular to the first direction, the plurality of stages are disposed in a plurality of island portions arranged along the second direction, and the at least one signal line includes at least one first conductive line disposed in the first bridge portions and at least one second conductive line disposed in the second bridge portions, and the at least one second conductive line extends across the plurality of island portions.

[0005] In one embodiment, the at least one first conductive line may include an output line through which the output signal of the at least one stage is output.

[0006] In one embodiment, the at least one second conductive line may include a voltage line that transmits voltage to the at least one stage and a clock line that transmits a clock signal.

[0007] In one embodiment, the voltage line and the clock line may be placed on different layers.

[0008] In one embodiment, a stage may be disposed in each of the plurality of island sections.

[0009] In one embodiment, an odd-numbered stage and an even-numbered stage may be disposed in each of the plurality of island sections.

[0010] A display panel according to one embodiment of the present invention comprises a non-display area defined with a plurality of island portions and a plurality of bridge portions connecting the island portions, a first driving circuit including a plurality of first stages in the non-display area, and a second driving circuit including a plurality of second stages in the non-display area, wherein the first driving circuit is closer to the display area than the second driving circuit. The plurality of island sections include first island sections in a first row in which the plurality of first stages are arranged and second island sections in a second row in which the plurality of second stages are arranged, and the plurality of bridge sections include first bridge sections in which at least one first signal line connected to the plurality of first stages is arranged and second bridge sections in which at least one second signal line connected to the plurality of second stages is arranged, the first bridge sections include first horizontal bridge sections extended along a first direction and first vertical bridge sections extended along a second direction perpendicular to the first direction, and the second bridge sections include second horizontal bridge sections extended along the first direction and second vertical bridge sections extended along the second direction, and the at least one first signal line includes at least one first horizontal conductor line arranged in the first horizontal bridge sections and at least one first vertical conductor line arranged in the first vertical bridge sections, and the at least one second signal line includes at least one arranged in the second horizontal bridge sections It includes one second horizontal conductor and at least one second vertical conductor disposed in the second vertical bridge sections, wherein the at least one first vertical conductor extends across the first island sections and the at least one second vertical conductor extends across the second island sections.

[0011] In one embodiment, a first stage may be disposed in each of the first island sections, and an odd-numbered second stage and an even-numbered second stage may be disposed in each of the second island sections.

[0012] In one embodiment, the first horizontal conductor includes a first output line through which the output signal of the first stage is output, and the second horizontal conductor may include a second output line through which the output signal of the odd-numbered second stage is output and a third output line through which the output signal of the even-numbered second stage is output.

[0013] In one embodiment, each of the first horizontal bridge sections may be connected to one of the first island sections and one of the second island sections arranged in the same row.

[0014] In one embodiment, the first output line is disposed in a second horizontal bridge section connected to a first horizontal bridge section disposed in a first row and a second island section disposed in the first row, and the second output line and the third output line are spaced apart in the second horizontal bridge section disposed in the first row, and in the second horizontal bridge section disposed in the first row, the first output line may overlap at least partially with the second output line and the third output line in a plane.

[0015] In one embodiment, a connecting electrode is disposed in a second island portion disposed in the first row, and the connecting electrode can connect a first output line disposed in a first horizontal bridge portion disposed in the first row and a first output line disposed in a second horizontal bridge portion disposed in the first row.

[0016] In one embodiment, the first output line placed in the first horizontal bridge section placed in the first row and the first output line placed in the second horizontal bridge section placed in the first row may be placed on different layers.

[0017] In one embodiment, the first vertical conductor includes a first voltage line that transmits voltage to the first stage and a first clock line that transmits a clock signal, and the second vertical conductor may include a second voltage line that transmits voltage to the odd-numbered second stage and the even-numbered second stage and a second clock line that transmits a clock signal.

[0018] In one embodiment, the first voltage line and the first clock line may be placed on different layers, the second voltage line may be placed on the same layer as the first voltage line, and the second clock line may be placed on the same layer as the first clock line.

[0019] In one embodiment, the first vertical conductor may further include a first carry line that transmits a start signal to the first stage, and the second vertical conductor may further include a second carry line that transmits a start signal to the odd-numbered second stage.

[0020] In one embodiment, the first carry line may be placed on a different layer from the first voltage line, the first voltage line may overlap the first carry line, and the second carry line may be placed on the same layer as the second voltage line.

[0021] An electronic device according to one embodiment of the present invention comprises: a display panel in which a display area in which a plurality of pixels are arranged and a non-display area outside the display area are defined; and a driving circuit disposed in the non-display area and outputting a gate signal to the plurality of pixels of the display panel. The non-display area is defined with a plurality of island portions and a plurality of bridge portions connecting the island portions. The driving circuit comprises a first driving circuit including a plurality of first stages; and a second driving circuit including a plurality of second stages; wherein the first driving circuit is closer to the display area than the second driving circuit. The plurality of island sections include first island sections in a first row in which the plurality of first stages are arranged and second island sections in a second row in which the plurality of second stages are arranged, and the plurality of bridge sections include first bridge sections in which at least one first signal line connected to the plurality of first stages is arranged and second bridge sections in which at least one second signal line connected to the plurality of second stages is arranged, the first bridge sections include first horizontal bridge sections extended along a first direction and first vertical bridge sections extended along a second direction perpendicular to the first direction, and the second bridge sections include second horizontal bridge sections extended along the first direction and second vertical bridge sections extended along the second direction, and the at least one first signal line includes at least one first horizontal conductor line arranged in the first horizontal bridge sections and at least one first vertical conductor line arranged in the first vertical bridge sections, and the at least one second signal line includes at least one arranged in the second horizontal bridge sections It includes one second horizontal conductor and at least one second vertical conductor disposed in the second vertical bridge sections, wherein the at least one first vertical conductor extends across the first island sections and the at least one second vertical conductor extends across the second island sections.

[0022] In one embodiment, a first stage may be disposed in each of the first island sections, and an odd-numbered second stage and an even-numbered second stage may be disposed in each of the second island sections.

[0023] In one embodiment, the first vertical conductor line may include a first voltage line that transmits voltage to the first stage, a first clock line that transmits a clock signal, and a first carry line that transmits a start signal, and the second vertical conductor line may include a second voltage line that transmits voltage to the odd-numbered second stage and the even-numbered second stage, a second clock line that transmits a clock signal, and a second carry line that transmits a start signal to the odd-numbered second stage. The first voltage line and the first clock line may be placed on different layers, the second voltage line may be placed on the same layer as the first voltage line, the second clock line may be placed on the same layer as the first clock line, the first carry line may be placed on a different layer from the first voltage line, and the second carry line may be placed on the same layer as the second voltage line.

[0024] According to embodiments of the present invention, a display device with improved display quality can be provided. Of course, the scope of the present invention is not limited by such effects.

[0025] FIG. 1 is a schematic perspective view of a display panel (1) according to one embodiment of the present invention.

[0026] FIGS. 2a and FIGS. 2b are perspective views showing the display panel (1) of FIG. 1 extended in the first direction.

[0027] FIG. 2c is a perspective view showing the display panel (1) of FIG. 1 extended in a second direction.

[0028] FIG. 2d is a perspective view showing the display panel (1) of FIG. 1 extended in the first direction and the second direction.

[0029] FIG. 2e is a perspective view showing the display panel (1) of FIG. 1 extended in a third direction.

[0030] FIG. 3 is a schematic plan view of a display panel (1) according to one embodiment.

[0031] FIG. 4 is a plan view of the IV portion of FIG. 3 as a part of a display panel (1) according to one embodiment.

[0032] FIG. 5a is a cross-sectional view schematically showing a first island portion and a first bridge portion arranged in a display area according to one embodiment.

[0033] FIG. 5b is a cross-sectional view schematically showing a second island section and a second bridge section placed in a non-display area according to one embodiment.

[0034] FIGS. 6a and FIGS. 6b are equivalent circuit diagrams of a pixel according to one embodiment.

[0035] FIG. 7a is a cross-sectional view schematically showing a light-emitting element of a display panel according to one embodiment.

[0036] FIG. 7b is a cross-sectional view schematically showing a light-emitting element of a display panel according to one embodiment.

[0037] FIG. 8 is a schematic diagram showing a display panel according to one embodiment.

[0038] FIG. 9 is a schematic diagram showing a gate driving circuit according to one embodiment.

[0039] FIG. 10 is a schematic diagram showing any stages constituting a gate driving circuit according to one embodiment.

[0040] FIG. 11 is a schematic diagram showing any stage of a first driving circuit (131) or a second driving circuit (133) according to one embodiment.

[0041] FIG. 12 is a schematic diagram showing any stage of a third driving circuit (135) according to one embodiment.

[0042] FIG. 13 is a schematic diagram showing any stage of the fourth driving circuit (137) according to one embodiment.

[0043] FIG. 14 is a schematic plan view showing a part of a gate driving circuit (130) according to one embodiment.

[0044] FIG. 15 is a schematic diagram showing a part of the fourth driving circuit (137) according to one embodiment.

[0045] FIGS. 16 to 19 are schematic drawings illustrating the components of the fourth driving circuit (137) shown in FIG. 15 layer by layer.

[0046] FIG. 20 is a cross-sectional view taken along Ia-Ia', IIa-IIa', and IIIa-IIIa' of the fourth driving circuit (137) shown in FIG. 15.

[0047] FIG. 21 is a schematic diagram showing a part of a third driving circuit (135) according to one embodiment.

[0048] FIGS. 22 to 25 are schematic drawings illustrating the components of the third driving circuit (135) shown in FIG. 21 layer by layer.

[0049] FIG. 26 is a cross-sectional view taken along Ib-Ib', IIb-IIb', and IIIb-IIIb' of the third driving circuit (135) shown in FIG. 21.

[0050] FIG. 27 is a schematic diagram showing a part of a second driving circuit (133) according to one embodiment.

[0051] FIGS. 28 to 31 are schematic drawings illustrating the components of the second driving circuit (133) shown in FIG. 27 layer by layer.

[0052] FIG. 32 is a cross-sectional view taken along Ic-Ic', IIc-IIc', and IIIc-IIIc' of the second driving circuit (133) shown in FIG. 27.

[0053] FIG. 33 is a schematic diagram showing a part of the first driving circuit (131) according to one embodiment.

[0054] FIGS. 34 to 37 are schematic drawings illustrating the components of the second driving circuit (133) shown in FIG. 33 layer by layer.

[0055] FIG. 38 is a cross-sectional view taken along Id-Id', IId-IId', and IIId-IIId' of the first driving circuit (131) shown in FIG. 33.

[0056] FIG. 39 is a schematic diagram showing a fourth conductive layer according to one embodiment.

[0057] FIG. 40 is a schematic diagram showing a fifth conductive layer according to one embodiment.

[0058] FIG. 41 is a schematic perspective view of an electronic device including a display panel according to one embodiment.

[0059] FIG. 42 is a block diagram of an electronic device according to one embodiment.

[0060] FIGS. 43a to 43i are schematic perspective views illustrating embodiments of an electronic device including a display panel according to one embodiment of the present invention.

[0061] A display panel according to one embodiment of the present invention includes a non-display area defined with a plurality of island portions and a plurality of bridge portions connecting the island portions, and a driving circuit including a plurality of stages is provided in the non-display area, at least one of the plurality of stages is disposed in each of the plurality of island portions, and at least one signal line connected to the plurality of stages is disposed in the plurality of bridge portions, the plurality of bridge portions include first bridge portions extended along a first direction and second bridge portions extended along a second direction perpendicular to the first direction, the plurality of stages are disposed in a plurality of island portions arranged along the second direction, and the at least one signal line includes at least one first conductive line disposed in the first bridge portions and at least one second conductive line disposed in the second bridge portions, and the at least one second conductive line extends across the plurality of island portions.

[0062] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0063] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0064] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0065] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0066] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0067] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. Additionally, in this specification, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0068] In the following embodiments, when X and Y are described as being connected, the cases may include X and Y being electrically connected, X and Y being functionally connected, or X and Y being directly connected. Here, X and Y may be objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Accordingly, the connection relationships are not limited to a predetermined connection relationship, for example, one indicated in the drawings or detailed description, and may include connection relationships other than those indicated in the drawings or detailed description.

[0069] Cases where X and Y are electrically connected may include, for example, cases where one or more elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, etc.) are connected between X and Y.

[0070] In the following embodiments, "ON" used in association with the device state may refer to the activated state of the device, and "OFF" may refer to the deactivated state of the device. "ON" used in association with the signal received by the device may refer to a signal that activates the device, and "OFF" may refer to a signal that deactivates the device. The device may be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it should be understood that the "ON" voltage for the P-type transistor and the N-type transistor is an opposite (low vs. high) voltage level.

[0071] In the following embodiments, the x direction, y direction, and z direction are not limited to directions following the three axes of an orthogonal coordinate system, but can be interpreted in a broad sense that includes them. For example, the x direction, y direction, and z direction may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

[0072] Where any embodiment in this specification can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the order described.

[0073] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0074] FIG. 1 is a schematic perspective view of a display panel (1) according to an embodiment of the present invention. FIG. 2a and FIG. 2b are perspective views showing the display panel (1) of FIG. 1 extended in a first direction. FIG. 2c is a perspective view showing the display panel (1) of FIG. 1 extended in a second direction. FIG. 2d is a perspective view showing the display panel (1) of FIG. 1 extended in the first direction and the second direction. FIG. 2e is a perspective view showing the display panel (1) of FIG. 1 extended in a third direction.

[0075] Referring to FIG. 1, the display panel (1) may be a display panel of a stretchable display device that can be stretched or contracted in various directions. The display panel (1) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a plurality of pixels. The display panel (1) may provide a predetermined image using light emitted from a plurality of pixels. The non-display area (NDA) may be placed outside the display area (DA). The non-display area (NDA) may completely surround the display area (DA).

[0076] The display panel (1) can be extended in a first direction (e.g., x direction and / or -x direction) by an external force applied by an external object or a user. In one embodiment, as shown in FIGS. 2a and 2b, the display area (DA) and / or non-display area (NDA) of the display panel (1) can be extended in a first direction (e.g., x direction and / or -x direction). For example, as shown in FIG. 2a, the display panel (1) can be extended along the x direction and -x direction, or it can be extended in the x direction or -x direction while one side of the display panel (1) remains fixed. FIG. 2b illustrates an example where the display panel (1) is extended along the x direction while one side remains fixed.

[0077] The display panel (1) can be extended in a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a user. In one embodiment, as shown in FIG. 2c, the display area (DA) and / or non-display area (NDA) of the display panel (1) can be extended in the y direction and the -y direction. In another embodiment, one side of the display panel (1) can be extended in the y direction or the -y direction while remaining fixed.

[0078] The display panel (1) can be extended in multiple directions, for example, a first direction (e.g., x direction and / or -x direction) and a second direction (e.g., y direction and / or -y direction) by an external force applied by an external object or a part of a person's body. As shown in FIG. 2d, the display area (DA) and / or non-display area (NDA) of the display panel (1) can be extended in the ±x direction and ±y direction.

[0079] The display panel (1) can be extended in a third direction (e.g., z direction or -z direction) by an external force applied by an external object or a part of a person's body. In one embodiment, FIG. 2e illustrates a part of the display panel (1), such as a part of the display area (DA), protruding in the z direction. In another embodiment, a part of the display panel (1), such as a part of the display area (DA), may protrude along the -z direction (or be sunken along the z direction).

[0080] FIGS. 2a to 2e illustrate a display panel (1) extended in a first direction, a second direction, and / or a third direction, but the present invention is not limited thereto. In other embodiments, the display panel (1) may be deformed into various irregular shapes, such as having two or more axes, such as being bent or twisted.

[0081] FIG. 3 is a schematic plan view of a display panel (1) according to one embodiment.

[0082] A display panel (1) may include a substrate (100). A plurality of pixels (PX) may be arranged in a display area (DA) of the substrate (100). Each pixel (PX) may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor, and may be a pixel driving circuit that controls the driving of the light-emitting element. Each pixel (PX) may be connected to a gate line (GL) and a data line (DL).

[0083] A driving circuit for providing electrical signals to light-emitting elements placed in the display area (DA) and pixel circuits electrically connected to the light-emitting elements may be placed in the non-display area (NDA) surrounding the display area (DA). A gate driving circuit (GDC) may be placed in the first non-display area (NDA1) and the second non-display area (NDA2), respectively, which are placed on both sides of the display area (DA). The gate driving circuit (GDC) may be connected to gate lines (GL) placed in the display area (DA). FIG. 3 illustrates a gate driving circuit (GDC) placed in the first non-display area (NDA1) and the second non-display area (NDA2), respectively, but the present invention is not limited thereto. In another embodiment, the gate driving circuit (GDC) may be placed in either the first non-display area (NDA1) or the second non-display area (NDA2). Part or all of the gate driving circuit (GDC) can be formed directly in the non-display area (NDA) during the process of forming transistors that constitute the pixel circuit in the display area (DA).

[0084] The data driving circuit (DDC) may be placed in a third non-display area (NDA3) and / or a fourth non-display area (NDA4) connecting the first non-display area (NDA1) and the second non-display area (NDA2). In one embodiment, FIG. 3 illustrates the data driving circuit (DDC) being placed in the fourth non-display area (NDA4). In another embodiment, the data driving circuit (DDC) may be placed in each of the third non-display area (NDA3) and the fourth non-display area (NDA4).

[0085] The data driving circuit (DDC) may be formed as an integrated circuit chip. In one embodiment, the data driving circuit (DDC) may be placed directly in the fourth non-display area (NDA4) of the substrate (100) as shown in FIG. 3, using a COG (Chip On Glass) or COP (Chip On Plastic) method. In another embodiment, the display panel (1) may further include a flexible circuit board (not shown) electrically connected through a terminal portion (not shown) placed in the fourth non-display area (NDA4) of the substrate (100), and the data driving circuit (DDC) may be placed on the flexible circuit board.

[0086] The elongation of the non-display area (NDA) may be equal to or less than the elongation of the display area (DA). In one embodiment, the elongation of the non-display area (NDA) may differ from area to area. For example, the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3) may have substantially the same elongation, but the elongation of the fourth non-display area (NDA4) may be less than the elongation of each of the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3). In this specification, elongation refers to a numerical value representing the change in length (△L / L) by which the display panel (1) can be stretched without physical damage to the display panel (1) when an external force is applied to the display panel (1). Here, △L is the amount of change in length of the display panel, and L represents the initial length of the display panel.

[0087] FIG. 4 is a plan view of the IV portion of FIG. 3 as a part of a display panel (1) according to one embodiment.

[0088] Referring to FIG. 4, the display panel (1) may include first island sections (11) that are spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a display area (DA), and first bridge sections (12) that connect adjacent first island sections (11).

[0089] In one embodiment, at least one of the sides of the first island portion (11) may be inclined at a predetermined angle with respect to a first direction (e.g., x direction or -x direction) and / or a second direction (e.g., y direction or -y direction). For example, the first island portion (11) may include four sides, and each of the four sides may extend in a direction oblique to the first direction and / or the second direction.

[0090] The first island section (11) can be connected to a plurality of first bridge sections (12). For example, the first island section (11) can be connected to four first bridge sections (12). The four first bridge sections (12) can each be connected to four sides of the first island section (11). Two first bridge sections (12) can each be connected to two sides located opposite each other with the first island section (11) in between along the first direction (e.g., x direction or -x direction), and the remaining two first bridge sections (12) can each be connected to two sides located opposite each other with the first island section (11) in between along the second direction (e.g., y direction or -y direction).

[0091] The display panel (1) may include second island sections (21) that are spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a non-display area, for example, a first non-display area (NDA1) shown in FIG. 3, and second bridge sections (22) that connect adjacent second island sections (21).

[0092] In one embodiment, at least one of the sides of the second island portion (21) may be inclined at a predetermined angle with respect to a first direction (e.g., x direction or -x direction) and / or a second direction (e.g., y direction or -y direction). For example, the second island portion (21) may include four sides, and each of the four sides may extend in a direction oblique to the first direction and / or the second direction.

[0093] The second island section (21) can be connected to a plurality of second bridge sections (22). For example, the second island section (21) can be connected to four second bridge sections (22). The four second bridge sections (22) can each be connected to four sides of the second island section (21). Two second bridge sections (22) can each be connected to two sides located opposite each other with the second island section (21) in between along the first direction (e.g., x direction or -x direction), and the remaining two second bridge sections (22) can each be connected to two sides located opposite each other with the second island section (21) in between along the second direction (e.g., y direction or -y direction). The second bridge sections (22) can be spaced apart from each other by a second opening (CS2) located between the second bridge sections (22).

[0094] Any row of second island sections (21) placed in the first non-display area (NDA1) may correspond to at least one row of first island sections (11) arranged in the display area (DA). For example, any row of second island sections (21) placed in the first non-display area (NDA1) may correspond to first island sections (11) arranged in k rows (where k is a positive number greater than or equal to 2). FIG. 4 is an example in which any row of second island sections (21) placed in the first non-display area (NDA1) corresponds to first island sections (11) arranged in the (i)th row and first island sections (11) arranged in the (i+1)th row of the display area (DA) (where i is a positive number greater than 0).

[0095] Third island sections (31) and third bridge sections (32) may be arranged in a boundary area (BA) adjacent to the display area (DA) in the first non-display area (NDA1) to connect the first island section (11) of the display area (DA) and the second island section (21) of the first non-display area (NDA1). The third island section (31) may be connected to a plurality of third bridge sections (32). For example, the third island section (31) may be connected to five third bridge sections (32). One third bridge section (32) may be connected to one side of the second island section (21) and one side of the third island section (31) in the first direction, respectively. Two third bridge sections (32) may be connected to one side of the third island section (31) and one side of the first island section (11) in the first direction, respectively. Two third bridge sections (32) can be connected to two sides located opposite each other along the second direction with the third island section (31) in between. The third bridge sections (32) can be spaced apart from each other by an opening (CS3) located between the third bridge sections (32).

[0096] In one embodiment, the first island section (11), the second island section (21), and the third island section (31) may be polygonal, such as a square, pentagon, or hexagon, or circular or elliptical. The first bridge section (12), the second bridge section (22), and the third bridge section (23) may have a straight shape or a serpentine shape, a sine wave shape, an alphabet S shape, or a wavy shape.

[0097] In one embodiment, the size of the second island section (21) may be larger than the size of the first island section (11). The size of the third island section (31) may be equal to the size of the first island section (11), or larger than the size of the first island section (11) and smaller than the size of the second island section (21). The size and / or width of the second bridge section (22) may be larger than the size and / or width of the first bridge section (12). The size and / or width of the third bridge section (32) may be equal to the size and / or width of the second bridge section (22) or smaller than the size and / or width of the second bridge section (22).

[0098] FIG. 5a is a schematic cross-sectional view showing a first island section and a first bridge section placed in a display area according to one embodiment. FIG. 5b is a schematic cross-sectional view showing a second island section and a second bridge section placed in a non-display area according to one embodiment.

[0099] A light-emitting element and a pixel circuit (PC) electrically connected thereto may be disposed in the first island section (11). Conductive lines (WL1) electrically connected to pixel circuits (PCs) disposed in adjacent first island sections (11) may be disposed in the first bridge section (12). At least one stage circuit (STC) among a plurality of stages constituting a gate driving circuit (GDC) may be disposed in the second island section (21). Conductive lines (WL2) electrically connected to stage circuits (STCs) disposed in adjacent second island sections (21) may be disposed in the second bridge section (22).

[0100] In the first island portion (11), a barrier layer (110) containing an inorganic insulating material is disposed on the substrate (100), and a pixel circuit (PC) and an insulating layer (IL) containing an inorganic insulating material and / or an organic insulating material may be disposed on the barrier layer (110). A light-emitting element (LED) may be electrically connected to the corresponding pixel circuit (PC). In the second island portion (21), a barrier layer (110) containing an inorganic insulating material is disposed on the substrate (100), and a stage circuit (STC) and an insulating layer (IL) may be disposed on the barrier layer (110).

[0101] An insulating layer (IL) containing an organic insulating material may be disposed on the substrate (100) in the first bridge section (12) and the second bridge section (22). Unlike the first island section (11) and the second island section (21), the first bridge section (12) and the second bridge section (22), which undergo relatively more deformation when the display panel (1) is stretched, may not have a layer containing an inorganic insulating material that is prone to cracking.

[0102] In one embodiment, the substrate (100) corresponding to the first bridge portion (12) and the second bridge portion (22) may have the same stacked structure as the substrate (100) corresponding to the first island portion (11) and the second island portion (21). In one embodiment, the substrate (100) corresponding to the first bridge portion (12) and the second bridge portion (22) and the substrate (100) corresponding to the first island portion (11) and the second island portion (21) may be polymer resin layers formed together in the same process. In another embodiment, the substrate (100) corresponding to the first bridge portion (12) may have a different stacked structure from the substrate (100) corresponding to the first island portion (11) and the second island portion (21). In some embodiments, the substrate (100) corresponding to the first island portion (11) and the second island portion (21) has a multilayer structure including a base layer including a polymer resin and a barrier layer including an inorganic insulating material, and the substrate (100) corresponding to the first bridge portion (12) and the second bridge portion (22) may have a structure of a polymer resin layer without a layer including an inorganic insulating material.

[0103] The conductive lines (WL1) of the first bridge section (12) may be signal lines (e.g., gate lines, data lines, driving voltage lines, initialization voltage lines, voltage connection lines, etc.) connected to the pixel circuit (PC) of the first island section (11). The conductive lines (WL2) of the second bridge section (22) may be signal lines (e.g., clock lines, voltage lines, input lines, output lines, etc.) connected to the stage circuit (STC) of the second island section (21). An encapsulation layer (300) may also be disposed in the first bridge section (12) and the second bridge section (22). In another embodiment, the encapsulation layer (300) may not exist in the first bridge section (12) and the second bridge section (22).

[0104] The substrate (100), barrier layer (110), insulating layer (IL), and encapsulation layer (300) may each include areas corresponding to the first island portion (11) and the second island portion (21), areas corresponding to the first bridge portion (12) and the second bridge portion (22), and openings corresponding to the first opening (CS1) and the second opening (CS2). Each of the opening (100OP1) of the substrate (100), the opening (200OP1) of the barrier layer (111) and the insulating layer (IL), and the opening (300OP1) of the encapsulation layer (300) may overlap with the first opening (CS1) and the second opening (CS2) and have a shape similar to the first opening (CS1) and the second opening (CS2).

[0105] The encapsulation layer (300) may be placed on a light-emitting element (LED) and a stage. The encapsulation layer (300) may include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer (300) may include a structure in which an inorganic encapsulation layer containing an inorganic insulating material, an organic encapsulation layer containing an organic insulating material, and an inorganic encapsulation layer containing an inorganic insulating material are laminated. In other embodiments, the encapsulation layer (300) may include an organic material such as resin. In some embodiments, the encapsulation layer (300) may include urethane epoxy acrylate. The encapsulation layer (300) may include a photosensitive material, such as a photoresist.

[0106] FIGS. 6a and FIGS. 6b are equivalent circuit diagrams of a pixel according to one embodiment.

[0107] Referring to FIG. 6a, a pixel (PX) may include a light-emitting element (LED) and a pixel circuit (PC) connected to the light-emitting element (LED). The pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a capacitor (Cst).

[0108] The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines and data lines (DL), such as a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), and a light emission control line (EML). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2) and a driving voltage line (VDDL).

[0109] The driving voltage line (VDDL) may be a driving voltage line that transmits a first power supply voltage (VDD) to a first transistor (T1). The first initialization voltage line (VIL1) may transmit a first initialization voltage (Vint) that initializes the gate of the first transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) may transmit a second initialization voltage (Vaint) that initializes the first electrode of the light-emitting element (LED) to the pixel circuit (PC).

[0110] The first transistor (T1) can be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The first transistor (T1) acts as a driving transistor and receives a data signal (Dm) according to the switching operation of the second transistor (T2) and supplies a driving current to the light-emitting element (LED).

[0111] The second transistor (T2) is electrically connected to the data line (DL) and the first node (N1). The gate of the second transistor (T2) is electrically connected to the first scan line (SL1). The second transistor (T2) is turned on according to the first scan signal (GW) received through the first scan line (SL1) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0112] The third transistor (T3) is electrically connected to the gate of the first transistor (T1) and one terminal of the first transistor (T1). The gate of the third transistor (T3) is electrically connected to the first scan line (SL1). The third transistor (T3) is turned on according to the first scan signal (GW) received through the first scan line (SL1) and the first transistor (T1) is diode-connected, thereby compensating for the threshold voltage of the first transistor (T1).

[0113] The fourth transistor (T4) is electrically connected to the gate of the first transistor (T1) and the first initialization voltage line (VIL1). The gate of the fourth transistor (T4) is electrically connected to the second scan line (SL2). The fourth transistor (T4) is turned on according to the second scan signal (GI) received through the second scan line (SL2) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate of the first transistor (T1) to initialize the voltage of the gate of the first transistor (T1).

[0114] The fifth transistor (T5) is electrically connected to the driving voltage line (VDDL) and the first node (N1). The sixth transistor (T6) is electrically connected to one terminal of the first transistor (T1) and the light-emitting element (LED). The gate of the fifth transistor (T5) and the gate of the sixth transistor (T6) are electrically connected to the light-emitting control line (EML). The fifth transistor (T5) and the sixth transistor (T6) are simultaneously turned on according to the light-emitting control signal (EM) received through the light-emitting control line (EML), thereby forming a current path so that a driving current can flow from the driving voltage line (VDDL) toward the light-emitting element (LED).

[0115] The seventh transistor (T7) can be electrically connected to the first electrode of the light-emitting element (LED) and the second initialization voltage line (VIL2). The gate of the seventh transistor (T7) can be electrically connected to the third scan line (SL3). The seventh transistor (T7) is turned on according to the third scan signal (GB) received through the third scan line (SL3), and can initialize the first electrode of the light-emitting element (LED) by transmitting the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting element (LED).

[0116] The capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate of the first transistor (T1), and the second electrode (CE2) is electrically connected to the driving voltage line (VDDL). The capacitor (Cst) can maintain the voltage applied to the gate of the first transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages across the driving voltage line (VDDL) and the gate of the first transistor (T1).

[0117] Referring to FIG. 6b, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a first capacitor (Cst), and a second capacitor (Ca).

[0118] The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines and data lines (DL), such as a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), and a light emission control line (EML). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), a hold voltage line (VSL), and a drive voltage line (VDDL).

[0119] The driving voltage line (VDDL) can transmit a first power supply voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) to the pixel circuit (PC) to initialize the gate of the first transistor (T1). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) to the pixel circuit (PC) to initialize the first electrode of the light-emitting element (LED). The holding voltage line (VSL) can provide a holding voltage (VSUS) to the second node (N2), for example, the second electrode (CE2) of the first capacitor (Cst), during the initialization and data writing sections.

[0120] The first transistor (T1) can be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8), and can be electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The first transistor (T1) acts as a driving transistor and can receive a data signal (Dm) according to the switching operation of the second transistor (T2) and supply driving current to the light-emitting element (LED).

[0121] The second transistor (T2) is electrically connected to the data line (DL) and the first node (N1). The gate of the second transistor (T2) is electrically connected to the first scan line (SL1). The second transistor (T2) is turned on according to the first scan signal (GW) received through the first scan line (SL1) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0122] The third transistor (T3) is electrically connected to the gate of the first transistor (T1) and one terminal of the first transistor (T1). The gate of the third transistor (T3) is electrically connected to the first scan line (SL1). The third transistor (T3) is turned on according to the first scan signal (GW) received through the first scan line (SL1) and the first transistor (T1) is diode-connected, thereby compensating for the threshold voltage of the first transistor (T1).

[0123] The fourth transistor (T4) is electrically connected to the gate of the first transistor (T1) and the first initialization voltage line (VIL1). The gate of the fourth transistor (T4) is electrically connected to the second scan line (SL2). The fourth transistor (T4) is turned on according to the second scan signal (GI) received through the second scan line (SL2) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate of the first transistor (T1) to initialize the voltage of the gate of the first transistor (T1).

[0124] The fifth transistor (T5) is electrically connected to the second node (N2) and the first node (N1). The sixth transistor (T6) is electrically connected to one terminal of the first transistor (T1) and to the light-emitting element (LED). The eighth transistor (T8) is electrically connected to the driving voltage line (VDDL) and the second node (N2). The gate of the fifth transistor (T5), the gate of the sixth transistor (T6), and the gate of the eighth transistor (T8) are electrically connected to the light-emitting control line (EML). The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are simultaneously turned on according to the light-emitting control signal (EM) received through the light-emitting control line (EML), thereby forming a current path so that a driving current can flow from the driving voltage line (VDDL) toward the light-emitting element (LED).

[0125] The seventh transistor (T7) can be electrically connected to the first electrode of the light-emitting element (LED) and the second initialization voltage line (VIL2). The gate of the seventh transistor (T7) can be electrically connected to the second scan line (SL2). The seventh transistor (T7) is turned on according to the second scan signal (GB) received through the second scan line (SL2), and can initialize the first electrode of the light-emitting element (LED) by transmitting the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting element (LED).

[0126] The ninth transistor (T9) is electrically connected to the second node (N2) and the holding voltage line (VSL). The gate of the ninth transistor (T9) is electrically connected to the third scan line (SL3). The ninth transistor (T9) is turned on according to the third scan signal (GB) received through the third scan line (SL3), and can transmit the holding voltage (VSUS) to the second node (N2), for example, the second electrode (CE2) of the first capacitor (Cst), during the initialization period and the data writing period.

[0127] In some embodiments, the eighth transistor (T8) may be turned off and the ninth transistor (T9) may be turned on during the initialization and data writing sections, and the eighth transistor (T8) may be turned on and the ninth transistor (T9) may be turned off during the light emission section. Since the holding voltage (VSUS) is transmitted to the second node (N2) during the initialization and data writing sections, the uniformity of brightness of the display panel (e.g., LRU, Long Range Uniformity) due to the voltage drop of the driving voltage line (VDDL) can be improved.

[0128] The first capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate of the first transistor (T1), and the second electrode (CE2) is electrically connected to the eighth transistor (T8) and the ninth transistor (T9).

[0129] The second capacitor (Ca) is electrically connected to the first electrode of the light-emitting element (LED) and the holding voltage line (VSL). By storing and maintaining a voltage corresponding to the voltage difference between the first electrode of the light-emitting element (LED) and the holding voltage line (VSL) while the seventh transistor (T7) and the ninth transistor (T9) are turned on, the problem of the black brightness rising when the sixth transistor (T6) is turned off can be prevented.

[0130] FIG. 7a is a cross-sectional view schematically showing a light-emitting element of a display panel according to one embodiment.

[0131] Referring to FIG. 7a, a light-emitting element according to one embodiment may include an organic light-emitting diode (220) containing an organic material. The organic light-emitting diode (220) may include a first electrode (221) disposed on an insulating layer (IL), a second electrode (225) facing the first electrode (221), and a light-emitting layer (223) interposed between the first electrode (221) and the second electrode (225). A first functional layer (222) may be disposed between the first electrode (221) and the light-emitting layer (223), and a second functional layer (224) may be disposed between the light-emitting layer (223) and the second electrode (225). The first electrode (221) may be connected to a pixel circuit (PC).

[0132] The edge of the first electrode (221) may be covered with a bank layer (BKL) containing an insulating material. The bank layer (BKL) may include an opening (B-OP) that overlaps a part of the first electrode (221).

[0133] The first electrode (221) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first electrode (221) may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the first electrode (221) may further include a layer formed of ITO, IZO, ZnO, AZO, or In2O3 above and below the aforementioned reflective layer.

[0134] The light-emitting layer (223) may include a polymer or low-molecular-weight organic material that emits light of a predetermined color. The first functional layer (222) may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer (224) may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0135] The second electrode (225) may be made of a conductive material with a low work function. For example, the second electrode (225) may include a (semi)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the second electrode (225) may further include a layer such as ITO, IZO, ZnO, AZO, or In2O3 on the (semi)transparent layer comprising the aforementioned materials.

[0136] FIG. 7b is a cross-sectional view schematically showing a light-emitting element of a display panel according to one embodiment.

[0137] Referring to FIG. 7b, a light-emitting element according to one embodiment may include an inorganic light-emitting diode (230) comprising an inorganic material. The inorganic light-emitting diode (230) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), a first electrode (235) electrically connected to the first semiconductor layer (231), and a second electrode (238) electrically connected to the second semiconductor layer (232). The first electrode (235) and the second electrode (238) of the inorganic light-emitting diode (230) may each be electrically connected to a first electrode pad (241) and a second electrode pad (242) disposed on the same layer. The first electrode pad (241) may be connected to a pixel circuit (PC).

[0138] In some embodiments, the first semiconductor layer (231) may include a p-type semiconductor layer. The p-type semiconductor layer is In x Al y Ga1 -x- y A semiconductor material having the composition formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) can be selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and p-type dopants such as Mg, Zn, Ca, Sr, and Ba can be doped.

[0139] The second semiconductor layer (232) may include, for example, an n-type semiconductor layer. The n-type semiconductor layer is In x Al y Ga1 -x- y A semiconductor material having the composition formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) can be selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and can be doped with n-type dopants such as Si, Ge, and Sn.

[0140] The intermediate layer (233) is a region where electrons and holes recombine, and as electrons and holes recombine, they transition to a lower energy level and can generate light having a corresponding wavelength. The intermediate layer (233) is, for example, In x Al y Ga1 -x- y It can be formed by including a semiconductor material having a composition formula of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multi-quantum well (MQW) structure. In addition, it may include a quantum wire structure or a quantum dot structure.

[0141] FIG. 8 is a schematic diagram showing a display panel according to one embodiment. FIG. 9 is a schematic diagram showing a gate driving circuit according to one embodiment. FIG. 10 is a schematic diagram showing any stages constituting a gate driving circuit according to one embodiment.

[0142] In one embodiment, the gate driving circuit (130) and the data driving circuit (150) shown in FIG. 8 may correspond to the gate driving circuit (GDC) and the data driving circuit (DDC) of FIG. 3, respectively. Below, a detailed description of the configuration that overlaps with the display panel shown in FIG. 1 and FIG. 3 is omitted.

[0143] Referring to FIG. 8, the gate driving circuit (130) may include a first gate driving circuit (130L) positioned to the left of the display area (DA) and a second gate driving circuit (130R) positioned to the right of the display area (DA). The first gate driving circuit (130L) and the second gate driving circuit (130R) may each include a first driving circuit (131), a second driving circuit (133), a third driving circuit (135), and a fourth driving circuit (137).

[0144] The first driving circuit (131) is connected to a plurality of first scan lines (SL1) and can sequentially supply a first scan signal (GW) to the first scan lines (SL1) according to a first driving control signal (GCS1). The second driving circuit (133) is connected to a plurality of second scan lines (SL2) and can sequentially supply a second scan signal (GI) to the second scan lines (SL2) according to a second driving control signal (GCS2). The third driving circuit (135) is connected to a plurality of third gate lines (SL2) and can sequentially supply a third gate signal (GB) to the third gate lines (SL3) according to a third driving control signal (GCS3). The fourth driving circuit (137) is connected to a plurality of light-emitting control lines (EML) and can sequentially supply a light-emitting control signal (EM) to the light-emitting control lines (EML) according to the fourth driving control signal (GCS4).

[0145] The data driving circuit (150) is connected to a plurality of data lines (DL) and can apply a data signal (Dm) representing a grayscale to the data lines (DL) according to the fifth driving control signal (DCS). The data driving circuit (150) can convert input image data having a grayscale input from the controller (190) into a data signal (Dm) in the form of voltage or current.

[0146] The power supply circuit (170) can generate voltages required for driving the pixel (PX) according to the sixth control signal (PCS). For example, the power supply circuit (170) can transmit each of the first power voltage (VDD), the second power voltage (VSS), the first initialization voltage (Vint), the second initialization voltage (Vaint), and the hold voltage (VSUS) to the display area (DA) through the global voltage line of the non-display area.

[0147] The power supply circuit (170) generates a first voltage (VGH) and a second voltage (VGL) required for driving the gate driving circuit (130) and can be delivered to the gate driving circuit (130). The first voltage (VGH) may be a higher voltage than the second voltage (VGL).

[0148] Referring to FIG. 9, each of the first driving circuit (131), the second driving circuit (133), the third driving circuit (135), and the fourth driving circuit (137) includes a plurality of stages (ST), and each stage (ST) may be connected to at least one clock line (CKL) that transmits at least one clock signal and at least one voltage line (VPL) that transmits at least one voltage signal (e.g., a first voltage (VGH) and a second voltage (VGL)). Each stage (ST) may receive a start signal and output a gate signal (GS). The start signal may be an external start signal and a carry signal (CR) output by a previous or subsequent stage. The gate signal (GS) may be a first to third scan signal (GW, GI, GB) and a light emission control signal (EM).

[0149] As illustrated in FIG. 10, a plurality of stages (ST) may include odd-numbered stages (STo) and even-numbered stages (STe). Each of the odd-numbered stages (STo) and even-numbered stages (STe) includes a stage circuit (STC), and the stage circuit (STC) may be connected to at least one voltage line (VPL) and at least one clock line (CKLo, CKLe). The stage circuit (STC) may be connected to a first signal line (SS1) that transmits a first signal and a second signal line (SS2) that transmits a second signal. In one embodiment, the first signal and the second signal may be a constant voltage signal of a first voltage level or a second voltage level, or a clock signal in which the first voltage level and the second voltage level swing alternately. In one embodiment, the first voltage level may be a high voltage level and the second voltage level may be a low voltage level.

[0150] FIG. 11 is a schematic diagram showing any stage of a first driving circuit (131) or a second driving circuit (133) according to one embodiment. FIG. 11 may be a stage of the first driving circuit (131) (hereinafter referred to as the first stage) or a stage of the second driving circuit (133) (hereinafter referred to as the second stage). The stage circuit (STC_GW) of the first stage is identical to the stage circuit (STC_GI) of the second stage.

[0151] Referring to FIG. 11, the stage circuit (STC_GW / STC_GI) may include first to eighth transistors (T1 to T8) and first and second capacitors (C1 and C2). In one embodiment, a first clock signal (GW / GI_CLK1) may be input to the first transistor (T1) of the odd-numbered stage circuit (STC_GW / C_GI), and a second clock signal (GW / GI_CLK2) may be input to the third transistor (T3) and the seventh transistor (T7). A second clock signal (GW / GI_CLK2) can be input to the first transistor (T1) of an even-numbered stage circuit (STC_GW / STC_GI), and a first clock signal (GW / GI_CLK1) can be input to the third transistor (T3) and the seventh transistor (T7). FIG. 11 is an example of an odd-numbered stage circuit (STC_GW / STC_GI).

[0152] The first transistor (T1) may include two subtransistors connected in series. When the first transistor (T1) is turned on by a first clock signal (GW / GI_CLK1) input to the gate, it can transmit a start signal (e.g., a carry signal) (GW / GI_CR) to the node (QF).

[0153] The second transistor (T2) can be turned on when the voltage of the node (QB) connected to the gate is at a low level, and the third transistor (T3) can be turned on when the second clock signal (GW / GI_CLK2) input to the gate is at a low level. When the second transistor (T2) and the third transistor (T3) are turned on, the first voltage (VGH) can be transmitted to the node (QF). Accordingly, when the voltage of the node (QB) is at a low level, the voltage of the node (QF) can be at a high level.

[0154] The fourth transistor (T4) is turned on when the voltage of the node (QF) connected to the gate is at a low level, and can transmit the high-level voltage of the first clock signal (GW / GI_CLK1) to the node (QB). Accordingly, when the voltage of the node (QF) is at a low level, the voltage of the node (QB) can be at a high level.

[0155] The fifth transistor (T5) can be turned on when the first clock signal (GW / GI_CLK1) input to the gate is at a low level, thereby transmitting the second voltage (VGL) to the node (QB). Accordingly, when the voltage of the node (QF) is at a high level, the voltage of the node (QB) can be at a low level.

[0156] The sixth transistor (T6) is turned on when the voltage of the node (QB) is at a low level, and the first voltage (VGH) can be output to the output line as an output signal (first scan signal (GW) or second scan signal (GI)) by the turned-on sixth transistor (T6).

[0157] The seventh transistor (T7) is turned on when the voltage of node (Q) is at a low level, and the low-level voltage of the second clock signal (GW / GI_CLK2) can be output to the output line as an output signal (first scan signal (GW) or second scan signal (GI)) by the turned-on seventh transistor (T7).

[0158] The eighth transistor (T8) receives the second voltage (VGL) as input to its gate and turns on, allowing it to electrically connect the nodes (QF and Q).

[0159] The first capacitor (C1) can store the voltage difference between the terminal to which the first voltage (VGH) is input and the terminal connected to the node (QB). The second capacitor (C2) can store the voltage difference between the terminal connected to the output line and the terminal connected to the node (Q). Due to the coupling effect of the second capacitor (C2), the voltage of the node (Q) and / or the node (QF) can fluctuate according to the voltage fluctuation of the terminal connected to the output line.

[0160] FIG. 12 is a schematic diagram showing any stage of a third driving circuit (135) according to one embodiment.

[0161] Referring to FIG. 12, the stage circuit (STC_GB) may include first to thirteenth transistors (T1 to T16) and first to fourth capacitors (C1 to C4). The fourth capacitor (C4) may be omitted.

[0162] In one embodiment, a first clock signal (GB_CLK1) may be input to the first transistor (T1) of the odd-numbered stage circuit (STC_GB), and a second clock signal (GB_CLK2) may be input to the third transistor (T3) and the seventh transistor (T7). A second clock signal (GB_CLK2) may be input to the first transistor (T1) of the even-numbered stage circuit (STC_GB), and a first clock signal (GB_CLK1) may be input to the third transistor (T3) and the seventh transistor (T7). FIG. 12 is an example of an odd-numbered stage circuit (STC_GB).

[0163] The first transistor (T1) is turned on when the first clock signal (GB_CLK1) input to the gate is at a low level, and can transmit a start signal (e.g., a carry signal) (GB_CR) to the node (QF1).

[0164] The second transistor (T2) can be turned on when the voltage of the node to which the gate is connected is at a low level. The third transistor (T3) can be turned on when the voltage of the node (QF2) to which the gate is connected is at a low level. The fourth transistor (T4) may include two sub-transistors connected in series. When the fourth transistor (T4) is turned on when the voltage of the node (QF1) to which the gate is connected is at a low level, it can transmit the first clock signal (GB_CLK1) to the gate of the second transistor (T2).

[0165] The fifth transistor (T5) is turned on when the first clock signal (GB_CLK1) input to the gate is at a low level and can transmit the second voltage (VGL) to the gate of the second transistor (T2).

[0166] The sixth transistor (T6) can be turned on when the second clock signal (GB_CLK2) input to the gate is at a low level. The seventh transistor (T7) is turned on when the node to which the gate is connected is at a low level and can transmit the second clock signal (GB_CLK2) to one terminal of the second capacitor (C2). The gate of the seventh transistor (T7) can be connected to the other terminal of the second capacitor (C2).

[0167] The eighth transistor (T8) can be turned on when the voltage of the node (QF1) connected to the gate is at a low level to transmit the first voltage (VGH) to the node (QB).

[0168] The ninth transistor (T9) is turned on when the voltage of the node (QB) connected to the gate is at a low level, and the first voltage (VGH) can be output to the output line as an output signal (third scan signal (GB)).

[0169] The 10th transistor (T10) is turned on when the voltage of the node (Q) connected to the gate is at a low level, and the second voltage (VGL) can be output to the output line as an output signal (third scan signal (GB)).

[0170] A second voltage (VGL) is input to the gate of the 11th transistor (T11), and the node to which the gate of the 2nd transistor (T2) is connected and the node to which the gate of the 7th transistor (T7) is connected can be electrically connected by the turned-on 11th transistor (T11).

[0171] A second voltage (VGL) is input to the gate of the 12th transistor (T12), and the node (QF1) and the node (Q) can be electrically connected by the turned-on 12th transistor (T12).

[0172] The 13th transistor (T13) is turned on when a low-level reset signal (ESR) is applied, and the node (QF1) becomes a high-level state by the first voltage (VGH), so that the 10th transistor (T10) can remain turned off.

[0173] The 14th transistor (T14) is turned on when the voltage of the node (QF2) connected to the gate is at a low level, so that the node (QF2) and the node (Q) can be electrically connected.

[0174] The 15th transistor (T15) can be turned on when the first clock signal (GB_CLK1) input to the gate is at a low level to transmit a start signal (GB_CR). A second voltage (VGL) is input to the gate of the 16th transistor (T16), and the start signal (GB_CR) transmitted by the 15th transistor (T15) can be transmitted to the node (QF2) by the turned-on 16th transistor (T16).

[0175] The 14th transistor (T14), the 15th transistor (T15), the 16th transistor (T16), and the 3rd capacitor (C3) can boost the start signal (GB_CR) at node (QF2) and transmit it to node (Q).

[0176] The first capacitor (C1) can store the voltage difference between the terminal where the first voltage (VGH) is input and the terminal connected to the node (QB). The second capacitor (C2) can store the voltage difference between the gate of the seventh transistor (T7) and one terminal. The third capacitor (C3) can store the voltage difference between the gate of the third transistor (T3) and one terminal. The fourth capacitor (C4) can store the voltage difference between the terminal connected to the output line and the terminal connected to the node (Q).

[0177] FIG. 13 is a schematic diagram showing any stage of the fourth driving circuit (137) according to one embodiment.

[0178] Referring to FIG. 13, the stage circuit (STC_EM) may include first to thirteen transistors (T1 to T13) and first to third capacitors (C1 to C3).

[0179] In one embodiment, a first clock signal (EM_CLK1) may be input to the first transistor (T1) of the odd-numbered stage circuit (STC_EM), and a second clock signal (EM_CLK2) may be input to the third transistor (T3), the sixth transistor (T6), and the seventh transistor (T7). A second clock signal (EM_CLK2) may be input to the first transistor (T1) of the even-numbered stage circuit (STC_GB), and a first clock signal (EM_CLK1) may be input to the third transistor (T3), the sixth transistor (T6), and the seventh transistor (T7). FIG. 13 is an example of an odd-numbered stage circuit (STC_EM).

[0180] In the stage circuit (STC_EM) of Fig. 13, the 14th to 16th transistors (T14 to T16) and the 4th capacitor (C4) are omitted from the stage circuit (STC_GB) of Fig. 12, and the connections of some components differ from those of the stage circuit (STC_GB) of Fig. 12.

[0181] The first transistor (T1) is turned on when the first clock signal (EM_CLK1) input to the gate is at a low level, and can transmit a start signal (e.g., a carry signal) (EM_CR) to the node (QF).

[0182] The second transistor (T2) can be turned on when the voltage of the node to which the gate is connected is at a low level. The third transistor (T3) can be turned on when the voltage of the node (Q) to which the gate is connected is at a low level. The fourth transistor (T4) may include two sub-transistors connected in series. When the fourth transistor (T4) is turned on when the voltage of the node (QF1) to which the gate is connected is at a low level, it can transmit the first clock signal (EM_CLK1) to the gate of the second transistor (T2).

[0183] The fifth transistor (T5) is turned on when the first clock signal (EM_CLK1) input to the gate is at a low level and can transmit the second voltage (VGL) to the gate of the second transistor (T2).

[0184] The sixth transistor (T6) can be turned on when the second clock signal (EM_CLK2) input to the gate is at a low level. The seventh transistor (T7) is turned on when the node to which the gate is connected is at a low level and can transmit the second clock signal (EM_CLK2) to one terminal of the second capacitor (C2). The gate of the seventh transistor (T7) can be connected to the other terminal of the second capacitor (C2).

[0185] The eighth transistor (T8) can be turned on when the voltage of the node (QF) connected to the gate is at a low level and can transmit the first voltage (VGH) to the node (QB).

[0186] The ninth transistor (T9) is turned on when the voltage of the node (QB) connected to the gate is at a low level, and the first voltage (VGH) can be output to the output line as an output signal (light emission control signal (EM)).

[0187] The 10th transistor (T10) is turned on when the voltage of the node (Q) connected to the gate is at a low level, and the second voltage (VGL) can be output to the output line as an output signal (light emission control signal (EM)).

[0188] A second voltage (VGL) is input to the gate of the 11th transistor (T11), and the node to which the gate of the 2nd transistor (T2) is connected and the node to which the gate of the 7th transistor (T7) is connected can be electrically connected by the turned-on 11th transistor (T11).

[0189] A second voltage (VGL) is input to the gate of the 12th transistor (T12), and the node (QF) and the node (Q) can be electrically connected by the turned-on 12th transistor (T12).

[0190] The 13th transistor (T13) is turned on when a low-level reset signal (ESR) is applied, and the node (QF) becomes a high-level state by the first voltage (VGH), so that the 10th transistor (T10) can remain turned off.

[0191] The first capacitor (C1) can store the voltage difference between the terminal where the first voltage (VGH) is input and the terminal connected to the node (QB). The second capacitor (C2) can store the voltage difference between the gate of the seventh transistor (T7) and one terminal. The third capacitor (C3) can store the voltage difference between the gate of the third transistor (T3) and one terminal.

[0192] FIG. 14 is a schematic plan view showing a part of a gate driving circuit (130) according to one embodiment.

[0193] The gate driving circuit (130) may be placed in the first non-display area (NDA1, FIG. 3) and / or the second non-display area (NDA2, FIG. 3). Referring to FIG. 14, the gate driving circuit (130) may include a first driving circuit (131), a second driving circuit (133), a third driving circuit (135), and a fourth driving circuit (137). The first driving circuit (131) may be placed closest to the display area (DA), and the fourth driving circuit (137) may be placed furthest from the display area (DA). The first driving circuit (131) may be placed in the first row, the second driving circuit (133) may be placed in the second row adjacent to the first row, the third driving circuit (135) may be placed in the third row adjacent to the second row, and the fourth driving circuit (137) may be placed in the fourth row adjacent to the third row. FIG. 14 illustrates the stage of the first driving circuit (131) (hereinafter, the first stage), the stage of the second driving circuit (133) (hereinafter, the second stage), the stage of the third driving circuit (135) (hereinafter, the third stage), and the stage of the fourth driving circuit (137) (hereinafter, the fourth stage) placed in any row.

[0194] In each of the first to fourth rows, a plurality of second island sections (21) and a plurality of second bridge sections (22) connecting the second island sections (21) may be arranged. The second bridge sections (22) may include horizontal bridge sections (22h) extended in a first direction and vertical bridge sections (22v) extended in a second direction. At least one horizontal conductor extending in the first direction may be arranged in the horizontal bridge section (22h). At least one vertical conductor extending in the second direction may be arranged in the vertical bridge section (22v). In a planar manner, at least one horizontal conductor and at least one vertical conductor may extend across the second island section (21). At least one horizontal conductor and at least one vertical conductor may extend with a curve according to the shape of the horizontal bridge section (22h) and the vertical bridge section (22v).

[0195] Hereinafter, for convenience of explanation, the horizontal bridge sections (22h) arranged in each row are referred to as the first horizontal bridge section (22h1), the second horizontal bridge section (22h2), the third horizontal bridge section (22h3), and the fourth horizontal bridge section (22h4) in the direction toward the display area (DA) along the first direction.

[0196] FIG. 15 is a schematic diagram showing a part of a fourth driving circuit (137) according to one embodiment. FIGS. 16 to 19 are schematic diagrams showing the components of the fourth driving circuit (137) shown in FIG. 15 layer by layer. FIG. 20 is a cross-sectional view taken along Ia-Ia', IIa-IIa', and IIIa-IIIa' of the fourth driving circuit (137) shown in FIG. 15.

[0197] The fourth stage of the fourth driving circuit (137) may be placed in the second island section (21) of the fourth column. FIG. 15 illustrates the odd-numbered stage (STo) and the even-numbered stage (STe) adjacent to the second direction of the fourth driving circuit (137). Referring to FIG. 15, the odd-numbered stage (STo) may be placed in the second island section (21o) of the odd-numbered row (hereinafter, the odd-numbered second island section (21o)), and the even-numbered stage (STe) may be placed in the second island section (21e) of the even-numbered row (hereinafter, the even-numbered second island section (21e)).

[0198] Referring to FIG. 16, a semiconductor layer (ACT), a first conductive layer (CDL1), and a second conductive layer (CDL2) may be sequentially disposed on the second island portion (21). A barrier layer (110, FIG. 20) may be disposed between the substrate (100, FIG. 20) and the semiconductor layer (ACT). The semiconductor layer (ACT) may include a silicon semiconductor. The semiconductor layer (ACT) may include a channel region, source regions on both sides of the channel region, and drain regions for each of the first to thirteenth transistors (T1 to T13) (Fig. 13). Depending on the case, the source region or drain region may be interpreted as the source electrode or drain electrode of the transistor.

[0199] A first insulating layer (111, FIG. 20) may be disposed over a semiconductor layer (ACT) on a barrier layer (110), and a first conductive layer (CDL1) may be disposed on the first insulating layer (111). The first conductive layer (CDL1) may include the gate electrodes of each of the first to thirteenth transistors (T1 to T13) and the lower electrodes of each of the first to third capacitors (C1 to C3) (Fig. 13). The gate electrodes may overlap the channel regions of the semiconductor layer (ACT).

[0200] A second insulating layer (112, FIG. 20) may be disposed over the first conductive layer (CDL1) on the first insulating layer (111), and a second conductive layer (CDL2) may be disposed on the second insulating layer (112). The second conductive layer (CDL2) may include the upper electrode of each of the first to third capacitors (C1 to C3). The upper electrode of each of the first to third capacitors (C1 to C3) may overlap with the lower electrode of each of the first to third capacitors (C1 to C3).

[0201] A second conductive layer (CDL2) is placed over the second insulating layer (112), and a third insulating layer (113, FIG. 20) is disposed thereon, and contact holes may be formed in the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113).

[0202] Subsequently, the area outside the region corresponding to the second island portion (21) in the barrier layer (110), the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) is removed, so that an opening corresponding to the area outside the region corresponding to the second island portion (21) can be defined in the barrier layer (110), the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113). That is, the barrier layer (110), the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) are not placed in the second bridge portions (22) but can be placed in the second island portion (21). The barrier layer (110), the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may have an island shape corresponding to the second island portion (21).

[0203] A fourth insulating layer (114) may be disposed in an area other than the region corresponding to the second island portion (21) of the substrate (100). That is, the fourth insulating layer (114) may not be disposed in the second island portion (21) but may be disposed in the second bridge portion (22).

[0204] Referring to FIG. 17, a third conductive layer may be disposed on the third insulating layer (113) of the second island section (21) and the fourth insulating layer (114) of the second bridge section (22). The third conductive layer may include a first clock connection line (EM_CKCL11), a second clock connection line (EM_CKCL21), source electrodes and drain electrodes, a carry line (EM_CRL) through which a start signal or previous carry signal is transmitted, a reset line (EM_ESRL) through which a reset signal is transmitted, and an output line (hereinafter, the fourth output line) (EM_OL) through which a light emission control signal (EM) is output.

[0205] A first clock connection line (EM_CKCL11) and a second clock connection line (EM_CKCL21) may be placed in the second island section (21). The first clock connection line (EM_CKCL11) placed in the odd-numbered second island section (210) is connected to the gate electrode of the first transistor (T1), and the second clock connection line (EM_CKCL21) may be connected to one of the source electrode and drain electrode of the third transistor (T3), the gate electrode of the sixth transistor (T6), and one of the source electrode and drain electrode of the seventh transistor (T7). The first clock connection line (EM_CKCL11) placed in the even-numbered second island section (21e) is connected to one of the source electrode and drain electrode of the third transistor (T3), the gate electrode of the sixth transistor (T6), and one of the source electrode and drain electrode of the seventh transistor (T7), and the second clock connection line (EM_CKCL21) can be connected to the gate electrode of the first transistor (T1).

[0206] Source electrodes and drain electrodes may be placed in the second island section (21). Each of the source electrodes may be connected to a corresponding source region of the semiconductor layer (ACT), and each of the drain electrodes may be connected to a corresponding drain region of the semiconductor layer (ACT).

[0207] A fourth output line (EM_OL) may be disposed in the first horizontal bridge section (22h1), and a carry line (EM_CRL) and a reset line (EM_ESRL) may be disposed spaced apart in the vertical bridge section (22v). The fourth output line (EM_OL) may extend from one of the source electrode and drain electrode of the ninth transistor (T9) and one of the source electrode and drain electrode of the tenth transistor (T10). The carry line (EM_CRL) may be connected to one of the source electrode and drain electrode of the first transistor (T1). The reset line (EM_ESRL) may be connected to the gate electrode of the thirteenth transistor (T13).

[0208] A fifth insulating layer (115, FIG. 20) may be disposed on the third insulating layer (113) of the second island portion (21) and the fourth insulating layer (114) of the second bridge portion (22), covering the third conductive layer. Contact holes may be formed in the fifth insulating layer (115).

[0209] Referring to FIG. 18, a fourth conductive layer may be disposed on the fifth insulating layer (115). The fourth conductive layer may include a first clock connection electrode (EM_CKCL12), a second clock connection electrode (EM_CKCL22), a reset connection line (ESRCL), a first voltage line (VGHL) through which a first voltage (VGH) is transmitted, and a second voltage line (VGLL) through which a second voltage (VGL) is transmitted.

[0210] A first clock connection electrode (EM_CKCL12), a second clock connection electrode (EM_CKCL22), and a reset connection line (ESRCL) may be placed in the second island section (21). The first clock connection electrode (EM_CKCL12) may be connected to the first clock connection line (EM_CKCL11), and the second clock connection electrode (EM_CKCL22) may be connected to the second clock connection line (EM_CKCL21). The reset connection line (ESRCL) may connect the reset lines (EM_ESRL) placed in the vertical bridge sections (22v) arranged in the second direction with the second island section (21) in between.

[0211] A first voltage line (VGHL) and a second voltage line (VGLL) are arranged in a vertical bridge section (22v), and the first voltage line (VGHL) and the second voltage line (VGLL) can be extended across a second island section (21). In the second island section (21), the first voltage line (VGHL) can be connected to one of the source electrode and drain electrode of the second transistor (T2), one of the source electrode and drain electrode of the eighth transistor (T8), one of the source electrode and drain electrode of the ninth transistor (T9), one of the source electrode and drain electrode of the thirteenth transistor (T13), and one electrode of the first capacitor (C1). The second voltage line (VGLL) can be connected to one of the source electrode and drain electrode of the fifth transistor (T5), one of the source electrode and drain electrode of the tenth transistor (T10), and the gate electrode of the twelfth transistor (T12).

[0212] Referring to FIG. 19, a sixth insulating layer (116, FIG. 20) may be disposed on the fifth insulating layer (115), covering the fourth conductive layer. Contact holes may be formed in the sixth insulating layer (116). A fifth conductive layer may be disposed on the sixth insulating layer (116). The fifth conductive layer may include a first clock line (EM_CKL1) and a second clock line (EM_CKL2).

[0213] A first clock line (EM_CKL1) and a second clock line (EM_CKL2) may be placed in the vertical bridge section (22v). The first clock line (EM_CKL1) and the second clock line (EM_CKL2) may extend across the second island section (21). In the second island section (21), the first clock line (EM_CKL1) may be connected to the first clock connection electrode (EM_CKCL12), and the second clock line (EM_CKL2) may be connected to the second clock connection electrode (EM_CKCL22).

[0214] A seventh insulating layer (117, FIG. 20) may be disposed on the sixth insulating layer (116), covering the fifth conductive layer.

[0215] As shown in FIG. 20, in the vertical bridge section (22v), the first voltage line (VGHL) can be superimposed on the reset line (EM_ESRL), and the second voltage line (VGLL) can be superimposed on the carry line (EM_CRL). The first clock line (EM_CKL1) can be superimposed on the second voltage line (VGLL), and the second clock line (EM_CKL2) can be superimposed on the first voltage line (VGHL).

[0216] FIG. 20 illustrates the semiconductor layer (51), gate electrode (53), source electrode and drain electrode (55, 57) of the 10th transistor (T10) placed in the 2nd island section (21), and the lower electrode (CE1) and upper electrode (CE2) of the 3rd capacitor (C3).

[0217] FIG. 21 is a schematic diagram showing a part of a third driving circuit (135) according to one embodiment. FIGS. 22 to 25 are schematic diagrams showing the components of the third driving circuit (135) shown in FIG. 21 layer by layer. FIG. 26 is a cross-sectional view taken along Ib-Ib', IIb-IIb', and IIIb-IIIb' of the third driving circuit (135) shown in FIG. 21.

[0218] The third stage of the third driving circuit (135) may be placed in the second island section (21) of the third row. FIG. 21 illustrates the odd-numbered stage (STo) and the even-numbered stage (STe) adjacent to the second direction of the third driving circuit (135). Referring to FIG. 21, the odd-numbered stage (STo) may be placed in the odd-numbered second island section (21o), and the even-numbered stage (STe) may be placed in the even-numbered second island section (21e).

[0219] Referring to FIG. 22, a semiconductor layer (ACT), a first conductive layer (CDL1), and a second conductive layer (CDL2) may be sequentially disposed on the second island portion (21). A barrier layer (110, FIG. 26) may be disposed between the substrate (100, FIG. 26) and the semiconductor layer (ACT). The semiconductor layer (ACT) may include a silicon semiconductor. The semiconductor layer (ACT) may include a channel region, source regions on both sides of the channel region, and drain regions for each of the first to sixteenth transistors (T1 to T16) (Fig. 12). Depending on the case, the source region or drain region may be interpreted as the source electrode or drain electrode of the transistor.

[0220] A first insulating layer (111, FIG. 26) may be disposed over a semiconductor layer (ACT) on a barrier layer (110), and a first conductive layer (CDL1) may be disposed on the first insulating layer (111). The first conductive layer (CDL1) may include the gate electrodes of each of the first to 16 transistors (T1 to T16) and the lower electrodes of each of the first to 3 capacitors (C1 to C3) (Fig. 12). The gate electrodes may overlap the channel regions of the semiconductor layer (ACT).

[0221] A second insulating layer (112, FIG. 26) may be disposed over the first insulating layer (111) while covering the first conductive layer (CDL1), and a second conductive layer (CDL2) may be disposed over the second insulating layer (112). The second conductive layer (CDL2) may include the upper electrode of each of the first to third capacitors (C1 to C3). The upper electrode of each of the first to third capacitors (C1 to C3) may overlap with the lower electrode of each of the first to third capacitors (C1 to C3).

[0222] A second conductive layer (CDL2) is placed over the second insulating layer (112), and a third insulating layer (113, FIG. 26) is disposed thereon, and contact holes may be formed in the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113).

[0223] Subsequently, as described with reference to FIG. 17, the area other than the region corresponding to the second island portion (21) in the barrier layer (110), the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may be removed. A fourth insulating layer (114) may be disposed in the area other than the region corresponding to the second island portion (21) of the substrate (100).

[0224] Referring to FIG. 23, a third conductive layer may be disposed on the third insulating layer (113) of the second island section (21) and the fourth insulating layer (114) of the second bridge section (22). The third conductive layer may include a first clock connection line (GB_CKCL11), a second clock connection line (GB_CKCL21), source electrodes and drain electrodes, a carry line (GB_CRL) through which a start signal or previous carry signal is transmitted, a reset line (GB_ESRL) through which a reset signal is transmitted, and an output line (hereinafter referred to as the third output line) (GB_OL) through which a third scan signal (GB) is output.

[0225] A first clock connection line (GB_CKCL11) and a second clock connection line (GB_CKCL21) may be placed in the second island section (21). The first clock connection line (GB_CKCL11) placed in the odd-numbered second island section (210) is connected to the gate electrode of the first transistor (T1), and the second clock connection line (GB_CKCL21) may be connected to one of the source electrode and drain electrode of the third transistor (T3), the gate electrode of the sixth transistor (T6), and one of the source electrode and drain electrode of the seventh transistor (T7). The first clock connection line (GB_CKCL11) placed in the even-numbered second island section (21e) is connected to one of the source electrode and drain electrode of the third transistor (T3), the gate electrode of the sixth transistor (T6), and one of the source electrode and drain electrode of the seventh transistor (T7), and the second clock connection line (GB_CKCL21) can be connected to the gate electrode of the first transistor (T1).

[0226] Source electrodes and drain electrodes may be placed in the second island section (21). Each of the source electrodes may be connected to a corresponding source region of the semiconductor layer (ACT), and each of the drain electrodes may be connected to a corresponding drain region of the semiconductor layer (ACT).

[0227] The third output line (GB_OL) and the fourth output line (EM_OL) may be spaced apart on the second horizontal bridge section (22h2). The carry line (GB_CRL) and the reset line (GB_ESRL) may be spaced apart on the vertical bridge section (22v). The third output line (GB_OL) may extend from one of the source electrode and drain electrode of the ninth transistor (T9) and one of the source electrode and drain electrode of the tenth transistor (T10). The carry line (GB_CRL) may be connected to one of the source electrode and drain electrode of the first transistor (T1). The reset line (GB_ESRL) may be connected to the gate electrode of the thirteenth transistor (T13).

[0228] Referring to FIG. 24, a fifth insulating layer (115, FIG. 26) may be disposed over the third insulating layer on the third insulating layer (113) of the second island portion (21) and the fourth insulating layer (114) of the second bridge portion (22). Contact holes may be formed in the fifth insulating layer (115). A fourth conductive layer may be disposed on the fifth insulating layer (115). The fourth conductive layer may include a first clock connection electrode (GB_CKCL12), a second clock connection electrode (GB_CKCL22), a reset connection line (ESRCL), an output connection line (EM_OCL), a first voltage line (VGHL) through which a first voltage (VGH) is transmitted, and a second voltage line (VGLL) through which a second voltage (VGL) is transmitted.

[0229] A first clock connection electrode (GB_CKCL12), a second clock connection electrode (GB_CKCL22), a reset connection line (ESRCL), and an output connection line (EM_OCL) may be arranged in the second island section (21). The first clock connection electrode (GB_CKCL12) may be connected to the first clock connection line (GB_CKCL11), and the second clock connection electrode (GB_CKCL22) may be connected to the second clock connection line (GB_CKCL21). The reset connection line (ESRCL) may connect the reset lines (GB_ESRL) arranged in the second direction on the vertical bridge sections (22v) with the second island section (21) in between. The output connection line (EM_OCL) may connect the fourth output line (EM_OL) of the first horizontal bridge section (22h1) and the fourth output line (EM_OL) of the second horizontal bridge section (22h2).

[0230] A first voltage line (VGHL) and a second voltage line (VGLL) are arranged in a vertical bridge section (22v), and the first voltage line (VGHL) and the second voltage line (VGLL) can be extended across a second island section (21). In the second island section (21), the first voltage line (VGHL) can be connected to one of the source electrode and drain electrode of the second transistor (T2), one of the source electrode and drain electrode of the eighth transistor (T8), one of the source electrode and drain electrode of the ninth transistor (T9), one of the source electrode and drain electrode of the thirteenth transistor (T13), and one electrode of the first capacitor (C1). The second voltage line (VGLL) can be connected to one of the source electrode and drain electrode of the fifth transistor (T5), one of the source electrode and drain electrode of the tenth transistor (T10), the gate electrode of the twelfth transistor (T12), and the gate electrode of the sixteenth transistor (T16).

[0231] Referring to FIG. 25, a sixth insulating layer (116, FIG. 26) may be disposed on the fifth insulating layer (115), covering the fourth conductive layer. Contact holes may be formed in the sixth insulating layer (116). A fifth conductive layer may be disposed on the sixth insulating layer (116). The fifth conductive layer may include a first clock line (GB_CKL1) and a second clock line (GB_CKL2).

[0232] A first clock line (GB_CKL1) and a second clock line (GB_CKL2) may be arranged in the vertical bridge section (22v). The first clock line (GB_CKL1) and the second clock line (GB_CKL2) may extend across the second island section (21). In the second island section (21), the first clock line (GB_CKL1) may be connected to the first clock connection electrode (GB_CKCL12), and the second clock line (GB_CKL2) may be connected to the second clock connection electrode (GB_CKCL22).

[0233] A seventh insulating layer (117, FIG. 26) may be disposed on the sixth insulating layer (116), covering the fifth conductive layer.

[0234] As shown in FIG. 26, in the vertical bridge section (22v), the first voltage line (VGHL) can be superimposed on the reset line (GB_ESRL), and the second voltage line (VGLL) can be superimposed on the carry line (GB_CRL). The first clock line (GB_CKL1) can be superimposed on the second voltage line (VGLL), and the second clock line (GB_CKL2) can be superimposed on the first voltage line (VGHL).

[0235] FIG. 26 illustrates the semiconductor layer (51), gate electrode (53), source electrode and drain electrode (55, 57) of the 10th transistor (T10) placed in the 2nd island section (21), and the lower electrode (CE1) and upper electrode (CE2) of the 3rd capacitor (C3).

[0236] FIG. 27 is a schematic diagram showing a part of a second driving circuit (133) according to one embodiment. FIGS. 28 to 31 are schematic diagrams showing the components of the second driving circuit (133) shown in FIG. 27 layer by layer. FIG. 32 is a cross-sectional view taken along Ic-Ic', IIc-IIc', and IIIc-IIIc' of the second driving circuit (133) shown in FIG. 27.

[0237] The second stage of the second driving circuit (133) may be placed in the second island section (21) of the second row. FIG. 27 illustrates the odd-numbered stage (STo) and the even-numbered stage (STe) adjacent to each other in the second direction of the second driving circuit (133). Referring to FIG. 27, the odd-numbered stage (STo) and the even-numbered stage (STe) may be placed adjacently in one second island section (21).

[0238] Referring to FIG. 28, a semiconductor layer (ACT), a first conductive layer (CDL1), and a second conductive layer (CDL2) may be sequentially disposed on the second island portion (21). A barrier layer (110, FIG. 32) may be disposed between the substrate (100, FIG. 32) and the semiconductor layer (ACT). The semiconductor layer (ACT) may include a silicon semiconductor. The semiconductor layer (ACT) may include a channel region, source regions on both sides of the channel region, and drain regions for each of the first to eighth transistors (T1 to T8) (Fig. 13). Depending on the case, the source region or drain region may be interpreted as the source electrode or drain electrode of the transistor.

[0239] A first insulating layer (111, FIG. 32) may be disposed over a semiconductor layer (ACT) on a barrier layer (110), and a first conductive layer (CDL1) may be disposed on the first insulating layer (111). The first conductive layer (CDL1) may include the gate electrodes of each of the first to eighth transistors (T1 to T8) and the lower electrodes of each of the first and second capacitors (C1 and C2) (Fig. 13). The gate electrodes may overlap the channel regions of the semiconductor layer (ACT).

[0240] A second insulating layer (112, FIG. 32) may be disposed over the first conductive layer (CDL1) on the first insulating layer (111), and a second conductive layer (CDL2) may be disposed on the second insulating layer (112). The second conductive layer (CDL2) may include the upper electrodes of each of the first and second capacitors (C1 and C2). The upper electrodes of each of the first and second capacitors (C1 and C2) may overlap with the lower electrodes of each of the first and second capacitors (C1 and C2).

[0241] A second conductive layer (CDL2) is placed over the second insulating layer (112), a third insulating layer (113, FIG. 32) is disposed thereon, and contact holes may be formed in the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113).

[0242] Subsequently, as described with reference to FIG. 17, the area other than the region corresponding to the second island portion (21) in the barrier layer (110), the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) may be removed. A fourth insulating layer (114) may be disposed in the area other than the region corresponding to the second island portion (21) of the substrate (100).

[0243] Referring to FIG. 29, a third conductive layer may be disposed on the third insulating layer (113) of the second island portion (21) and the fourth insulating layer (114) of the second bridge portion (22). The third conductive layer may include source electrodes, drain electrodes, and an output line (hereinafter referred to as the second output line) (GI_OL) through which a second scan signal (GI) is output.

[0244] Source electrodes and drain electrodes may be placed in the second island section (21). Each of the source electrodes may be connected to a corresponding source region of the semiconductor layer (ACT), and each of the drain electrodes may be connected to a corresponding drain region of the semiconductor layer (ACT).

[0245] The second output line (GI_OL1) of the odd-numbered stage (STo) and the second output line (GI_OL2) of the even-numbered stage (STe) may be placed in the third horizontal bridge section (22h3). The second output lines (GI_OL1, GI_OL2) may extend from one of the source electrode and drain electrode of the sixth transistor (T6) and one of the source electrode and drain electrode of the seventh transistor (T7).

[0246] A fifth insulating layer (115, FIG. 32) may be disposed on the third insulating layer (113) of the second island portion (21) and the fourth insulating layer (114) of the second bridge portion (22), covering the third conductive layer. Contact holes may be formed in the fifth insulating layer (115).

[0247] Referring to FIG. 30, a fourth conductive layer may be disposed on the fifth insulating layer (115). The fourth conductive layer may include a first clock connection electrode (GI_CKCL1), a second clock connection electrode (GI_CKCL2), a first connection electrode (EM_OCL1), a second connection electrode (EM_OCL2), a third connection electrode (GB_OCL1), a fourth connection electrode (GB_OCL2), a carry line (GI_CRL), a first voltage line (VGHL), and a second voltage line (VGLL).

[0248] A first clock connection electrode (GI_CKCL1), a second clock connection electrode (GI_CKCL2), a first connection electrode (EM_OCL1), a second connection electrode (EM_OCL2), a third connection electrode (GB_OCL1) and a fourth connection electrode (GB_OCL2) may be placed in the second island section (21).

[0249] The first clock connection electrode (GI_CKCL1) can be connected to the gate electrode of the first transistor (T1) of the odd-numbered stage (STo), one of the source electrode and drain electrode of the fourth transistor (T4), and the gate electrode of the fifth transistor (T5). The first clock connection electrode (GI_CKCL1) can be connected to the gate electrode of the third transistor (T3) of the even-numbered stage (STe) and one of the source electrode and drain electrode of the seventh transistor (T7). The second clock connection electrode (GI_CKCL2) can be connected to the gate electrode of the third transistor (T3) of the odd-numbered stage (STo) and one of the source electrode and drain electrode of the seventh transistor (T7). The second clock connection electrode (GI_CKCL2) can be connected to the gate electrode of the first transistor (T1) of the even-numbered stage (STe), one of the source electrode and drain electrode of the fourth transistor (T4), and the gate electrode of the fifth transistor (T5).

[0250] The first connecting electrode (EM_OCL1) can be connected to the fourth output line (EM_OL) of the second horizontal bridge section (22h2). The third connecting electrode (GB_OCL1) can be connected to the third output line (GB_OL) of the second horizontal bridge section (22h2).

[0251] A carry line (GI_CRL), a first voltage line (VGHL), and a second voltage line (VGLL) may be placed in the vertical bridge section (22v). The carry line (GI_CRL) placed in the upper vertical bridge section (22v) may be connected to one of the source electrode and drain electrode of the first transistor (T1) of the odd-numbered stage (STo). The carry line (GI_CRL) placed in the lower vertical bridge section (22v) may be connected to an output line (GI_OL2) connected to the seventh transistor (T7) of the even-numbered stage (STe). The first voltage line (VGHL) and the second voltage line (VGLL) may extend across the second island section (21). In the second island section (21), the first voltage line (VGHL) can be connected to one of the source electrode and drain electrode of the second transistor (T2), one of the source electrode and drain electrode of the sixth transistor (T6), and one electrode of the first capacitor (C1). The second voltage line (VGLL) can be connected to one of the source electrode and drain electrode of the fifth transistor (T5) and the gate electrode of the eighth transistor (T8).

[0252] Referring to FIG. 31, a sixth insulating layer (116, FIG. 32) may be disposed on the fifth insulating layer (115), covering the fourth conductive layer. Contact holes may be formed in the sixth insulating layer (116). A fifth conductive layer may be disposed on the sixth insulating layer (116). The fifth conductive layer may include a first clock line (GI_CKL1), a second clock line (GI_CKL2), a fifth connecting electrode (EM_OCL3), a sixth connecting electrode (GB_OCL3), a fourth output line (EM_OL), and a third output line (GB_OL).

[0253] A fifth connecting electrode (EM_OCL3) and a sixth connecting electrode (GB_OCL3) may be placed in the second island section (21). The fifth connecting electrode (EM_OCL3) may be connected to the first connecting electrode (EM_OCL1) and the second connecting electrode (EM_OCL2). The sixth connecting electrode (GB_OCL3) may be connected to the third connecting electrode (GB_OCL1) and the fourth connecting electrode (GB_OCL2).

[0254] A first clock line (GI_CKL1) and a second clock line (GI_CKL2) may be arranged in the vertical bridge section (22v). The first clock line (GI_CKL1) and the second clock line (GI_CKL2) may extend across the second island section (21). In the second island section (21), the first clock line (GI_CKL1) may be connected to the first clock connection electrode (GI_CKCL1), and the second clock line (GI_CKL2) may be connected to the second clock connection electrode (GI_CKCL2).

[0255] A fourth output line (EM_OL) and a third output line (GB_OL) may be placed in the third horizontal bridge section (22h). The fourth output line (EM_OL) may be extended to the second island section (21) and connected to the second connecting electrode (EM_OCL2) in the second island section (21). The third output line (GB_OL) may be extended to the second island section (21) and connected to the fourth connecting electrode (GB_OCL2) in the second island section (21).

[0256] A seventh insulating layer (117, FIG. 32) may be disposed on the sixth insulating layer (116), covering the fifth conductive layer.

[0257] As illustrated in FIG. 32, in the vertical bridge section (22v), the first clock line (GI_CKL1) may overlap with part of the second voltage line (VGLL) and the carry line (GI_CRL), and the second clock line (GI_CKL2) may overlap with part of the first voltage line (VGHL) and the carry line (GI_CRL). In the horizontal bridge section (22h), the fourth output line (EM_OL) may overlap with the second output line (GI_OL1) of the odd-numbered stage (STo), and the third output line (GB_OL) may overlap with the second output line (GI_OL2) of the even-numbered stage (STe).

[0258] FIG. 32 illustrates the semiconductor layer (51), gate electrode (53), source electrode and drain electrode (55, 57) of the sixth transistor (T6) placed in the second island section (21), and the lower electrode (CE1) and upper electrode (CE2) of the first capacitor (C1).

[0259] FIG. 33 is a schematic diagram showing a part of a first driving circuit (131) according to one embodiment. FIGS. 34 to 37 are schematic diagrams showing the components of the second driving circuit (133) shown in FIG. 33 layer by layer. FIG. 38 is a cross-sectional view taken along Id-Id', IId-IId', and IIId-IIId' of the first driving circuit (131) shown in FIG. 33.

[0260] The stage circuits of the first driving circuit (131) shown in FIG. 33 are identical to the stage circuits of the second driving circuit (133) shown in FIG. 27, except for the arrangement of the output lines, and the differences will be explained below.

[0261] The first stage of the first driving circuit (131) may be placed in the second island section (21) of the first row. FIG. 33 illustrates an odd-numbered stage (STo) and an even-numbered stage (STe) adjacent to each other in the second direction of the first driving circuit (131). Referring to FIG. 33, the odd-numbered stage (STo) and the even-numbered stage (STe) may be placed adjacently in one second island section (21).

[0262] The arrangement of the first to eighth transistors (T1 to T8) and the first and second capacitors (C1 and C2) in the second island section (21) shown in FIGS. 34 and 35 is the same as the arrangement of the first to eighth transistors (T1 to T8) and the first and second capacitors (C1 and C2) in the second island section (21) shown in FIGS. 28 and 29.

[0263] Referring to FIG. 35, a third conductive layer may be disposed on the third insulating layer (113, FIG. 38) of the second island portion (21) and the fourth insulating layer (114, FIG. 38) of the second bridge portion (22). The third conductive layer may include source electrodes and drain electrodes, second output lines (GI_OL1, GI_OL2), and an output line (hereinafter, first output line) (GW_OL) through which a first scan signal (GW) is output.

[0264] Source electrodes and drain electrodes can be placed in the second island section (21).

[0265] The first output line (GW_OL1) of the odd-numbered stage (STo) and the first output line (GW_OL2) of the even-numbered stage (STe) may be spaced apart in the fourth horizontal bridge section (22h4). The first output lines (GW_OL1, GW_OL2) may extend from one of the source electrode and drain electrode of the sixth transistor (T6) and one of the source electrode and drain electrode of the seventh transistor (T7).

[0266] The second output lines (GI_OL1, GI_OL2) placed in the third horizontal bridge section (22h3) may be extended to the second island section (21) and the fourth horizontal bridge section (22h4). In the second island section (21), the second output lines (GI_OL1, GI_OL2) may be extended in opposite directions along the edges of the second island section (21). In the fourth horizontal bridge section (22h4), the first output lines (GW_OL1, GW_OL2) and the second output lines (GI_OL1, GI_OL2) may be spaced apart.

[0267] A fifth insulating layer (115, FIG. 34) may be disposed on the third insulating layer (113) of the second island portion (21) and the fourth insulating layer (114) of the second bridge portion (22), covering the third conductive layer. Contact holes may be formed in the fifth insulating layer (115).

[0268] Referring to FIG. 36, a fourth conductive layer may be disposed on the fifth insulating layer (115). The fourth conductive layer may include clock connection electrodes, output connection electrodes, a carry line (GW_CRL), a first voltage line (VGHL), and a second voltage line (VGLL).

[0269] Clock connection electrodes and output connection electrodes may be placed in the second island section (21). Among the clock connection electrodes, the first clock connection electrode may be connected to the gate electrode of the first transistor (T1) of the odd-numbered stage (STo), one of the source electrode and drain electrode of the fourth transistor (T4), the gate electrode of the fifth transistor (T5), the gate electrode of the third transistor (T3) of the even-numbered stage (STe), and one of the source electrode and drain electrode of the seventh transistor (T7). Among the clock connection electrodes, the second clock connection electrode can be connected to the gate electrode of the third transistor (T3) of the odd-numbered stage (STo) and one of the source electrode and drain electrode of the seventh transistor (T7), the gate electrode of the first transistor (T1) of the even-numbered stage (STe), one of the source electrode and drain electrode of the fourth transistor (T4), and the gate electrode of the fifth transistor (T5).

[0270] A carry line (GW_CRL), a first voltage line (VGHL), and a second voltage line (VGLL) may be placed in the vertical bridge section (22v). The carry line (GW_CRL) placed in the upper vertical bridge section (22v) may be connected to one of the source electrode and drain electrode of the first transistor (T1) of the odd-numbered stage (STo). The carry line (GW_CRL) placed in the lower vertical bridge section (22v) may be connected to the first output line (GW_OL2) connected to the seventh transistor (T7) of the even-numbered stage (STe). The first voltage line (VGHL) and the second voltage line (VGLL) may extend across the second island section (21). In the second island section (21), the first voltage line (VGHL) can be connected to one of the source electrode and drain electrode of the second transistor (T2), one of the source electrode and drain electrode of the sixth transistor (T6), and one electrode of the first capacitor (C1). The second voltage line (VGLL) can be connected to one of the source electrode and drain electrode of the fifth transistor (T5) and the gate electrode of the eighth transistor (T8).

[0271] Referring to FIG. 37, a sixth insulating layer (116, FIG. 34) may be disposed on the fifth insulating layer (115), covering the fourth conductive layer. Contact holes may be formed in the sixth insulating layer (116). A fifth conductive layer may be disposed on the sixth insulating layer (116). The fifth conductive layer may include a first clock line (GW_CKL1), a second clock line (GW_CKL2), a fourth output line (EM_OL), and a third output line (GB_OL).

[0272] A first clock line (GW_CKL1) and a second clock line (GW_CKL2) may be arranged in the vertical bridge section (22v). The first clock line (GW_CKL1) and the second clock line (GW_CKL2) may extend across the second island section (21). In the second island section (21), the first clock line (GW_CKL1) may be connected to the first clock connection electrode, and the second clock line (GW_CKL2) may be connected to the second clock connection electrode.

[0273] A fourth output line (EM_OL) and a third output line (GB_OL) may be placed in the fourth horizontal bridge section (22h4). The fourth output line (EM_OL) and the third output line (GB_OL) extend to the second island section (21) and may be connected to output connection electrodes in the second island section (21). The output connection electrodes may be connected to the fourth output line (EM_OL) and the third output line (GB_OL) placed in the third horizontal bridge section (22h3).

[0274] A seventh insulating layer (117, FIG. 34) may be disposed on the sixth insulating layer (116), covering the fifth conductive layer.

[0275] As illustrated in FIG. 38, in the vertical bridge section (22v), the first clock line (GI_CKL1) may overlap with part of the second voltage line (VGLL) and the carry line (GI_CRL), and the second clock line (GI_CKL2) may overlap with part of the first voltage line (VGHL) and the carry line (GI_CRL). In the horizontal bridge section (22h), the fourth output line (EM_OL) may overlap with the second output line (GI_OL1) of the odd-numbered stage (STo), and the third output line (GB_OL) may overlap with the second output line (GI_OL2) of the even-numbered stage (STe).

[0276] As illustrated in FIG. 38, in the vertical bridge section (22v), the first clock line (GW_CKL1) may overlap with a part of the second voltage line (VGLL) and the carry line (GW_CRL), and the second clock line (GW_CKL2) may overlap with a part of the first voltage line (VGHL) and the carry line (GW_CRL). In the fourth horizontal bridge section (22h4), the fourth output line (EM_OL) may overlap with the second output line (GI_OL1) of the odd-numbered stage (STo) and the first output line (GW_OL1) of the odd-numbered stage (STo), and the third output line (GB_OL) may overlap with the second output line (GI_OL2) of the even-numbered stage (STe) and the first output line (GW_OL2) of the even-numbered stage (STe).

[0277] FIG. 38 illustrates the semiconductor layer (51), gate electrode (53), source electrode and drain electrode (55, 57) of the sixth transistor (T6) placed in the second island section (21), and the lower electrode (CE1) and upper electrode (CE2) of the first capacitor (C1).

[0278] FIG. 39 is a schematic diagram showing a fourth conductive layer according to one embodiment.

[0279] Referring to FIG. 39, in each column, the first voltage line (VGHL) and the second voltage line (VGLL) can be extended along the second direction to the vertical bridge sections (22v). The first voltage line (VGHL) and the second voltage line (VGLL) can pass through the second island sections (21) connected between the vertical bridge sections (22v) and overlap with the stage circuit (STC). By extending the first voltage line (VGHL) and the second voltage line (VGLL) across the second island sections (21) as a single conductive line in the second direction, the effects of resistance and coupling capacitance can be minimized.

[0280] The first voltage line (VGHL) and the second voltage line (VGLL) can be connected to the stage circuit through a contact hole in the second island section (21) to transmit a signal to the stage circuit.

[0281] In the third driving circuit (135) and the fourth driving circuit (137), the first voltage line (VGHL) and the second voltage line (VGLL) may be placed on the upper portion of the carrier line and the reset line formed by the third conductive layer. In the first driving circuit (131) and the second driving circuit (133), the first voltage line (VGHL) and the second voltage line (VGLL) may be placed on the same layer as the carrier line. By placing the carrier line on the same layer as the first voltage line (VGHL) and the second voltage line (VGLL), the connection to the stage circuit can be optimized by reducing the number of contact holes for connecting the conductor line and the stage circuit within the second island portion while reducing the capacitance caused by the overlap between the conductor lines.

[0282] In one embodiment, the first voltages (VGH) delivered by the first voltage lines (VGHL) connected to the first driving circuit (131), the second driving circuit (133), the third driving circuit (135), and the fourth driving circuit (137) may be the same or different. The second voltage (VGL) delivered by the second voltage line (VGLL) connected to the first driving circuit (131), the second driving circuit (133), the third driving circuit (135), and the fourth driving circuit (137) may be the same or different.

[0283] FIG. 40 is a schematic diagram showing a fifth conductive layer according to one embodiment.

[0284] Referring to FIG. 40, in each column, the first clock line (EM_CKL1, GB_CKL1, GI_CKL1, GW_CKL1) and the second clock line (EM_CKL2, GB_CKL2, GI_CKL2, GW_CKL2) may be extended and arranged along the second direction in the vertical bridge sections (22v). The first clock line (EM_CKL1, GB_CKL1, GI_CKL1, GW_CKL1) and the second clock line (EM_CKL2, GB_CKL2, GI_CKL2, GW_CKL2) may pass through the second island sections (21) connected between the vertical bridge sections (22v) and overlap with the stage circuit (STC). Resistance can be minimized by the first clock line (EM_CKL1, GB_CKL1, GI_CKL1, GW_CKL1) and the second clock line (EM_CKL2, GB_CKL2, GI_CKL2, GW_CKL2) extending in the second direction across the second island section (21) as a single conductive wire.

[0285] The first clock line (EM_CKL1, GB_CKL1, GI_CKL1, GW_CKL1) and the second clock line (EM_CKL2, GB_CKL2, GI_CKL2, GW_CKL2) can be connected to the stage circuit through a contact hole in the second island section (21) to transmit a signal to the stage circuit.

[0286] In the first driving circuit (131) and the second driving circuit (133), the first clock line (EM_CKL1, GB_CKL1, GI_CKL1, GW_CKL1) and the second clock line (EM_CKL2, GB_CKL2, GI_CKL2, GW_CKL2) and the third output line (GB_OL) and the fourth output line (EM_OL) may be arranged in the horizontal bridge section (22h) along the first direction on the same layer as the first clock line (EM_CKL1, GB_CKL1, GI_CKL1, GW_CKL2).

[0287] A first clock signal (GW_CLK1) transmitted by a first clock line (GW_CKL1) connected to a first driving circuit (131) and a second clock signal (GW_CLK2) transmitted by a second clock line (GW_CKL2), a first clock signal (GI_CLK1) transmitted by a first clock line (GI_CKL1) connected to a second driving circuit (133) and a second clock signal (GI_CLK2) transmitted by a second clock line (GI_CKL2), a first clock signal (GB_CLK1) transmitted by a first clock line (GB_CKL1) connected to a third driving circuit (135) and a second clock signal (GB_CLK2) transmitted by a second clock line (GB_CKL2), a first clock signal (EM_CLK1) transmitted by a first clock line (EM_CKL1) connected to a fourth driving circuit (137) and The second clock signal (EM_CLK2) transmitted by the second clock line (EM_CKL2) may be the same or at least one may be different.

[0288] A display panel according to embodiments of the present invention can implement a high-stretch and high-resolution display device by defining island sections and bridge sections in a display area and a non-display area, and arranging the sides of the island sections to be tilted at a predetermined angle. In the non-display area of ​​the display panel according to embodiments of the present invention, signal lines connected to a stage circuit can be arranged to overlap the stage circuit by crossing the island sections where the stage circuit is arranged, rather than being placed in an island section separately arranged around the island section where the stage circuit is arranged. Accordingly, the size of the non-display area can be reduced. The display panel according to embodiments of the present invention can minimize the load on the display panel by reducing the resistance of the conductive lines and minimizing the coupling capacitance by forming the signal lines connected to the stage circuit as a single conductive line (e.g., a voltage line formed by a fourth conductive layer, a clock line formed by a fifth conductive layer).

[0289] FIG. 41 is a schematic perspective view of an electronic device including a display panel according to one embodiment.

[0290] Referring to FIG. 41, the electronic device (1000) can be freely deformed in three dimensions and can provide a three-dimensional image surface through the display area (DA). The statement that the electronic device (1000) can be freely deformed in three dimensions is distinguished from the operation of an electronic device having a rollable display panel, such as when a part of the rolled-up display area is visible to the user, and then another part of the rolled-up display area is unfolded so that the entire display area is visible to the user (or when the entire unfolded display area is visible to the user, and then the display area is rolled up so that only a part of the display area is visible to the user). The electronic device (1000) according to embodiments of the present invention may exhibit a deformation such as the area of ​​the entire display area (DA) increasing or decreasing again as the electronic device (1000) is deformed in the x direction, y direction, and / or z direction.

[0291] FIG. 42 is a block diagram of an electronic device according to one embodiment.

[0292] Referring to FIG. 42, an electronic device (1000) according to one embodiment may include a display module (1100), a processor (1200), a memory (1300), and a power module (1400).

[0293] The electronic device (1000) can output various information through the display module (1100) within the operating system.

[0294] The processor (1200) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. In one embodiment, the processor (1200) may be provided divided into two or more parts from a functional or structural perspective. For example, the processor (1200) may include a main processor in the form of a first driving chip that includes a central processing unit, and an auxiliary processor in the form of a second driving chip that includes a controller that receives an image signal from the main processor and processes the image signal to match the interface specifications of the display module (1100).

[0295] The memory (1300) may include at least one of non-volatile memory and volatile memory. Data information necessary for the operation of the processor (1200) or the display module (1100) may be stored in the memory (1300). When the processor (1200) executes an application stored in the memory (1300), an image data signal and / or an input control signal is transmitted to the display module (1100), and the display module (1100) can process the received signal and output image information through a display screen.

[0296] The power module (1400) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (1000). Power conversion by the power conversion module may include DC-DC conversion, AC-DC conversion, and DC-AC conversion, but is not limited thereto.

[0297] At least one of each component of the aforementioned electronic device (1000) may be included within the display device according to the embodiments described above. Additionally, some of the individual modules functionally included within a single module may be included within the display device, while others may be provided separately from the display device. For example, the display device may include an auxiliary processor among the display module (1100) and the processor (1200), and the main processor, memory (1300), and power module (1400) among the processor (1200) may be provided in the form of other devices within the electronic device (1000) other than the display device. As another example, the power module (1400) may be provided within the display device and may supply power to the processor (1200) and memory (1300) provided within the electronic device (1000) other than the display device, but is not limited to the above examples.

[0298] FIGS. 43a to 43i are schematic perspective views illustrating embodiments of an electronic device including a display panel according to one embodiment of the present invention.

[0299] Referring to FIG. 43a, a display panel according to one embodiment of the present invention can be utilized in a wearable electronic device (1000A) that can be worn on a part of a user's body. The wearable electronic device (1000A) may include a body part (3110) and a display part (3120) provided in the body part (3110). The display panel according to embodiments of the present invention can be used as the display part (3120) of the wearable electronic device (1000A). As illustrated in FIG. 43a, the wearable electronic device (1000A) may be modified. In one embodiment, it can be used as a smart watch or a smartphone depending on the user's choice.

[0300] FIG. 43b illustrates a medical electronic device (1000B). In one embodiment, the medical electronic device (1000B) may include a body part (3210) and a light-emitting part (3220). A display panel according to embodiments of the present invention may be used as the light-emitting part (3220) of the medical electronic device (1000B). The light-emitting part (3220) may emit light of a specific wavelength band (e.g., infrared, visible light, etc.) to the patient's body. In one embodiment, the body part (3210) may have a stretchable fiber material and may have a structure that can be worn on the user's body.

[0301] FIG. 43c illustrates an educational electronic device (1000C). In one embodiment, the educational electronic device may include a display unit (3320) provided within a housing (3310). The display unit (3320) may utilize a display panel according to embodiments of the present invention. The display unit (3320) may provide images such as a sea with waves, a snow-covered mountain, or a volcano with flowing lava, wherein the display unit (3320) may extend in the height direction (e.g., z-direction) to reflect the height of the waves, mountain, or volcano. In some embodiments, a portion of the display unit (3320) may sequentially vary in height along the direction of the lava flow to show the movement of the lava in three dimensions. The educational electronic device (1000C) may include a plurality of pins (or stroke units, 3330) arranged on the back of the display unit (3320) so that the display unit (3320) extends in the height direction. The pins (3330) can be implemented to move along a third direction (e.g., z direction or -z direction) so that the image displayed on the display unit (3320) has a three-dimensional height. FIG. 39c describes an educational electronic device (1000C), but its use is not limited as long as it provides a certain image information.

[0302] FIGS. 43d and FIGS. 43e illustrate the use of a display panel in a wearable electronic device (1000D-1, 1000D-2), such as a smart watch.

[0303] In one embodiment, as illustrated in FIG. 43d, the display panel corresponding to the display unit (3320) of the electronic device (1000D-1) can be stretched three-dimensionally, so it can provide various haptic information to the user in addition to visual information through images. In one embodiment, the electronic device (1000D-1) can provide haptic information such as Braille markings for the visually impaired or tactile stimulation linked to images by using a plurality of pins (or stroke unit, 3330) placed below the display unit (3320). Since the display panel forming the display unit (3320) can be stretched three-dimensionally, it can provide the aforementioned haptic information to the user. The electronic device (1000D-1) may include a body part (3310) that includes a housing (3314) in which a display panel forming a display part (3320) and pins (or stroke part, 3330) are housed, and a frame (3312) that can be coupled to the housing (3314) with the display panel in between. In some embodiments, the frame (3312) may be formed integrally with the housing (3314).

[0304] The electronic device (1000D-2) of FIG. 43e may include a body part (3310) as in FIG. 43d and a display part (3320) that is housed in the body part (3310) and can provide visual information. In some embodiments, the display panel corresponding to the display part (3320) may include a dome-shaped display part (3320) because it is stretchable in three dimensions. In one embodiment, the display panel may be assembled on a dome-shaped body frame during the manufacturing process of the electronic device (1000D-2), and since the display panel is stretchable in three dimensions, it may be assembled in a stretched state along the shape of a hemispherical body frame.

[0305] FIG. 43f illustrates that in one embodiment of the present invention, another electronic device (1000E) includes a robot. The robot can recognize movement or objects using a camera module (3470) and can display a predetermined image to a user through a display unit (3420, 3430).

[0306] As a partial embodiment, the display panels according to one embodiment of the present invention can be assembled to a body frame having a hemispherical shape, as they can be extended in various directions as described above, and thus the robot may include a hemispherical display unit (3420, 3430).

[0307] FIG. 33g illustrates a vehicle display device (1000F) as another electronic device in one embodiment of the present invention. The vehicle display device (1000F) may include a cluster (3510), a Center Information Display (CID) (3520), and / or a co-driver display (3530). Since the display panel according to the embodiment of the present invention can be extended in various directions, it can be used for the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display (3530) without being constrained by the shape of the vehicle's internal frame.

[0308] FIG. 43h illustrates the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display (3530) being separated, but the invention is not limited thereto. In another embodiment, two or more selected from the cluster (3510), the Center Information Display (CID) (3520), and the co-driver display (3530) may be connected as a single unit.

[0309] In some embodiments, the vehicle display device (1000F) may include a button (3540) capable of displaying a predetermined image. Referring to the enlarged view of FIG. 43h, the hemispherical button (3540) may include an object (3542) that provides a sense of use of the button while moving in the z-direction or -z-direction, and a display panel placed on the object (3542). In some embodiments, if the object (3542) has a three-dimensionally rounded surface, the display panel may also have a three-dimensionally rounded surface.

[0310] FIG. 43h illustrates that an electronic device according to one embodiment of the present invention is an electronic device (1000G) for advertising or display. In some embodiments, the electronic device (1000G) for advertising or display may be installed on a fixed structure (3610), such as a wall or a column. If the structure (3610) includes an uneven surface as shown in FIG. 43h, the electronic device (1000G) for advertising or display may also be placed along the uneven surface of the structure (3610). In some embodiments, the electronic device (1000G) for advertising or display may be installed on the structure (3610) using a heat-shrink film or the like.

[0311] FIG. 43i illustrates that an electronic device (1000H) according to one embodiment of the present invention is a controller. The controller may include image-type buttons. For example, the controller may include first to third button areas (3720, 3730, 3740) in which a portion of the display portion (3710) protrudes in the z-direction or protrudes in the -z-direction (or is recessed in the z-direction). In some embodiments, the first and third button areas (3720, 3740) may protrude in the z-direction, and the second button area (3730) may protrude in the -z-direction (or be recessed in the z-direction).

[0312] As such, the present invention has been described with reference to an embodiment illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A display panel comprising a non-display area defined by a plurality of island portions and a plurality of bridge portions connecting the island portions, A driving circuit including a plurality of stages is provided in the above non-display area, and At least one of the plurality of stages is disposed in each of the plurality of island sections, and At least one signal line connected to the plurality of stages is disposed on the plurality of bridge sections, and The plurality of bridge sections include first bridge sections extended along a first direction and second bridge sections extended along a second direction perpendicular to the first direction, and The above plurality of stages are arranged in a plurality of island sections arranged along the second direction, and The above at least one signal line includes at least one first conductive line disposed in the first bridge sections and at least one second conductive line disposed in the second bridge sections, and The above at least one second conductive line extends across the plurality of island sections, forming a display panel.

2. In Paragraph 1, A display panel comprising at least one first conductive line, wherein the output line through which the output signal of the at least one stage is output.

3. In Paragraph 1, A display panel comprising at least one second conductor line, the above-mentioned voltage line for transmitting voltage to at least one stage and a clock line for transmitting a clock signal.

4. In Paragraph 3, A display panel in which the voltage line and the clock line are arranged on different layers.

5. In Paragraph 1, A display panel having a stage disposed in each of the aforementioned plurality of island sections.

6. In Paragraph 1, A display panel having odd-numbered stages and even-numbered stages arranged in each of the aforementioned plurality of island sections.

7. A display panel comprising a non-display area defined by a plurality of island portions and a plurality of bridge portions connecting the island portions, A first driving circuit comprising a plurality of first stages in the above non-display area; and A second driving circuit comprising a plurality of second stages in the above non-display area is provided; and the first driving circuit is closer to the display area than the second driving circuit, and The plurality of island sections include first island sections in a first row in which the plurality of first stages are arranged, and second island sections in a second row in which the plurality of second stages are arranged. The plurality of bridge sections include first bridge sections having at least one first signal line connected to the plurality of first stages, and second bridge sections having at least one second signal line connected to the plurality of second stages. The first bridge sections include first horizontal bridge sections extended along a first direction and first vertical bridge sections extended along a second direction perpendicular to the first direction. The second bridge sections include second horizontal bridge sections extended along the first direction and second vertical bridge sections extended along the second direction, and The above at least one first signal line includes at least one first horizontal conductor line disposed in the first horizontal bridge sections and at least one first vertical conductor line disposed in the first vertical bridge sections, and The above at least one second signal line includes at least one second horizontal conductor line disposed in the second horizontal bridge sections and at least one second vertical conductor line disposed in the second vertical bridge sections, and A display panel in which at least one first vertical conductor extends across the first island sections, and at least one second vertical conductor extends across the second island sections.

8. In Paragraph 7, A first stage is placed in each of the above first island sections, and A display panel having an odd-numbered second stage and an even-numbered second stage arranged in each of the above second island sections.

9. In Paragraph 8, The first horizontal conductor above includes a first output line through which the output signal of the first stage is output, and A display panel comprising a second horizontal conductor line to which the output signal of the odd-numbered second stage is output and a third output line to which the output signal of the even-numbered second stage is output.

10. In Paragraph 9, Each of the first horizontal bridge sections is a display panel connected to one of the first island sections and one of the second island sections arranged in the same row.

11. In Paragraph 10, The first output line is arranged in a second horizontal bridge connected to a first horizontal bridge section arranged in the first row and a second island section arranged in the first row, and The second output line and the third output line are spaced apart from each other in the second horizontal bridge section arranged in the first row above, and A display panel in which, in the second horizontal bridge portion arranged in the first row above, the first output line on the plane overlaps at least partially with the second output line and the third output line.

12. In Paragraph 11, A connecting electrode is placed in the second island portion arranged in the first row above, and The above connecting electrode is a display panel that connects a first output line disposed in a first horizontal bridge portion disposed in the first row and a first output line disposed in a second horizontal bridge portion disposed in the first row.

13. In Paragraph 12, A display panel in which a first output line disposed in a first horizontal bridge portion disposed in the first row and a first output line disposed in a second horizontal bridge portion disposed in the first row are disposed on different layers.

14. In Paragraph 8, The first vertical conductor above includes a first voltage line that transmits voltage to the first stage and a first clock line that transmits a clock signal, and A display panel comprising a second vertical conductor that transmits voltage to the odd-numbered second stage and the even-numbered second stage, and a second clock line that transmits a clock signal.

15. In Paragraph 14, The first voltage line and the first clock line are placed on different layers, and The second voltage line is placed on the same layer as the first voltage line, and The above second clock line is a display panel disposed on the same layer as the above first clock line.

16. In Paragraph 15, The first vertical conductor further includes a first carry line that transmits a start signal to the first stage, and A display panel comprising a second vertical conductor that further includes a second carrier line that transmits a start signal to the odd-numbered second stage.

17. In Paragraph 15, The first carry line is disposed on a different layer from the first voltage line, and the first voltage line overlaps the first carry line, and The above second carry line is a display panel disposed on the same layer as the above second voltage line, 18. A display panel having a display area in which multiple pixels are arranged and a non-display area outside the display area defined therein; and A driving circuit disposed in the above non-display area and outputting a gate signal to the plurality of pixels of the above display panel; comprising The above non-display area is defined with a plurality of island sections and a plurality of bridge sections connecting the island sections, and The above driving circuit is, A first driving circuit comprising a plurality of first stages; and A second driving circuit comprising a plurality of second stages; wherein the first driving circuit is closer to the display area than the second driving circuit, and The plurality of island sections include first island sections in a first row in which the plurality of first stages are arranged, and second island sections in a second row in which the plurality of second stages are arranged. The plurality of bridge sections include first bridge sections having at least one first signal line connected to the plurality of first stages, and second bridge sections having at least one second signal line connected to the plurality of second stages. The first bridge sections include first horizontal bridge sections extended along a first direction and first vertical bridge sections extended along a second direction perpendicular to the first direction. The second bridge sections include second horizontal bridge sections extended along the first direction and second vertical bridge sections extended along the second direction, and The above at least one first signal line includes at least one first horizontal conductor line disposed in the first horizontal bridge sections and at least one first vertical conductor line disposed in the first vertical bridge sections, and The above at least one second signal line includes at least one second horizontal conductor line disposed in the second horizontal bridge sections and at least one second vertical conductor line disposed in the second vertical bridge sections, and An electronic device in which at least one first vertical conductor extends across the first island sections, and at least one second vertical conductor extends across the second island sections.

19. In Paragraph 18, A first stage is placed in each of the above first island sections, and An electronic device having an odd-numbered second stage and an even-numbered second stage arranged in each of the above-mentioned second island sections.

20. In Paragraph 19, The first vertical conductor above includes a first voltage line that transmits voltage to the first stage, a first clock line that transmits a clock signal, and a first carry line that transmits a start signal. The second vertical conductor includes a second voltage line that transmits voltage to the odd-numbered second stage and the even-numbered second stage, a second clock line that transmits a clock signal, and a second carry line that transmits a start signal to the odd-numbered second stage. The first voltage line and the first clock line are placed on different layers, and The second voltage line is placed on the same layer as the first voltage line, and The second clock line is placed on the same layer as the first clock line, and The first carry line is disposed on a different layer from the first voltage line, and The above second carry line is an electronic device disposed on the same layer as the above second voltage line.

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