Latch-based low-density parity check (LDPC) implementations
Replacing D flip-flops with gated D latches in LDPC decoders reduces computational resource requirements, improving the efficiency of error correction in memory devices like SSDs.
WO2026143196A1PCT designated stage Publication Date: 2026-07-02SK HYNIX NAND PRODUCT SOLUTIONS CORP (D B A SOLIDIGM)
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SK HYNIX NAND PRODUCT SOLUTIONS CORP (D B A SOLIDIGM)
- Filing Date
- 2025-12-24
- Publication Date
- 2026-07-02
AI Technical Summary
Technical Problem
Implementing Min-Sum and Bit-Flipping algorithms for error correction in memory devices, such as SSDs, requires significant computational resources due to the use of flip-flops in LDPC decoders.
Method used
Replace edge-triggered D flip-flops with smaller level-triggered gated D latches in LDPC decoders, reducing the gate count and improving computational resource utilization by using latches in data correction decoders.
Benefits of technology
Reduces the gate count by approximately 1.5 gates per stored data bit, saving computational resources and enhancing the efficiency of LDPC decoders in memory devices.
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Smart Images
Figure US2025061299_02072026_PF_FP_ABST
Abstract
This application is directed to data validation and correction in an electronic device that includes an input data interface, a plurality of input latch units, a logic, and an output unit. The input data interface is configured to receive a plurality of check node data items each including parallel input bits. Each input latch unit corresponds to a respective check node data item and includes a plurality of parallel input latches configured to be controlled by a control signal to hold the parallel input bits of the respective check node data item. The logic configured to process the plurality of check node data items and generate a variable node data item including a plurality of parallel output bits. The output unit is configured to be controlled by the control signal to hold the parallel output bits of the variable node data item.
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