Package structure, packaging device, and electronic device

Abstract

A package structure, a packaging device, and an electronic device. The package structure comprises: a package substrate; a first stacked member, located on the package substrate and comprising a plurality of first chip groups; and a second stacked member, located on the package substrate and comprising a plurality of second chip groups. The first stacked member and the second stacked member are connected to a same signal channel, the number of first chip groups is different from the number of second chip groups, chips in the first chip groups belong to different columns, and chips in the second chip groups belong to different columns. The package structure has a small volume.

Description

Packaging structure, packaged device, electronic device

[0001] This application claims priority to Chinese Patent Application No. 202510007684.6, filed on January 2, 2025, entitled "Packaging Structure, Packaging Device, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a packaging structure, a packaging device, and an electronic device. Background Technology

[0003] Recently, the demand for portable devices in the electronics market has increased rapidly, leading to a growing need for miniaturization and weight reduction of electronic components installed in electronic products. However, as the storage capacity required by electronic components increases, their size also increases. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a packaging structure is provided, comprising:

[0005] Packaging substrate;

[0006] The first stack is located on the packaging substrate and includes a plurality of first chipsets;

[0007] The second stack is located on the packaging substrate and includes multiple second chipsets;

[0008] The first stack and the second stack are connected to the same signal channel. The number of the first chipset is different from the number of the second chipset. The chips in the first chipset belong to different columns, and the chips in the second chipset belong to different columns.

[0009] In some embodiments, each of the first chipsets is connected to each data signal, multiple first chipsets are connected to the same control signal, each of the second chipsets is connected to each data signal, and multiple second chipsets are connected to the same control signal.

[0010] In some embodiments, the first chipset includes:

[0011] Chip removal;

[0012] The upper chip is offset on the lower chip;

[0013] The lower chip and the upper chip are connected by leads, and the leads are connected to the packaging substrate.

[0014] In some embodiments, in the vertical direction, the projection areas of a plurality of first chipsets overlap, and the projection areas of a plurality of second chipsets overlap.

[0015] In some embodiments, the structure of the upper chip is the same as that of the lower chip, and the lower chip includes:

[0016] Multiple edge data pads are located on the side of the lower chip;

[0017] Multiple intermediate data pads are located at the center of the lower chip;

[0018] Each of the edge data pads is connected to each of the intermediate data pads via signal traces.

[0019] In some embodiments, the lower chip includes:

[0020] Multiple edge control signal pads are located on the side of the lower chip;

[0021] Multiple intermediate control signal pads are located at the center of the lower chip;

[0022] Each of the edge control signals is connected to each of the intermediate control signal pads via metal traces.

[0023] In some embodiments, the plurality of edge control signal pads and the plurality of edge data pads are located on the same straight line.

[0024] In some embodiments, a ground pad or a power pad is provided between adjacent edge data pads and between adjacent edge control signal pads.

[0025] In some embodiments, two adjacent chips in the first stack belong to different columns, two adjacent chips in the second stack belong to different columns, and some chips in the first stack and some chips in the second stack belong to the same column.

[0026] In some embodiments, the first stack or the second stack may further include a virtual chipset to make the height of the first stack and the height of the second stack the same.

[0027] According to a second aspect of the present disclosure, a packaging device is provided, comprising:

[0028] Packaging substrate;

[0029] The first stack is located on the packaging substrate and includes a plurality of first chipsets;

[0030] The second stack is located on the packaging substrate and includes multiple second chipsets;

[0031] A first lead connects each of the first chipsets to the packaging substrate;

[0032] The second lead connects each of the second chipsets to the packaging substrate;

[0033] The first stack and the second stack are connected to the same signal channel. The number of the first chipset is different from the number of the second chipset. The chips in the first chipset belong to different columns, and the chips in the second chipset belong to different columns.

[0034] In some embodiments, the chips in the first chipset are connected via the first lead, and the chips in the second chipset are connected via the second lead.

[0035] In some embodiments, the first chipset includes:

[0036] The lower chip is located on the packaging substrate;

[0037] The upper chip is offset on the lower chip, exposing the lower edge signal pads on the lower chip;

[0038] The packaging substrate is provided with contact signal pads, and the upper edge signal pad is provided on the side of the upper chip.

[0039] The first lead connects the contact signal pad, the lower edge signal pad, and the upper edge signal pad.

[0040] In some embodiments, the lower chip further includes a lower intermediate signal pad, which is connected to a lower edge signal pad via a lower metal trace, and the upper chip further includes an upper intermediate signal pad, which is connected to the lower edge signal pad via an upper metal trace.

[0041] In some embodiments, ground pads or power pads are provided between the lower edge signal pads and between the upper edge pads.

[0042] In some embodiments, a plurality of first chipsets are stacked and connected to the same first control signal pad on the packaging substrate via the first lead, and a plurality of second chipsets are stacked and connected to the same second control signal pad on the packaging substrate via the second lead.

[0043] According to a third aspect of the present disclosure, an electronic device is provided, comprising:

[0044] Motherboard, including the processor;

[0045] A semiconductor package is soldered onto the motherboard, and the processor communicates with the semiconductor package via a signal channel.

[0046] The semiconductor package is the above-described packaging structure or the above-described packaging device.

[0047] In summary, this disclosure provides a packaging structure, a packaging device, and an electronic device. The packaging structure includes a first stack and a second stack, which share the same signal channel. The number of first chipsets in the first stack differs from the number of second chipsets in the second stack. Furthermore, the chips in the first chipsets belong to different columns, and the chips in the second chipsets belong to different columns. This allows the first and second chipsets to use different data signals, thereby reducing the path of data signals within the same chipset and minimizing signal loss. Additionally, since this packaging structure can include two sets of chip stacks, the height of the packaging structure can be reduced, thus decreasing the package size. Attached Figure Description

[0048] Figure 1A is a schematic diagram of an electronic device according to an exemplary embodiment;

[0049] Figure 1B is a schematic diagram of a first storage block according to an exemplary embodiment;

[0050] Figure 2 is a schematic diagram of a packaging structure according to an exemplary embodiment;

[0051] Figure 3 is a schematic diagram of the first stack in Figure 2 in the X direction according to an exemplary embodiment;

[0052] Figure 4 is a schematic diagram of the second stack in Figure 3 in the X direction according to an exemplary embodiment;

[0053] Figure 5 is a top view of a first stacked component according to an exemplary embodiment;

[0054] Figure 6 is a schematic diagram of the first bonding pad in Figure 5 in the X direction according to an exemplary embodiment;

[0055] Figure 7 is a schematic diagram of the third bonding pad in Figure 5 in the X direction according to an exemplary embodiment;

[0056] Figure 8 is a schematic diagram of a first upper chip according to an exemplary embodiment;

[0057] Figure 9 is another schematic diagram of a first stack and a second stack according to an exemplary embodiment;

[0058] Figure 10 is another schematic diagram of a first stacked component according to an exemplary embodiment;

[0059] Figure 11 is a schematic diagram of a packaged device according to an exemplary embodiment;

[0060] Figure 12 is a schematic diagram illustrating a fourth bonding pad according to an exemplary embodiment;

[0061] Figure 13 is a schematic diagram of a packaged device according to an exemplary embodiment;

[0062] Figure 14 is another schematic diagram of a packaged device according to an exemplary embodiment;

[0063] Figure 15 is another schematic diagram of an electronic device according to an exemplary embodiment. Detailed Implementation

[0064] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0065] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0066] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0067] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0068] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0069] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0070] In related technologies, semiconductor chips can be stacked to increase the storage capacity of semiconductor products. However, as the number of semiconductor chips increases, the electrical connections between these semiconductor chips become relatively complex, which also leads to signal loss in the semiconductor chips.

[0071] As shown in Figure 1A, this disclosure presents an electronic device 10. This electronic device 10 can be used in a personal computer or a mobile electronic device. The mobile electronic device can be a laptop computer, mobile phone, smartphone, tablet PC, personal digital assistant (PDA), enterprise digital assistant (EDA), digital still camera, digital video camera, portable multimedia player (PMP), personal navigation device or portable navigation device (PND), handheld game console, mobile internet device (MID), wearable computer, Internet of Things (IoT) device, Internet of Everything (IoE) device, and / or drone.

[0072] As shown in Figure 1A, the electronic device 10 may include a processor 11 and a memory system 12. The processor 11 is the primary component of the electronic device 10, used to process and manage instructions, such as for executing operating systems and applications. The processor 11 may be configured to distribute workloads across multiple computing entities for parallel processing to solve complex operations or tasks, such as in a distributed computing environment. The processor 11 is a functional block, firmware, or a combination thereof configured to execute one or more machine-executable commands or software segments. The processor 11 may be implemented using hardware (i.e., various circuit elements and devices) that perform computations and other operations (e.g., control operations or configuration operations) in the electronic device 10. The processor 11 may be implemented as an integrated circuit (IC), a system-on-a-chip (SoC), an application processor (AP), a mobile AP, a chipset, and / or a set of chips. In some embodiments, the processor 110 may be a semiconductor device performing memory control functions and may include a memory controller. The processor 11 may further include random access memory (RAM), a central processing unit (CPU), a graphics processing unit (GPU), and / or a modem.

[0073] As shown in Figure 1A, the memory system 12 may include a first memory block 121 and a second memory block 122. The first memory block 121 and the second memory block 122 may have the same structure. Either the first memory block 121 or the second memory block 122 may include multiple memory dies 102. These memory dies 102 are all disposed on the package substrate 101. In this embodiment, the first memory block 121 and the second memory block 122 may be divided into different ranks, with the first memory block 121 belonging to rank 0 and the second memory block 122 belonging to rank 1. Alternatively, the first memory block 121 may belong to rank 1 and the second memory block 122 may belong to rank 0. In this embodiment, a "rank" may be a collection, grouping, or other organization of memory dies in the memory system 12. Each rank may include one or more memory dies, and the number of memory dies associated with each rank may be the same or different. In this example embodiment, the memory system 12 is shown as having a dual-rank structure, but is not limited to this, and may have various other rank structures.

[0074] As shown in Figure 1A, the processor 11 communicates with the memory system 12 via signal channel 13. Channel 13 can be a bus, which includes command / address signal lines for transmitting command / address (CMD / ADDR), data transmission (DQ), and clock signal lines for transmitting data clock signals (WCK and WCKB) and read clock signals (RDQS and RDQSB). Channel 13 may further include clock signal lines for transmitting clock signals (CK and CKB), and chip select signal lines for transmitting chip select signals (CS0 and CS1) to distinguish between the first memory block 121 (rank0) and the second memory block 122 (rank1), respectively. The WCK and WCKB clock signals are complementary, the RDQS and RDQSB clock signals are complementary, and the CK and CKB clock signals are complementary. Clock signals can be defined as "complementary" when the rising edge of the first clock signal is synchronized with the falling edge of the second clock signal, and when the rising edge of the second clock signal is synchronized with the falling edge of the first clock signal. The first storage block 121 and the second storage block 122 can share the clock signal line, command / address signal line and data line of the signal channel 13.

[0075] As shown in Figure 1B, to increase the storage capacity of the electronic device 10, it is necessary to increase the storage capacity of the first storage block 121. The first storage block 121 has a large number of memory dies 102 disposed on the packaging substrate 101. For example, multiple memory dies 102 are disposed on the packaging substrate 101. These memory dies 102 can be DRAM. Since these memory dies 102 in Figure 1B are individually fixed on the packaging substrate 101, increasing the storage capacity will also increase the size of the first storage block 121, which is not conducive to applying the first storage block 121 to the miniaturized electronic device 10.

[0076] As shown in Figure 2, this disclosure presents a packaging structure 100 with a small volume, suitable for use in miniaturized electronic devices. The packaging structure 100 may include a packaging substrate 101, a first stack 200, and a second stack 300. Both the first stack 200 and the second stack 300 are disposed on the packaging substrate 101. The first stack 200 and the second stack 300 can be arranged side-by-side. Since this packaging structure 100 can replace the first memory block 121 in Figure 1A, the first stack 200 and the second stack 300 can share the same signal channel. Both the first stack 200 and the second stack 300 include multiple memory chips, thereby increasing the storage capacity of the packaging structure 100. Simultaneously, the first stack 200 and the second stack 300 occupy a small area of ​​the packaging substrate 101, and since they are arranged side-by-side (not stacked), the height of the packaging structure 100 is small, thus reducing the packaging volume. In the Y direction, the spacing between the first stack 200 and the second stack 300 can be between 800-1200um, for example, 900um, 1000um, or 1100um, thereby ensuring a small spacing between the first stack 200 and the second stack 300.

[0077] As shown in Figure 3, Figure 3 is a schematic diagram of the structure of the first stack 200 in Figure 2 in the X direction. The first stack 200 may include multiple first chipsets 201. For example, Figure 3 shows that the first stack 200 includes two first chipsets 201, or it may include three or more first chipsets 201. These first chipsets 201 have the same structure. These first chipsets 201 can be stacked on the packaging substrate 101. The first chipset 201 may include a first lower chip 203 and a first upper chip 204. The first lower chip 203 can be fixed to the packaging substrate 101 by a first adhesive layer 202, and the first upper chip 204 can be fixed to the first lower chip 203 by the first adhesive layer 202. The first lower chip 203 and the first upper chip 204 can be the same memory chip, for example, both are DRAM, such as DDR5 or DDR6. The first adhesive layer 202 can be a DAF (Digital Adhesive Layer). The first upper chip 204 can be offset onto the first lower chip 203. For example, in the X direction, the first upper chip 204 is offset relative to the first lower chip 203, thereby exposing the pads on the side of the first lower chip 203. In this embodiment, the first stack 200 includes four chips. The two first lower chips 203 are aligned in the Z direction (vertical direction) and aligned in the X direction (horizontal direction). The two first upper chips 204 are aligned in the Z direction (vertical direction) and aligned in the X direction (horizontal direction). That is, in the vertical direction, the projection areas of the two first chip groups 201 overlap. Thus, in the horizontal direction, the upper first chip group 201 will not exceed the lower first chip group 201. Therefore, the first stack 200 can reduce its horizontal dimensions, thereby reducing the package volume.

[0078] As shown in Figure 4, which is a schematic diagram of the second stack 300 in Figure 2 in the X direction, the second stack 300 may include a plurality of second chipsets 301, for example, three or more second chipsets 301. These second chipsets 301 are stacked. The structures of these second chipsets 301 may be identical. Each second chipset 301 may include a second lower chip 303 and a second upper chip 304, which may be the same memory chip. The second lower chip 303 is fixed to the packaging substrate 101 by a second adhesive layer 302, and the second upper chip 304 is fixed to the second lower chip 303 by the second adhesive layer 302. In the horizontal direction, the second upper chip 304 is offsetly disposed on the second lower chip 303. In this embodiment, the second stack 300 may include six memory chips, with three second lower chips 303 aligned in the Z direction (vertical direction) and aligned in the X direction (horizontal direction). The three second upper chips 304 are aligned in the Z direction (vertical direction) and in the X direction (horizontal direction). That is, in the vertical direction, the projection areas of the three second chipsets 301 overlap. Thus, in the horizontal direction, the upper second chipset 301 will not exceed the lower second chipset 301. Therefore, the second stack 300 can reduce the horizontal dimension and thus reduce the package volume.

[0079] As shown in Figures 2-4, the first stack 200 and the second stack 300 are arranged side by side. The first stack 200 includes two first chipsets 201, and for example, includes four memory chips. The second stack 300 includes three second chipsets 301, and for example, includes six memory chips. The structure of the second chipsets 301 can also be the same as that of the first chipsets 201. The structure of the first lower chip 203 in the first stack 200 can be the same as that of the second lower chip 303 in the second stack 300, that is, the first lower chip 203 and the second lower chip 303 can be the same memory chip. At the same time, the first upper chip 204 and the second upper chip 304 can be the same memory chip, and the first adhesive layer 202 and the second adhesive layer 302 are made of the same adhesive material. The first stack 200 and the second stack 300 are arranged side by side, which can reduce the package size compared to stacking these chips into a single stack.

[0080] As shown in Figures 3 and 4, the first stack 200 includes, for example, four memory chips, namely, a first lower chip 203, a first upper chip 204, and a first upper chip 204 in the Z direction. To better facilitate data signal transmission, adjacent memory chips belong to different ranks. Specifically, in the vertical direction, from bottom to top, the first lower chip 203 belongs to the first column (rank 0), and the first upper chip 204 belongs to the second column (rank 1). Thus, the two memory chips in the first chipset 201 belong to different columns. Of course, the first lower chip 203 can belong to the second column, and the first upper chip 204 can belong to the first column. The second stack 300 includes, for example, six memory chips, namely, in the Z direction, a second lower chip 303, a second upper chip 304, a second lower chip 303, a second upper chip 304, a second lower chip 303, and a second upper chip 304. To better facilitate data transmission, adjacent memory chips belong to different ranks. That is, in the vertical direction, from bottom to top, the second lower chip 303 belongs to the first column (rank 0), and the second upper chip 304 belongs to the second column (rank 1). In other words, the two memory chips in the second chipset 301 belong to different columns. Of course, the second lower chip 303 can belong to the second column, and the second upper chip 304 can belong to the first column. In this embodiment, the first lower chip 203 in the first stack 200 can belong to the same column (rank 0) as the second lower chip 303 in the second stack 300, and the first upper chip 204 in the first stack 200 can belong to the same column (rank 1) as the second upper chip 304 in the second stack 300. This allows some memory chips in the first stack 200 and some memory chips in the second stack 300 to belong to the same column (rank). Since some memory chips in the first stack 200 and some memory chips in the second stack 300 belong to the same column, when data is transmitted between the first stack 200 and the second stack 300, the data can be stored in memory chips belonging to the same column in both stacks, thus ensuring data consistency.

[0081] As shown in Figures 5 and 6, Figure 5 is a top view of the first stack 200, and Figure 6 is a cross-sectional view of the first stack 200. Since the structures of the first stack 200 and the second stack 300 are basically the same, this embodiment uses the first stack 200 as an example to illustrate the connection relationship between the first stack 200 and the packaging substrate 101. The packaging substrate 101 may include a first bonding pad 104 and a second bonding pad 105, that is, two rows of bonding pads are arranged side by side on the packaging substrate 101. The first bonding pad 104 is closer to the side of the packaging substrate 101 than the second bonding pad 105. There is a lower edge pad 206 on the side of the first lower chip 203, and an upper edge pad 205 on the side of the first upper chip 204. The first upper chip 204 is offset relative to the first lower chip 203, thereby exposing the lower edge pad 206 on the first lower chip 203. The lower edge pad 206 and the upper edge pad 205 are correspondingly set, that is, one upper edge pad 205 corresponds to one lower edge pad 206. The lower edge pad 206 on the upper first lower chip 203 is electrically connected to the first bonding pad 104 on the packaging substrate 101 through the first upper lead 209. At the same time, the first upper lead 209 is also connected to the upper edge pad 205 on the upper first upper chip 204. That is, the two memory chips in the upper first chipset 201 are electrically connected through the first upper lead 209, and then electrically connected to the packaging substrate 101 through the first upper lead 209. The lower edge pad 206 on the first lower chip 203 is electrically connected to the second bonding pad 105 on the packaging substrate 101 via a first lower lead 210. Simultaneously, this first lower lead 210 is also connected to the upper edge pad 205 on the first upper chip 204. That is, the two memory chips in the lower first chipset 201 are electrically connected via the first lower lead 210, and then electrically connected to the packaging substrate 101 via the same first lower lead 210. In this embodiment, the first upper lead 209 and the first lower lead 210 can be defined as first leads, and the first bonding pad 104 and the second bonding pad 105 can be defined as contact signal pads. It should be noted that the black dots in the first bonding pad 104 in Figure 5 are the solder joints of the first upper lead 209 on the first bonding pad 104.

[0082] As shown in Figure 6, this embodiment uses the first chipset 201 as an example to illustrate data signal transmission. The first upper chip 204, for example, belongs to the first column (rank 0), and the first lower chip 203, for example, belongs to the second column (rank 1). The data signal (DQ) can be transmitted from the first bonding pad 104 to the first lower chip 203 and the first upper chip 204 via the first upper lead 209. In some embodiments, the data DQ received by the first stack 200 includes an 8-bit data width, which can be divided into 4-bit low-order byte data DQ0-DQ3 and 4-bit high-order byte data DQ4-DQ7. During data transmission, a chip selection signal is used to select either the first column or the second column to store this data. For example, the 4-bit low-order byte data DQ0-DQ3 and the 4-bit high-order byte data DQ4-DQ7 can be stored in the first upper chip 204 or the first lower chip 203. In some embodiments, the data DQ received by the first stack 200 includes a 16-bit data width, which can be divided into 8-bit low-order byte data DQ0 to DQ7 and 8-bit high-order byte data DQ8 to DQ15. The 8-bit low-order byte data DQ0 to DQ7 and the 8-bit high-order byte data DQ8 to DQ15 can be stored in the first lower chip 203 or the first upper chip 204.

[0083] As shown in Figures 5 and 7, a third bonding pad 106 is also provided on the packaging substrate 101. The width of the third bonding pad 106 in the X direction is greater than the sum of the widths of the first bonding pad 104 and the second bonding pad 105, thus making the area of ​​the third bonding pad 106 larger than the sum of the areas of the first bonding pad 104 and the second bonding pad 105, i.e., the area of ​​the third bonding pad 106 is relatively large. An upper edge control signal pad 207 is also provided on the side of the first upper chip 204, and a lower edge control signal pad 208 is also provided on the side of the first lower chip 203. The upper edge control signal pad 207 can be aligned with the upper edge pad 205, i.e., the upper edge control signal pad 207 and the upper edge pad 205 are on the same straight line. The lower edge control signal pad 208 can be aligned with the lower edge pad 204, i.e., the lower edge control signal pad 208 and the lower edge pad 204 are on the same straight line. The upper edge control signal pad 207 on the upper first chip 204 is connected to the lower edge control signal pad 208 on the upper first lower chip 203 via a first upper lead 209. That is, the two chips in the upper first chipset 201 are connected via the first upper lead 209, which is also connected to the third bonding pad 106. Similarly, the upper edge control signal pad 207 on the lower first chip 204 is connected to the lower edge control signal pad 208 on the lower first lower chip 203 via a first lower lead 210. That is, the two chips in the lower first chipset 201 are connected via the first lower lead 210, which is also connected to the third bonding pad 106. In this embodiment, since the third bonding pad 106 is used to transmit control signals, the upper first chipset 201 and the lower first chipset 201 can be connected to the same control signal pad. The third bonding pad 106 can also be called the first control signal pad. The third bonding pad 106 can be used to transmit CA (CMD / ADDR) signals of rank 0 and rank 1. It should be noted that the dots on the third bonding pad 106 in Figure 5 are the solder joints of the first upper lead 209 on the third bonding pad 106.

[0084] As shown in Figure 8, in some embodiments, an intermediate signal pad 211 and an intermediate control signal pad 212 are provided on the middle region of the first upper chip 204. The intermediate signal pad 211 and the intermediate control signal pad 212 can be on the same straight line. The signal is transmitted to the first upper chip 204 after passing through the intermediate signal pad 211 and the intermediate control signal pad 212. Of course, other signal pads can also be provided on the middle region of the first upper chip 204. At the same time, there is an upper edge pad 205 on the side of the first upper chip 204, which can include an upper edge power pad 205P, an upper edge signal pad 205S, and an upper edge ground pad 205G. The upper edge pad 205 can be connected to the middle signal pad 211 via the upper metal trace 213. That is, the upper edge power pad 205P can be connected to the middle power pad via the metal trace 213, the upper edge signal pad 205S can be connected to the middle signal pad via the upper metal trace 213, and the upper edge ground pad 205G can be connected to the middle ground pad via the upper metal trace 213. Simultaneously, adjacent upper edge signal pads 205S can be separated by the upper edge ground pad 205G or the upper edge power pad 205P; that is, the two upper edge signal pads 205S are not closely spaced, thereby improving crosstalk between signals. In some embodiments, an upper edge control signal pad 207 is also provided at the edge of the first upper chip 204, and the upper edge control signal pad 207 can be connected to the middle control signal pad 212 via the upper metal trace 213. Since the structure of the first upper chip 204 is the same as that of the first lower chip 203, the lower middle signal pad and the lower edge signal pad will also be set on the first lower chip 203. At this time, the lower middle signal pad can also be connected to the lower edge signal pad through the lower metal trace.

[0085] As shown in Figures 3-4 and 9, in this embodiment, the number of chips in the first stack 200 and the second stack 300 are different. For example, the first stack 200 includes four memory chips, and the second stack 300 includes six memory chips. In the first stack 200 and the second stack 300, the two memory chips in each chip group belong to different ranks, and the two memory chips in the same chip group are connected by leads, thereby reducing the data signal transmission path within the same chip group and reducing signal loss. In some embodiments, if the number of chips in the first stack 200 and the second stack 300 is the same, that is, both the first stack 200 and the second stack 300 include five memory chips (Figure 9). Figure 9(a) shows that the first stack 200 includes five first lower chips 203, and Figure 9(b) shows that the second stack 300 includes five second lower chips 303. In some embodiments, the five memory chips in the first stack 200 belong to the same column (rank 0), and the five memory chips in the second stack 300 belong to the same column (rank 1). In this case, each memory chip in the first stack 200 and the second stack 300 can be individually connected to the packaging substrate 101. This increases the data path length of the two chips in the first stack 200 and the second stack 300 that belong to the same data signal (DQ), thereby increasing signal loss. Since the first stack 200 and the second stack 300 in FIG. 9 include an odd number of memory chips, even if the first stack 200 and the second stack 300 adopt the connection method of FIG. 4, there will still be at least one group of chips belonging to the same data signal but in different columns in the first stack 200 and the second stack 300 respectively, thus increasing the signal transmission path of this group. Therefore, this embodiment uses an even number of memory chips in the first stack 200 and the second stack 300 respectively, thereby reducing the signal transmission path.

[0086] In some embodiments, if there is only one set of first chipsets 201 in the first stack 200, the second stack 300 can be provided with four sets of second chipsets 301. In this case, the height of the second stack 300 will be further increased, and the bonding wire of the uppermost second chipset 301 in the second stack 300 will also be longer, which is not conducive to reducing the package size.

[0087] As shown in Figure 10, in some embodiments, a virtual chipset 201a can also be provided on the first stack 200. The virtual chipset 201a may include two virtual chips 204a. The virtual chipset 204a is not used for storing signals. The virtual chipset 204a is located on the first chipset 201, thereby allowing the height of the first stack 200 to be the same as the height of the second stack 300, thus improving the warpage problem caused by the difference in height between the first stack 200 and the second stack 300. Of course, if the height of the second stack 300 is less than the height of the first stack 200, that is, the number of chipsets in the second stack 300 is less than the number of chipsets in the first stack 200, the virtual chipset 201a can also be provided on the second stack 300 to improve the warpage problem.

[0088] As shown in Figure 11, this disclosure also discloses another packaging device 1000, which may include a packaging substrate 101, a first stack 200, and a second stack 300. The first stack 200 and the second stack 300 are placed on the packaging substrate 101. The first stack 200 is connected to a packaging pad 216 on the packaging substrate 101 via a first lead 214. The second stack 300 is connected to the packaging pad 216 on the packaging substrate 101 via a second lead 215. The first lead 214 and the second lead 215 are located on the same side of the packaging substrate 101. The first stack 200 and the second stack 300 are connected to different packaging pads 216. The structure of the first stack 200 can be referred to Figure 3, and the structure of the second stack 300 can be referred to Figure 4. The first lead 214 may include a first upper lead 209 and a first lower lead 210. The first upper lead 209 and the first lower lead 210 can be referred to Figure 6. Since the first stack 200 and the second stack 300 have the same wiring method, the second lead 215 can also refer to the first lead 214.

[0089] As shown in Figures 5, 6, and 11, in this embodiment, the package pad 216 may include a first bonding pad 104, a second bonding pad 105, and a third bonding pad 106. The first bonding pad 104 is connected to the lower edge signal pad 206 on the upper first lower chip 203 via a first upper lead 209, and the first upper lead 209 is also connected to the upper edge signal pad 205 on the upper first upper chip 204. The second bonding pad 105 is connected to the lower edge signal pad 206 on the lower first lower chip 203 via a first lower lead 210, and the first lower lead 210 is also connected to the upper edge signal pad 205 on the lower first upper chip 204. Simultaneously, the two chip groups in the first stack 200 are connected to the same third bonding pad 106 via the first upper lead 209 and the first lower lead 210, respectively. In this embodiment, the first bonding pad 104 and the second bonding pad 105 can also be referred to as contact signal pads, and the third bonding pad 106 can be defined as the first control signal pad.

[0090] As shown in Figure 12, the packaging substrate 101 may further include a fourth bonding pad 217, a fifth bonding pad 218, a sixth bonding pad 219, and a second control signal pad 220. Multiple fourth bonding pads 217, multiple fifth bonding pads 218, multiple sixth bonding pads 219, and multiple second control signal pads 220 can be arranged in a row. The fourth bonding pads 217, fifth bonding pads 218, sixth bonding pads 219, and second control signal pads 220 are used to provide signals to the second stack 300. The fourth bonding pads 217, fifth bonding pads 218, sixth bonding pads 219, and second control signal pads 220 can be located on the same side of the packaging substrate 101. Simultaneously, the first bonding pad 104 can be located in the same row as the fifth bonding pad 218, and the second bonding pad 105 can be located in the same row as the sixth bonding pad 219. The fourth bonding pad 217 can be connected to the uppermost second chipset 301 in the second stack 300 via the second lead 215. The fifth bonding pad 218 can be connected to the middle second chipset 301 in the second stack 300 via the second lead 215. The sixth bonding pad 219 can be connected to the lowermost second chipset 301 in the second stack 300 via the second lead 215. The second control signal pad 220 can be connected to all the second chipsets 301 via the second lead 215, meaning that the three second chipsets 301 in the second stack 300 are connected to the same second control signal pad 220.

[0091] As shown in Figure 13, in this embodiment, the first stack 200 and the second stack 300 are disposed on the front side of the packaging substrate 101, and an external terminal 1011 is disposed on the back side of the packaging substrate 101. The external terminal 1011 can be a solder ball, solder bump, microbump, etc. The packaging device 1000 can be directly soldered to the motherboard (PCB) through the external terminal 1011. The packaging device 1000 can be a ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric square flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), and wafer-level processing stacked package (WSP).

[0092] As shown in Figure 14, this disclosure also discloses another packaging device 1000. The packaging device 1000 may include a packaging substrate 101, a first stack 200, and a second stack 300. The first stack 200 and the second stack 300 are located on the front side of the packaging substrate 101. The first stack 200, for example, includes four first lower chips 203, which are offset and stacked to form a stepped shape. The first stack 200 may include two chip groups, with the lower two first lower chips 203 forming one chip group and the upper two first lower chips 203 forming another chip group. Two chips within each chip group are connected by a first lead 214 and also connected to the packaging substrate 101 via the first lead 214. The second stack 300, for example, includes six second lower chips 303, which are offset and stacked to form a stepped shape. The offset direction of the first stack 200 is opposite to the offset direction of the second stack 300. The second stack 300 may include three chipsets: the bottom two second lower chips 303 form one chipset, the top two second lower chips 303 form another chipset, and the middle two second lower chips 303 form yet another chipset. Two chips within each chipset are connected via a second lead 215, and are also connected to the package substrate 101 via the same second lead 215. The second lead 215 and the first lead 214 are located on opposite sides of the package substrate 101. External terminals 1011, such as solder balls, are located on the back side of the package substrate 101, allowing the packaged device 1000 to be directly mounted to the motherboard.

[0093] As shown in Figure 14, in this embodiment, the first stack 200 and the second stack 300 are disposed on the packaging substrate 101. The memory chips in the first stack 200 are offset towards the second stack 300, and the memory chips in the second stack 300 are offset towards the first stack 200. Since the number of memory chips in the first stack 200 and the second stack 300 is different, the heights of the first stack 200 and the second stack 300 are different. Consequently, the first protrusion 221 of the first stack 200 is located directly below the second protrusion 222 of the second stack 300, that is, the second protrusion 222 and the first protrusion 221 overlap vertically. In this embodiment, the first protrusion 221 is the protruding portion of the uppermost first lower chip 203 in the first stack 200, and the second protrusion 222 is the protruding portion of the uppermost second lower chip 303 in the second stack 300. In this embodiment, the first protrusion 221 can protrude toward the second stack 300, and the second protrusion 222 can protrude toward the first stack 200. Therefore, the first protrusion 221 can be located directly below the second protrusion 222 and can be spaced apart from the second protrusion 221, such that the first protrusion 221 and the second protrusion 222 overlap each other in the vertical direction. Therefore, the first stack 200 and the second stack 300 are arranged side by side on the packaging substrate 101, which can also reduce the total width of the first stack 200 and the second stack 300, thereby reducing the width of the packaging device 1000 and thus reducing the packaging volume.

[0094] As shown in Figure 15, this disclosure also discloses another electronic device 10, which may include a motherboard 15. The motherboard 15 has a processor 11 and multiple semiconductor packages 14. The processor 11 communicates with the multiple semiconductor packages 14 through a signal channel 13. The structure of the semiconductor package 14 can refer to the packaged device 1000 described above. The electronic device 10 may include one or more of the following: for example, smartphones, tablet PCs, mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable multimedia players (PMPs), MPEG-1 audio layer 3 (MP3) players, mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices may be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices may be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted devices (HMDs). The electronic device 10 can also be used in large servers, such as data centers, AI computers, and other fields.

[0095] In summary, this disclosure provides a packaging structure comprising two stacked components arranged side-by-side. This results in a lower height for each individual stacked component, reducing the overall size of the packaging structure. The packaging structure includes a first stacked component and a second stacked component, which share a common signal channel. The number of first chipsets in the first stacked component differs from the number of second chipsets in the second stacked component. Furthermore, the chips in the first chipsets belong to different columns, and the chips in the second chipsets belong to different columns. This allows the first and second chipsets to use different data signals, thereby shortening the data signal path within the same chipset and reducing signal loss.

[0096] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A packaging structure (100), comprising: Packaging substrate (101); A first stack (200) is located on the packaging substrate and includes a plurality of first chipsets (201); The second stack (300) is located on the packaging substrate and includes a plurality of second chipsets (300); The first stack and the second stack are connected to the same signal channel. The number of the first chipset is different from the number of the second chipset. The chips in the first chipset belong to different ranks, and the chips in the second chipset belong to different ranks.

2. The packaging structure according to claim 1, wherein, Each of the first chipsets is connected to each data signal, and multiple first chipsets are connected to the same control signal. Each of the second chipsets is connected to each data signal, and multiple second chipsets are connected to the same control signal.

3. The packaging structure according to claim 1 or 2, wherein, The first chipset includes: Chip removal; The upper chip is offset on the lower chip; The lower chip and the upper chip are connected by leads, and the leads are connected to the packaging substrate.

4. The packaging structure according to claim 3, wherein, In the vertical direction, the projection areas of multiple first chipsets overlap, and the projection areas of multiple second chipsets overlap.

5. The packaging structure according to claim 3, wherein, The upper chip has the same structure as the lower chip, and the lower chip includes: Multiple edge data pads are located on the side of the lower chip; Multiple intermediate data pads are located at the center of the lower chip; Each of the edge data pads is connected to each of the intermediate data pads via signal traces.

6. The packaging structure according to claim 5, wherein, The lower chip includes: Multiple edge control signal pads are located on the side of the lower chip; Multiple intermediate control signal pads are located at the center of the lower chip; Each of the edge control signals is connected to each of the intermediate control signal pads via metal traces.

7. The packaging structure according to claim 5 or 6, wherein, The multiple edge control signal pads and the multiple edge data pads are located on the same straight line.

8. The packaging structure according to claim 5 or 6, wherein, Grounding pads or power pads are provided between adjacent edge data pads and between adjacent edge control signal pads.

9. The packaging structure according to claim 1, wherein, In the first stack, two adjacent chips belong to different columns; in the second stack, two adjacent chips belong to different columns; and some chips in the first stack and some chips in the second stack belong to the same column.

10. The packaging structure according to claim 1, wherein, The first or second stack also includes a virtual chipset to make the height of the first stack and the height of the second stack the same.

11. A packaged device (1000), comprising: Packaging substrate (101); A first stack (200) is located on the packaging substrate and includes a plurality of first chipsets (201); The second stack (300) is located on the packaging substrate and includes a plurality of second chipsets (301); A first lead (214) connects each of the first chipsets to the packaging substrate; The second lead (215) connects each of the second chipsets to the packaging substrate; The first stack and the second stack are connected to the same signal channel. The number of the first chipset is different from the number of the second chipset. The chips in the first chipset belong to different ranks, and the chips in the second chipset belong to different ranks.

12. The packaging device according to claim 11, wherein, The chips in the first chipset are connected via the first lead, and the chips in the second chipset are connected via the second lead.

13. The packaging device according to claim 11, wherein, The first chipset includes: The lower chip is located on the packaging substrate; The upper chip is offset on the lower chip, exposing the lower edge signal pads on the lower chip; The packaging substrate is provided with contact signal pads, and the upper edge signal pad is provided on the side of the upper chip. The first lead connects the contact signal pad, the lower edge signal pad, and the upper edge signal pad.

14. The packaging device according to claim 13, wherein, The lower chip also includes a lower intermediate signal pad, which is connected to the lower edge signal pad via a lower metal trace. The upper chip also includes an upper intermediate signal pad, which is connected to the lower edge signal pad via an upper metal trace.

15. The packaged device according to claim 13 or 14, wherein, Grounding pads or power pads are provided between the lower edge signal pads and between the upper edge pads.

16. The packaged device according to claim 13 or 14, wherein, Multiple first chipsets are stacked together, and each of the multiple first chipsets is connected to the same first control signal pad on the packaging substrate via the first lead. Multiple second chipsets are stacked together, and each of the multiple second chipsets is connected to the same second control signal pad on the packaging substrate via the second lead.

17. An electronic device (10), comprising: Motherboard (15), including processor (11); A semiconductor package (14) is soldered onto the motherboard, and the processor communicates with the semiconductor package through a signal channel; The semiconductor package includes the packaging structure (100) according to any one of claims 1-10, or the packaging device (1000) according to any one of claims 11-16.

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