Display panel and display apparatus

Abstract

A display panel (100) and a display apparatus (200). The display panel (100) comprises a base substrate (110), a driving circuit layer (120), a display film layer (130), an encapsulation film layer (140), an encapsulation blocking dam (150), a planarization layer (160), and a touch routing layer (170), wherein the planarization layer (160) is provided with a via hole (180) in a region where the encapsulation blocking dam (150) is located, and the touch routing layer (170) extends towards an edge of the display panel (100) along the via hole (180). By means of providing the via hole (180) in the planarization layer (160), touch routing lines (171) have a good performance, and thus the display and touch effects of the display panel (100) are better.

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. CN202510004421X, filed on January 2, 2025, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0003] OLED (Organic Light Emitting Diode) display devices are widely used in various fields due to their lightweight, wide viewing angle, fast response, low-temperature resistance, high luminous efficiency, and the ability to fabricate flexible displays. With increasingly mature mass production technology, OLED display panels are gradually becoming the mainstream display panels.

[0004] For touch display panels, there are generally two types: embedded touch and external touch. In embedded touch panels, the touch wiring layer needs to be placed in the film layer of the display panel. When the touch wiring layer is placed on the planarization layer of the OLED display panel, the large height difference between the planarization layer and the film section of the bonding area or terminal side can cause the touch wiring layer to have broken lines or short circuits, affecting the display of the display panel. Summary of the Invention

[0005] The purpose of this application is to provide a display panel and display device. By setting vias on the planarization layer, the touch trace layer on the planarization layer extends downward from the encapsulation barrier layer, avoiding the problem of touch trace breakage and short circuit caused by process reasons in the cross section of the planarization layer. This results in good performance of the touch trace and better display and touch effects of the display panel.

[0006] This application discloses a display panel including a display area and a non-display area. The display panel further includes a substrate, a driving circuit layer, a display film layer, an encapsulation film layer, an encapsulation barrier dam, a planarization layer, and a touch wiring layer. The driving circuit layer is disposed on the substrate; the display film layer is disposed on the driving circuit layer; the encapsulation film layer is disposed on the display film layer and extends from the display area to the non-display area; the encapsulation barrier dam is disposed between the driving circuit layer and the encapsulation film layer and is located in the non-display area; the planarization layer is disposed on the encapsulation film layer, and the touch wiring layer is disposed on the planarization layer; wherein, the planarization layer has a via in the area where the encapsulation barrier dam is located, and the touch wiring layer extends along the via to the edge of the display panel.

[0007] This application discloses a display device, including a driving circuit and the aforementioned display panel, wherein the driving circuit is used to drive the display panel to display.

[0008] This application addresses issues such as overexposure or underexposure, uneven photoresist, and incomplete etching of the touch trace layer during the etching process, particularly when the touch trace layer extends downwards from the encapsulation barrier layer on the planarization layer. By reducing the height difference, this application lowers the probability of overexposure or underexposure, improves the uneven photoresist etching of the touch trace layer during patterning, and results in more uniform linewidths for the touch traces. It also avoids the problem of broken or short-circuited touch traces due to process variations caused by the planarization layer, thus enhancing the performance of the touch traces and improving the display and touch effects of the display panel. Attached Figure Description

[0009] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0010] Figure 1 is a schematic diagram of an exemplary display panel of this application;

[0011] Figure 2 is a schematic diagram of the display panel of the first embodiment of this application;

[0012] Figure 3 is a top view of the display panel of this application;

[0013] Figure 4 is an enlarged schematic diagram of M in Figure 3 of this application;

[0014] Figure 5 is a cross-sectional schematic diagram of the AA cutting line in Figure 4 of this application;

[0015] Figure 6 is a cross-sectional schematic diagram of the BB cutting line in Figure 4 of this application;

[0016] Figure 7 is a cross-sectional schematic diagram of another display panel according to the second embodiment of this application;

[0017] Figure 8 is a schematic diagram of the display device of this application. Detailed Implementation

[0018] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0019] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature specified as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. Furthermore, terms such as "upper," "lower," "left," "right," "vertical," and "horizontal," indicating orientation or positional relationships, are based on the orientation or relative positional relationships shown in the accompanying drawings and are only for the purpose of simplifying the description of this application, not indicating that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this application. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0020] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0021] Figure 1 is a schematic diagram of an exemplary display panel of this application, and Figure 2 is a schematic diagram of a display panel of a first embodiment of this application. Referring to Figures 1-2, this application discloses a display panel, which includes a display area and a non-display area. The display panel further includes a substrate 110, a driving circuit layer 120, a display film layer, an encapsulation film layer 140, an encapsulation barrier 150, a planarization layer 160, and a touch trace layer 170. The driving circuit layer 120 is disposed on the substrate 110; the display film layer is disposed on the driving circuit layer 120; the encapsulation barrier 150 is disposed on the encapsulation layer 160; the encapsulation barrier 150 is disposed on the display film ... A film layer 140 is disposed on the display film layer and extends from the display area to the non-display area; an encapsulation barrier 150 is disposed between the driving circuit layer 120 and the encapsulation film layer 140 and is located in the non-display area; a planarization layer 160 is disposed on the encapsulation film layer 140, and a touch trace layer 170 is disposed on the planarization layer 160; wherein, the planarization layer 160 has a via 180 in the area where the encapsulation barrier 150 is located, and the touch trace layer 170 extends along the via 180 to the edge of the display panel.

[0022] This application addresses issues such as overexposure or underexposure, uneven photoresist, and incomplete etching of the touch trace layer 170 by providing vias 180 on the planarization layer 160 and utilizing the height of the encapsulation barrier layer. This is particularly relevant during the etching process, where the touch trace layer 170 extends downwards from the encapsulation barrier layer. By reducing the height difference, this application lowers the probability of overexposure or underexposure, improves the uneven photoresist etching of the touch trace layer 170 during patterning, and results in more uniform linewidths for the touch traces 171 within the touch trace layer 170. Furthermore, it avoids the problem of broken or short-circuited touch traces 171 due to process variations at the cross-section of the planarization layer 160, thus enhancing the performance of the touch traces 171 and improving the display and touch effects of the display panel.

[0023] Referring to Figure 1, the height difference between the upper surface of the planarization layer 160 and the upper surface of the encapsulation barrier layer is less than the height difference between the upper surface of the planarization layer 160 and the upper surface of the display panel bonding side. Specifically, the display panel substrate 110 and the planarization layer 160 include a driving circuit layer 120, a display film layer, and an encapsulation film layer 140. When the planarization layer 160 descends directly to the bonding area at the edge of the display panel, there will be a large film layer step difference, forming the aforementioned cross-section, i.e., the side surface of the planarization layer 160. When the touch trace layer 170 provided on the planarization layer 160 extends from the planarization layer 160 to the bonding area of ​​the display panel, the film layer interface is relatively steep, i.e., the cross-section of the bonding area between the planarization layer 160 and the substrate 110 is relatively steep, which easily leads to broken lines and short circuits. In particular, when the cross-section is steeper, there is uneven photoresist during the etching of the touch trace 171, which tends to accumulate at lower levels, resulting in thinner photoresist closer to the top. During subsequent exposure, overexposure or underexposure occurs, resulting in more etching of the touch trace layer 170 towards the top and less etching towards the bottom. This causes the touch trace 171 to have a problem of being narrow at the top and wide at the bottom. In some cases, the top part is completely etched, which can easily lead to short circuits or open circuits.

[0024] This application utilizes the height of the encapsulation barrier layer to etch a via 180 into the planarization layer 160 at the encapsulation barrier layer location. The cross-section of the via 180 is not very steep, and the distance is relatively short, greatly reducing the possibility of the aforementioned problems, thereby improving the short circuit phenomenon in the touch wiring layer 170. On the other hand, the encapsulation barrier layer location can be used to pre-set a connection line 121. When etching the via 180, the connection line 121 connects to the touch wiring 171 from the via 180, realizing the electrical connection to the touch wiring layer 170.

[0025] In one embodiment, the via 180 can be configured as a large through slot or as multiple independent through holes. When the via 180 is a large through slot, multiple touch traces 171 in the touch trace layer 170 are connected to their respective connecting lines 121 through the through slot. When the via 180 is multiple independent through holes, each touch trace 171 is connected to a connecting line 121 through one through hole. Relatively speaking, the independent through-hole method allows each touch trace 171 to be set up individually, resulting in better insulation, but it is more difficult to manufacture.

[0026] Specifically, the driving circuit layer 120 includes a stack of multiple conductive layers and multiple insulating layers. Thin film transistors and driving lines are formed in the driving circuit layer 120, and pixel driving circuits for driving the light-emitting unit are formed through the thin film transistors and driving lines.

[0027] Figure 3 is a top view of the display panel of this application, Figure 4 is an enlarged view of M in Figure 3 of this application, Figure 5 is a cross-sectional view of the AA cutting line in Figure 4 of this application, and Figure 6 is a cross-sectional view of the BB cutting line in Figure 4 of this application. Referring to Figures 3-6, for a general display panel 100, the film layer position of the touch wiring layer 170 can also be set below the planarization layer 160, that is, the wiring is set from above the encapsulation layer and below the planarization layer 160, thereby avoiding the problem of short circuit and open circuit of the touch wiring layer 170 caused by the cross-section of the planarization layer 160. However, for the use of a partition structure in the non-display area 102 to isolate the organic light-emitting unit in the light-emitting unit, or to set a partition structure in the non-display area 102 to increase the moisture intrusion path, or to set a partition structure in the non-display area 102, after setting the partition structure in the non-display area 102, when the touch wiring layer 170 is formed on the partition structure, the touch wiring 171 will be broken due to the partition structure.

[0028] This application, by setting a planarization layer 160, can planarize the partition structure, allowing the touch wiring layer 170 to be placed on the planarization layer 160, thus avoiding the problem of broken touch wiring 171 at the location of the partition structure. Of course, this embodiment is not limited to the touch wiring layer 170. When it is necessary to form metal wiring above the partition structure, and the planarization layer 160 is needed to planarize the metal wiring, such metal wiring also falls within the protection scope of this embodiment.

[0029] In this embodiment, the planarization layer 160 can be used to fill the protruding partition portion between the conductive portion and the partition portion in the partition structure, so that it no longer has a partitioning function, allowing the touch trace 171 above the planarization layer 160 to pass smoothly. When the planarization layer 160 has a cross-sectional problem as in the previous embodiment, the solution in Embodiment 1 can also be used, which will not be described in detail here.

[0030] In another embodiment, multiple planarization layers 160 can be designed. After the bottom planarization layer 160 completes the planarization partition structure, a touch trace layer 170 is formed, and then another planarization layer 160 is formed to reduce the film height of the planarization layer 160 near the bonding area, so that the touch trace 171 can extend directly to the bonding area.

[0031] In this embodiment, a partition structure is used as an encapsulation barrier dam 150 for specific illustration.

[0032] This application discloses a display panel 100, which includes a display area 101 and a non-display area 102. The display panel further includes a substrate 110, a driving circuit layer 120, a display film layer 130, an encapsulation film layer 140, an encapsulation barrier 150, a planarization layer 160, and a touch trace layer 170. The driving circuit layer 120 is disposed on the substrate 110; the display film layer 130 is disposed on the driving circuit layer 120; and the encapsulation film layer 140 is disposed on the display film layer 130 and is formed by the... The display area 101 extends toward the non-display area 102; the encapsulation barrier 150 is disposed between the driving circuit layer 120 and the encapsulation film layer 140, and is located in the non-display area; the planarization layer 160 is disposed on the encapsulation film layer 140, and the touch trace layer 170 is disposed on the planarization layer 160; wherein, the planarization layer 160 has a via 180 in the area where the encapsulation barrier 150 is located, and the touch trace layer 170 extends along the via 180 toward the edge of the display panel.

[0033] Specifically, the encapsulation barrier 150 includes a first barrier 151 and a second barrier 152, wherein the first barrier 151 is disposed around the display area 101 and the second barrier 152 is disposed around the first barrier 151.

[0034] The encapsulation film layer 140 includes a first inorganic layer 141, an organic encapsulation layer 142, and a second inorganic layer 143. The organic encapsulation layer 142 is disposed between the first inorganic layer 141 and the second inorganic layer 143, and the second inorganic layer 143 is disposed on the first inorganic layer 141. The organic encapsulation layer 142 extends from the display area 101 to the non-display area 102 and is blocked by the first barrier dam 151. The first inorganic layer 141 and the second inorganic layer 143 extend from the display area 101 to the non-display area 102 and cover the first barrier dam 151 and the second barrier dam 152.

[0035] The main function of the encapsulation barrier 150 in this embodiment is to prevent the organic encapsulation layer 142 from diffusing outward. When the organic encapsulation layer 142 is manufactured by inkjet printing, it needs a certain amount of time to level and then cure. During the leveling process, the encapsulation barrier 150 is needed to block the diffusion to the edge of the display panel 100.

[0036] When the display panel 100 is formed using a maskless vapor deposition technique to create the light-emitting film layer, the encapsulation barrier 150 in this embodiment utilizes the partition structure in the maskless vapor deposition technique to achieve flow leveling barrier against the organic encapsulation layer 142. That is, it is formed synchronously with the partition structure of the display area 101.

[0037] The display film layer 130 includes a pixel definition layer 131, a conductive isolation structure 134, and multiple light-emitting units. The display area can be divided into an open area and a non-open area. The light-emitting units are disposed in the open area. Adjacent light-emitting units are separated by the pixel definition layer 131 and the conductive isolation structure 134. The pixel definition layer 131 is disposed on the driving circuit layer 120, and the conductive isolation structure 134 is disposed on the pixel definition layer 131. The conductive isolation structure 134 is formed in the same process as the first barrier dam 151 and the second barrier dam 152.

[0038] The first barrier 151 includes a first conductive part 1511 and a first partition part 1512. The first partition part 1512 is disposed on the first conductive part 1511, and the radial width of the first partition part 1512 is greater than the radial width of the first conductive part 1511. The second barrier 153 includes a second conductive part 1531 and a second partition part 1532. The second partition part 1532 is disposed on the second conductive part 1531, and the radial width of the second partition part 1532 is greater than the radial width of the second conductive part 1531.

[0039] The conductive isolation structure 134 includes a third conductive part 1341 and a third isolation part 1342. The third isolation part 1342 is disposed on the third conductive part 1341, and the radial width of the third isolation part 1342 is greater than the radial width of the third conductive part 1341.

[0040] The first conductive portion 1511, the second conductive portion 1531, and the third conductive portion 1341 of the above three components are formed in the same process, and the first partition portion 1512, the second partition portion 1532, and the third partition portion 1342 are formed in the same process. Specifically, after forming a pixel definition layer 131 on the driving circuit layer 120, conductive material and partition material are deposited sequentially over the entire surface. After deposition, a patterning process is performed. The partitions in the non-opening areas of the display area 101 and the partitions in the encapsulation barrier dam 150 area of ​​the non-display area 102 are retained, forming a first partition 1512, a second partition 1532, and a third partition 1342. Using the first partition 1512, the second partition 1532, and the third partition 1342 as protective layers, a wet etching process is performed on the conductive material, thereby forming a first partition 1512, a second partition 1532, and a third partition 1342 whose widths are greater than the widths of the first conductive part 1511, the second conductive part 1531, and the third conductive part 1341, respectively.

[0041] It is understood that the width of the third partition 1342 mentioned in the display area 101 refers to the width of the third partition 1342 between two adjacent light-emitting units. The width of the first partition 1512 mentioned in the non-display area 102 refers to the width in the direction from the display area 101 to the non-display area 102 and perpendicular to the edge of the display panel 100. In other words, the first partition 1512 is provided around the display area 101. Taking the direction of extension around as the length direction, the direction perpendicular to the length direction is the width direction, and the direction of film stacking is the thickness direction.

[0042] In this embodiment, the partition is a key structure used in maskless vapor deposition technology. By utilizing the fact that the upper part (e.g., the third partition 1342) of the conductive partition structure 134 is wider than the lower part (e.g., the third conductive part 1341), a mask is not required during the vapor deposition process, allowing the formation of multiple patterned light-emitting units in the light-emitting film layer fabrication process. Specifically, when forming the organic light-emitting layer in the light-emitting unit, the conductive partition structure 134 is used to separate the organic light-emitting layers of light-emitting units at different locations, forming multiple independently packaged light-emitting units. This conductive partition structure 134 is also referred to as a cantilever structure or eaves structure. For the cathode layer in the light-emitting unit, it can be connected through the third conductive part 1341 in the conductive partition structure 134, thereby forming front-side cathode layer wiring and reducing cathode resistance drop.

[0043] Because the first barrier 151 and the second barrier 152 are designed with isolation structures, when the touch trace 171 is formed above the barrier 150, the isolation function of the first barrier 151 and the second barrier 152 will cause the touch trace 171 to break. In this embodiment, a planarization layer 160 is also provided on the barrier 150, so that the touch trace 171 is designed to run along the planarization layer 160.

[0044] Furthermore, the second blocking dam 152 includes a plurality of spaced second blocking portions 153, which are insulated from each other; under the orthographic projection of the substrate 110, a plurality of vias 180 overlap with a plurality of second blocking portions 153 respectively; the driving circuit layer 120 is provided with a plurality of connecting lines 121, and the touch wiring layer 170 is electrically connected to the connecting lines 121 through the second blocking portions 153.

[0045] In this embodiment, the first barrier 151 is mainly used to block the organic encapsulation layer 142, and the second barrier 152 is mainly used to connect the touch wiring layer 170. Since each touch wiring 171 needs to be individually connected, the second barrier 152 needs to be configured as multiple second blocking parts 153, each second blocking part 153 connecting one touch wiring 171 to the connecting line 121. It is worth noting that the number of second blocking parts 153 is the same as the number of touch wiring 171. In areas where the touch wiring layer 170 is not present, the second barrier 152 remains a continuous, wraparound structure, with multiple spaced-apart second blocking parts 153 only present in the area where the touch wiring layer 170 is located.

[0046] In one embodiment, the touch wiring layer 170 is electrically connected to the connection line 121 through the second conductive portion 1531. That is, when forming the via 180, the second partition portion 1532, the first inorganic layer 141, and the second inorganic layer 143 above the second conductive portion 1531 are all opened up, so that the touch wiring 171 in the touch wiring layer 170 is directly connected to the second conductive portion 1531, and then connected to the connection line 121 provided on the driving circuit layer 120 through the second conductive portion 1531. The electrical signal is transmitted to the external driving chip by the connection line 121 provided on the driving circuit layer 120.

[0047] In another embodiment, the second partition 1532 is also formed of a conductive material, and the touch wiring layer 170 is electrically connected to the connecting line 121 through the second partition 1532 and the second conductive part 1531. In this embodiment, the second partition 1532 does not need to be drilled, and can be directly connected to the connecting line 121 below the second conductive part 1531 through the second partition 1532 and the second conductive part 1531.

[0048] In this embodiment, it is no longer necessary to drill holes in the second partition portion 1532; electrical connections can be directly established using the second partition portion 1532. However, it is worth noting that the material of the second conductive portion 1531 is different from the conductive material used in the second partition portion 1532. For example, the material of the second partition portion 1532 is Ti, while the material of the second conductive portion 1531 is aluminum or molybdenum. Etching the second conductive portion 1531 will not affect the second partition portion 1532.

[0049] Specifically, the first inorganic layer 141 and the second inorganic layer 143 are provided with through holes corresponding to the via 180, and the touch wiring layer 170 is connected to the second blocking part 153 through the through holes.

[0050] In this process, the via 180 and the through hole in this embodiment are completed by etching process. When the second partition 1532 is formed by conductive material, it is not necessary to further etch the second partition 1532. The first inorganic layer 141 and the second inorganic layer 143 above the second partition 1532 can be directly drilled.

[0051] Specifically, the driving circuit layer 120 further includes an insulating layer 122, which covers the connecting line 121; a first through hole 123 is provided on the insulating layer 122, and the second conductive part 1531 passes through the first through hole 123 and is connected to the connecting line 121; under the orthographic projection of the substrate 110, the first through hole 123 overlaps with the via 180.

[0052] In this embodiment, a first through hole 123 is provided directly below the second conductive portion 1531 of the second blocking portion 153, so that the second conductive portion 1531 is directly electrically connected to the connecting line 121 provided below when it is formed. The advantage of this embodiment is that when only one insulating layer 122 is provided between the connecting line 121 and the second blocking portion 153, the process of forming the first through hole 123 on the insulating layer 122 is relatively convenient, and direct connection is possible.

[0053] However, when other membrane layers are provided below the second blocking part 153, the via 180 and the through hole on the insulating layer 122 need to be configured to not overlap.

[0054] Figure 7 is a cross-sectional schematic diagram of another display panel according to the second embodiment of this application. Referring to Figure 7, the display film layer 130 includes a pixel definition layer 131. The pixel definition layer 131 is disposed in the display area 101. The pixel definition layer 131 is further provided with a first pixel definition layer extension 132 and a second pixel definition layer extension 133 in the non-display area 102. The first pixel definition layer extension 132 is disposed under the first blocking dam 151, and the second pixel definition layer extension 133 is disposed under the second blocking dam 152.

[0055] In this embodiment, the pixel definition layer 131, the first pixel definition layer extension 132, and the second pixel definition layer extension 133 are formed using the same process. Material from the extension of the pixel definition layer 131 is applied to the encapsulation barrier dam 150 region to raise the first barrier dam 151 and the second barrier dam 152. It is understood that during the process of raising the first barrier dam 151 and the second barrier dam 152, a planarization film layer in the driving circuit layer 120 can also be used to increase the height of the first barrier dam 151 and the second barrier dam 152, thereby creating a better barrier effect. The planarization film layer and the planarization layer 160 may use the same or different materials. The planarization film layer in the driving circuit layer 120 can be formed using organic or inorganic materials, but the planarization layer 160 generally uses an organic layer for coating to achieve film planarization.

[0056] The driving circuit layer 120 further includes an insulating layer 122, which covers the connecting line 121. The second blocking portion 153 is further provided with a second blocking portion extension 154. Under the orthographic projection of the substrate 110, the second blocking portion extension 154 does not overlap with the second pixel definition layer extension 133. A second through hole 124 is provided on the insulating layer 122. The second through hole 124 is located under the second blocking portion extension 154. The second conductive portion 1531 passes through the second through hole 124 and connects to the connecting line 121. Under the orthographic projection of the substrate, the second through hole 124 does not overlap with the via 180.

[0057] In this embodiment, by setting an extension portion, the second blocking extension portion 154 is disposed on the side of the second pixel definition layer extension portion 133. The second blocking extension portion 154 does not need to be disposed on the second pixel definition layer extension portion 133. By forming a second through hole 124 between the second blocking extension portion 154 and the connecting line 121, the second conductive portion 1531 also extends to the second through hole 124 and connects with the connecting line 121, thereby realizing the electrical signal transmission of the touch wiring layer 170.

[0058] In one embodiment, the height of the first barrier dam 151 is higher than the height of the second barrier dam 152. The main purpose of the higher height of the first barrier dam 151 is to increase the leveling ability of the organic encapsulation layer 142 and prevent the organic encapsulation layer 142 from overflowing. The height of the second barrier dam 152 does not need to be limited. Of course, the higher the height of the second barrier dam 152, the smaller the cross-sectional height difference between the corresponding planarization layer 160 and the second barrier dam 152, and the better the process accuracy of the touch trace 171.

[0059] Figure 8 is a schematic diagram of the display device of this application. Referring to Figure 8, this application discloses a display device 200, including a driving circuit 210 and the above-mentioned display panel 100, wherein the driving circuit 210 is used to drive the display panel 100 to display.

[0060] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0061] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A display panel, comprising a display area and a non-display area, the display panel further comprising: Substrate; A driving circuit layer is disposed on the substrate. A display film layer is disposed on the driving circuit layer; An encapsulation film layer is disposed on the display film layer and extends from the display area to the non-display area; An encapsulation barrier is disposed between the driving circuit layer and the encapsulation film layer, and located in the non-display area; A planarization layer is disposed on the encapsulation film layer, and A touch-sensitive trace layer is disposed on the planarization layer; The planarization layer has a via in the area where the encapsulation barrier is located, and the touch trace layer extends along the via to the edge of the display panel.

2. The display panel according to claim 1, wherein, The encapsulation barrier includes a first barrier and a second barrier, wherein the first barrier is arranged around the display area and the second barrier is arranged around the first barrier; The second barrier dam includes a plurality of spaced-apart second barrier sections, which are insulated from each other; In the orthographic projection of the substrate, the plurality of vias overlap with the plurality of second blocking portions respectively; The driving circuit layer is provided with multiple connecting lines, and the touch wiring layer is electrically connected to the connecting lines through the second blocking part.

3. The display panel according to claim 2, wherein, The first barrier includes a first conductive part and a first partition part. The first partition part is disposed on the first conductive part, and the radial width of the first partition part is greater than the radial width of the first conductive part. The second blocking portion includes a second conductive portion and a second blocking portion. The second blocking portion is disposed on the second conductive portion, and the radial width of the second blocking portion is greater than the radial width of the second conductive portion. The touch trace layer is electrically connected to the connecting line through the second conductive part.

4. The display panel according to claim 3, wherein, The second partition is also formed of a conductive material, and the touch wiring layer is electrically connected to the connecting line through the second partition and the second conductive part.

5. The display panel according to claim 3, wherein, The driving circuit layer also includes an insulating layer that covers the connecting lines. The insulating layer is provided with a first through hole, and the second conductive part passes through the first through hole and is connected to the connecting line. In the orthographic projection of the substrate, the first via overlaps with the through hole.

6. The display panel according to claim 3, wherein, The display film layer includes a pixel definition layer, which is disposed in the non-display area. The pixel definition layer is further provided with a first pixel definition layer extension and a second pixel definition layer extension in the non-display area. The first pixel definition layer extension is disposed under a first barrier, and the second pixel definition layer extension is disposed under the second barrier.

7. The display panel according to claim 6, wherein, The driving circuit layer further includes an insulating layer that covers the connecting lines. The second blocking portion is further provided with a second blocking portion extension portion, which does not overlap with the second pixel definition layer extension portion under the orthographic projection of the substrate. The insulating layer is provided with a second through hole, which is located below the extension of the second blocking portion, and the second conductive portion passes through the second through hole and is connected to the connecting line. Under the orthographic projection of the substrate, the second via does not overlap with the via hole.

8. The display panel according to claim 2, wherein, The height of the first barrier dam is higher than the height of the second barrier dam.

9. The display panel according to claim 2, wherein, The encapsulation film layer includes a first inorganic layer, an organic encapsulation layer, and a second inorganic layer. The organic encapsulation layer is disposed between the first inorganic layer and the second inorganic layer, and the second inorganic layer is disposed on the first inorganic layer. The organic encapsulation layer extends from the display area to the non-display area and is blocked by the first barrier dam; The first inorganic layer and the second inorganic layer extend from the display area to the non-display area and cover the first barrier and the second barrier. The first inorganic layer and the second inorganic layer are provided with through holes corresponding to the vias, and the touch trace layer is connected to the second blocking part through the through holes.

10. The display panel according to claim 3, wherein, The display film layer further includes a conductive barrier structure and a pixel definition layer. The pixel definition layer is disposed on the driving circuit layer, and the conductive barrier structure is disposed on the pixel definition layer. The conductive barrier structure is formed in the same process as the first barrier dam and the second barrier dam.

11. The display panel according to claim 1, wherein, The touch trace layer extends along the via to the edge of the display panel and into the bonding area.

12. The display panel according to claim 1, wherein, The display panel also includes a connecting line disposed at the encapsulation barrier layer, and the connecting line is used to connect the touch trace from the via.

13. A display device, comprising a driving circuit and a display panel, wherein, The driving circuit is used to drive the display panel to display; The display panel includes a display area and a non-display area, and the display panel further includes: Substrate; A driving circuit layer is disposed on the substrate. A display film layer is disposed on the driving circuit layer; An encapsulation film layer is disposed on the display film layer and extends from the display area to the non-display area; An encapsulation barrier is disposed between the driving circuit layer and the encapsulation film layer, and located in the non-display area; A planarization layer is disposed on the encapsulation film layer, and A touch-sensitive trace layer is disposed on the planarization layer; The planarization layer has a via in the area where the encapsulation barrier is located, and the touch trace layer extends along the via to the edge of the display panel.

14. The display panel according to claim 13, wherein, The encapsulation barrier includes a first barrier and a second barrier, wherein the first barrier is arranged around the display area and the second barrier is arranged around the first barrier; The second barrier dam includes a plurality of spaced-apart second barrier sections, which are insulated from each other; In the orthographic projection of the substrate, the plurality of vias overlap with the plurality of second blocking portions respectively; The driving circuit layer is provided with multiple connecting lines, and the touch wiring layer is electrically connected to the connecting lines through the second blocking part.

15. The display panel according to claim 14, wherein, The first barrier includes a first conductive part and a first partition part. The first partition part is disposed on the first conductive part, and the radial width of the first partition part is greater than the radial width of the first conductive part. The second blocking portion includes a second conductive portion and a second blocking portion. The second blocking portion is disposed on the second conductive portion, and the radial width of the second blocking portion is greater than the radial width of the second conductive portion. The touch trace layer is electrically connected to the connecting line through the second conductive part.

16. The display panel according to claim 15, wherein, The second partition is also formed of a conductive material, and the touch wiring layer is electrically connected to the connecting line through the second partition and the second conductive part.

17. The display panel according to claim 15, wherein, The driving circuit layer further includes an insulating layer that covers the connecting lines. The insulating layer is provided with a first through hole, and the second conductive part passes through the first through hole and is connected to the connecting line. In the orthographic projection of the substrate, the first via overlaps with the through hole.

18. The display panel according to claim 15, wherein, The display film layer includes a pixel definition layer, which is disposed in the non-display area. The pixel definition layer is further provided with a first pixel definition layer extension and a second pixel definition layer extension in the non-display area. The first pixel definition layer extension is disposed under a first barrier, and the second pixel definition layer extension is disposed under the second barrier.

19. The display panel according to claim 18, wherein, The driving circuit layer further includes an insulating layer that covers the connecting lines. The second blocking portion is further provided with a second blocking portion extension portion, which does not overlap with the second pixel definition layer extension portion under the orthographic projection of the substrate. The insulating layer is provided with a second through hole, which is located below the extension of the second blocking portion, and the second conductive portion passes through the second through hole and is connected to the connecting line. Under the orthographic projection of the substrate, the second via does not overlap with the via hole.

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