Silicon wafer, solar cell and photovoltaic module

Abstract

The present application discloses a silicon wafer, a solar cell and a photovoltaic module. The silicon wafer has a first surface, a second surface, and a side surface located between the first surface and the second surface, wherein the first surface and the second surface each have two opposite first edges and two opposite second edges; one of the first edges is connected to two adjacent second edges by means of first chamfers on the side surface, and the other first edge is connected to two adjacent second edges by means of second chamfers on the side surface of the silicon wafer; and the ratio of the length of the first edges to the length of the second edges is between 1.2 and 6. In the silicon wafer in the present application, by means of setting the ratio of the length of the first edges to the length of the second edges to be between 1.2 and 6, ineffective gaps and blank areas in a photovoltaic module caused by solar cells prepared from such a silicon wafer are reduced, thereby increasing the power generation area on a module of the same size, and thus directly improving the power of the photovoltaic module. After a solar cell is prepared from the silicon wafer, the solar cell already has first chamfer structures and second chamfer structures that can assist in distinguishing between a positive electrode and a negative electrode, and therefore no additional mark needs to be provided on the silicon wafer, thereby improving the machining efficiency.

Description

A silicon wafer, a solar cell, and a photovoltaic module

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Application No. 202411997628.3, filed on December 31, 2024, entitled "A Silicon Wafer, a Solar Cell and a Photovoltaic Module", and to Chinese Application No. 202411996958.0, filed on December 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of silicon wafer technology, and more particularly to a silicon wafer, a solar cell, and a photovoltaic module. Background Technology

[0004] Currently, the vast majority of solar cells use monocrystalline silicon wafers as their raw material. The cost and photoelectric conversion efficiency of monocrystalline silicon wafers directly affect the development of solar cells. To further increase the photoelectric conversion efficiency of the cells, existing back-contact solar cells place both the positive and negative electrodes on the back of the cell. Since the P / N regions are on the same side of the cell, there is no grid line obstruction, which improves the absorption efficiency of sunlight. However, its improvement on the power of photovoltaic modules is still relatively limited. Therefore, a technology that can further improve the power of photovoltaic modules is needed. Summary of the Invention

[0005] The purpose of this application is to provide a silicon wafer, a solar cell, and a photovoltaic module that reduces the blank space of solar cells made from such silicon wafers in the photovoltaic module and increases power generation.

[0006] In a first aspect, this application provides a silicon wafer having a first surface and a second surface, and a side surface located between the first surface and the second surface. Each of the first surface and the second surface has two opposing first edges and two opposing second edges. One of the first edges is connected to the two adjacent second edges by a first chamfer on the side surface of the silicon wafer, and the other first edge is connected to the two adjacent second edges by a second chamfer on the side surface of the silicon wafer. The ratio of the length of the first edge to the length of the second edge is 1.2 to 6.

[0007] With the above technical solution, the ratio of the length of the first side and the length of the second side of the silicon wafer is set between 1.2 and 6, which reduces the ineffective gaps and blank spaces in the photovoltaic module made of such silicon wafers, thereby increasing the power generation area on the same size module and directly improving the power of the photovoltaic module.

[0008] In some possible implementations, the length of the first chamfer is greater than the length of the second chamfer.

[0009] With the above technical solution, the ratio of the first side to the second side is 1.2 to 6, and the length of the second chamfer is less than the length of the first chamfer. Using such a silicon wafer to manufacture solar cells, since the lengths of the first and second sides of the silicon wafer are between 1.2 and 6, the utilization rate of silicon rods can be effectively improved during the silicon wafer manufacturing process. When the module layout is determined, the space of the container can be fully utilized. At the same time, since the two opposite sides of the back-contact solar cell have a first chamfer and a second chamfer respectively, and the length of the first chamfer is greater than the length of the second chamfer, the placement direction of the solar cell can be easily identified to assist in the alignment of the PN region between multiple solar cells and to distinguish the positive and negative electrodes of the solar cell. Therefore, there is no need to set additional markings on the silicon wafer or solar cell, which eliminates the marking process, saves time, and improves processing efficiency.

[0010] In some possible implementations, the projected length of the first chamfer is less than 5 mm, and the projected length of the first chamfer is greater than or equal to the projected length of the second chamfer; the side where the second chamfer is located has multiple first grooves, and the angle between the extension direction of the first grooves and the first surface and / or the second surface of the silicon wafer is 0° to 10°.

[0011] With the above technical solution, the projected length of the first chamfer on the silicon wafer is less than 5mm, and the projected length of the first chamfer is greater than or equal to the projected length of the second chamfer. The angle between the extension direction of the first groove of the second chamfer and the surface of the silicon wafer is 0° to 10°. Thus, when the projected length of the silicon wafer is too small, the stress distribution at the edge of the silicon wafer can be improved by setting the first groove at the chamfer. At the same time, since the diamond wire contacts the first surface and / or the second surface during cutting to form the first texture on the first surface and / or the second surface, the extension direction of the first groove on the second chamfer is different from the first texture on the first surface and / or the second surface of the silicon wafer. Therefore, no superimposed stress will be generated at the second chamfer of the silicon wafer, which solves the problem of the probability of superimposed stress forming at the chamfer during the silicon wafer processing and will not lead to the problem of weakened silicon wafer strength, fragmentation, and edge chipping. Due to the increasing size of silicon wafers and the trend towards smaller chamfers, during the fabrication of solar cells using the aforementioned silicon wafers, when removing the phosphosilicate glass or surrounding coating from the solar cell using a "floating on water" method, the silicon wafer floats and moves on the cleaning solution. The cleaning solution cleans the sides of the silicon wafer and the phosphosilicate glass or surrounding coating on the side in contact with the cleaning solution. When the angle between the first groove of the second chamfer and the first and / or second surfaces of the silicon wafer is 0° to 10°, that is, when it is substantially parallel to the first and / or second surfaces of the silicon wafer, then the silicon wafer... When the water floats and moves on the liquid surface, the direction of water flow is the same as the extension direction of the first trench. Therefore, it can reduce the cleaning dead angle of the phosphosilicate glass or the coating on the second chamfer. Moreover, the water flow in front of the second chamfer is guided to the side by the first trench. Compared with the existing situation where the water flow is guided to the upper surface of the silicon wafer when the first trench at the chamfer is inclined to the first surface and / or the second surface of the silicon wafer, the direction of the first trench in this application reduces the occurrence of liquid flooding, which is beneficial to the cleaning of the coating and reduces the damage to the film layer on the first surface and / or the second surface of the silicon wafer.

[0012] In some possible implementations, the spacing between two adjacent first trenches is less than or equal to 3 μm. Within this range, the spacing of the first trenches improves stress distribution at the chamfer and reduces the risk of fragmentation. If the spacing exceeds this range, it reduces the uniformity of strength and smoothness of the second chamfer, affecting the photoelectric conversion efficiency of the battery.

[0013] In some possible implementations, the width of the first trench is 1μm to 20μm. When the width of the first trench is greater than 1μm, the width of the first trench is too large. During the chamfering process, the particle size of the diamond abrasive used in grinding is larger, which increases the grinding resistance and is not conducive to grinding. This increases the chipping rate and breakage rate during silicon wafer processing. When the width of the first trench is less than 20μm, it cannot effectively solve the problem of high breakage rate caused by stress at the edge of the silicon wafer.

[0014] In some possible implementations, the silicon wafer thickness ranges from 70μm to 130μm. When the silicon wafer thickness is greater than 130μm, the stress on the silicon wafer is more concentrated, and the stress at the edge of the silicon wafer is significantly reduced. During the cleaning stage of silicon wafer processing, the breakage rate of the silicon wafer is less than 0.2%. When the silicon wafer thickness is less than 70μm, the processing and manufacturing difficulty increases, and the problem of wafer cracking may also occur due to the excessive thickness.

[0015] In some possible implementations, the length of the first side is 182mm to 300mm, the length of the second side is 182mm to 300mm, and the lengths of the first and second sides are different. The larger the silicon wafer size, the larger the surface area of ​​the cell, and the higher the power generation of the photovoltaic module. When the silicon wafer size is within the above range, the utilization rate of silicon rods during silicon wafer processing can be effectively improved, and the manufacturing cost of silicon wafers can be reduced.

[0016] In some possible implementations, the length of the first side is 182mm to 300mm, and the length of the second side is 91mm to 150mm. Solar cells fabricated from this silicon wafer do not require laser scribing, preventing laser damage or defects at the edges of the cells, ensuring passivation, and improving the photoelectric conversion efficiency of the solar cells. It is suitable for various cell sizes and photovoltaic module designs.

[0017] In some possible implementations, the second chamfer is an arc chamfer, and the first included angle between the tangent of the end of the arc chamfer that connects to the first side and the first side is 30° to 60°.

[0018] Using the technical solution of this application, when the first included angle is less than 30°, the chamfer is too sharp, which increases the breakage rate of the silicon wafer edge. When the first included angle between the tangent of the end of the arc chamfer connected to the first side and the first side is greater than 60°, the projected length of the arc chamfer is large, resulting in more blank space at the module end, which affects the power generation of the module.

[0019] And / or, the second included angle between the tangent of the end of the arc chamfer connected to the second side and the second side is 30° to 50°.

[0020] By adopting the above technical solution, since the second side is smaller than the first side, the stress on the second side is more concentrated. By setting the tangent of the end of the arc chamfer connected to the second side and the second angle of the second side within the above range, the stress distribution at the second side and the chamfer can be effectively dispersed, and the fragmentation rate can be reduced.

[0021] In some possible implementations, the second chamfer is a linear chamfer, with the angle between the linear chamfer and the first side ranging from 35° to 85°. The angle is acute, ensuring the angle between the linear chamfer and the first side is greater than 35° to prevent the silicon wafer chamfer from being too sharp, leading to a high breakage rate during transportation. When the angle between the linear chamfer and the first side is less than 85°, it prevents the angle between the linear chamfer and the adjacent second side from being too large, resulting in an excessively large blank area at the module end, which would affect the power generation at the module end.

[0022] In some possible implementations, the first chamfer has multiple second trenches, the extension directions of which intersect the surface of the silicon wafer. After the silicon wafer is fabricated into a solar cell, the extension directions of the conductive interconnects on the solar cell form an angle with the second trenches. Therefore, during the string bonding process of the conductive interconnects passing through the first chamfer, the second trenches on the first chamfer have a certain limiting effect on the conductive interconnects, which can reduce the slippage of the conductive interconnects on the first and / or second surfaces of the silicon wafer.

[0023] In some possible implementations, the first and / or second surfaces of the silicon wafer have a plurality of spaced-apart first ridges, the extension direction of which is the same as that of the first edge. The first ridges are cutting lines formed on the first and / or second surfaces of the silicon wafer during diamond wire cutting. When the extension direction of the first ridges is the same as that of the first edge, the silicon wafer exhibits improved edge stress distribution in the direction of extension of the first edge due to the arrangement of the first ridges, without resulting in a reduction in the strength of the silicon wafer.

[0024] In some possible implementations, the projected length of the first chamfer is greater than or equal to 0.05 mm and less than or equal to 9 mm.

[0025] When the above technical solution is adopted, due to the excessive thermal stress at the chamfer, if the projected length of the first chamfer is less than 0.05mm, the projected length of the first chamfer will be too small, which will lead to an increase in the area removed from the original silicon rod during silicon wafer processing, affecting the utilization rate of the silicon rod and increasing the processing cost of silicon wafer. When the projected length of the first chamfer is greater than 9mm, the chamfer of the silicon wafer is too large. Using such a silicon wafer to prepare solar cells will result in a large blank area between solar cells, which will affect the power generation of photovoltaic modules.

[0026] In some possible implementations, the projected length of the second chamfer is greater than 0 mm and less than or equal to 8.5 mm.

[0027] With the above technical solution, the projected length of the second chamfer is greater than 0 to prevent the chamfer from being too sharp, which would prevent the stress at the edge of the silicon wafer from being released in time and increase the breakage rate of the silicon wafer during transportation or transfer; the projected length of the second chamfer is less than or equal to 8.5mm to prevent the blank area between the cells from being too large due to the chamfer of the silicon wafer, which would affect the power generation of the photovoltaic module.

[0028] In some possible implementations, the difference between the projected length of the first chamfer on the first side and the projected length of the first chamfer on the second side is less than or equal to 2 mm;

[0029] And / or, the difference between the projected length of the second chamfer on the first side and the projected length on the second side is less than or equal to 1 mm.

[0030] With the above technical solution, the projections of the first chamfer on the first and second sides are different. Considering the different stress concentrations on different sides of the silicon wafer, setting the projection difference of the first chamfer on different sides to be less than or equal to 2mm can reasonably alleviate the stress on the edge of the silicon wafer and prevent the projection difference of the first chamfer on the first and second sides from being too large, thus reducing the utilization rate of the silicon rod used for processing silicon.

[0031] In some possible implementations, the projection length of the first chamfer on the first side is 0.05mm to 9mm, and the projection length of the first chamfer on the second side is 0.05mm to 7mm.

[0032] And / or, the projection length of the second chamfer on the first side is 0.05mm to 5mm, and the projection length of the second chamfer on the second side is 0.05mm to 5mm.

[0033] With the above technical solution, the projected length of the first chamfer on the first side can be greater than the projected length of the first chamfer on the second side, and the projected length of the second chamfer on the first side can be less than or equal to the projected length of the second chamfer on the second side. Because the projection of the first chamfer on the long side is longer, it effectively alleviates the problem of edge stress concentration corresponding to the long side; the projection on the second side is shorter, which can alleviate the degree of stress concentration at the second edge. Since the stress dispersion of each chamfer is relatively uniform and the overall stress of the silicon wafer is relatively uniform, warping and uneven strength distribution can be effectively avoided. At the same time, it prevents excessive blank space at the module end, which would affect the power generation of the photovoltaic module.

[0034] In some possible implementations, the difference between the projected length of the first chamfer on the first side and the projected length of the second chamfer on the first side is 0.05mm to 8mm;

[0035] And / or, the difference between the projected length of the first chamfer on the second side and the projected length of the second chamfer on the second side is 0.05mm to 8mm.

[0036] When the above technical solution is adopted, the difference is within this range, which can make it easy to observe the size relationship between the first chamfer and the second chamfer with the naked eye. This prevents the difference from being less than 0.05mm, which makes it difficult to identify the positive and negative electrode arrangement order of the subsequently prepared solar cells. If the difference is greater than 8mm, the projected length of the first chamfer will be too large. In the silicon wafer preparation process, more silicon rods will be removed, resulting in low utilization of silicon rods and increased cost of silicon wafer preparation.

[0037] In some possible implementations, the first chamfer is an arc-shaped chamfer or a linear chamfer; and / or, the second chamfer is an arc-shaped chamfer or a linear chamfer. When the first and second chamfers are arc-shaped, less part of the silicon rod is removed, thereby improving the utilization rate of silicon wafer cutting. The arc-shaped chamfer makes the transition between the first and second edges smooth, preventing excessive edge stress and excessive silicon wafer breakage during transportation or processing. When the first and second chamfers are linear, compared with arc-shaped chamfers, the processing is simpler, improving processing efficiency and reducing processing costs. In addition, with the same projected length, the solar cells made from silicon wafers with linear chamfers have less blank space between cells when processed into modules, resulting in higher power generation of the modules.

[0038] In some possible implementations, the length of the first side is 182mm to 300mm, and the length of the second side is 83mm to 150mm. Silicon wafers of this size eliminate the need for laser scribing during cell fabrication, improving edge passivation and increasing photoelectric conversion efficiency. This design is suitable for various cell sizes and photovoltaic module designs.

[0039] In some possible implementations, the silicon wafer surface has multiple spaced-apart first ridges, with the spacing between two adjacent first ridges ranging from 1mm to 4mm, and the distance between the highest and lowest points of the first ridges ranging from 0.5mm to 4mm. The first ridges are the cutting lines formed on the silicon wafer surface during the cutting process. When the spacing between adjacent first ridges is less than this range, the first ridges are relatively dense, reducing the mechanical strength of the silicon wafer. If the spacing is greater than this range, the silicon wafer surface is smooth, making it easy for conductive interconnects to slip. When the distance between the highest and lowest points of the first ridges is less than 0.5mm, it affects the silicon wafer processing efficiency and increases the manufacturing cost. When the distance between the highest and lowest points of the first ridges is greater than 4mm, it affects the flatness of the silicon wafer surface.

[0040] In some possible implementations, the spacing between two adjacent first textures at the first chamfer is 0.05mm to 3mm, and / or the spacing between adjacent first textures at the second chamfer is 0.1mm to 4mm. If the spacing between two adjacent first textures at the chamfer is less than 0.05mm, the first textures at the chamfer are relatively dense, reducing the mechanical strength of the chamfer; if the spacing between two adjacent first textures at the chamfer is greater than 4mm, it will affect the flatness of the silicon wafer surface.

[0041] Secondly, this application also provides a battery cell prepared from a silicon wafer as described in any of the above claims, wherein the surface of the battery cell has a first electrode extending along a first edge of the silicon wafer.

[0042] In some possible implementations, the first electrode is a sub-gate line.

[0043] Since the solar cell is fabricated from the silicon wafer of the first aspect, it has the same beneficial effects as the first aspect, and will not be described again. In some possible implementations, the surface of the solar cell has a first texture, and the first texture extends in the same direction as the first electrode. This arrangement reduces the risk of grid breakage of the first electrode caused by the first texture. In a third aspect, this application also provides a photovoltaic module, including at least two solar cells and at least one conductive interconnect, the conductive interconnect connecting two adjacent solar cells, the conductive interconnect extending along a first edge of the silicon wafer, and the solar cell of this application is the solar cell as described in any of the above. Since the photovoltaic module includes the solar cell of the second aspect, it has the same beneficial effects as the first and second aspects, and will not be described again. Attached Figure Description

[0044] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0045] Figure 1 is a schematic diagram of a silicon wafer according to an embodiment of this application;

[0046] Figure 2 is a schematic diagram of a silicon wafer with a first texture on its first surface according to an embodiment of this application;

[0047] Figure 3 is a partial schematic diagram of the side of the silicon wafer provided according to an embodiment of this application, where the second chamfer is located;

[0048] Figure 4 is a partial schematic diagram of the side of the silicon wafer provided according to an embodiment of this application, where the first chamfer is located;

[0049] Figure 5 is a schematic diagram of a silicon wafer fabrication method according to an embodiment of this application;

[0050] Figure 6 is a schematic diagram of another silicon wafer fabrication method provided according to an embodiment of this application;

[0051] Figure 7 is a schematic diagram of a silicon wafer according to an embodiment of this application;

[0052] Figure 8 is a schematic diagram of a silicon wafer with a first texture provided in an embodiment of this application.

[0053] Reference numerals in the attached figures: 1 is a circular silicon rod, 2 is a rectangular silicon rod, 21 is the first surface, 22 is the second surface, 23 is the tangent plane, 3 is a half rod, 4 is a silicon wafer, 10 is the first side, 20 is the second side, 30 is the first chamfer, 301 is the second groove, 40 is the second chamfer, 401 is the first groove, and 50 is the first texture. Detailed Implementation

[0054] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0055] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0057] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0058] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0059] The vast majority of solar cells use monocrystalline silicon wafers as their raw material. The cost and photoelectric conversion efficiency of monocrystalline silicon wafers directly affect the development of solar cells. Solar cells are usually made by first cutting monocrystalline silicon rods into square rods, then cutting the square rods into silicon wafers, and finally using these silicon wafers to make photovoltaic cells.

[0060] Currently, with the industry's relentless pursuit of silicon wafer cost and photoelectric conversion efficiency, existing back-contact solar cells place both positive and negative electrodes on the back of the cell in order to further increase the photoelectric conversion efficiency. Since the P / N regions are on the same side of the cell and there is no grid line obstruction, the absorption efficiency of sunlight is improved. However, its improvement on the power of photovoltaic modules is still relatively limited. Therefore, a technology that can further improve the power of photovoltaic modules is needed.

[0061] Therefore, the applicant of this application provides a new silicon wafer.

[0062] As shown in Figures 1-4, this application provides a silicon wafer 4, which has a first surface and a second surface, as well as a side surface located between the first surface and the second surface. Each of the first surface and the second surface has two opposing first edges 10 and two opposing second edges 20. One of the first edges 10 is connected to the two adjacent second edges 20 through a first chamfer 30 on the side surface of the silicon wafer, and the other first edge 10 is connected to the two adjacent second edges 20 through a second chamfer 40 on the side surface of the silicon wafer. The ratio of the length of the first edge to the length of the second edge is 1.2 to 6.

[0063] This ratio can specifically be 1.2, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, etc. Such silicon wafers reduce the ineffective gaps and blank spaces in photovoltaic modules, thereby increasing the power generation area on modules of the same size and directly improving the power output of photovoltaic modules.

[0064] As silicon wafer dimensions increase, chamfer dimensions gradually decrease. However, a smaller chamfer dimension hinders the dispersion of edge stress, leading to a persistently high breakage rate during wafer manufacturing. Therefore, the applicant of this application further proposes to improve the silicon wafer's...

[0065] The projected length of the first chamfer 30 is less than 5mm, and the projected length of the first chamfer 30 is greater than or equal to the projected length of the second chamfer 40; the side where the second chamfer 40 is located has multiple first grooves 401, and the angle between the extension direction of the first groove 401 and the surface of the silicon wafer is 0° to 10°, specifically 0°, 1°, 3°, 5°, 7°, 9°, and 10°.

[0066] It should be noted that the projected length of the silicon wafer chamfer refers to the projected length on the first or second side of the silicon wafer after the edge or corner of the wafer has been chamfered. The shape of the silicon wafer chamfer can be an arc chamfer or a linear chamfer, where linear chamfers include right angles, bevels, etc.; arc chamfers include rounded chamfers, curved chamfers, etc. When the shape of the chamfer is a linear chamfer, the projected length mentioned in this application refers to the projected length of the linear chamfer on the first or second side.

[0067] The projected length of a chamfer can be measured using optical measurement, scanning microscopy, or other measurement methods to assess the size of the chamfer.

[0068] In this application, the projected lengths of the first chamfer 30 and the second chamfer 40 refer to the projections of the first chamfer 30 and the second chamfer 40 onto the first side 10 and / or the second side 20. The projection length of the first chamfer 30 being greater than or equal to the projection length of the second chamfer 40 means that the projection length of the first chamfer 30 onto the first side 10 is greater than or equal to the projection length of the second chamfer 40 onto the first side 10, and the projection length of the first chamfer 30 onto the second side 20 is greater than or equal to the projection length of the second chamfer 40 onto the second side 20.

[0069] With the above technical solution, the current method of preparing silicon wafers using diamond wire cutting can lead to an excessively large angle between the first groove on the chamfer and the first and / or second surfaces of the silicon wafer, causing a risk of edge chipping at the chamfer. Therefore, in this application, the angle between the extension direction of the first groove 401 on the second chamfer 40 and the surface of the silicon wafer 4 is reduced to 0°–10°. By adjusting the direction of the first groove on the chamfer, a first groove 401 that is substantially parallel to the first and / or second surfaces of the silicon wafer is obtained. The extension direction of the first groove 401 on the second chamfer 40 is parallel to the surface of the silicon wafer. The first texture 50 on the first surface and / or the second surface of the silicon wafer are different, so no superimposed stress is generated at the second chamfer 40 of the silicon wafer. This solves the problem of the probability of superimposed stress forming at the chamfer during silicon wafer processing, and will not lead to problems such as weakening of silicon wafer strength, fragmentation, and edge chipping. In addition, since the preparation of silicon rods requires high-temperature crystal pulling, the thermal stress at the edge is large. Since the silicon wafer is a product cut from a square rod taken out of a silicon round rod, the chamfer on the silicon wafer is closest to the edge of the original round rod. This area is subject to greater thermal shock during the crystal pulling process, resulting in greater thermal stress at the silicon wafer chamfer. The first groove 401 at the second chamfer can improve the stress distribution at the edge of the silicon wafer and reduce the fragmentation rate. When the angle is 0°, that is, when the extension direction of the first trench 401 is parallel to the first surface and / or the second surface of the silicon wafer, during the process of manufacturing a solar cell using such a silicon wafer, when removing the phosphosilicate glass or the coating on the solar cell using the "floating on water" method, that is, the solar cell prepared from silicon wafer 4 floats and moves on the cleaning liquid. The cleaning liquid cleans the sides of the solar cell and the phosphosilicate glass or the coating on the side facing the liquid surface. Since the first trench 401 of the second chamfer 40 is parallel to the surface of the silicon wafer 4, when the solar cell prepared from silicon wafer 4 floats and moves on the liquid surface... The water flow direction is the same as the extension direction of the first trench 401. Therefore, it can reduce the cleaning dead angle of the phosphosilicate glass or the coating on the second chamfer 40. The water flow in front of the second chamfer 40 is guided to the side by the first trench 401. Compared with the existing chamfer where the grinding marks are inclined to the first and / or second surfaces of the silicon wafer, the water flow is guided to the upper surface of the silicon wafer. The direction of the first trench 401 in this application reduces the occurrence of liquid flooding, which is beneficial for cleaning the coating and reduces the damage to the film layer on the upper surface of the silicon wafer, thus helping to improve the photoelectric conversion efficiency of the battery.

[0070] In some embodiments, the spacing between two adjacent first trenches 401 is less than or equal to 3 μm. Specifically, the spacing between adjacent first trenches 401 can be 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.7 μm, 2 μm, 2.3 μm, 2.6 μm, 2.8 μm, 3 μm, etc. The first trenches 401 within this spacing range can improve the stress distribution at the chamfer of the silicon wafer and reduce the risk of fragmentation. If the spacing between two adjacent first trenches 401 is greater than this spacing range, it reduces the strength uniformity of the second chamfer 40 and the flatness of the first surface and / or the second surface of the silicon wafer, affecting the photoelectric conversion efficiency of the cell.

[0071] In some embodiments, the width of the first trench 401 is 1μm to 20μm. Specifically, the width of the first trench 401 can be 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 19μm, 20μm, etc. When the width of the first trench 401 is greater than 20μm, the width of the first trench 401 is too large. During the processing of the second chamfer 40, the particle size of the diamond abrasive used in grinding is larger, the grinding resistance increases, which is not conducive to grinding and increases the chipping rate and fragmentation rate during silicon wafer processing. When the width of the first trench 401 is less than 1μm, it cannot solve the problem of high fragmentation rate caused by stress at the edge of the silicon wafer.

[0072] In some embodiments, the thickness of silicon wafer 4 is less than or equal to 130 μm. When the thickness of silicon wafer is greater than 130 μm, the stress on silicon wafer 4 is more concentrated. When it is less than or equal to 130 μm, the stress at the edge of silicon wafer 4 is significantly reduced. During the cleaning process of silicon wafer 4, the breakage rate of silicon wafer 4 is less than 0.2%.

[0073] In some embodiments, the distance between the first side 10 and the second side 20 is 182mm to 300mm, and the distance between the first side 10 and the second side 20 is different. Due to the presence of chamfers, the length of the first side 10 can be represented by the distance between the two opposing second sides 20, i.e., the sum of the length of the first side 10 and the projected length of the two first chamfers 30 on the first side 10 is 182mm to 300mm. Specifically, the length of the first side 10 can be 182mm, 185mm, 190mm, 195mm, 200mm, 205mm, 210mm, 220mm, 230mm, 240mm, 250mm, 270mm, 290mm, 300mm, etc.; the distance between the second side 20 and the second side 20 is 182mm to 300mm. The length can be represented by the distance between the two opposite first sides 10, that is, the sum of the length of the second side 20, the projected length of the first chamfer 30 on the second side 20, and the projected length of the second chamfer 40 on the second side 20, which is 182mm to 300mm. The specific length of the second side 20 can be 182mm, 185mm, 190mm, 195mm, 200mm, 205mm, 210mm, 220mm, 230mm, 240mm, 250mm, 270mm, 290mm, 300mm, etc. The length of the first side 10 can be greater than the length of the second side 20. The larger the silicon wafer size, the larger the surface area of ​​the cell, and the higher the photoelectric conversion efficiency. When the size of the silicon wafer is within the above range, the utilization rate of the silicon rod during the silicon wafer processing can be effectively improved, and the manufacturing cost of the silicon wafer can be reduced.

[0074] In other embodiments, the length of the first side 10 is 182mm to 300mm, specifically 182mm, 185mm, 190mm, 195mm, 200mm, 205mm, 210mm, 220mm, 230mm, 240mm, 250mm, 270mm, 290mm, 300mm, etc.; the length of the second side 20 is 91mm to 150mm, specifically 91mm, 95mm, 98mm, 100mm, 105mm, 110mm, 115mm, 120mm, 125mm, 130mm, 135mm, 140mm, 145mm, 150mm, etc. The solar cell fabricated from this silicon wafer does not require laser scribing; the silicon wafer of this size can be directly fabricated into a solar cell without laser damage or defects at the edges, ensuring passivation and improving the photoelectric conversion efficiency of the solar cell. Suitable for various sizes and shapes of solar cells and photovoltaic modules.

[0075] Table 1 shows the fragmentation rate data for silicon wafers with different side lengths and different chamfer projection lengths, with the first trench direction on the second chamfer 40 changing or remaining unchanged. The fragmentation rate is the fragmentation rate caused by the cleaning step in the silicon wafer preparation process.

[0076] In this embodiment, the first trench direction remains unchanged, meaning that the angle between the first trench direction formed at the second chamfer and the first and / or second surfaces of the silicon wafer is greater than 80° when using the existing grinding and chamfering process. The change in the first trench direction is the direction of the first trench in this application.

[0077] Table 1. Fragmentation rates of silicon wafers with different side lengths and projected lengths.

[0078] Based on the dimensions of the silicon wafer 4 in the above embodiments and the data in Table 1, it can be seen that, for example, through the comparison of Embodiment 1 and Comparative Example 1, Embodiment 2 and Comparative Example 2, Embodiment 3 and Comparative Example 3, Embodiment 4 and Comparative Example 4, Embodiment 5 and Comparative Example 5, and Embodiment 6 and Comparative Example 6, when the silicon wafer size is within 182mm to 300mm and is the same, the fragmentation rate decreases when the projected length is less than 5mm; in the comparison of Embodiment 7 and Comparative Example 7, when the silicon wafer size is too large, such as one side being greater than 300mm, and the projected length is less than 5mm, changing the direction of the groove at the chamfer does not change the fragmentation rate.

[0079] By comparing Examples 1-6 and Comparative Examples 1-6 where the direction of the first trench at the chamfer remains unchanged and the direction of the first trench at the chamfer changes, it can be seen that when the angle between the extension direction of the first trench and the first surface and / or the second surface of the silicon wafer in this application is 0° to 10°, the corresponding silicon wafer fragmentation rate is significantly reduced.

[0080] In some embodiments, the second chamfer 40 is an arc-shaped chamfer, which can reduce the edge stress of the silicon wafer 4. The first included angle between the tangent at the end of the arc-shaped chamfer connected to the first side 10 and the first side 10 is 30° to 60°, specifically 30°, 35°, 40°, 45°, 50°, 55°, 60°, etc. When the first included angle is less than 30°, the chamfer is too sharp, resulting in an increased breakage rate at the edge of the silicon wafer. When the first included angle between the tangent at the end of the arc-shaped chamfer connected to the first side 10 and the first side 10 is greater than 60°, the projected length of the arc-shaped chamfer is large, resulting in more blank space at the module end, which affects the power generation of the module.

[0081] And / or, the second included angle between the tangent at the other end of the arc chamfer that connects to the second side 20 and the second side 20 is 30° to 50°, specifically 30°, 35°, 40°, 45°, 50°, etc.

[0082] By adopting the above technical solution, since the second side 20 is smaller than the first side 10, the stress on the second side 20 is more concentrated. By setting the tangent of the end of the arc chamfer connected to the second side 20 and the second angle of the second side 20 within the above range, the stress distribution at the second side 20 and the second chamfer 40 can be effectively dispersed, thereby reducing the fragmentation rate.

[0083] In some embodiments, the second chamfer 40 is a linear chamfer, which improves the utilization rate of silicon rods for large-sized silicon wafers. The angle between the linear chamfer and the first side 10 is 35° to 85°, specifically 35°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, etc. An acute angle ensures that the angle formed by the linear chamfer and the first side 10 is greater than 35°, preventing the silicon wafer chamfer from being too sharp and resulting in a high breakage rate during transportation. When the angle formed by the linear chamfer and the first side 10 is less than 85°, it prevents the angle between the linear chamfer and the adjacent second side 20 from being too large, resulting in an excessively large blank area at the module end, affecting the effective utilization area of ​​the solar cells.

[0084] It should be noted that the line chamfers in this application may specifically include straight lines, oblique lines, or multi-segment lines, and chamfer shapes that are generally straight lines or line structures are all within the protection scope of this application.

[0085] In some embodiments, the first chamfer 30 is an arc-shaped chamfer or a linear chamfer. When the first chamfer 30 is an arc-shaped chamfer, it can reduce the edge stress of the silicon wafer 4. When the first chamfer 30 is a linear chamfer, the linear chamfer can improve the utilization rate of the silicon rod for large-sized silicon wafers.

[0086] As shown in Figure 4, in some possible implementations, the first chamfer 30 has multiple second trenches 301. The extension direction of the second trenches 301 intersects the surface of the silicon wafer 4, that is, there is an angle between the second trenches 301 and the surface of the silicon wafer 4, which is less than 90°. Specifically, it can be 10°, 20°, 30°, 45°, 60°, 80°, 85°, etc. The second trenches 301 are grinding marks formed when grinding the first chamfer 30. After the silicon wafer is used to prepare the solar cell, the extension direction of the conductive interconnects on the solar cell has an angle with the second trenches 301. Therefore, during the string bonding process of the conductive interconnects passing through the first chamfer 30, the second trenches 301 on the first chamfer 30 have a certain limiting effect on the conductive interconnects, which can reduce the slippage of the conductive interconnects on the first surface and / or the second surface of the silicon wafer.

[0087] As shown in Figure 2, in some embodiments, the surface of the silicon wafer 4 has multiple spaced-apart first ridges 50, the extension direction of which is the same as the extension direction of the first edge 10. It should be noted that the first ridges 50 are frictional textures formed on the first and / or second surfaces of the silicon wafer during the wafer fabrication process, caused by friction between the dicing wires and the first and / or second surfaces of the wafer. As the silicon rod feeds relative to the dicing wire mesh, the dicing wires bear pressure from the silicon rods, and while the dicing wires reciprocate, they bend to a certain extent in the feed direction. Consequently, each first ridge 50 formed appears as a visible arc on the first and / or second surfaces of the silicon wafer. Figure 2 schematically illustrates some of the first ridges 50 on the silicon wafer 4 to show their outline and curvature, but does not represent the actual structure of the first ridges 50. Multiple first ridges 50 are densely arranged along the dicing direction as seen in the figure.

[0088] When the extension direction of the first ridge 50 is the same as the extension direction of the first side 10, the extension direction of the first electrode on the solar cell made from this silicon wafer is the same as the long side direction of the solar cell, reducing the risk of grid breakage of the first electrode caused by the first ridge. Therefore, during the fabrication of the silicon wafer, the extension direction of the first ridge 50 on the silicon wafer is the same as the long side of the silicon wafer 4, that is, the same as the extension direction of the first side 10. In addition, the setting of the first ridge in the direction of extension of the first side improves the distribution of edge stress of the silicon wafer and does not lead to a decrease in the strength of the silicon wafer.

[0089] It is worth noting that during the silicon wafer fabrication process, the silicon rod is fed relative to the dicing wire mesh, and the dicing wire is subjected to pressure from the silicon rod. As the dicing wire moves back and forth, it forms a certain degree of bending in the feeding direction. The corresponding first texture 50 appears as a visible arc on the first surface and / or the second surface of the silicon wafer. The extension direction of the first texture is the same as the long side of the silicon wafer, that is, it is roughly the same or consistent.

[0090] In some embodiments, the spacing between two adjacent first textures 50 is 1mm to 4mm. Specifically, the spacing between two adjacent first textures 50 is 1mm, 2mm, 3mm, 4mm, etc. Since the first texture 50 is slightly curved and has a highest point and a lowest point, the distance between the highest point and the lowest point on the first texture 50 is 0.5mm to 4mm. Specifically, the distance between the highest point and the lowest point on the first texture 50 can be 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, etc.

[0091] The spacing between two adjacent first ridges 50 refers to the distance between the lowest points or the highest points on the first ridge. This distance can be measured using a sorting machine or vernier calipers, or it can be obtained from data collected by a displacement sensor. This application does not impose specific limitations on this.

[0092] When the spacing between two adjacent first ridges 50 is less than this range, the first ridges 50 are relatively dense, reducing the mechanical strength of the silicon wafer and lowering the efficiency of slicing by the cutting lines. If the spacing between the first ridges 50 is greater than this range, the spacing between the first ridges 50 is too large, resulting in uneven flatness of the first and / or second surfaces of the silicon wafer, affecting the overall appearance. Furthermore, the excessively small surface roughness in some areas of the silicon wafer can easily cause slippage of conductive interconnects. When the distance between the highest and lowest points of the first ridge 50 is less than 0.5mm, it means that the cutting speed of the dicing line is slow and the force on the dicing line is small, which reduces the slicing efficiency. In this case, the first and / or second surfaces of the silicon wafer are smooth, which can easily cause the conductive interconnects to slip. When the distance between the highest and lowest points of the first ridge 50 is greater than 4mm, the force on the dicing line is large, which can easily cause excessive pressure on the silicon wafer during the cutting process, resulting in fragmentation and affecting the life of the dicing line. If the cutting speed is too fast, the spacing of the first ridge will be too large, and the flatness of the first and / or second surfaces of the silicon wafer will be uneven, affecting the overall appearance. In addition, if the surface roughness of the silicon wafer is too small in some areas, the conductive interconnects can easily slip.

[0093] In addition, the current method of cutting solar cells usually uses laser technology to dicing the whole solar cell into smaller solar cells. Due to the effect of the laser, the small silicon wafers formed in this way will have laser damage and defect states at the edge of the cell, which will affect the passivation and other properties of the cell, and thus affect the photoelectric conversion efficiency of the solar cell. Therefore, there is an urgent need for a solar cell with good edge uniformity.

[0094] To prepare solar cells with good edge uniformity, one method is to prepare silicon wafers into smaller pieces. Since the silicon wafers are prepared by diamond wire cutting, the edges of such silicon wafers have a good passivation effect, which can improve the photoelectric conversion efficiency of solar cells.

[0095] As shown in Figures 7 and 8, this embodiment of the application also provides a silicon wafer 4. The silicon wafer 4 has a first surface and a second surface, as well as a side surface located between the first surface and the second surface. Each of the first surface and the second surface has two opposing first edges 10 and two opposing second edges 20. One of the first edges 10 is connected to the two adjacent second edges 20 through a first chamfer 30 on the side surface of the silicon wafer, and the other first edge 10 is connected to the two adjacent second edges 20 through a second chamfer 40 on the side surface of the silicon wafer. The ratio of the length of the first edge 10 to the length of the second edge 20 is 1.2 to 6, and this ratio can specifically be 1.2, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, etc.; the length of the first chamfer is greater than the length of the second chamfer. Since the shape of the silicon wafer chamfer can be either an arc chamfer or a linear chamfer, when the first chamfer and / or the second chamfer is an arc chamfer, the length of the arc chamfer refers to the distance between the two endpoints of the arc chamfer. When the first chamfer and / or the second chamfer is a linear chamfer, the length of the linear chamfer refers to the straight line length between the two endpoints of the linear chamfer.

[0096] The projected length of the first chamfer refers to its projection onto the first side and / or the second side, and the projected length of the second chamfer refers to its projection onto the first side and / or the second side. The projection length of the first chamfer being greater than the projection length of the second chamfer means that the projection length of the first chamfer 30 on the first side 10 is greater than the projection length of the second chamfer 40 on the first side 10, and the projection length of the first chamfer 30 on the second side 20 is greater than or equal to the projection length of the second chamfer 40 on the second side 20; or, the projection length of the first chamfer 30 on the first side 10 is greater than or equal to the projection length of the second chamfer 40 on the first side 10, and the projection length of the first chamfer 30 on the second side 20 is greater than the projection length of the second chamfer 40 on the second side 20. That is, when the projection length of the first chamfer 30 on the first side 10 is greater than the projection length of the second chamfer 40 on the first side 10, the projection length of the first chamfer 30 on the second side 20 cannot be less than the projection length of the second chamfer 40 on the second side 20, so that the projection length of the first chamfer 30 is greater than the projection length of the second chamfer 40. Alternatively, when the projected length of the first chamfer 30 on the second side 20 is greater than the projected length of the second chamfer 40 on the second side 20, the projected length of the first chamfer 30 on the first side 10 cannot be less than the projected length of the second chamfer 40 on the first side 10, so that the projected length of the first chamfer 30 is greater than the projected length of the second chamfer 40.

[0097] With the above technical solution, the silicon wafer has two first chamfers 30 on one first side 10 of the silicon wafer 4, and two second chamfers 40 on the other first side 10. Comparing the lengths of the first chamfers 30 and the second chamfers 40, the length of the first chamfer 30 is greater than the length of the second chamfer 40. That is, compared with the second chamfer 40, the first chamfer 30 is a larger chamfer, and the second chamfer 40 is a smaller chamfer. When using such a silicon wafer to prepare solar cells, since the opposite sides of the solar cell have the first chamfers 30 and the second chamfers 40 respectively, and the length of the first chamfer 30 is greater than or equal to the length of the second chamfer 40, the placement direction of the solar cell can be easily identified, which helps to align the PN regions between multiple solar cells and distinguish the positive and negative electrodes. For example, when arranging multiple solar cells to form a module's battery string, if each cell is placed in the same direction and aligned sequentially in a row with the first chamfer 30°, the second chamfer 40°, the first chamfer 30°, and the second chamfer 40°, the P-area of ​​the previous cell automatically aligns with the P-area or N-area of ​​the next cell. This allows for convenient selection of suitable conductive interconnects and stringing processes to produce the battery module. Therefore, there is no need to add additional markings to the silicon wafers or solar cells, eliminating the marking process, saving time, and improving processing efficiency. Simultaneously, the ratio of the length of the first side 10 to the length of the second side 20 of the silicon wafer is 1.2 to 6, which effectively improves the utilization rate of silicon rods during wafer fabrication; and given a fixed module layout, it allows for full utilization of container space.

[0098] In some embodiments, the projected length of the first chamfer 30 is greater than or equal to 0.05 mm and less than or equal to 9 mm, that is, the projected length of the first chamfer 30 on the first side 10 and / or the second side 20 is greater than or equal to 0.5 mm and less than or equal to 9 mm. Specifically, the projected length of the first chamfer 30 can be 0.05 mm, 0.1 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, 9 mm, etc.

[0099] When the above technical solution is adopted, due to the excessive thermal stress at the chamfer, when the projected length of the first chamfer 30 is less than 0.05mm, the projected length of the first chamfer 30 is too small, which will lead to an increase in the area removed from the original silicon rod during silicon wafer processing, affecting the utilization rate of the silicon rod and increasing the processing cost of silicon wafer; when the projected length of the first chamfer 30 is greater than 9mm, due to the excessive chamfer of the silicon wafer, using such a silicon wafer to prepare solar cells results in a large blank area between solar cells, affecting the power generation of photovoltaic modules.

[0100] In some embodiments, the projected length of the second chamfer 40 is greater than 0 mm and less than or equal to 8.5 mm. That is, the projected length of the second chamfer 40 on the first side 10 and / or the second side 20 is greater than 0 mm and less than or equal to 8.5 mm. Specifically, the projected length of the second chamfer 40 can be 0.05 mm, 0.1 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, 8.5 mm, etc.

[0101] With the above technical solution, the projected length of the second chamfer 40 is greater than 0 to prevent the chamfer from being too sharp, which would cause the stress at the edge of the silicon wafer to not be released in time and increase the breakage rate of the silicon wafer during transportation or transfer; the projected length of the second chamfer is less than or equal to 8.5mm to prevent the blank area between the cells from being too large due to the chamfer of the silicon wafer, which would affect the power generation of the photovoltaic module.

[0102] Further, in this embodiment, the difference between the projected length of the first chamfer 30 on the first side 10 and the projected length on the second side 20 is less than or equal to 2mm. Specifically, the difference can be 0, 0.2mm, 0.5mm, 0.8mm, 1mm, 1.2mm, 1.5mm, 1.7mm, 2mm, etc. That is, the projected length of the first chamfer 30 on the first side 10 and the projected length on the second side 20 can be the same or different. And / or, the difference between the projected length of the second chamfer 40 on the first side 10 and the projected length on the second side 20 is 0mm to 1mm. Specifically, the difference can be 0, 0.2mm, 0.5mm, 0.8mm, 1mm, etc. That is, the projected length of the second chamfer 40 on the first side 10 and the projected length of the second chamfer 40 on the second side 20 can be the same or different. When the projected lengths of the chamfer on the first and second sides are the same, it can be simply referred to as the projected length of the first chamfer 30 or the projected length of the second chamfer 40, which simplifies the processing of the first chamfer 30 and the second chamfer 40. When the projected lengths of the chamfer on the first and second sides are different, the projected length of the first chamfer 30 on the first side 10 can be greater than the projected length of the first chamfer 30 on the second side 20, and the projected length of the second chamfer 40 on the first side 10 can be greater than or equal to the projected length of the second chamfer 40 on the second side 20. Since the first side 10 is the long side of the silicon wafer and the second side 20 is the short side of the silicon wafer, that is, the projection of the chamfer on the long side is longer and the projection on the short side is shorter. Thus, the projections of the first chamfer on the first and second sides are different. Considering the different stress concentrations on different sides of the silicon wafer, setting the difference in the projection of the first chamfer on different sides within 0 to 2 mm can alleviate the stress at the edge of the silicon wafer and prevent a large difference in the projection of the first chamfer on the first and second sides, thus reducing the utilization rate of the silicon rod used for processing silicon.

[0103] For example, the projected length of the first chamfer 30 on the first side 10 is 0.05mm to 9mm, specifically 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.5mm, 6mm, 6.5mm, 7mm, 7.5mm, 8mm, 8.5mm, 9mm, etc. The projected length of the first chamfer 30 on the second side 20 is 0.05mm to 7mm, specifically 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 4mm, 5mm, 6mm, 7mm, etc. It is acceptable as long as the projected length of the first chamfer 30 on the first side 10 is greater than the projected length on the second side 20.

[0104] For example, the projected length of the second chamfer 40 on the first side 10 is 0.05mm to 5mm, specifically 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, etc. The projected length of the second chamfer on the second side is 0.05mm to 5mm, specifically 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, etc. It is acceptable as long as the projected length of the second chamfer 40 on the first side 10 is greater than the projected length on the second side 20.

[0105] With the above technical solution, the projected length of the first chamfer on the first side can be greater than the projected length of the first chamfer on the second side, and the projected length of the second chamfer on the first side can be greater than the projected length of the second chamfer on the second side. Because the projection of the first chamfer on the long side is longer, it effectively alleviates the problem of edge stress concentration corresponding to the long side; the projection on the short side is shorter, which alleviates stress concentration at the short edge while preventing excessively long projections on the short side from causing excessive blank space at the module end, thus affecting the power generation of the photovoltaic module.

[0106] In some embodiments, the difference between the projected length of the first chamfer 30 on the first side 10 and the projected length of the second chamfer 40 on the first side 10 is 0.05mm to 8mm, and the specific difference can be 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 6mm, 7mm, 8mm, etc.; indicating that the projected length of the first chamfer 30 on the first side 10 is greater than the projected length of the second chamfer 40 on the first side 10.

[0107] And / or, the difference between the projected length of the first chamfer 30 on the second side 20 and the projected length of the second chamfer 40 on the second side 20 is 0.05mm to 8mm, and the specific difference can be 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 6mm, 7mm, 8mm, etc.; indicating that the projected length of the first chamfer 30 on the second side 20 is greater than the projected length of the second chamfer 40 on the second side 20.

[0108] Within the aforementioned range, the size relationship between the first chamfer 30 and the second chamfer 40 can be easily observed visually. If the difference is less than 0.05mm, it is difficult to identify the positive and negative electrode arrangement order of the solar cell prepared from this silicon wafer. If the difference is greater than 8mm, the projected length of the first chamfer 30 is too large, resulting in more silicon rod removal during silicon wafer preparation, lower utilization of the silicon rod, and increased cost of silicon wafer preparation. Alternatively, if the difference is too large, the second chamfer 40 may be too small, causing stress concentration at the corners of the silicon wafer 4 and increasing the risk of fragmentation. Therefore, the projected lengths of the first and second chamfers on the first and second sides of the silicon wafer, respectively, are within the aforementioned range, which allows for identification of the chamfer size relationship, improves material utilization, and reduces the risk of fragmentation.

[0109] As shown in Figures 7 and 8, in some embodiments, the first chamfer 30 is an arc-shaped chamfer or a linear chamfer; and / or, the second chamfer 40 is an arc-shaped chamfer or a linear chamfer. That is, the first chamfer 30 and the second chamfer 40 can both be arc-shaped chamfers or both be linear chamfers, or the first chamfer 30 can be one of arc-shaped chamfers or linear chamfers, and the second chamfer 40 can be another of arc-shaped chamfers or linear chamfers. When the first chamfer 30 and the second chamfer 40 are the same type of chamfer, it is convenient to use the same grinding process to grind the first chamfer 30 and the second chamfer 40. Of course, when the first chamfer 30 and the second chamfer 40 are different types of chamfers, the chamfering method can be selected according to the needs.

[0110] When the first chamfer 30 and the second chamfer 40 are curved chamfers, the projection length of the curved chamfer on the first side 10 and the second side 20 is the projection length.

[0111] When the chamfer is set to an arc chamfer, less part of the silicon rod is removed, thereby improving the utilization rate of silicon wafer cutting. Since the first side 10 and the second side 20 are smoothly transitioned by an arc chamfer, it can prevent the silicon wafer from having excessive edge stress and excessive wafer breakage rate during transportation or processing.

[0112] When the first chamfer 30 and the second chamfer 40 are linear chamfers, the size of the linear chamfer can be represented by the length of the bevel angle, which is the projected length of the chamfer. Compared with the arc chamfer, the linear chamfer is simple to process, improves processing efficiency, and reduces processing costs. In addition, with the same projected length, the solar cells made from silicon wafers with linear chamfers have a smaller blank space between the solar cells when they are processed into modules, resulting in higher power generation of the modules.

[0113] In some embodiments, the side distance of the first side 10 is 182mm to 300mm. Due to the presence of chamfers, the side length of the first side 10 can be represented by the distance between the two opposing second sides 20. That is, the sum of the length of the first side 10 and the projected length of the two first chamfers 30 on the first side 10 is 182mm to 300mm, defined as the long side distance. The long side distance can specifically be 182mm, 185mm, 190mm, 195mm, 200mm, 205mm, 210mm, 220mm, 230mm, 240mm, 250mm, 270mm, 290mm, 300mm, etc.; the second side 20 The length of the second side 20 is 83mm to 150mm. Due to the presence of chamfers, the length of the second side 20 can be defined as the distance between the two opposite first sides 10, which is 83mm to 150mm. That is, the sum of the length of the second side 20, the projection length of the first chamfer 30 on the second side 20, and the projection length of the second chamfer 40 on the second side 20 is 83mm to 150mm, which is defined as the short side distance. The specific short side distance can be 83mm, 85mm, 90mm, 91mm, 96mm, 100mm, 105mm, 110mm, 115mm, 120mm, 125mm, 135mm, 145mm, 150mm, etc.

[0114] Those skilled in the art choose the first side 10 and the second side 20 within the aforementioned length range. Compared to other side lengths, the silicon rod has a higher utilization rate. At the same time, when using such silicon wafers to prepare modules, the blank area between the cells is small, which can maximize the use of the container size and improve the utilization rate of the container at the module end.

[0115] The silicon rod utilization data corresponding to silicon wafers with different edge distances and different sizes of first chamfer 30 and second chamfer 40 are shown in Table 2 below. The silicon rod utilization rate is the ratio of the area of ​​one side of the silicon wafer 4 prepared after slicing to the area of ​​the circular end face of the circular silicon rod 1 parallel to the slicing direction.

[0116] Table 2. Silicon rod utilization rate corresponding to the projected length of different chamfers on silicon wafers with different edge distances.

[0117] Based on the dimensions of the silicon wafer 4 in the above embodiments and the data in Table 2, it can be seen from Embodiments 8 and 8, and Embodiments 9 and 9, that for the same silicon wafer size, when the projected length of the chamfer is different, the smaller the projected length of the chamfer, the higher the utilization rate of the silicon rod. From Embodiments 9 and 10, when the projected length of the chamfer is the same, the larger the silicon wafer size, the higher the utilization rate of the silicon rod. From Embodiments 11 and 10, it can be seen that when the projected length of the chamfer is the same, the utilization rate of the silicon rod decreases as the silicon wafer size exceeds the range of this application. Therefore, it can be concluded that within the silicon wafer size range of this application, when the projected length of the chamfer is different, the utilization rate of the silicon rod is relatively high.

[0118] As shown in Figure 8, in some embodiments, the surface of the silicon wafer has multiple spaced first ridges 50. The spacing between two adjacent first ridges 50 is 1mm to 4mm, specifically, the spacing between two adjacent first ridges 50 is 1mm, 2mm, 3mm, 4mm, etc. The distance between the highest and lowest points on the first ridge 50 is 0.5mm to 4mm, specifically, the distance between the highest and lowest points on the first ridge 50 can be 0.5mm, 1mm, 2mm, 3mm, 4mm, etc. It should be noted that the first ridges 50 are marks formed on the silicon wafer surface during the slicing process, formed by the grinding between the cutting wire and the silicon wafer surface during the reciprocating movement of the cutting wire. As the silicon rod feeds relative to the cutting wire mesh, the cutting wire bears pressure from the silicon rod, and the cutting wire bends to a certain extent in the feed direction while reciprocating, resulting in each first ridge 50 appearing as a visible arc on the silicon wafer surface. Because the first ridge 50 is arc-shaped, it has a highest point and a lowest point. Figure 8 schematically illustrates a portion of the first ridge 50 on the silicon wafer 4 to show its outline and curvature, but does not represent the actual structure of the first ridge 50. Multiple first ridges 50 are densely arranged along the cutting direction as seen in the figure.

[0119] When the spacing between two adjacent first ridges 50 is less than this range, the first ridges 50 are relatively dense, reducing the mechanical strength of the silicon wafer and lowering the efficiency of slicing by the cutting lines. If the spacing between the first ridges 50 is greater than this range, the excessive spacing of the first ridges 50 affects the appearance of the silicon wafer and can easily cause slippage of the conductive interconnects when the cells are connected in series at the module end.

[0120] The spacing between two adjacent first ridges 50 refers to the distance between the lowest point or the highest point on the first ridge 50. This distance can be measured using a sorting machine or vernier calipers, or it can be obtained from data collected by a displacement sensor. This application does not impose specific limitations on this.

[0121] Typically, the extension direction of the first electrode on the solar cell made from the silicon wafer 4 is the same as the extension direction of the first side of the solar cell. Thus, the extension direction of the first ridge 50 on the solar cell is the same as the extension direction of the first electrode, reducing the risk of the first electrode grid breaking due to the first ridge 50. Therefore, during the fabrication of the silicon wafer 4, the extension direction of the first ridge 50 on the silicon wafer 4 is the same as the extension direction of the first side 10 of the silicon wafer 4.

[0122] In some embodiments, the spacing between two adjacent first textures 50 at the first chamfer 30 is 0.05mm to 3mm, specifically 0.05mm, 1mm, 2mm, or 3mm; and / or, the spacing between two adjacent first textures 50 at the second chamfer 40 is 0.1mm to 4mm, specifically 0.1mm, 0.5mm, 1mm, 2mm, 3mm, or 4mm. If the spacing between two adjacent first textures 50 at the chamfer is less than this range, the first textures 50 at the chamfer are more dense, reducing the mechanical strength of the chamfer. If the spacing between two adjacent first textures 50 is greater than this range, it indicates that the arrangement density of the first textures 50 on the surface of the silicon wafer 4 is lower, the surface of the silicon wafer 4 is smoother, which is not conducive to the positioning of conductive interconnects (such as solder ribbons) and the silicon wafer 4, and may lead to slippage and misalignment, which can easily cause short circuits or poor conductivity. In addition, since the second chamfer 40 is smaller than the first chamfer 30, the stress is more concentrated at the second chamfer 40. Therefore, the spacing between adjacent first textures 50 at the second chamfer 40 is greater than the spacing between two adjacent first textures 50 at the first chamfer 30, in order to reduce the stress concentration at the second chamfer 40 and further reduce the risk of fragmentation and hidden cracks.

[0123] The distance between two adjacent first textures at the first chamfer refers to the distance between the lowest points of two adjacent first textures in the chamfer area. It can usually be detected by a sorting machine or a vernier caliper. For those skilled in the art, the distance between the highest points of the first textures can also be detected. This distance, as the distance between two adjacent first textures, is also within the scope of protection of this application. This application does not limit the method of distance detection.

[0124] It should be further explained that the first texture at the first chamfer refers to the texture formed on the surface of the silicon wafer in the area where the first chamfer is located during the silicon wafer cutting process, when the cutting line reciprocates and grinds against the surface of the silicon wafer. That is, the first texture is on the surface of the silicon wafer, and the surface is in the area where the silicon wafer is chamfered.

[0125] Based on the silicon wafer 4 described in any of the above embodiments, this application also provides a battery cell, which is prepared from the silicon wafer described in any of the above embodiments. The surface of the battery cell has a first electrode that extends along a first side of the silicon wafer. The battery cell can be a back-contact battery cell, with both positive and negative electrodes disposed on the back side of the battery cell.

[0126] Since the solar cells are made from the silicon wafers described in any of the above embodiments, they have the same beneficial effects as the silicon wafers in the above embodiments, and will not be repeated here.

[0127] In some embodiments, the surface of the solar cell has a plurality of spaced-apart first ridges, and the extending direction of the first ridges is the same as the extending direction of the first electrode. This reduces the risk of grid breakage in the first electrode caused by the first ridges.

[0128] It should be noted that the extension direction of the first texture and the first electrode in this application is the same, specifically meaning that the direction of the first texture and the first electrode is basically the same or consistent. Since the first texture has a certain curvature, its extension direction is approximately parallel to the first electrode.

[0129] In some embodiments, the first electrode may include a main grid line and / or a sub-grid line. For a cell without a main grid line, since the sub-grid line is relatively small, the extension direction of the sub-grid line on the half-cell made from the silicon wafer in this application is parallel to the length direction of the cell, which can reduce the risk of grid breakage at the sub-grid line caused by the first ripple.

[0130] This application also provides a photovoltaic module, including at least two solar cells and at least one conductive interconnect. The conductive interconnect connects two adjacent solar cells, and the solar cells are as described in any of the above embodiments. The conductive interconnect can be a solder strip, with one end connected to the positive electrode on the back of the previous solar cell and the other end connected to the negative electrode on the back of the next solar cell, thus achieving positive and negative electrode connection between adjacent solar cells. The positive and negative electrodes of the solar cells are identified and arranged based on the first and second chamfers on the cells to prevent incorrect connection.

[0131] Since the photovoltaic module includes solar cells, it has the same beneficial effects as the silicon wafers and solar cells described in any of the above embodiments, and will not be repeated here.

[0132] Based on the silicon wafer described in any of the above embodiments, this application also provides a method for preparing a silicon wafer, comprising the following steps:

[0133] Step S101: A circular silicon rod 1 is provided. The circular silicon rod 1 can be a silicon rod manufactured by the Czochralski method.

[0134] Step S102: Cut the circular silicon rod 1 to obtain a rectangular silicon rod 2. The rectangular silicon rod 2 has two opposing first surfaces 21 and two opposing second surfaces 22.

[0135] In practical applications, a diamond wire cutting device can be used to cut a circular silicon rod 1. The circular silicon rod 1 can be cut synchronously by forming a rectangle with four diamond wires, or one face of a rectangular silicon rod 2 can be cut out each time by a single diamond wire.

[0136] Step S103: Grind the rectangular silicon rod 2 to obtain a rectangular silicon rod 2 with four first chamfers 30 or four second chamfers 40, or a rectangular silicon rod 2 with two first chamfers 30 and two second chamfers 40. After slicing the rectangular silicon rod 2, a silicon wafer can be obtained by connecting the first surface 21 and the second surface 22 through the first chamfers 30 and / or the second chamfers 40.

[0137] It should be noted that when the chamfer shapes of silicon wafers are the same, if the projected length of the first chamfer 30 is equal to the projected length of the second chamfer 40 (i.e., the first chamfer 30 and the second chamfer 40 are equal), a rectangular silicon rod can be ground to form a rectangular silicon rod with four first chamfers 30 or four second chamfers 40. Slicing the silicon rod will yield a silicon wafer with four identical chamfers. If the projected length of the first chamfer 30 is greater than the projected length of the second chamfer 40 (i.e., the first chamfer 30 and the second chamfer 40 are not equal), grinding the rectangular silicon rod will form a rectangular silicon rod with two first chamfers 30 and two second chamfers 40. Slicing such a silicon rod will yield a silicon wafer with two first chamfers 30 and two second chamfers 40.

[0138] In practical applications, the four surfaces of the rectangular silicon rod 2 and the intersection of the four surfaces are ground and polished by grinding equipment to obtain four flat surfaces and four first chamfers 30. The surfaces of the rectangular silicon rod 2 and the first chamfers 30 can be formed by multiple grinding operations or by grinding simultaneously in one operation. The grinding process is selected according to the grinding equipment.

[0139] During this process, the diamond on the grinding wheel grinds the first chamfer 30 to obtain multiple second grooves 301. The extension direction of the second grooves 301 intersects with the two end faces of the silicon rod.

[0140] For those skilled in the art, the four surfaces of the rectangular silicon rod 2 and the intersection of the four surfaces can also be ground and polished using grinding equipment to obtain four flat surfaces and four second chamfers 40. The surfaces and second chamfers 40 of the rectangular silicon rod 2 can be formed by multiple grinding operations or by grinding simultaneously in one operation, depending on the grinding equipment selected.

[0141] During this process, the diamond on the grinding wheel grinds the second chamfer 40 to obtain multiple first grooves 401. The angle between the extension direction of the first grooves 401 and the surface of the silicon wafer is 0° to 10°.

[0142] As shown in Figure 5, this application also includes a step of cutting the rectangular silicon rod in half before slicing the rectangular silicon rod 2 during silicon wafer preparation, in order to prepare a silicon wafer that can be directly used for solar cell preparation. This eliminates the need to laser scribing the silicon wafer before preparing the solar cell, thus avoiding poor edge passivation of the silicon wafer caused by laser scribing, which would affect the photoelectric conversion efficiency of the solar cell.

[0143] In step S104, the rectangular silicon rod 2 is cut into two equal halves along the cutting plane 23 parallel to the first surface 21 to obtain two rectangular silicon rods, which are half rods 3. Similarly, the rectangular silicon rod 2 can be gradually cut along its length using diamond wire to obtain two identical half rods 3. The newly cut cutting plane 23 is set opposite to and parallel to the first surface 21, and the first surface 21 of each half rod 3 has two first chamfers 30.

[0144] In step S105, the half-bar 3 is ground so that two second chamfers 40 are formed at the junction of the cutting plane 23 and the two second surfaces 22. In practical applications, the same grinding equipment and process as in step S300 can be used to grind and polish the cutting plane 23 and the junction of the cutting plane 23 and the two second surfaces 22 to obtain a flat cutting plane and second chamfers 40. At this time, the projected length of the second chamfer 40 is less than the projected length of the first chamfer 30.

[0145] During this process, the diamond on the grinding wheel grinds the second chamfer 40 to obtain multiple first grooves 401. The extension direction of the first grooves 401 is parallel to the two end faces of the silicon rod. The chamfer size can be referred to the description of the chamfer size in the silicon wafer 4 above, and will not be repeated here.

[0146] Step S106: Slice the half-rod 3 to obtain a silicon wafer 4 with two first chamfers 30 and two second chamfers 40. The silicon wafer 4 has two opposing first edges 10 and two opposing second edges 20. The first edges 10 are obtained by slicing the half-rod 3 with its first surface 21 and cutting plane 23, and the second edges 20 are obtained by slicing the half-rod 3 with its second surface 22. The first chamfers 30 and second chamfers 40 of the silicon wafer 4 correspond to the first chamfers 30 and second chamfers 40 of the half-rod 3, respectively. One of the first edges 10 is connected to two adjacent second edges 20 through the first chamfer 30, and the other first edge 10 is connected to two adjacent second edges 20 through the second chamfer 40.

[0147] During this process, the projected length of the first chamfer 30 can be greater than the projected length of the second chamfer, and the ratio of the length of the first side to the length of the second side can be 1.2 to 6.

[0148] The dimensional descriptions of the first chamfer 30 and the second chamfer 40 of the obtained silicon wafer 4 can be found in the relevant descriptions in the silicon wafer examples, and will not be repeated here.

[0149] In the above technical solution, a circular silicon rod 1 is cut into a rectangular silicon rod 2, which is then ground to obtain four first chamfers 30. The rectangular silicon rod 2 is then cut into two equal halves 3, each half having two first chamfers 30. The half-rocks 3 are then ground to obtain two new second chamfers 40. Finally, the half-rocks are sliced ​​to obtain a silicon wafer 4 with two first chamfers 30 and two second chamfers 40. Compared to the existing method of using a laser to scribing a large silicon wafer to obtain half-wafers, which causes damage and defects on the cross-section of the silicon wafer, affecting the photoelectric conversion efficiency of the solar cell, this application directly obtains half-wafers during the silicon rod processing and after slicing. Because both the rectangular silicon rod and the half-rocks are ground, the surface and chamfer morphology of the silicon rod are relatively smooth. The side and chamfer morphology of the half-wafer obtained directly after slicing are better. After preparing the solar cell, the passivation effect of the solar cell can be improved, thereby improving the quality of the solar cell and increasing the photoelectric conversion efficiency. Furthermore, the projected length of the second chamfer 40 of the prepared silicon wafer 4 is smaller than the projected length of the first chamfer 30. After the silicon wafer 4 is prepared into a back contact half-cell, since the two opposite sides of the back contact half-cell are two sets of first chamfer 30 and second chamfer 40 of different sizes, it already has a chamfer structure of different sizes and shapes that can distinguish the positive and negative electrode directions. Therefore, there is no need to set additional marks on the silicon wafer or cell, which saves the marking process, saves time, and improves processing efficiency.

[0150] As shown in Figure 6, based on the silicon wafer described in any of the above embodiments, this application also provides another silicon wafer fabrication method, including the following steps:

[0151] Step S201: A circular silicon rod 1 is provided. The circular silicon rod 1 can be a silicon rod manufactured by the Czochralski method.

[0152] Step S202: Cut the circular silicon rod 1 to obtain a rectangular silicon rod 2. The rectangular silicon rod 2 has two opposing first surfaces 21 and two opposing second surfaces 22.

[0153] In practical applications, a diamond wire cutting device can be used to cut a circular silicon rod 1. The circular silicon rod 1 can be cut synchronously by forming a rectangle with four diamond wires, or one face of a rectangular silicon rod 2 can be cut out each time by a single diamond wire.

[0154] In step S203, the rectangular silicon rod 2 is cut into two equal halves along the cutting plane 23 parallel to the first surface 21 to obtain two half rods 3. Similarly, the rectangular silicon rod 2 can be gradually cut along its length using diamond wire to obtain two identical half rods 3. The newly cut cutting plane 23 is set opposite to and parallel to the first surface 21. At this time, the half rods 3 do not have grinding chamfers.

[0155] Step S204: Grind the half rod 3 so that two first chamfers 30 are formed at the connection between the first surface 21 and the two second surfaces 22 of the half rod 3, and two second chamfers 40 are formed at the connection between the cutting plane 23 and the two second surfaces 22 of the half rod 3.

[0156] During this process, the diamond abrasive of the grinding wheel grinds the second chamfer 40 to obtain multiple first grooves. The extension direction of the first grooves can be parallel to the two end faces of the silicon rod. The diamond abrasive of the grinding wheel grinds the first chamfer 30 to obtain multiple second grooves. The extension direction of the second grooves can intersect with the two end faces of the silicon rod.

[0157] In practical applications, the four surfaces and the intersections of the four surfaces of the half rod 3 are ground and polished by grinding equipment to obtain four flat surfaces and two first chamfers 30 and two second chamfers 40. The surface of the rectangular silicon rod 2 can be formed by multiple grinding operations or by grinding simultaneously in one operation. The grinding process is selected according to the grinding equipment, and the first chamfers 30 and the second chamfers 40 are ground separately. The chamfer dimensions can be referred to the description of the chamfer dimensions in the silicon wafer above, and will not be repeated here.

[0158] In step S205, the half-rod 3 is sliced ​​to obtain a silicon wafer 4 with two first chamfers 30 and two second chamfers 40. The silicon wafer 4 has two opposing first edges 10 and two opposing second edges 20. The first edges 10 are obtained by slicing the half-rod 3 with its first surface 21 and cutting plane 23, and the second edges 20 are obtained by slicing the half-rod 3 with its second surface 22. The first chamfers 30 and 40 of the silicon wafer 4 correspond to the first chamfers 30 and 40 of the half-rod 3, respectively. One of the first edges 10 is connected to two adjacent second edges 20 through the first chamfer 30, and the other first edge 10 is connected to two adjacent second edges 20 through the second chamfer 40.

[0159] During this process, the projected length of the first chamfer 30 can be greater than the projected length of the second chamfer.

[0160] The dimensional descriptions of the first chamfer 30 and the second chamfer 40 of the obtained silicon wafer 4 can be found in the relevant descriptions in the silicon wafer examples, and will not be repeated here.

[0161] In the above technical solution, a circular silicon rod 1 is cut into a rectangular silicon rod 2, which is then cut into two equal halves 3. The halves 3 are then ground to obtain two first chamfers 30 and two second chamfers 40. Finally, the halves 3 are sliced ​​to obtain a silicon wafer 4 with two first chamfers 30 and two second chamfers 40. Compared to the existing method of using a laser to scribing a large silicon wafer to obtain half wafers, which causes damage and defects on the cross-section of the silicon wafer, affecting the photoelectric conversion efficiency of the solar cell, this application directly obtains half wafers during the silicon rod processing and after slicing. Because both the rectangular silicon rod and the half wafers are ground, the surface and chamfer morphology of the silicon rod are relatively smooth. The side surface and chamfer morphology of the half wafer obtained directly after slicing are better. After preparing the solar cell, the passivation effect of the solar cell can be improved, thereby improving the quality of the solar cell and increasing the photoelectric conversion efficiency. Furthermore, the size of the second chamfer 40 of the prepared silicon wafer 4 is smaller than the size of the first chamfer 30. After the silicon wafer is used to prepare a back-contact half-cell, since the two opposite sides of the back-contact half-cell have two sets of first and second chamfers of different sizes, the placement direction of the cell can be easily identified, which helps to align the PN regions between multiple cells and distinguish the positive and negative electrodes. For example, when multiple cells are arranged to form a cell string for a module, if each cell is placed in the same direction and aligned in a column with the first chamfer 30, second chamfer 40, first chamfer 30, and second chamfer 40 in sequence, the P region of the previous cell will automatically align with the P region or N region of the next cell. This allows for easy selection of appropriate conductive interconnects and string bonding processes to produce the cell module. Therefore, there is no need to set additional markings on the silicon wafer or cell, eliminating the marking process, saving time, and improving processing efficiency.

[0162] Furthermore, the difference between the second silicon wafer preparation method and the first silicon wafer preparation method is that the first chamfer 30 and the second chamfer 40 are obtained by grinding after halving. This can further simplify the grinding and cutting process, reduce the number of times the equipment needs to be changed between grinding and cutting equipment, and further improve the processing efficiency.

[0163] In both of the above silicon wafer fabrication methods, the first chamfer 30 can be a portion of the curved surface of the circular silicon rod 1. That is, when the circular silicon rod 1 is cut into a rectangular silicon rod 2, the rectangular silicon rod 2 retains a portion of the curved surface of the circular silicon rod 1, which is then ground and directly used as the first chamfer 30. In this way, the slicing utilization rate of the circular silicon rod 1 can be improved, the waste of silicon rod material can be reduced, and the cost can be lowered.

[0164] In the two silicon wafer fabrication methods described above, the slicing of the half-rod 3 in steps S106 and S205 specifically includes the following steps:

[0165] The first surface 21 or the cutting plane 23 of the half-rod 3 is bonded to the carrier plate, and the distance between the two second surfaces 22 is greater than the distance between the first surface 21 and the cutting plane 23. The carrier plate can be a resin plate or a plastic plate, and the half-rod 3 is bonded and fixed to the crystal holder through the carrier plate.

[0166] The carrier plate and the dicing wire mesh are moved closer to each other along a direction perpendicular to the first surface 21, and the half rod 3 is sliced ​​by the moving dicing wire mesh. In a specific application, the crystal holder is driven to move, which causes the carrier plate and the half rod 3 to move closer to each other relative to the dicing wire mesh. At the same time, the dicing wire mesh performs wire cutting, and the half rod 3 is cut by the dicing wire mesh until it is cut into the carrier plate, thus completing the slicing.

[0167] Afterwards, the drive crystal holder moves the cut silicon wafer away from the cutting wire mesh, completing the slicing and separating the adjacent attached silicon wafers 4. Finally, the silicon wafer 4 is separated from the carrier to obtain silicon wafer 4.

[0168] When the above technical solution is adopted, the slicing direction of the half rod 3 makes the first ridge 50 on the silicon wafer 4 parallel to the long side direction of the silicon wafer 4, that is, the first side 10. The extension direction of the first electrode on the half cell made from the silicon wafer is parallel to the long side direction of the half cell, so that the first electrode is parallel to the first ridge on the cell, thereby reducing the risk of grid breakage of the first electrode caused by the first ridge.

[0169] When the above technical solution is adopted, the first electrode may include a main grid line and / or a sub-grid line. For a cell without a main grid line, since the sub-grid line is relatively small, the extension direction of the sub-grid line on the half cell made from the silicon wafer in this application is parallel to the long side direction of the cell, which can reduce the risk of grid breakage at the sub-grid line caused by the first ripple.

[0170] In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. That is, in the above one or more embodiments, an embodiment can exist alone or be combined with other embodiments, and the technical features of the above embodiments can be combined arbitrarily. The descriptions of each embodiment above have their own emphasis, and for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described; however, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0171] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A silicon wafer, wherein, The silicon wafer has a first surface and a second surface, and a side surface located between the first surface and the second surface. Each of the first surface and the second surface has two opposing first edges and two opposing second edges. One of the first edges is connected to the two adjacent second edges through a first chamfer on the side surface of the silicon wafer, and the other first edge is connected to the two adjacent second edges through a second chamfer on the side surface of the silicon wafer. The ratio of the length of the first edge to the length of the second edge is 1.2 to 6.

2. The silicon wafer according to claim 1, wherein, The projected length of the first chamfer is less than 5mm, and the projected length of the first chamfer is greater than or equal to the projected length of the second chamfer; The side where the second chamfer is located has a plurality of first grooves, and the angle between the extension direction of the first grooves and the first surface and / or the second surface of the silicon wafer is 0° to 10°.

3. The silicon wafer according to claim 1, wherein, The length of the first chamfer is greater than the length of the second chamfer.

4. The silicon wafer according to any one of claims 1-3, wherein, The length of the first side is 182mm to 300mm, and the length of the second side is 91mm to 150mm.

5. The silicon wafer according to claim 2, wherein, The second chamfer is an arc-shaped chamfer, and the first angle between the tangent of the end of the arc-shaped chamfer that connects to the first side and the first side is 30° to 60°. And / or, the second included angle between the tangent of the end of the arc chamfer connected to the second side and the second side is 30° to 50°.

6. The silicon wafer according to claim 2, wherein, The second chamfer is a linear chamfer, and the angle between the linear chamfer and the first side is 35° to 85°.

7. The silicon wafer according to claim 2, wherein, The side where the first chamfer is located has a plurality of second grooves, the extension direction of which intersects the first surface and / or the second surface of the silicon wafer.

8. The silicon wafer according to claim 3, wherein, The projected length of the first chamfer is greater than or equal to 0.05 mm and less than or equal to 9 mm; And / or, the projected length of the second chamfer is greater than 0 mm and less than or equal to 8.5 mm.

9. The silicon wafer according to claim 3, wherein, The difference between the projected length of the first chamfer on the first side and the projected length of the first chamfer on the second side is less than or equal to 2 mm; And / or, the difference between the projected length of the second chamfer on the first side and the projected length on the second side is less than or equal to 1 mm.

10. The silicon wafer according to claim 3, wherein, The projection length of the first chamfer on the first side is 0.05mm to 9mm, and the projection length of the first chamfer on the second side is 0.05mm to 7mm. And / or, the projection length of the second chamfer on the first side is 0.05mm to 5mm, and the projection length of the second chamfer on the second side is 0.05mm to 5mm.

11. The silicon wafer according to claim 3, wherein, The difference between the projected length of the first chamfer on the first side and the projected length of the second chamfer on the first side is 0.05mm to 8mm; And / or, the difference between the projected length of the first chamfer on the second side and the projected length of the second chamfer on the second side is 0.05mm to 8mm.

12. The silicon wafer according to claim 3, wherein, The distance between two opposing second sides is 182mm to 300mm, and the distance between two opposing first sides is 83mm to 150mm.

13. The silicon wafer according to claim 3, wherein, The surface of the silicon wafer has a plurality of spaced first lines, the spacing between two adjacent first lines is 1 mm to 4 mm, and the distance between the highest point and the lowest point on the first line is 0.5 mm to 4 mm.

14. A type of battery cell, wherein, The solar cell is prepared from a silicon wafer according to any one of claims 1-13, and the surface of the solar cell has a first electrode extending along a first side of the silicon wafer.

15. The battery cell according to claim 14, wherein, The surface of the battery cell has a first texture, and the first texture extends in the same direction as the first electrode.

16. A photovoltaic module comprising at least two solar cells and at least one conductive interconnect, the conductive interconnect connecting two adjacent solar cells, wherein, The battery cell is the battery cell as described in any one of claims 14-15.

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