Solar cell and photovoltaic module

Abstract

The present application discloses a solar cell and a photovoltaic module. The solar cell comprises: a cell body, comprising a first surface and a second surface that are disposed opposite each other; a passivation layer at least disposed on the first surface, and the passivation layer being provided with a plurality of openings extending through a thickness of the passivation layer; a seed layer, comprising a portion disposed corresponding to the openings, and an overflow portion extending from the openings to a side of the passivation layer away from the cell body, a ratio of a width of the overflow portion in a first direction to a thickness of the overflow portion in a thickness direction of the cell body being 0.5-10, and the first direction being parallel to the first surface. This not only ensures sufficient adhesion between a seed layer and a cell body and reduces the risk of detachment, but also ensures an appropriate contact area between the seed layer and an electrode, allowing for relatively small contact resistance between the seed layer and the electrode.

Description

A solar cell and a photovoltaic module

[0001] This application claims priority to Chinese Patent Application No. 202510012368.8, filed on January 3, 2025, entitled "A Solar Cell and a Photovoltaic Module," the entire contents of which are incorporated herein by reference; this application claims priority to Chinese Patent Application No. 202510773451.7, filed on June 10, 2025, entitled "A Solar Cell and a Photovoltaic Module," the entire contents of which are incorporated herein by reference; this application claims priority to Chinese Patent Application No. 202511841485.1, filed on December 8, 2025, entitled "A Solar Cell and a Photovoltaic Module," the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of photovoltaic technology, and more particularly to a solar cell and a photovoltaic module. Background Technology

[0003] Solar cells are increasingly being used as a new energy alternative. Photovoltaic solar cells, in particular, are devices that convert sunlight into electrical energy. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, thus facilitating the efficient use of electrical energy.

[0004] As the photovoltaic industry market and production capacity continue to expand, the industry's demand for silver paste has also surged, causing the price of silver paste to rise accordingly, increasing costs and squeezing profit margins. Summary of the Invention

[0005] The purpose of this application is to provide a solar cell that reduces the manufacturing cost of the solar cell while improving the adhesion of the transport layer and preventing the transport layer from falling off.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] A solar cell, comprising:

[0008] The battery body includes a first surface and a second surface that are disposed opposite to each other;

[0009] An anti-reflective layer is provided on at least the first surface, and the anti-reflective layer has an opening that penetrates its thickness;

[0010] The seed layer includes a portion disposed corresponding to the opening and an overflow portion extending from the opening to the side of the anti-reflection layer away from the battery body; wherein the ratio of the width of the overflow portion along the first direction to the thickness of the overflow portion along the thickness direction of the battery body is 0.5 to 10; the first direction is parallel to the first surface.

[0011] If the width of the overflow portion is small and its thickness is much greater than its width, the adhesion between the seed layer and the battery body cannot be guaranteed, making it prone to detachment. Conversely, if the width of the overflow portion is much greater than its thickness, the thickness of the overflow portion is too small, and the width of the overflow portion is much greater than its thickness, which increases the contact resistance between the seed layer and the transport layer. In view of the above, this technical solution controls the width and thickness of the overflow portion within the range of 0.5 to 10. This ensures sufficient adhesion between the seed layer and the battery body, reducing the risk of detachment, while also ensuring a moderate contact area between the seed layer and the transport layer, and minimizing the contact resistance between them.

[0012] Optionally, the width of the overflow portion along the first direction is less than the thickness of the overflow portion along the thickness direction of the battery body. With this configuration, the thickness of the overflow portion along the thickness direction of the battery body is slightly greater than its width along the first direction. The relatively thicker seed layer can better prevent water, oxygen, and other elements from entering the battery body at the opening, reducing the erosion or damage caused by these elements. Furthermore, the contact area between the overflow portion and the transport layer along the thickness direction of the battery body can be appropriately increased, i.e., the contact area between the side of the overflow portion and the transport layer can be increased, further improving the contact area between the seed layer and the transport layer, reducing the contact resistance between the seed layer and the transport layer, and decreasing current loss.

[0013] Optionally, the ratio of the width of the overflow portion along the first direction to the thickness of the overflow portion along the thickness direction of the battery body is 0.5 to 1. With this setting, the thickness of the overflow portion along the thickness direction of the battery body is slightly greater than the width of the overflow portion along the first direction, which can reduce the erosion or damage to the battery body by other elements.

[0014] Optionally, the width of the overflow portion along the first direction is greater than the thickness of the overflow portion along the thickness direction of the battery body. In this case, the seed layer can be formed by chemical plating. This configuration results in a larger width of the overflow portion along the first direction, which increases the area of ​​the upper surface of the seed layer, thereby increasing the contact area between the upper surface of the seed layer and the transport layer, improving the adhesion between the upper surface of the seed layer and the transport layer, and further reducing the risk of transport layer detachment; at the same time, it reduces the contact resistance between the upper surface of the seed layer and the transport layer, reducing current loss.

[0015] Optionally, the ratio of the width of the overflow portion along the first direction to the thickness of the overflow portion along the thickness direction of the battery body is 1 to 10. This configuration can increase the contact area between the upper surface of the seed layer and the transport layer, improve the adhesion between the upper surface of the seed layer and the transport layer, and further reduce the risk of the transport layer falling off; it can also reduce the contact resistance between the upper surface of the seed layer and the transport layer, thereby reducing current loss.

[0016] Alternatively, the seed layer fills the opening, with the overflow portion protruding beyond it. This arrangement, where the overflow portion surrounds the opening, facilitates processing and manufacturing.

[0017] Optionally, along the length or width of the battery body, the width of the overflow portion on the first side of the opening is greater than the width of the overflow portion on the second side.

[0018] Optionally, the thickness of the overflow portion along the thickness direction of the battery body is 60nm to 1200nm; this is to prevent the overflow portion thickness h from being too thick, which would prolong the process time, and to ensure that the upper surface area of ​​the seed layer is moderate, thereby ensuring sufficient adhesion between the seed layer and the battery body. Simultaneously, it prevents the overflow portion thickness h from being too small, which would result in an insufficient contact area between the side of the overflow portion and the transport layer, increasing the contact resistance between the seed layer and the transport layer. And / or,

[0019] Along the first direction, the width of the overflow portion is 60nm to 1200nm. This is to prevent the width b of the overflow portion from being too small, thereby ensuring sufficient adhesion between the seed layer and the battery body, while reducing the contact resistance between the seed layer and the transport layer; at the same time, it is to prevent the width b of the overflow portion from being too wide, which would lead to material waste.

[0020] Optionally, along the first direction, the ratio of the width of the overflow portion to the maximum width of the seed layer projected onto the first surface is 0.05-0.2. This technical solution avoids excessively wide overflow portions, which would lead to material waste; simultaneously, it ensures a large contact area between the seed layer and the transport layer, thereby guaranteeing sufficient adhesion between the seed layer and the battery body.

[0021] Optionally, along the thickness direction of the battery body, the ratio of the thickness of the overflow portion to the thickness of the corresponding opening in the seed layer is 50%-96%. This setting can prevent the thickness h of the overflow portion from being too small, which would result in an insufficient contact area between the side of the overflow portion and the transmission layer, increasing the contact resistance between the seed layer and the transmission layer.

[0022] Optionally, the thickness of the antireflective layer is 60nm to 180nm along the thickness direction of the battery body. This ensures passivation while preventing extended processing time.

[0023] Optionally, the battery body includes a silicon substrate, a first doped semiconductor layer and a second doped semiconductor layer, wherein the first doped semiconductor layer is disposed on a first surface of the silicon substrate, and the second doped semiconductor layer is disposed on either the first or second surface of the silicon substrate, and the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types.

[0024] An anti-reflection layer covers the side of the first doped semiconductor layer and the second doped semiconductor layer away from the silicon substrate. The anti-reflection layer has a first opening corresponding to the first doped semiconductor layer and a second opening corresponding to the second doped semiconductor layer. Along the first direction, the equivalent width of the first opening is different from the equivalent width of the second opening.

[0025] The number of first openings is multiple and arranged along the second direction, the number of second openings is multiple and arranged along the second direction, and the first direction and the second direction intersect.

[0026] The equivalent width is defined as the ratio of the area of ​​the first opening to the distance between two adjacent first openings, or the ratio of the area of ​​the second opening to the distance between two adjacent second openings. This configuration ensures that the contact resistance between the doped semiconductor layer with lower conductivity and the seed layer is equal to or closer to the contact resistance between the doped semiconductor layer with higher conductivity and the seed layer. This reduces the current difference between the seed layer and the second doped semiconductor layer, as well as between the seed layer and the first doped semiconductor layer, thereby reducing current loss and ensuring battery performance. Furthermore, after pretreatment of the battery body, the first and second openings have different plating activity. Therefore, the equivalent widths of the first and second openings are different, allowing the openings with lower plating activity to have a wider equivalent width, thus reducing the plating difficulty.

[0027] Optionally, the second doped semiconductor layer is a P-type doped semiconductor layer; along the first direction, the equivalent width of the first opening is smaller than the equivalent width of the second opening; thus, when the conductivity of the first doped semiconductor layer is greater than that of the second doped semiconductor layer, it is ensured that the contact resistance between the second doped semiconductor layer with lower conductivity and the transport layer is equal to or closer to the contact resistance between the first doped semiconductor layer with higher conductivity and the transport layer, thereby reducing the current difference between the transport layer and the second doped semiconductor layer and between the transport layer and the first doped semiconductor layer, and reducing the current loss of the battery.

[0028] And / or, along the first direction, the equivalent width of the first opening is 3μm to 20μm; this makes the equivalent width of the first opening more compatible with the conductivity of the first doped semiconductor, reduces the contact resistance between the first doped semiconductor and the transport layer, and reduces current loss; at the same time, it avoids damage to the battery during the laser opening process and reduces recombination.

[0029] And / or, along the first direction, the equivalent width of the second aperture is 5μm to 30μm. This makes the equivalent width of the second aperture more compatible with the conductivity of the second doped semiconductor, reducing the contact resistance between the second doped semiconductor and the transport layer, and reducing current loss; at the same time, it avoids damage to the cell during laser aperture opening and reduces recombination.

[0030] Optionally, the total area of ​​the first opening is different from the total area of ​​the second opening. To maximize the contact area between the doped semiconductor layer with lower conductivity and the seed layer, in some examples, the equivalent width of the opening in the doped semiconductor layer with lower conductivity can be set larger. This makes the contact resistance between the doped semiconductor layer with lower conductivity and the transport layer equal to or closer to the contact resistance between the doped semiconductor layer with higher conductivity and the transport layer. This reduces the current difference between the transport layer and the second doped semiconductor layer and between the transport layer and the first doped semiconductor layer, reducing current loss in the battery and ensuring battery performance.

[0031] Optionally, the battery body includes a silicon substrate, a first doped semiconductor layer, and a second doped semiconductor layer. The first doped semiconductor layer is disposed on a first surface of the silicon substrate, and the second doped semiconductor layer is disposed on either the first or second surface of the silicon substrate. The first and second doped semiconductor layers have opposite conductivity types. An anti-reflection layer covers the side of the first and second doped semiconductor layers that is away from the silicon substrate. The anti-reflection layer has a first opening corresponding to the first doped semiconductor layer and a second opening corresponding to the second doped semiconductor layer.

[0032] The seed layer includes a first seed layer and a second seed layer. The first seed layer includes a portion disposed at the first opening and a first overflow portion extending from the first opening to the side of the anti-reflection layer away from the battery body. The second seed layer includes a portion disposed at the second opening and a second overflow portion extending from the second opening to the side of the anti-reflection layer away from the battery body.

[0033] Along the first direction, the width of the first overflow portion and the width of the second overflow portion are different.

[0034] Optionally, the solar cell further includes a transport layer disposed on the side of the seed layer away from the cell body, the transport layer covering at least a portion of the surface of the seed layer away from the cell body.

[0035] Optionally, the transport layer covers the surface and sides of the seed layer away from the cell body, thereby maximizing the contact area between the transport layer and the seed layer, further reducing the contact resistance between the transport layer and the seed layer, and improving the efficiency of the solar cell.

[0036] And / or, the width of the transport layer is 40μm to 200μm. By adopting this technical solution, setting the transport layer within a reasonable range of 40μm to 200μm can prevent leakage caused by excessively wide transport layer width contacting the doped semiconductor layer with opposite polarity, while also preventing excessively narrow transport layer width to ensure low contact resistance between the transport layer and the seed layer.

[0037] Optionally, the thickness of the overflow portion gradually decreases along the direction from the center of the opening to the edge. This makes the contact between the seed layer and the transport layer stronger, further reducing the risk of detachment.

[0038] The purpose of this application is to provide a solar cell that reduces the manufacturing cost of solar cells while reducing current transmission loss and improving the adhesion of the transmission layer.

[0039] To achieve the above objectives, this application provides the following technical solution:

[0040] A solar cell, comprising:

[0041] A silicon substrate, the silicon substrate including opposing first and second surfaces, the first surface having a first doped semiconductor layer;

[0042] An anti-reflection layer covers at least the side of the first doped semiconductor layer opposite to the silicon substrate;

[0043] A first seed layer, which is electrically connected to a first doped semiconductor layer through an antireflection layer; a plurality of first metal particles and a plurality of second metal particles deposited on at least a local surface of the first metal particles, wherein the particle size of the first metal particles is a, the particle size of the second metal particles is b, ab≥40nm and / or a≥1.5b;

[0044] Multiple first transport layers extend along a first direction and are spaced apart along a second direction, with at least a portion of the first transport layers disposed on the side of the first seed layer away from the silicon substrate.

[0045] Wherein, the second direction is orthogonal to the first direction; when the first direction is the length direction of the battery body, the second direction is the width direction of the battery body; when the first direction is the width direction of the battery body, the second direction is the length direction of the battery body.

[0046] The first seed layer comprises a plurality of first metal particles stacked together; and a plurality of second metal particles are stacked on at least a partial surface of the first metal particles, wherein the particle size 'a' of the first metal particles and the particle size 'b' of the second metal particles differ by at least 40 nm, and / or, 'a' ≥ 1.5b. Using this technical solution, the particle size of the first metal particles is relatively large, and the stacking of multiple first metal particles creates a height difference between the multiple first metal particles on the surface of the first seed layer. Simultaneously, the placement of multiple second particles on the upper side of the first metal particles increases the surface undulation of the first seed layer, thereby increasing the surface roughness of the first seed layer and thus increasing its specific surface area. After the first transport layer comes into contact with the first seed layer, it creates more metal contact points between the first seed layer and the first transport layer, thereby forming more metal contacts, reducing the contact resistance between the first seed layer and the first transport layer, and improving the power generation efficiency of the battery. At the same time, it improves the adhesion of the first transport layer, preventing it from detaching. Furthermore, when multiple second metal particles surround the first metal particles, the smaller particle size of the second metal particles is suitable for reducing current transmission loss between adjacent first metal particles, improving current transmission efficiency between adjacent first metal particles, and further improving the power generation efficiency of the battery.

[0047] Optionally, 100nm ≥ a ≥ 1000nm; and / or, 10nm ≥ b ≥ 60nm; and / or, ab ≤ 990nm; and / or, a ≤ 100b.

[0048] Optionally, the first doped semiconductor layer is an N-type doped semiconductor layer, and the second doped semiconductor layer is a P-type semiconductor layer; the particle size of the first metal particle in the first seed layer is a1, and the particle size of the second metal particle in the first seed layer is b1; the particle size of the first metal particle in the second seed layer is a2, and the particle size of the second metal particle in the first seed layer is b2.

[0049] a1≥a2; and / or, b1≥b2; and / or, the number of first metal particles contained in the first seed layer is greater than the number of first metal particles contained in the second seed layer; and / or, the number of second metal particles contained in the first seed layer is greater than the number of second metal particles contained in the second seed layer.

[0050] Optionally, the antireflection layer has a plurality of first openings exposing the first doped semiconductor layer; the first seed layer includes a portion disposed corresponding to the first openings and a second overflow portion located on the side of the antireflection layer away from the silicon substrate.

[0051] Using the above technical solution, the first seed layer further includes a second overflow portion located on the side surface opposite to the silicon substrate. The formation of the second overflow portion increases the contact area between the first seed layer and the first transport layer, which helps to improve the adhesion between the first transport layer and the first seed layer, prevents the first transport layer from falling off, and thus improves the performance stability of the solar cell. Furthermore, when the overflow portion is conductively connected to the portion of the first seed layer corresponding to the first opening, it helps to improve the conductivity between the first seed layer and the first transport layer, reduce transmission loss, and improve current transmission efficiency.

[0052] Optionally, the second overflows around at least two adjacent first openings are at least partially connected.

[0053] Optionally, the second overflow portion is dispersed around the first opening.

[0054] Optionally, the first doped semiconductor layer is an N-type doped semiconductor layer, and the width of the first opening is 3μm to 20μm; or, the first doped semiconductor layer is a P-type doped semiconductor layer, and the width of the first opening is 5μm to 30μm.

[0055] This invention provides a solar cell and a photovoltaic module to solve the problem of degraded electrical performance of the electrode transport layer in related technologies.

[0056] To solve the above problems, the present invention is implemented as follows:

[0057] In a first aspect, embodiments of the present invention provide a solar cell, comprising:

[0058] Silicon substrate, doped semiconductor layer, antireflection layer, and electrodes;

[0059] The electrode includes a seed layer and a transport layer;

[0060] The doped semiconductor layer is disposed on at least one surface of the silicon substrate; at least a portion of the doped semiconductor layer on the side opposite to the silicon substrate is provided with the anti-reflection layer; the surface of the doped semiconductor layer includes openings where the anti-reflection layer is not disposed.

[0061] The seed layer is disposed on the side of the doped semiconductor layer opposite to the silicon substrate, and the seed layer at least covers the opening; the transport layer is disposed on the side of the seed layer opposite to the doped semiconductor layer.

[0062] The height of the edge region of the seed layer is greater than the height of the seed layer away from the edge region.

[0063] Optionally, the height difference between the position at the edge region of the seed layer and the position in the seed layer away from the edge region is 20-300 nm.

[0064] Optionally, the doped semiconductor layer includes a first doped semiconductor layer and a second doped semiconductor layer;

[0065] The first doped semiconductor layer is an N-type doped semiconductor layer, and the second doped semiconductor layer is a P-type semiconductor layer;

[0066] The seed layer in the opening on the surface of the first doped semiconductor layer is the first seed layer, and the seed layer in the opening on the surface of the second doped semiconductor layer is the second seed layer.

[0067] From the position in the edge region to the position away from the edge region, the rate of change of the height of the first seed layer is less than the rate of change of the height of the second seed layer.

[0068] Alternatively, the height difference between the position of the first seed layer in the edge region and the position away from the edge region is less than the height difference between the position of the second seed layer in the edge region and the position away from the edge region.

[0069] Optionally, the surface of the doped semiconductor layer located in the opening has a first protrusion structure;

[0070] For the seed layer located in the opening, the height of the seed layer is positively correlated with the density of the first protrusion structure on the surface of the doped semiconductor layer.

[0071] Optionally, the seed layer has a plurality of second protrusion structures on the side near the transport layer.

[0072] Optionally, the number of second protrusions on the side of the first seed layer closest to the transmission layer is greater than the number of second protrusions on the side of the second seed layer closest to the transmission layer.

[0073] Optionally, along the thickness direction of the solar cell, the projection of the second protrusion structure into the opening coincides with at least a portion of the first protrusion structure.

[0074] Optionally, the height of the seed layer is greater than the height of the antireflection layer, and the seed layer extends beyond the opening to cover part of the antireflection layer.

[0075] Optionally, in the seed layer, the thickness located in the opening and close to the edge of the opening is the first thickness D1, the thickness extending outward from the opening in the seed layer is the second thickness D2, and the thickness of the anti-reflection layer is the third thickness D3, then: D1≥D2+D3.

[0076] Optionally, the first thickness D1 and the second thickness D2 satisfy: D1:D2=4:(1~3).

[0077] Optionally, in the seed layer, the thickness extending beyond the opening is the second thickness D2, and the width extending beyond the opening is the first width W1, then: D2:W1 = 0.25:(1~3).

[0078] Optionally, in the seed layer, the width of the portion located in the opening along the extension direction perpendicular to the electrode is the second width W2, then along the extension direction perpendicular to the electrode, we have: W1:W2 = 1:(25~900).

[0079] Optionally, the seed layer has at least one recess on the side near the transport layer, and the transport layer has at least one protrusion on the side near the seed layer; the protrusion engages with the recess.

[0080] Optionally, the thickness of the antireflection layer is 50-150 nm, and / or the thickness of the seed layer is 300-1200 nm, and / or the thickness of the doped semiconductor layer located outside the opening is 50-250 nm.

[0081] In a second aspect, embodiments of the present invention provide a photovoltaic module, including a cover plate, a back sheet, and a battery string disposed between the cover plate and the back sheet, the battery string including a plurality of solar cells connected in series by interconnecting elements; the solar cells including the solar cells described in any one of the first aspects above.

[0082] In this invention, the solar cell includes a silicon substrate, a doped semiconductor layer, an antireflection layer, and an electrode. The electrode includes a seed layer and a transport layer. The seed layer at least covers the opening in the doped semiconductor layer where the antireflection layer is not located, ensuring good ohmic contact between the electrode and the doped semiconductor layer. A transport layer is located on the seed layer to collect current. The height of the edge region of the seed layer is greater than the height of the region away from the edge of the seed layer. When openings are created using a laser, the antireflection layer at the opening edge is prone to cracking due to the heat effect of the laser, and the antireflection layer near the opening edge becomes thinner. This reduces the blocking effect of the antireflection layer on the transport layer near the opening, allowing metal ions in the transport layer to easily diffuse into the opening of the doped semiconductor layer, inducing undesirable metal recombination and weakening the electrical performance of the solar cell. In this invention, the higher edge region of the seed layer allows it to effectively block the transport layer, preventing the main metal ions of the transport layer from diffusing into the doped semiconductor layer through the opening edge, avoiding metal recombination, and ensuring the electrical performance of the solar cell.

[0083] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0084] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0085] Figure 1 is a schematic diagram of a photovoltaic module provided in an embodiment of this application;

[0086] Figure 2 is a cross-sectional view of the battery body provided in an embodiment of this application;

[0087] Figure 3 is a partial cross-sectional view of the solar cell provided in an embodiment of this application;

[0088] Figure 4 is a partial enlarged view of the edge of the seed layer provided in an embodiment of this application;

[0089] Figure 5 is a SEM image of the overflow portion of the seed layer provided in the embodiment of this application;

[0090] Figure 6 is a partial cross-sectional SEM image of the solar cell provided in the embodiment of this application;

[0091] Figure 7 is a SEM image of the first seed layer provided in an embodiment of this application;

[0092] Figure 8 is a cross-sectional SEM image of the first seed layer provided in an embodiment of this application;

[0093] Figure 9 is a top-view SEM image of the first seed layer provided in an embodiment of this application;

[0094] Figure 10 is a schematic diagram of the N-region seed layer provided in an embodiment of this application;

[0095] Figure 11 is a schematic diagram of the P-region seed layer provided in an embodiment of this application;

[0096] Figure 12 is a partial cross-sectional view of a solar cell provided in another embodiment of this application;

[0097] Figure 13 is a top-view SEM image of the passivation layer opening of the solar cell provided in the embodiment of this application;

[0098] Figure 14 is a partial top-view SEM image of the solar cell provided in the embodiment of this application;

[0099] Figure 15 is a partial top view of the solar cell provided in an embodiment of this application;

[0100] Figure 16 is a partial top view of a solar cell provided in another embodiment of this application;

[0101] Figure 17 is a partial cross-sectional schematic diagram of the solar cell provided in an embodiment of this application;

[0102] Figure 18 is a partial top view of a solar cell provided in another embodiment of this application;

[0103] Figure 19 is a partial top-view SEM image of a solar cell provided in another embodiment of this application;

[0104] Figure 20 is a partial top view of a solar cell provided in another embodiment of this application;

[0105] Figure 21 is a partial cross-sectional schematic diagram of a solar cell provided in another embodiment of this application;

[0106] Figure 22 is a partial top-view SEM image of a solar cell provided in another embodiment of this application;

[0107] Figure 23 is a partial top view of a solar cell provided in another embodiment of this application;

[0108] Figure 24 is a schematic diagram of the first opening provided in an embodiment of this application;

[0109] Figure 25 shows a side cross-sectional view of a solar cell according to an embodiment of the present invention;

[0110] Figure 26 shows a side cross-sectional view of another solar cell in an embodiment of the present invention;

[0111] Figure 27 shows a side cross-sectional view of another solar cell in an embodiment of the present invention;

[0112] Figure 28 shows a top view of the seed layer included in a solar cell according to an embodiment of the present invention;

[0113] Figure 29 shows a side cross-sectional microstructure of a solar cell according to an embodiment of the present invention;

[0114] Figure 30 shows a side cross-sectional view of another solar cell in an embodiment of the present invention;

[0115] Figure 31 shows a top view microstructure of a second doped semiconductor layer included in a solar cell according to an embodiment of the present invention;

[0116] Figure 32 shows a partial top view microstructure of the second doped semiconductor layer included in a solar cell according to an embodiment of the present invention;

[0117] Figure 33 shows a top view microstructure of a seed layer included in a solar cell according to an embodiment of the present invention;

[0118] Figure 34 shows a top view microstructure of a first doped semiconductor layer included in a solar cell according to an embodiment of the present invention;

[0119] Figure 35 shows a partial top view microstructure diagram of the first doped semiconductor layer included in a solar cell according to an embodiment of the present invention;

[0120] Figure 36 shows a top view microstructure of a seed layer included in another solar cell according to an embodiment of the present invention;

[0121] Figure 37 shows a schematic diagram of the dimensions of a solar cell according to an embodiment of the present invention;

[0122] Figure 38 shows a schematic diagram of a photovoltaic module according to an embodiment of the present invention.

[0123] Reference numerals: 1-Silicon substrate, 2-Antireflection layer, 3-Aperture, 301-First aperture, 302-Second aperture, 4-Seed layer, 402-First metal particle, 403-Second metal particle, 411-First overflow, 412-Second overflow, 413-Second protrusion structure; 414-Edge region, 415-Recess, 421-First seed layer, 422-Second seed layer, 5-Transfer layer, 511-First transfer layer, 512-Second transfer layer, 52-Protrusion, 6-First doped semiconductor layer, 61-First protrusion structure; 7-Second doped semiconductor layer, 8-Passivation layer; 12-First interface layer; 401-Overflow; 11-Transition region; 51-First passivation layer; 9-Doped semiconductor layer; 10-Electrode. Specific Implementation

[0124] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0125] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0126] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise expressly specified. "Several" means one or more, unless otherwise expressly specified.

[0127] In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0128] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0129] This application provides a photovoltaic module comprising multiple solar cells electrically connected together in series and / or parallel. For example, Figure 1 provides a schematic diagram of multiple solar cells electrically connected together. As shown in Figure 1, multiple solar cells are arranged sequentially along direction A to form a cell string, and the multiple solar cells in the cell string are connected in series. Two or more cell strings are arranged sequentially along direction A to form a group of cell strings, and multiple groups of cell strings are arranged sequentially along direction B.

[0130] In the fabrication of solar cells, silver electrodes are typically formed using high-temperature silver paste through screen printing. Compared to low-temperature silver paste, the silver paste used in high-temperature sintering is more expensive, and the increasing price of silver paste leads to a continuous rise in the manufacturing cost of solar cells. Furthermore, in some solar cell structures, the electrodes need to be sintered through the antireflection layer 2 to contact the doped semiconductor layer. This limits the contact area between the electrode and the doped semiconductor layer, resulting in a smaller contact area and consequently, a higher contact resistance.

[0131] In view of the above, in order to reduce the manufacturing cost of solar cells, this application also provides a solar cell that can be used in the aforementioned photovoltaic modules.

[0132] As shown in Figures 2 and 3, the solar cell provided in this embodiment includes a cell body, an anti-reflection layer 2, and a seed layer 4. The cell body includes a first surface and a second surface disposed opposite to each other, that is, two surfaces opposite to each other along the thickness direction of the cell body are the first surface and the second surface, respectively. The first surface may correspond to the light-facing side of the solar cell, and the second surface may correspond to the back-lighting side of the solar cell; alternatively, the first surface may correspond to the back-lighting side of the solar cell, and the second surface may correspond to the light-facing side of the solar cell.

[0133] Specifically, the battery body may include a silicon substrate 1, a first doped semiconductor layer 6, and a second doped semiconductor layer 7, with opposite side surfaces of the silicon substrate corresponding to the first surface and the second surface, respectively. The first doped semiconductor layer 6 and the second doped semiconductor layer 7 have opposite conductivity types to collect and export electrons and holes, respectively, facilitating the formation of photocurrent. In the case of a back-contact solar cell, both the first doped semiconductor layer 6 and the second doped semiconductor layer 7 are located on the first surface, and there is an electrical isolation structure, i.e., a transition region, between the first doped semiconductor layer 6 and the second doped semiconductor layer 7. In this case, the first doped semiconductor layer 6 and the second doped semiconductor layer 7 can be alternately distributed along a first direction on the first surface. In the case of a bifacial solar cell, the first doped semiconductor layer 6 is located on the first surface, and the second doped semiconductor layer 7 is located on the second surface. In this case, the first doped semiconductor layer 6 can be disposed entirely on the first surface or partially, for example, the first doped semiconductor layer 6 can be disposed in a strip shape on the first surface; the second doped semiconductor layer 7 can be disposed entirely on the second surface or partially, for example, the second doped semiconductor layer 7 can be disposed in a strip shape on the second surface.

[0134] The anti-reflection layer 2 is provided at least on the first surface. Specifically, the anti-reflection layer 2 may be provided only on the first surface, or it may be provided on both the first and second surfaces. Furthermore, the anti-reflection layer 2 has an opening 3 that penetrates its thickness, and the opening 3 is provided corresponding to the first doped semiconductor layer 6 or the second doped semiconductor layer 7.

[0135] In some embodiments, the seed layer 4 includes a portion disposed corresponding to the opening 3, and a first overflow portion 411 extending from the opening 3 to the side of the antireflection layer 2 away from the battery body 1. Specifically, the first overflow portion 411 may be disposed around the opening 3, and continuously disposed from the portion corresponding to the opening 3 to the first overflow portion 411, so as to ensure that there is electrical conductivity between the portion of the seed layer 4 corresponding to the opening 3 and the first overflow portion 411. The first direction is parallel to the first surface, and can be any direction parallel to the first surface.

[0136] Using the above technical solution, a seed layer 4 is first formed within the opening 3 of the antireflection layer 2, and then a transport layer 5 is formed on the seed layer 4. The seed layer 4 can be made of various metals, such as one or more of Al, Zn, Fe, Co, Mg, Cu, Ag, Ni, and their alloys. Similarly, the transport layer 5 can also be made of various metals, such as one or more of Cu, Ni, Cr, Ti, W, Mo, Ag, Sn, and their alloys. The material of the transport layer 5 can be the same as or different from that of the seed layer 4. The formed transport layer 5 is shown in Figure 4. Compared to the prior art where silver paste is burned through the antireflection layer 2 to form the silver electrode as a whole, the material forming the electrode no longer needs to penetrate the opening 3, thus reducing the amount of silver paste required to fabricate the overall electrode structure of the solar cell and lowering the overall electrode structure manufacturing cost. Furthermore, the above-mentioned metal fabrication of the seed layer 4 and transport layer 5 can employ low-temperature processes. Specifically, the seed layer 4 can be formed by electroplating or chemical plating, and the transport layer 5 can be formed by electroplating or screen printing, reducing manufacturing difficulty and saving energy consumption, further reducing production costs.

[0137] It should be noted that after the antireflection layer 2 forms the opening 3, the area of ​​the opening 3 can be pretreated to improve the activity of the battery body surface. Then, an electroplating or electroless plating deposition can be used to form the seed layer 4, so that the bottom of the seed layer 4 can form good contact with the battery body. It can be understood that the electrode 10 includes the seed layer 4 and the transport layer 5.

[0138] As shown in Figure 3, the ratio of the width of the first overflow portion 411 along the first direction to the thickness of the first overflow portion 411 along the thickness direction of the battery body 1 is 0.5 to 10. That is, the width of the first overflow portion 411 along the first direction is b, and the thickness of the first overflow portion 411 along the thickness direction of the battery body 1 is h, where b / h is in the range of 0.5 to 10. The thickness of the first overflow portion 411 refers to the average thickness of the first overflow portion 411, or the thickness of the first overflow portion 411 at its thickest point.

[0139] It is understandable that if the width of the first overflow portion 411 is small and its thickness is much greater than its width, the adhesion between the seed layer 4 and the battery body cannot be guaranteed, making it prone to detachment. Conversely, if the width of the first overflow portion 411 is much greater than its thickness, its thickness becomes too small, increasing the contact resistance between the seed layer 4 and the transport layer 5. Therefore, this technical solution controls the width and thickness of the first overflow portion 411 within the range of 0.5 to 10 mm. This ensures sufficient adhesion between the seed layer 4 and the battery body, reducing the risk of detachment, while also maintaining a suitable contact area between the seed layer 4 and the transport layer 5 and minimizing the contact resistance between them.

[0140] For example, the ratio of the width of the first overflow portion 411 along the first direction to the thickness of the first overflow portion 411 along the thickness direction of the battery body is 0.5, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 8.5, 9, 9.5 or 10, etc.

[0141] In some embodiments, the width of the first overflow portion 411 along the first direction is smaller than the thickness of the first overflow portion 411 along the thickness direction of the battery body, i.e., b / h is less than 1. In this case, the seed layer 4 can be formed by electroplating and / or chemical plating. With this configuration, the thickness of the first overflow portion 411 along the thickness direction of the battery body is slightly greater than the width of the first overflow portion 411 along the first direction. The relatively thicker seed layer 4 can better block water, oxygen, and other elements from entering the battery body at the opening 3, reducing the erosion or damage to the battery body by other elements. In addition, the contact area between the first overflow portion 411 and the transmission layer 5 in the thickness direction of the battery body can be appropriately increased, i.e., the contact area between the side of the first overflow portion 411 and the transmission layer 5 can be increased, further improving the contact area between the seed layer 4 and the transmission layer 5, reducing the contact resistance between the seed layer 4 and the transmission layer 5, and reducing current loss.

[0142] In some embodiments, the ratio of the width of the first overflow portion 411 along the first direction to the thickness of the first overflow portion 411 along the thickness direction of the battery body 1 is 0.5 to 1, i.e., b / h is in the range of 0.5 to 1. This configuration, where the thickness of the first overflow portion 411 along the thickness direction of the battery body 1 is slightly greater than its width along the first direction, can reduce the erosion or damage to the battery body 1 by other elements. Furthermore, the contact area between the first overflow portion 411 and the transport layer 5 in the thickness direction of the battery body 1 can be appropriately increased, i.e., the contact area between the side of the first overflow portion 411 and the transport layer 5 can be increased, further improving the contact area between the seed layer 4 and the transport layer 5, reducing the contact resistance between the seed layer 4 and the transport layer 5, and reducing current loss. However, the thickness of the first overflow portion 411 along the thickness direction of the battery body 1 cannot be too large, i.e., b / h is less than 0.5, otherwise the contact area between the seed layer 4 and the passivation surface will be too small, reducing the bonding force between the seed layer 4 and the surface of the antireflection layer 2. For example, the ratio of the width of the first overflow portion 411 along the first direction to the thickness of the first overflow portion 411 along the thickness direction of the battery body 1 is 0.5, 0.6, 0.7, 0.8, 0.9 or 1, etc.

[0143] In other embodiments, the width of the first overflow portion 411 along the first direction is greater than the thickness of the first overflow portion 411 along the thickness direction of the battery body 1, i.e., b / h is greater than 1. In this case, the seed layer 4 can be formed by chemical plating. This configuration makes the width of the first overflow portion 411 along the first direction larger, which can increase the area of ​​the upper surface of the seed layer 4, thereby increasing the contact area between the seed layer 4 and the anti-reflection layer 2, improving the adhesion between the seed layer 4 and the anti-reflection layer 2, and further reducing the risk of seed layer 4 falling off; at the same time, it increases the contact area between the seed layer 4 and the transport layer 5, improving the contact performance between the seed layer 4 and the transport layer 5.

[0144] In some embodiments, the ratio of the width of the first overflow portion 411 along the first direction to the thickness of the first overflow portion 411 along the thickness direction of the battery body 1 is 1 to 10, that is, b / h is in the range of 1 to 10. This configuration can increase the contact area between the seed layer 4 and the anti-reflection layer 2, improve the adhesion between the seed layer 4 and the anti-reflection layer 2, and further reduce the risk of seed layer 4 falling off; it can also improve the contact performance between the upper surface of the seed layer 4 and the transport layer 5, and reduce current loss.

[0145] For example, the ratio of the width of the first overflow portion 411 along the first direction to the thickness of the first overflow portion 411 along the thickness direction of the battery body 1 is 1, 1.2, 1.8, 2.2, 2.8, 3.2, 3.8, 4.2, 4.8, 5.2, 5.8, 6.2, 6.8, 7.2, 7.8, 8.2, 8.8, 9.2, 9.8 or 10, etc.

[0146] Furthermore, when the ratio of the thickness of the first overflow portion 411 along the thickness direction of the battery body 1 to the width of the first overflow portion 411 along the first direction is greater than or equal to 0.8, the longitudinal contact area between the seed layer 4 and the transmission layer 5 can be increased, reducing the contact resistance while ensuring good contact between the seed layer 4 and the battery body 1.

[0147] As shown in Figure 4, the edge thickness of the first overflow portion 411 gradually decreases along the direction from the center of the opening 3 to the edge. That is, along the first direction, there is a smooth transition from the upper surface to the side surface of the first overflow portion 411, which makes the contact between the seed layer 4 and the transport layer 5 more solid and further reduces the risk of detachment.

[0148] In some embodiments, as shown in FIG3, the seed layer 4 fills the opening 3, and the seed layer 4 protrudes from the opening 3 and has a first overflow portion 411 extending onto the anti-reflection layer 2. Specifically, the bottom of the seed layer 4 fills the interior of the opening 3, and the top of the seed layer 4 overflows from the opening 3. The portion of the seed layer 4 that overflows from the opening 3 extends in both the direction surrounding the opening 3 and the thickness direction of the anti-reflection layer 2, ultimately forming the first overflow portion 411 on the anti-reflection layer 2, and the upper surface of the seed layer 4 is higher than the upper surface of the anti-reflection layer 2. This configuration, with the first overflow portion 411 surrounding the opening 3, facilitates processing and manufacturing.

[0149] In some embodiments, along the length or width direction of the battery body 1, the width of the first overflow portion 411 located on the first side of the opening 3 is greater than the width of the first overflow portion 411 located on the second side. For example, as shown in FIG3, the left side of the opening 3 is the first side, the right side of the opening 3 is the second side, and the first direction is along the length direction of the battery body 1.

[0150] In some embodiments, as shown in Figures 4 and 5, the thickness h of the first overflow portion 411 along the thickness direction of the battery body 1 is 60 nm to 1200 nm. This is to prevent the thickness h of the first overflow portion 411 from being too thick, which would prolong the process time and ensure that the upper surface area of ​​the seed layer 4 is moderate, thereby ensuring sufficient adhesion between the seed layer 4 and the battery body 1. At the same time, it prevents the thickness h of the first overflow portion 411 from being too small, which would result in an insufficient contact area between the side of the first overflow portion 411 and the transport layer 5, increasing the contact resistance between the seed layer 4 and the transport layer 5. For example, the thickness h of the first overflow portion 411 can be 60 nm, 100 nm, 150 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, or 1200 nm, etc.

[0151] Furthermore, as shown in Figures 4 and 5, along the first direction, the width b of the first overflow portion 411 is 60nm to 1200nm. This is to prevent the width b of the first overflow portion 411 from being too small, thereby ensuring sufficient adhesion between the seed layer 4 and the battery body 1, while reducing the contact resistance between the seed layer 4 and the transport layer 5; it also prevents the width b of the first overflow portion 411 from being too wide, leading to material waste. For example, the width b of the first overflow portion 411 can be 60nm, 100nm, 150nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, 1100nm, or 1200nm, etc.

[0152] In some embodiments, as shown in FIG3, the ratio of the width of the first overflow portion 411 to the maximum width of the seed layer 4 projected onto the first surface along the first direction is 0.05-0.2. That is, the ratio of the width b of the first overflow portion 411 to the total width of the upper surface of the seed layer 4 along the first direction is 0.05-0.2. This technical solution avoids the first overflow portion 411 being too wide, leading to material waste; at the same time, it ensures a large contact area between the seed layer 4 and the transport layer 5, thereby ensuring sufficient adhesion between the seed layer 4 and the battery body 1. For example, the ratio of the width of the first overflow portion 411 to the width of the seed layer 4 on the surface away from the battery body 1 is 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, or 0.2, etc.

[0153] In other embodiments, along the first direction, the ratio of the sum of the widths of the first overflow portions 411 on both sides of the seed layer 4 to the maximum width of the seed layer 4 projected onto the first surface is 0.1-0.4. For example, the ratio of the sum of the widths of the first overflow portions 411 on both sides of the seed layer 4 to the maximum width of the seed layer 4 projected onto the first surface can be 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, or 0.4, etc.

[0154] In other embodiments, the ratio of the thickness of the first overflow portion 411 to the thickness of the portion of the seed layer 4 corresponding to the opening 3 along the thickness direction of the battery body 1 is 50%-96%. This setting prevents the thickness h of the first overflow portion 411 from being too small, which would result in an insufficient contact area between the side of the first overflow portion 411 and the transmission layer 5, increasing the contact resistance between the seed layer 4 and the transmission layer 5. For example, the ratio of the thickness of the first overflow portion 411 to the thickness of the portion of the seed layer 4 located within the opening 3 is 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, or 96%, etc.

[0155] Furthermore, if the thickness of the antireflective layer 2 is too small, it will affect the passivation effect; if the thickness of the antireflective layer 2 is too thick, it will lead to a prolonged processing time. Considering the above, in this solution, the thickness of the antireflective layer 2 along the thickness direction of the battery body 1 is 60nm to 180nm. This ensures both passivation effect and prevents prolonged processing time. For example, the thickness of the antireflective layer 2 can be 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, or 180nm, etc.

[0156] In some embodiments, the antireflection layer 2 includes one or more stacked layers of silicon nitride, silicon oxynitride, and silicon oxide. Specifically, when the antireflection layer 2 has a two-layer structure, it may include stacked silicon nitride and silicon oxynitride layers, or stacked silicon nitride and silicon oxide layers, or stacked silicon oxynitride and silicon oxide layers, wherein the stacking order of each layer can be set according to the actual situation. When the antireflection layer 2 has a three-layer structure, it may include stacked silicon nitride, silicon oxynitride, and silicon oxide layers, wherein the stacking order of the silicon nitride, silicon oxynitride, and silicon oxide layers can be set according to the actual situation.

[0157] In the case where the solar cell includes a first doped semiconductor layer 6 and a second doped semiconductor layer 7, the antireflection layer 2 covers the side of the first doped semiconductor layer 6 and the second doped semiconductor layer 7 facing away from the silicon substrate 1. That is, the antireflection layer 2 covers both the first doped semiconductor layer 6 and the second doped semiconductor layer 7. The antireflection layer 2 has a first opening 301 corresponding to the first doped semiconductor layer 6 and a second opening 302 corresponding to the second doped semiconductor layer 7. Along the first direction, the equivalent width of the first opening 301 is different from the equivalent width of the second opening 302. Specifically, the equivalent width of the first opening 301 is the ratio of the area of ​​the first opening 301 to the distance between two adjacent first openings 301, and the equivalent width of the second opening 301 is the ratio of the area of ​​the second opening 302 to the distance between two adjacent second openings 302. This configuration allows for adjustment of the equivalent widths of the first aperture 301 and the second aperture 302 as needed. This ensures that the contact resistance between the doped semiconductor layer with lower conductivity and the transport layer 5 is equal to or closer to the contact resistance between the doped semiconductor layer with higher conductivity and the transport layer 5. This reduces the current difference between the transport layer 5 and the second doped semiconductor layer 7, and between the transport layer 5 and the first doped semiconductor layer 6, thereby reducing battery current loss and ensuring battery performance. Furthermore, after battery body pretreatment, because the doping types of the doped semiconductor layers 9 corresponding to the first aperture 301 and the second aperture 302 are different, their plating activity differs. Therefore, the equivalent widths of the first aperture 301 and the second aperture 302 are different, allowing the aperture with lower plating activity to have a wider equivalent width, thus reducing plating difficulty.

[0158] For example, if the opening 3 is a circular hole with a diameter of 14 μm and a spacing of 20 μm between two adjacent circular holes, the equivalent opening width is (π*7*7) / 20 = 7.7 μm; if the opening 3 is a square hole with a width of 20 μm along the first direction and a spacing of 100 μm between two adjacent square holes, the equivalent opening width is (20*20) / 100 = 4 μm.

[0159] In some embodiments, the number of first openings 301 is multiple and arranged along a second direction, and the number of second openings 301 is also multiple and arranged along a second direction, which is parallel to the first surface. Specifically, the multiple first openings 301 can be distributed in multiple rows or in a single row, with each row of first openings 301 arranged along the second direction; similarly, the multiple second openings 302 can be distributed in multiple rows or in a single row, with each row of second openings 302 arranged along the second direction. The first openings 301 can be distributed in one, two, three, or more rows; the second openings 302 can be distributed in one, two, three, or more rows. The second direction can be either the length direction of the silicon substrate 1 or the width direction of the silicon substrate 1.

[0160] In some embodiments, the second doped semiconductor layer 7 is a P-type doped semiconductor layer. Along the second direction, the equivalent width of the first opening 301 is smaller than the equivalent width of the second opening 302. In this way, when the conductivity of the first doped semiconductor layer 6 is greater than the conductivity of the second doped semiconductor layer 7, the contact resistance between the second doped semiconductor layer 7 with lower conductivity and the transport layer 5 is made equal to or closer to the contact resistance between the first doped semiconductor layer 6 with higher conductivity and the transport layer 5. This reduces the current difference between the transport layer 5 and the second doped semiconductor layer 7, as well as between the transport layer 5 and the first doped semiconductor layer 6, thereby reducing the current loss of the battery.

[0161] In some embodiments, if the equivalent width of the first aperture 301 is too small, the contact resistance between the first doped semiconductor and the transport layer 5 increases, leading to increased current loss. If the equivalent width of the first aperture 301 is too large, the battery is easily damaged during laser aperture drilling, and the more of the first doped semiconductor layer 6 is exposed, the easier it is for recombination. In view of the above, along the first direction, the equivalent width of the first aperture 301 is 3μm to 20μm. This ensures that the equivalent width of the first aperture 301 is more closely matched to the conductivity of the first doped semiconductor, reducing the contact resistance between the first doped semiconductor and the transport layer 5 and decreasing current loss. Simultaneously, it avoids damage to the battery during laser aperture drilling and reduces recombination. For example, the equivalent width of the first aperture 301 can be 3μm, 5μm, 8μm, 10μm, 12μm, 15μm, 18μm, or 20μm, etc.

[0162] In other embodiments, the equivalent width of the second opening 302 along the first direction is 5μm to 30μm, and the technical effect is the same as that described for the first opening 301, which will not be repeated here. For example, the equivalent width of the second opening 302 can be 5μm, 8μm, 10μm, 12μm, 15μm, 18μm, or 20μm, etc.

[0163] In some embodiments, the total area of ​​the first opening 301 is different from the total area of ​​the second opening 302. Specifically, the total area of ​​the first opening 301 is the total area of ​​all the first openings 301 on the first doped semiconductor layer 6; the total area of ​​the second openings 302 is the total area of ​​all the second openings 302 on the second doped semiconductor layer 7. To maximize the contact area between the doped semiconductor layer with lower conductivity and the seed layer 4, in some examples, the total area of ​​the openings in the doped semiconductor layer with lower conductivity can be set larger. This makes the contact resistance between the doped semiconductor layer with lower conductivity and the seed layer 4 equal to or closer to the contact resistance between the doped semiconductor layer with higher conductivity and the seed layer 4. This reduces the current difference between the seed layer 4 and the second doped semiconductor layer 7 and between the seed layer 4 and the first doped semiconductor layer 6, reducing battery current loss and ensuring battery performance.

[0164] In some embodiments, the battery body includes a silicon substrate 1, a first doped semiconductor layer 6, and a second doped semiconductor layer 7, wherein the first doped semiconductor layer 6 and the second doped semiconductor layer 7 have opposite conductivity types; an anti-reflection layer 2 covers the side of the first doped semiconductor layer 6 and the second doped semiconductor layer 7 away from the silicon substrate, that is, the anti-reflection layer 2 covers both the first doped semiconductor layer 6 and the second doped semiconductor layer 7. The anti-reflection layer 2 has a first opening 301 corresponding to the first doped semiconductor layer 6 and a second opening 302 corresponding to the second doped semiconductor layer 6; a seed layer 4 includes a first seed layer 421 and a second seed layer 422, wherein the first seed layer 421 includes a portion disposed corresponding to the first opening 301 and a first overflow portion 411 extending from the first opening 301 to the side of the anti-reflection layer 2 away from the battery body; the second seed layer 422 includes a portion disposed corresponding to the second opening 302 and a first overflow portion 411 extending from the second opening 302 to the side of the anti-reflection layer 2 away from the battery body 1. In this technical solution, the width b1 of the first overflow portion 411 of the first seed layer 301 and the width b2 of the first overflow portion 411 of the second seed layer 302 are different.

[0165] At the opening, the doped semiconductor layer 9 forms an electrical contact with the electrode through the seed layer. The doped semiconductor layer 9 corresponding to the first opening 301 and the second opening 302 has a different conductivity type. Therefore, the width of the first overflow portion 411 of the first seed layer 421 and the second seed layer 422 is different. This can adjust the contact performance between the doped semiconductor layer 9 of different doping types and the electrode, reduce the current difference between the second seed layer 422 and the second doped semiconductor layer 7 and between the second seed layer 422 and the first doped semiconductor layer 6, reduce the current loss of the battery, and ensure the performance of the battery.

[0166] In some embodiments, a first seed layer 421 is disposed on an N-type doped semiconductor layer, and a second seed layer 422 is disposed on a P-type doped semiconductor layer. Since the width of the first overflow portion 411 of the first seed layer 301 is smaller than the width of the first overflow portion 411 of the second seed layer 422, and due to the poor contact performance of the P-region, increasing the width of the first overflow portion 411 in the P-region increases the contact area between the electrode in the P-region and the second seed layer 422, thereby reducing contact resistance, improving contact performance, and enhancing the photoelectric conversion efficiency of the solar cell.

[0167] The contact resistance between the first seed layer 421 and the transmission layer 5 can be less than or equal to 0.3 mΩ*cm2, and the contact resistance between the second seed layer 422 and the transmission layer 5 can be less than or equal to 0.8 mΩ*cm2.

[0168] In other embodiments, a first seed layer 421 is disposed on an N-type doped semiconductor layer, and a second seed layer 422 is disposed on a P-type doped semiconductor layer. The width of the first overflow portion 411 of the first seed layer 301 is smaller than the width of the first overflow portion 411 of the second seed layer 422. By increasing the width of the first overflow portion 411 corresponding to the N-type doped semiconductor layer, the contact performance between the N-region electrode and the first seed layer can be improved, thereby reducing the number of openings in the N-region. With a reduced number of openings, the damage to the N-region caused by laser mold opening is reduced, effectively ensuring the passivation effect of the N-region.

[0169] The solar cell also includes a transport layer 5 disposed on the side of the seed layer 4 facing away from the cell body 1. The transport layer 5 covers at least a portion of the surface of the seed layer 4 facing away from the cell body 1. Specifically, the transport layer 5 may cover only the upper surface of the seed layer 4, or it may cover both the upper surface and the side surface of the seed layer 4. Specifically, the transport layer 5 may be formed on the exposed seed layer 4 using processes such as screen printing, electroplating, sputtering, or vapor deposition.

[0170] The transport layer 5 can cover the surface and sides of the seed layer 4 facing away from the cell body 1, maximizing the contact area between the transport layer 5 and the seed layer 4, further reducing the contact resistance between the transport layer 5 and the seed layer 4, and improving the efficiency of the solar cell. The transport layer 5 may include a main grid and / or a fine grid.

[0171] Furthermore, the width of the transport layer 5 is 40μm to 200μm. By adopting this technical solution and setting the width of the transport layer 5 within the reasonable range of 40μm to 200μm, leakage due to excessive width can be prevented, while excessive width ensures a low contact resistance between the transport layer 5 and the seed layer 4. For example, the width of the transport layer 5 can be 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm, or 200μm. It should be noted that the width of the transport layer 5 may vary at different locations along its extension direction. Therefore, in this application, the width of transport layer 5 can refer to the average width of transport layer 5 or the maximum width of transport layer 5.

[0172] The silicon substrate 1 can be made of materials such as silicon (Si), germanium (Ge), or gallium arsenide (GaAs). Obviously, in terms of conductivity type, the silicon substrate 1 can be an intrinsically conductive substrate, an n-type conductive substrate, or a p-type conductive substrate. Optionally, the silicon substrate 1 is a p-type conductive substrate or an n-type conductive substrate. Compared to an intrinsically conductive substrate, a p-type or n-type conductive substrate has better conductivity, resulting in a lower bulk resistivity in the final solar cell, thereby improving the efficiency of the solar cell.

[0173] Furthermore, the materials of the first doped semiconductor layer 6 and the second doped semiconductor layer 7 can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs), etc. The first doped semiconductor layer 6 can be additionally formed on the silicon substrate by deposition technology, or it can be formed in the silicon substrate by diffusion, ion implantation, or other methods.

[0174] Regarding the conductivity type, the first doped semiconductor layer 6 can be an n-type doped semiconductor layer and the second doped semiconductor layer 7 can be a p-type doped semiconductor layer; or, the first doped semiconductor layer 6 can be a p-type doped semiconductor layer and the second doped semiconductor layer 7 can be an n-type doped semiconductor layer.

[0175] Furthermore, the materials of the first doped semiconductor layer 6 and the second doped semiconductor layer 7 can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs), etc. Taking the case where both the first doped semiconductor layer 6 and the second doped semiconductor layer 7 are made of silicon (Si) as an example, the first doped semiconductor layer 6 can be one or more of doped monocrystalline silicon, doped polycrystalline silicon, doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The second doped semiconductor layer 7 can also be one or more of doped monocrystalline silicon, doped polycrystalline silicon, doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0176] In some embodiments, the solar cell may further include a first interface layer, which is located at least between the first doped semiconductor layer 6 and the silicon substrate 1. In this case, the passivated contact structure formed by the first interface layer and the first doped semiconductor layer 6 has excellent interface passivation effect and can achieve selective collection of charge carriers, reducing the carrier recombination rate in the region on the first surface of the silicon substrate 1 where the first doped semiconductor layer 6 is formed, and further improving the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer can be set according to the material of the first doped semiconductor layer 6 and actual needs, and are not specifically limited here.

[0177] The material of the first interface layer can be determined based on the material of the first doped semiconductor layer 6. For example, if the first doped semiconductor layer 6 includes a doped polycrystalline silicon layer, the first interface layer is a tunneling oxide layer. Thus, the first doped semiconductor layer 6 and the first interface layer form a tunneling oxide passivation contact. Tunneling oxide passivation technology can form a tunneling film between the first electrode and the silicon substrate, isolating the electrode from the silicon substrate, reducing contact recombination losses, and ensuring that electrons can tunnel through the film without affecting current transfer. Simultaneously, passivation can bend the surface bandgap, reducing surface recombination losses on the silicon wafer. As another example, if the first doped semiconductor layer 6 includes a doped amorphous silicon layer, the first interface layer includes an intrinsic amorphous silicon layer. Furthermore, the embodiments of the present invention do not specifically limit the material of the first interface layer.

[0178] In some embodiments, the solar cell may further include a second interface layer, which is located at least between the second doped semiconductor layer 7 and the silicon substrate 1. The projection of the second interface layer onto the silicon substrate 1 may overlap with the projection of the second doped semiconductor layer 7 onto the silicon substrate. In this case, the passivated contact structure formed by the second interface layer and the second doped semiconductor layer 7 can achieve selective collection of charge carriers and reduce the carrier recombination rate in the region where the second doped semiconductor layer 7 is formed on the first surface of the silicon substrate 1. The material and thickness of the second interface layer can be set according to the material of the second doped semiconductor layer 7 and actual needs, and are not specifically limited here. For example, when the material of the second doped semiconductor layer 7 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface layer includes one or more of intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic nanocrystalline silicon. As another example, when the material of the second doped semiconductor layer 7 includes doped polycrystalline silicon, the second interface layer includes a tunneling oxide layer.

[0179] It should be noted that the transport layer 5 includes a first transport layer 511 and a second transport layer 512. The first transport layer 511 and the first seed layer 421 are located on the side opposite to the battery body, and the second transport layer 512 is disposed on the side of the second seed layer 422 opposite to the battery body. The transport layer can also be referred to as an electrode, the first transport layer 512 can also be referred to as a first electrode or a first gate line, and the second transport layer 522 can also be referred to as a second electrode or a second gate line.

[0180] For example, the first surface of this solar cell is a light-facing surface, and the second surface is a backlight surface. The first surface sequentially comprises an emitter, an anti-reflection layer 2, a first seed layer 421, and a first transport layer 511. The anti-reflection layer 2 has a first opening 302 corresponding to the emitter, and the first seed layer 432 passes through the first opening 301 and is electrically connected to the first transport layer 511. The second surface sequentially comprises a tunneling oxide layer, a doped polycrystalline silicon layer, an anti-reflection layer 2, a second seed layer 422, and a second transport layer 512. The anti-reflection layer 2 has a second opening 302 corresponding to the doped polycrystalline silicon layer, and the second seed layer 422 passes through the second opening 302 and is electrically connected to the second transport layer 512.

[0181] For example, the first surface of the solar cell is a light-facing surface, and the second surface is a backlight surface. The first surface is sequentially provided with a first tunneling oxide layer, a first doped polycrystalline silicon layer, an antireflection layer 2, a first seed layer 421, and a first transport layer 511. The antireflection layer 2 has a first opening 301 corresponding to the first doped polycrystalline silicon layer, and the first seed layer 421 is conductively connected to the first transport layer 511 through the first opening 301. The second surface is sequentially provided with a second tunneling oxide layer, a second doped polycrystalline silicon layer, an antireflection layer 2, a second seed layer 422, and a second transport layer 512. The antireflection layer 2 has a second opening 302 corresponding to the second doped polycrystalline silicon layer, and the second seed layer 422 is conductively connected to the second transport layer 512 through the second opening 302.

[0182] In realizing the concept of this application, it was discovered that the seed layer 4 contains metal particles within a specific size range. These metal particles help increase the transport performance of the seed layer 4 and the pull between the seed layer 4 and the electrode 10, thereby improving the reliability of the electrode connection. Furthermore, by controlling the size range of the metal particles in the seed layer 4, and the size relationship between the metal particles in the first seed layer 421 and the second seed layer 422, it is helpful to control the differences in contact performance and pull between the seed layer 4 connected to the electrode 10 for different polarity doped semiconductor layers 9, thereby achieving a balance between current collection between different polarity regions and the reliability of the electrode 10 connection.

[0183] On the one hand, this application provides a solar cell that reduces the manufacturing cost of the solar cell while reducing current transmission loss and improving the adhesion of the transmission layer.

[0184] Referring to FIG. 6, the solar cell provided by the embodiment of the present application includes a silicon substrate 1, a first doped semiconductor layer 6, an antireflection layer 2, a first seed layer 421, and a first transport layer 511. Among them, the silicon substrate 1 includes opposite first and second surfaces, that is, the two surfaces opposite along the thickness direction of the silicon substrate 1 are the first surface and the second surface respectively. The first surface may correspond to the backlight surface of the solar cell, and the second surface may correspond to the light-facing surface of the solar cell; or, the first surface may correspond to the light-facing surface of the solar cell, and the second surface may correspond to the backlight surface of the solar cell.

[0185] The first surface has a first doped semiconductor layer 6. Specifically, the first doped semiconductor layer 6 may be disposed entirely or partially on the first surface. When the first doped semiconductor layer 6 is partially disposed on the first surface, the first doped semiconductor layer 6 may be arranged at intervals on the first surface in a strip shape or a shape similar to a rich font; there is an isolation region between adjacent first doped semiconductor layers 6.

[0186] The antireflection layer 2 at least covers the side of the first doped semiconductor layer 6 facing away from the silicon substrate 1. The antireflection layer 2 can protect the surface of the battery chip, prevent water vapor and oxygen from penetrating into the interior of the battery chip, thereby avoiding performance degradation of the battery chip caused by oxidation or hydrolysis; and, the setting of the antireflection layer 2 can reduce the surface recombination rate of the battery chip, thereby improving the photoelectric conversion efficiency of the battery. The antireflection layer 2 may be a single-layer structure; or, the antireflection layer 2 may also be a multi-layer structure. Specifically, the antireflection layer 2 is at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer or a composite film stacked by them. Exemplarily, the antireflection layer 2 may be a bilayer structure, which includes an aluminum oxide layer and a silicon nitride layer, and the aluminum oxide layer is located on the side of the silicon nitride layer close to the silicon substrate 1.

[0187] The first seed layer 421 is electrically connected to the first doped semiconductor layer 6 through the antireflection layer 2, that is, the carriers collected by the first doped semiconductor layer 6 are exported through the first seed layer 421. As shown in FIG. 7, the first seed layer 421 includes a plurality of first metal particles 402 and a plurality of second metal particles 403 stacked on at least a partial surface of the first metal particles 402. Specifically, the second metal particles 403 may adhere to the surface of the first metal particles 402; or, a part of the second metal particles 403 adheres to the surface of the first metal particles 402, and another part of the second metal particles 403 fills the gap between adjacent two first metal particles 402. The particle size of the first metal particles 402 is a, and the particle size of the second metal particles 403 is b, a - b ≥ 40 nm and / or a ≥ 1.5b. Among them, the particle size of the first metal particles 402 may be the equivalent diameter of the first metal particles 402. The particle size of the second metal particles 403 may be the equivalent diameter of the second metal particles 403. Specifically, the equivalent diameter may be the screening equivalent diameter, the volume equivalent diameter or the surface area equivalent diameter.

[0188] Using the above technical solution, a first seed layer 421 is first formed, and then a first transport layer 511 is formed on the first seed layer 421. The first seed layer 421 can be made of various metals, such as one or more of Al, Zn, Fe, Co, Mg, Ag, Ni, and their alloys. The first transport layer 511 can be formed from base metal paste. Compared to the prior art where silver paste is burned through the antireflection layer 2 to form the silver electrode as a whole, this method can significantly reduce the amount of silver paste required to fabricate the overall electrode structure of the solar cell, thus reducing the manufacturing cost of the overall electrode structure.

[0189] Furthermore, the first seed layer 421 includes a plurality of first metal particles 402, which are stacked together; and a plurality of second metal particles 403 are stacked on at least a partial surface of the first metal particles 402, wherein the particle size a of the first metal particles 402 and the particle size b of the second metal particles 403 differ by at least 40 nm, and / or a ≥ 1.5b. In this technical solution, the first metal particles 402 have a relatively large particle size. Multiple first metal particles 402 are stacked together, creating a height difference between them on the surface of the first seed layer 421. Simultaneously, the presence of multiple second metal particles 403 on the upper side of the first metal particles 402 increases the surface undulation of the first seed layer 421, thereby increasing its surface roughness and specific surface area. When the first transport layer contacts the first seed layer 421, it creates more metal contact points, reducing the contact resistance between them and improving the battery's power generation efficiency. Furthermore, it enhances the adhesion of the first transport layer, preventing it from detaching. Furthermore, multiple second metal particles 403 are arranged around the first metal particle 402. The particle size of the second metal particles 403 is smaller and suitable for use between the first metal particles 402 to reduce the current transmission loss between adjacent first metal particles 402, improve the current transmission efficiency between adjacent first metal particles 402, and further improve the power generation efficiency of the battery.

[0190] Optionally, ab ≥ 50 nm, or ab ≥ 80 nm, or ab ≥ 100 nm, or ab ≥ 200 nm, etc. For example, the difference ab between the particle size a of the first metal particle 402 and the particle size b of the second metal particle 403 can be 40 nm, 42 nm, 45 nm, 46 nm, 48 nm, 49 nm, 50 nm, 52 nm, 55 nm, 58 nm, 60 nm, 62 nm, 65 nm, 68 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, or 990 nm. To avoid an excessive difference between the particle size a of the first metal particle 402 and the particle size b of the second metal particle 403, ab ≤ 990 nm is ensured. This prevents the contact area between the second metal particle 403 and the first metal particle 402 from being too small, thus ensuring low current transmission loss between them and further improving the power generation efficiency of the battery.

[0191] Optionally, a ≥ 2b, or a ≥ 5b, or a ≥ 10b, or a ≥ 30b, etc. For example, the particle size a of the first metal particle 402 can be 1.5b, 1.7b, 1.8b, 2b, 2.2b, 2.5b, 2.8b, 3b, 3.2b, 3.5b, 3.8b or 4b, 5b, 6b, 7b, 8b, 9b, 10b, 15b, 20b, 25b, 30b, 35b, 40b, 45b, 50b, 55b, 60b, 65b, 70b, 75b, 80b, 85b, 90b, 95b or 100b, etc. To avoid an excessive difference between the particle size a of the first metal particle 402 and the particle size b of the second metal particle 403, a ≤ 100b is ensured. This prevents the contact area between the second metal particle 403 and the first metal particle 402 from being too small, thus ensuring low current transmission loss between them and further improving the power generation efficiency of the battery.

[0192] The inventors of this application analyzed and compared two cases: the first seed layer 421 containing first metal particles 402 and second metal particles 403, and the first seed layer 421 having a smooth surface, and obtained the following table:

[0193] As shown in the table above, when the first seed layer 421 includes first metal particles 402 and second metal particles 403, the series resistance of the solar cell is significantly reduced, and the power generation efficiency is significantly improved. When ab ≥ 40 nm or a ≥ 1.5b, the series resistance of the solar cell is significantly lower than when ab < 40 nm or a < 1.5b; and the power generation efficiency of the solar cell is significantly higher than when ab < 40 nm or a < 1.5b. In some embodiments, if the particle size a of the first metal particles 402 is too large, it will result in a large transmission resistance of the first seed layer 421 itself, leading to high current transmission loss; if the particle size a of the first metal particles 402 is too small, it will reduce the surface roughness of the first seed layer 421, resulting in a reduced contact area between the first seed layer 421 and the first transmission layer, an increased contact resistance, and an increased transmission loss between the first seed layer 421 and the first transmission layer. In view of the above two situations, in this technical solution, the particle size 'a' of the first metal particle 402 is set within a reasonable range of 100nm ≥ a ≥ 1000nm. This ensures that the transmission resistance of the first seed layer 421 is low while increasing the surface roughness of the first seed layer 421, thereby reducing the transmission loss between the first seed layer 421 and the first transmission layer. For example, the particle size 'a' of the first metal particle 402 can be 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, 850nm, 900nm, 950nm, or 1000nm.

[0194] In some embodiments, as shown in FIG8, if the particle size b of the second metal particle 403 is too large, the transmission resistance between adjacent first metal particles 402 will increase, resulting in increased current transmission loss of the first seed layer 421 itself; if the particle size b of the second metal particle 403 is too small, the content of organic matter in the gaps between the metal particles will decrease, resulting in reduced adhesion of the first seed layer 421 and easy susceptibility to contamination.

[0195] To balance the above two aspects, in this application, the particle size b of the second metal particle 403 is set within a reasonable range of 10nm ≥ b ≥ 60nm. This ensures that the transmission resistance of the first seed layer 421 itself is low while increasing the content of organic matter in the gaps between the metal particles, thereby improving the adhesion of the first seed layer 421. For example, the particle size b of the second metal particle 403 can be 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, or 60nm, etc.

[0196] In some embodiments, the first metal particles 402 are uniformly distributed inside and on the surface of the first seed layer 421, meaning that the first metal particles 402 are deposited on both the surface and inside of the first seed layer 421. This arrangement helps to reduce the current transmission differences at various locations in the first seed layer 421, ensuring that the current transmission efficiency differences at various locations in the first seed layer 421 are small, preventing excessively large or small local currents, and avoiding situations such as local overheating or large local current transmission losses. In some embodiments, at least some of the first metal particles 402 are independent quasi-spherical; that is, some of the first metal particles 402 are independent particles that are not connected to the other first metal particles 402. The independent first metal particles 402 are quasi-spherical, such as ellipsoidal, spherical, etc. In this technical solution, the independent first metal particles 402 are more conducive to increasing the surface undulation of the first seed layer 421, thereby increasing the specific surface area of ​​the first seed layer 421, so that there are more metal contact points between the first seed layer 421 and the first transmission layer 511, thereby forming more metal contacts and reducing the contact resistance between the first seed layer 421 and the first transmission layer.

[0197] In some embodiments, at least two or more first metal particles 402 are bonded together, meaning that at least two of all the first metal particles 402 are bonded together. Among the bonded first metal particles 402, at least two adjacent first metal particles 402 have their surfaces in contact. This results in lower transmission losses between the bonded first metal particles 402, which is beneficial for further improving power generation efficiency.

[0198] The solar cell provided in this application also includes a second doped semiconductor layer 7. The material, conductivity type and arrangement of the second doped semiconductor layer 7 can be referred to the above text and will not be repeated here.

[0199] In some embodiments, the antireflection layer 2 further covers the side of the second doped semiconductor layer 7 facing away from the silicon substrate 1. The solar cell also includes a second seed layer 422 and a second transport layer 512. A plurality of second transport layers 512 extend along a first direction and are spaced apart along a second direction. At least a portion of the second transport layers 512 is disposed on the side of the first seed layer 421 facing away from the silicon substrate 1. The second seed layer includes a plurality of first metal particles 402 and a plurality of second metal particles 403 deposited on at least a partial surface of the first metal particles 402. The technical features and effects of the first metal particles 402 and the second metal particles 403 are described above and will not be repeated here.

[0200] In some embodiments, the first metal particle 402 and the second metal particle 403 may be made of the same or different materials. The first metal particle 402 may be made of one or more of Al, Zn, Fe, Co, Mg, Ag, Ni, and their alloys. The second metal particle 403 may be made of one or more of Al, Zn, Fe, Co, Mg, Ag, Ni, and their alloys.

[0201] In some embodiments, the first doped semiconductor layer 6 is an N-type doped semiconductor layer, that is, the first doped semiconductor layer 6 is doped with group V or group VI elements, such as phosphorus (P), arsenic (As), antimony (Sb), etc. The first doped semiconductor layer 6 is also a P-type semiconductor layer, doped with group III elements, such as boron (B), aluminum (Al), gallium (Ga), etc. In this technical solution, the particle size of the first metal particle 402 in the first seed layer 421 is a1, and the particle size of the second metal particle 403 in the first seed layer 421 is b1; the particle size of the first metal particle 402 in the second seed layer is a2, and the particle size of the second metal particle 403 in the first seed layer 421 is b2. As shown in Figures 10 and 11, a1 ≥ a2; and / or, b1 ≥ b2; and / or, the number of first metal particles 402 in the first seed layer 421 is greater than the number of first metal particles 402 in the second seed layer; and / or, the number of second metal particles 403 in the first seed layer 421 is greater than the number of second metal particles 403 in the second seed layer. Specifically, the particle size of the first metal particles 402 in the seed layer of the N-region is larger than that in the seed layer of the P-region; and / or, the particle size of the second metal particles 403 in the seed layer of the N-region is larger than that in the seed layer of the P-region; and / or, the number of first metal particles 402 in the seed layer of the N-region is greater than the number of first metal particles 402 in the seed layer of the P-region; and / or, the number of second metal particles 403 in the seed layer of the N-region is greater than the number of second metal particles 403 in the seed layer of the P-region. With this configuration, when the solar cell is operating normally, electrons in the N-region can be transported to the paste layer more efficiently through the numerous paths formed by the surface structure of the larger metal particles, reducing electron transport obstacles. In contrast, the relatively smaller metal particle structure in the P-region is more stable in terms of hole transport. The synergistic effect of the PN regions—the P-region stabilizing hole transport and the N-region enhancing electron transport—improves the separation and transport efficiency of photogenerated carriers, thereby increasing the short-circuit current density of the cell and ultimately improving the photoelectric conversion efficiency of the cell.

[0202] In some embodiments, the first metal particle 402 may be spherical or ellipsoidal. The second metal particle 403 may be spherical or ellipsoidal. Spherical or ellipsoidal particles have a larger contact area with organic matter, which is beneficial for the formation of the seed layer.

[0203] On the other hand, embodiments of the present invention also provide a method for manufacturing a solar cell, which can prepare the solar cell described in any of the above embodiments, and the method for manufacturing the solar cell includes the following steps:

[0204] S100: Provides a silicon substrate 1, the silicon substrate 1 having opposing first and second surfaces.

[0205] Prior to this step, in some embodiments, the silicon substrate 1 may be immersed in a polishing and cleaning machine to remove the cutting damage layer of the silicon substrate 1 using a polishing slurry. Furthermore, in this step, the morphology of the first and second surfaces of the silicon substrate 1 after polishing and cleaning can be adjusted by regulating parameters such as temperature, time, type of cleaning slurry, and concentration of the cleaning slurry. It should be noted that in some examples, the polishing and cleaning step may be omitted.

[0206] S200: A first doped semiconductor layer 6 is formed on the first surface.

[0207] In this step, the first doped semiconductor layer 6 can be formed entirely or partially on the first surface. The first doped semiconductor layer 6 can be additionally formed on the first surface of the silicon substrate 1 by deposition technology, or it can be formed within the silicon substrate 1 by diffusion, ion implantation, or other methods.

[0208] S300: An anti-reflection layer 2 is formed on the first surface, and the anti-reflection layer 2 covers the side of the first doped semiconductor layer 6 away from the silicon substrate 1.

[0209] Specifically, the antireflection layer 2 can be formed by deposition or other methods. The material and structure of the antireflection layer 2 can be referred to in the previous text and will not be repeated here.

[0210] S400: A first seed layer 421 is formed, which is electrically connected to the first doped semiconductor layer 6 through the passivation layer. The first seed layer 421 includes a plurality of first metal particles 402 and a plurality of second metal particles 403 deposited on at least a partial surface of the first metal particles 402. The particle size of the first metal particles 402 is a, and the particle size of the second metal particles 403 is b, where ab ≥ 40 nm and / or a ≥ 1.5b;

[0211] S500: A first transport layer 511 is formed, extending along a first direction and spaced apart along a second direction, with at least a portion of the first transport layer 511 disposed on the side of the first seed layer 421 away from the silicon substrate 1.

[0212] Compared with the prior art, the manufacturing method of this solar cell has the same beneficial effects as the aforementioned solar cells, and will not be repeated here.

[0213] On the other hand, this application also provides a solar cell, as shown in Figure 12, which includes a silicon substrate 1, a first doped semiconductor layer 6, an antireflection layer 2, a first seed layer 421, and a first transport layer 511. The technical features of the silicon substrate 1, the first doped semiconductor layer 6, and the antireflection layer 2 can be referred to above, and will not be repeated here.

[0214] As shown in Figure 13, the antireflection layer 2 has multiple first openings 301 exposing the first doped semiconductor layer 6, and the multiple first openings 301 can be arranged in multiple groups. A first seed layer 421 is first formed in the first openings 301 of the antireflection layer 2, and then a first transport layer 511 is formed on the first seed layer 421. The process of fabricating the first seed layer 421 and the first transport layer 511 with metal can adopt a low-temperature process, which reduces the fabrication difficulty and saves energy consumption, thereby further reducing production costs.

[0215] The first seed layer 421 includes a portion disposed corresponding to the first opening 301 and an overflow portion 401 located on the side of the anti-reflection layer 2 away from the silicon substrate 1. That is, a portion of the first seed layer 421 is disposed corresponding to the first opening 301, and this portion is electrically connected to the first semiconductor. Another portion of the first seed layer 421 is located on the surface of the anti-reflection layer 2 away from the silicon substrate 1. The portion of the first seed layer 421 located on the surface of the anti-reflection layer 2 away from the silicon substrate 1 is the overflow portion 401. As shown in Figure 6 or Figure 12, the overflow portion includes a first overflow portion 411. As shown in any one of Figures 14-29, the overflow portion also includes a second overflow portion 412. The second overflow portion 412 and the portion of the first seed layer 421 corresponding to the first opening 301 can be continuously disposed or discontinuously disposed; that is, the overflow portion 401 and the portion of the first seed layer 421 corresponding to the first opening 301 can be electrically conductive or non-conductive. There are multiple first seed layers 421, and each first opening 301 is provided with a corresponding first seed layer 421. The first seed layer 421 can be formed by processes such as screen printing, electroplating, sputtering or vapor deposition.

[0216] The first transport layer 511 extends along a first direction, meaning the length of the first transport layer 511 is set along the first direction. Multiple first transport layers 511 are spaced apart along a second direction. At least a portion of the first transport layer 511 is disposed on the side of the first seed layer 421 facing away from the silicon substrate 1. Each first transport layer 511 can be electrically connected to a set of first seed layers 421 corresponding to a set of first openings 301, meaning the first seed layers 421 corresponding to the same set of first openings 301 are electrically connected to the same first transport layer 511, so as to utilize the first transport layer 511 and the first seed layer 421 to extract the charge carriers collected by the first doped semiconductor layer 6. The first transport layer 511 can be formed from a base metal paste, which is a non-burn-through paste. The base metal paste can be considered as a paste with a base metal content greater than 50%, such as copper paste, aluminum paste, silver-coated copper, or other relatively inexpensive conductive metals. The first transport layer 511 can be formed using processes such as screen printing, electroplating, sputtering, or vapor deposition.

[0217] Using the above technical solution, the first seed layer 421 further includes an overflow portion 401 located on the side surface opposite to the silicon substrate 1. The formation of the overflow portion 401 increases the contact area between the first seed layer 421 and the first transport layer 511, which helps to improve the adhesion between the first transport layer 511 and the first seed layer 421, prevents the first transport layer 511 from falling off, and thus improves the performance stability of the solar cell. Furthermore, when the overflow portion 401 is partially conductively connected to the first seed layer 421 corresponding to the first opening 301, it helps to improve the conductivity between the first seed layer 421 and the first transport layer 511, reduce transmission loss, and improve current transmission efficiency.

[0218] It is understood that, from a microscopic perspective, the first seed layer includes a first metal particle 402 and a second metal particle 403. From a macroscopic perspective, the first seed layer includes a portion disposed corresponding to the first opening 301, and an overflow portion 401 located on the side of the antireflection layer 2 away from the silicon substrate 1. Both the overflow portion 401 and the portion of the first seed layer disposed corresponding to the first opening 301 include the first metal particle 402 and the second metal particle 403.

[0219] In some embodiments, the overflow portions around at least two adjacent first openings 301 are partially connected, that is, the overflow portions around adjacent first openings 301 extend to be partially connected, which further increases the conductive area and contact area between the first seed layer 421 and the first transmission layer 511, and can simultaneously improve the conductivity between the first seed layer 421 and the first transmission layer 511 as well as the adhesion of the first transmission layer 511.

[0220] In some embodiments, as shown in Figures 14-17, the overflow portions 401 around at least two adjacent first openings 301 are discontinuous. That is, the overflow portion 401 corresponding to the first seed layer 421 of one first opening 301 is spaced apart and discontinuous from the overflow portion 401 of the first seed layer 421 of the corresponding adjacent first opening 301. The overflow portion 401 can be formed by extending the first opening 301 in any direction. Specifically, one end of the overflow portion 401 can connect with the portion of the first seed layer 421 corresponding to the first opening 301, and the other end of the overflow portion 401 can face any direction. With this configuration, the overflow portion 401 is electrically connected to the portion corresponding to the first seed layer 421 and the first opening 301, which increases the conductive area and contact area between the first seed layer 421 and the first transmission layer 511. This can simultaneously improve the conductivity between the first seed layer 421 and the first transmission layer 511, as well as the adhesion of the first transmission layer 511. It can also reduce the use of raw materials for the first seed layer 421, reduce manufacturing costs, and avoid waste of raw materials for the first seed layer 421.

[0221] In some embodiments, as shown in Figures 18-21, the overflow portions 401 around at least two adjacent first openings 301 are connected and continuous. Specifically, the overflow portion 401 of the first seed layer 421 corresponding to one first opening 301 is connected to the overflow portion 401 of the first seed layer 421 corresponding to another adjacent first opening 301, meaning that the overflow portion 401 is continuous and uninterrupted between the two adjacent first openings 301. This technical solution can further increase the conductive area and contact area between the first seed layer 421 and the first transmission layer 511, thereby further improving the conductivity and adhesion of the first transmission layer 511.

[0222] In some embodiments, as shown in Figures 22-23, the overflow portion 401 can also be dispersedly disposed around the first opening 301. That is, the dispersed overflow portion 401 is in the form of scattered points, and the dispersed overflow portion 401 can be electrically connected to or not electrically connected to the portion of the first seed layer 421 corresponding to the first opening 301. This arrangement helps to save raw materials for the first seed layer 421 while ensuring battery performance. At the same time, the dispersed overflow portion 401 also helps to increase the contact area between the first seed layer 421 and the first transport layer 511, thereby increasing the adhesion of the first transport layer 511 and preventing the first transport layer 511 from falling off.

[0223] In some embodiments, the overflow portion 401 around the first opening 301 can extend along a first direction, such that the extension direction of the overflow portion 401 is the same as the extension direction of the first transmission layer 511, which can further increase the contact area between the first seed layer 421 and the first transmission layer 511, and further improve the adhesion of the first transmission layer 511.

[0224] In some embodiments, as shown in Figures 14, 16, and 19, the overflow portions 401 around at least two adjacent first openings 301 extend discontinuously along a first direction. Specifically, the overflow portions 401 may be formed extending from the first openings 301 along the first direction, i.e., the length direction of the overflow portions 401 extends along the first direction.

[0225] In some embodiments, as shown in Figures 19-24, overflow portions 401 around at least two adjacent first openings 301 are connected and continuous along a first direction. The overflow portions 401 may be formed extending from the first openings 301 along the first direction.

[0226] In the above technical solution, the overflow portions 401 of multiple first seed layers 421 are sequentially connected along the first direction, and the first transport layer 511 also extends continuously along the first direction. This facilitates further increasing the contact area between the first transport layer 511 and the first seed layer 421, and further improving the adhesion of the first transport layer 511. Furthermore, when the solar cell is a back-contact cell, it prevents the overflow portions 401 from extending along the second direction into the isolation area or areas with opposite polarity, thereby avoiding leakage.

[0227] The following comparison addresses the above scenarios:

[0228] As shown in the table above, when the first seed layer 421 includes the overflow portion 401, the adhesion of the first transmission layer 511 is higher, and the proportion of detachment is significantly lower. When the overflow portions 401 between two adjacent first openings 301 are connected, the proportion of detachment of the first transmission layer 511 is the lowest, the series resistance is the lowest, and the power generation efficiency is the highest.

[0229] In some embodiments, the first doped semiconductor layer 6 is an N-type doped semiconductor layer, meaning that the first doped semiconductor layer 6 is doped with group V or group VI elements, such as phosphorus (P), arsenic (As), and antimony (Sb). In this technical solution, the N-type doped semiconductor layer collects fewer charge carriers than the P-type semiconductor layer. Therefore, the width of the first opening 301 can be 3μm to 20μm to match the efficiency of the N-type doped semiconductor layer in collecting charge carriers. This ensures the carrier transport efficiency of the N-type doped semiconductor layer while avoiding an excessively large width of the first opening 301, thus reducing recombination. For example, the width of the first opening 301 can be 3μm, 5μm, 8μm, 10μm, 12μm, 15μm, 18μm, or 20μm. The contact resistance between the N-type doped semiconductor layer and the first seed layer 421 is less than or equal to 0.1mΩ*cm².

[0230] In other embodiments, the first doped semiconductor layer 6 is a P-type semiconductor layer doped with group III elements, such as boron (B), aluminum (Al), and gallium (Ga). In this technical solution, the P-type semiconductor layer collects more charge carriers than the N-type doped semiconductor layer. Therefore, the width of the first aperture 301 can be 5μm to 30μm to match the carrier collection efficiency of the P-type semiconductor layer, ensuring the carrier transport efficiency of the P-type semiconductor layer while avoiding a large width of the first aperture 301 to reduce recombination. For example, the width of the first aperture 301 can be 5μm, 8μm, 10μm, 12μm, 15μm, 18μm, 20μm, 22μm, 25μm, 28μm, or 30μm. The contact resistance between the P-type semiconductor layer and the first seed layer 421 is less than or equal to 0.8mΩ*cm².

[0231] Of course, the shape of the first opening 301 may include a circular hole, an elliptical hole, and / or a polygonal hole, which is not limited here.

[0232] This invention also provides a method for manufacturing a solar cell, which can prepare the solar cell described in any of the above embodiments. The method for manufacturing the solar cell includes the following steps:

[0233] S101: Provides a silicon substrate 1, the silicon substrate 1 having opposing first and second surfaces.

[0234] Prior to this step, in some embodiments, the silicon substrate 1 may be immersed in a polishing and cleaning machine to remove the cutting damage layer of the silicon substrate 1 using a polishing slurry. Furthermore, in this step, the morphology of the first and second surfaces of the silicon substrate 1 after polishing and cleaning can be adjusted by regulating parameters such as temperature, time, type of cleaning slurry, and concentration of the cleaning slurry. It should be noted that in some examples, the polishing and cleaning step may be omitted.

[0235] S201: A first doped semiconductor layer 6 is formed on the first surface.

[0236] In this step, the first doped semiconductor layer 6 can be formed entirely or partially on the first surface. The first doped semiconductor layer 6 can be additionally formed on the first surface of the silicon substrate 1 by deposition technology, or it can be formed within the silicon substrate 1 by diffusion, ion implantation, or other methods.

[0237] S301: An anti-reflection layer 2 is formed on the first surface, and the anti-reflection layer 2 covers the side of the first doped semiconductor layer 6 away from the silicon substrate 1.

[0238] Specifically, the antireflection layer 2 can be formed by deposition or other methods. The material and structure of the antireflection layer 2 can be referred to in the previous text and will not be repeated here.

[0239] S401: Multiple first openings 301 are formed on the anti-reflection layer 2 to expose the first doped semiconductor layer 6.

[0240] Specifically, a laser grooving process can be used to form multiple sets of first openings 301 on the antireflective layer 2. In some embodiments, after this step, the solar cell can be cleaned to remove dust particles generated during the grooving process.

[0241] S501: Form a first seed layer 421, the first seed layer 421 including a portion disposed corresponding to the first opening 301, and an overflow portion 401 located on the side of the anti-reflection layer 2 away from the silicon substrate 1.

[0242] The portion of the first seed layer 421 located on the side of the antireflection layer 2 facing away from the silicon substrate 1 is called the overflow portion 401. The first seed layer 421 can be formed using processes such as screen printing, electroplating, sputtering, or vapor deposition.

[0243] S600: A first transport layer 511 is formed, extending along a first direction and spaced apart along a second direction, with at least a portion of the first transport layer 511 disposed on the side of the first seed layer 421 away from the silicon substrate 1.

[0244] The first transport layer 511 can be formed from a base metal paste, which is a non-burn-through type paste. The base metal paste can be considered as a paste with a base metal content greater than 50%, such as copper paste, aluminum paste, silver-coated copper, and other relatively inexpensive conductive metals. The first transport layer 511 can be formed using processes such as screen printing, electroplating, sputtering, or vapor deposition.

[0245] In the solar cell manufactured using the above method, the formation of the overflow portion of the first seed layer 421 increases the contact area between the first seed layer 421 and the first transport layer 511, which helps to improve the adhesion between the first transport layer 511 and the first seed layer 421, prevents the first transport layer 511 from falling off, and thus improves the performance stability of the solar cell. Simultaneously, the first seed layer 421 is first formed within the first opening 301 of the antireflection layer 2, and then the first transport layer 511 is formed on the first seed layer 421. The first transport layer 511 can be formed from base metal paste. Compared with the prior art where silver paste is burned through the antireflection layer 2 to form a single silver electrode, this method can significantly reduce the amount of silver paste required for the overall electrode structure of the solar cell, thereby reducing the manufacturing cost of the overall electrode structure.

[0246] Compared with the prior art, the beneficial effects of the photovoltaic module provided in this application are the same as those of the solar cell and the manufacturing method of the solar cell described above, and will not be repeated here. Furthermore, in the solar cell used in this photovoltaic module, the plurality of first metal particles 402 on the surface of the first seed layer 421 have a height difference, which is beneficial to improving the adhesion between the first transport layer and the first seed layer 421, as well as the adhesion between the solder ribbon and the first transport layer.

[0247] Figures 25, 26, 27, 28 and 29 show the solar cell provided by the present invention. Figure 4 is a side cross-sectional microstructure diagram of the solar cell, while Figures 25, 26 and 27 are schematic diagrams of the side cross-sectional structure of the solar cell. Figures 25, 26 and 27 show the side cross-sectional structures of three different seed layers, and Figure 28 shows a top view schematic diagram of the seed layer in the solar cell.

[0248] The solar cell includes: a silicon substrate 1, a doped semiconductor layer 9, an antireflection layer 3, and an electrode 10; the electrode 10 includes a seed layer 4 and a transport layer 5; the doped semiconductor layer 9 is disposed on at least one surface of the silicon substrate 1; at least a portion of the doped semiconductor layer 9 on the side opposite to the silicon substrate 1 is provided with the antireflection layer 3; the surface of the doped semiconductor layer 9 includes an opening 3 without the antireflection layer 3; the seed layer 4 is disposed on the side of the doped semiconductor layer 9 opposite to the silicon substrate 1, and the seed layer 4 at least covers the opening 3; the transport layer 5 is disposed on the side of the seed layer 4 opposite to the doped semiconductor layer 9; the height of the edge region 414 in the seed layer 4 is greater than the height of the edge region 414 in the seed layer 4.

[0249] In this embodiment of the invention, when preparing a solar cell, the silicon substrate 1 is first texturized and impurities are diffused to prepare a doped semiconductor layer 9 on the surface of the silicon substrate 1. Then, a film is deposited on the surface of the doped semiconductor layer 9 to prepare an antireflection layer 3. After the antireflection layer 3 is prepared, the antireflection layer 3 is opened according to the designed transport layer pattern by means of laser engraving and other processes, and part of the antireflection layer 3 is removed to form a transport layer trench structure, so that the surface of the doped semiconductor layer 9 includes an opening 3 without the antireflection layer 3. It can be understood that the opening 3 is the bottom surface of the transport layer trench structure. The electrode 10 of the solar cell includes a seed layer 4 and a transport layer 5. First, the seed layer 4 is chemically deposited in the opening 3 to at least cover the opening 3. Then, the transport layer 5 is coated on the back side of the seed layer 4, so that the seed layer 4 and the transport layer 5 form the electrode 10.

[0250] The electrode 10 prepared above mainly includes fine grids in the electrode 10. The main grid in the electrode 10 can be made of only the transmission layer 5 and is disposed on the surface of the anti-reflection layer 3 outside the opening 3, connecting each fine grid to form a grid-shaped electrode 10.

[0251] The antireflection layer 3 can be used to block external metal ions, water and other substances from corroding the solar cell, and can reduce the reflection of sunlight and improve the absorption efficiency of the solar cell. In some embodiments, the antireflection layer 3 is also called an antireflection film.

[0252] The seed layer 4 can either fill only the opening 3 or extend beyond the opening 3. That is, it can either cover only the opening 3 or cover the part of the anti-reflection layer 3 adjacent to the opening 3 on the basis of covering the opening 3.

[0253] The edge region 414 can be determined based on the size of the seed layer 4 extending along the surface of the silicon substrate 1. Referring to FIG28, for example, if the size of the seed layer 4 in the direction perpendicular to the extension of the electrode 10 in the multiple directions extending along the surface of the silicon substrate 1 is L, then the region with a size of 0.2L, pointing from the edge of the seed layer 4 to the geometric center of the seed layer, can be selected as the edge region 414. It can be understood that the edge region 414 can be an annular region; the edge region 414 can extend inward from the edge of the seed layer 4 by 20%-30% (i.e., 0.2L-0.3L).

[0254] Referring to Figures 25 and 26, the edge region 414 includes at least the following cases: if the seed layer 4 only fills the opening 3, then as shown in Figure 26, the edge region 414 includes the portion of the seed layer 4 located at the edge of the opening 3, i.e., the inner side of the opening of the anti-reflection layer 3; if the seed layer 4 extends beyond the opening 3, then as shown in Figure 25, the position of the edge region 414 includes both the portion of the seed layer 4 located at the edge of the opening 3 and the portion of the seed layer 4 extending outwards. The high point of the seed layer edge region is located outside the opening, i.e., the extended portion; alternatively, the high point of the seed layer edge region may be located within the opening.

[0255] The height of the seed layer 4 at the edge region 414 is greater than the height of the position away from the edge region 414. In this invention, the surface of the silicon substrate 1, or any plane parallel to the surface between the seed layer 4 and the surface of the silicon substrate 1, is used as the reference plane. A point on the seed layer 4 away from the surface of the silicon substrate 1 is selected, and the vertical distance between this point and the reference plane is the height of the seed layer 4. It can be understood that the height of the edge region 414 is the vertical distance between the point selected in the edge region 414 and the reference plane.

[0256] The surface of the seed layer 4 facing away from the silicon substrate 1 can be a flat surface and / or a surface with irregularities. If the surface of the seed layer 4 facing away from the silicon substrate 1 is a surface with irregularities, the vertical distance between the vertex of the protrusion and the reference surface can be selected as the height of the protrusion, and the vertical distance between the vertex of the depression and the reference surface can be selected as the height of the depression. If there are multiple protrusions or depressions on the surface with irregularities, multiple protrusions or depressions can be selected.

[0257] For each of the convex or concave vertices, based on the same reference plane, multiple height values ​​are calculated, and then the average of the multiple calculated values ​​is taken as the height of seed layer 4.

[0258] It should be noted that the height of the edge region 414 is greater than the height of the part away from the edge region 414. This can mean that the height of the edge region 414 is greater than the height of the part away from the edge region 414, or it can be understood as the height of the edge region 414 being greater than the height of the adjacent edge region, as shown in Figure 2.

[0259] As shown in Figure 7, the seed layer 4 faces the transmission layer 5. The middle part of the seed layer 4, which is far from the edge region 414, may also have other depressions and protrusions. These protrusions are caused by other processes of the seed layer 4 and are not the focus of this research and development. However, this case does not exclude such morphological conditions. It is worth noting that only the height of the depression is less than the height of the edge region 414.

[0260] After the transport layer 5 is set, the antireflection layer 3 can block the diffusion of metal ions in the transport layer 5 to the doped semiconductor layer 9. However, due to the thermal effect of the laser, the antireflection layer 3 near the opening 3 will be thinned. The antireflection layer 3 located at the edge of the opening 3 is prone to cracks due to uneven stress changes, thereby generating diffusion channels for metal ions. The metal ions in the transport layer 5 will diffuse into the opening 3 through this channel and recombine with the ions in the doped semiconductor layer 9, weakening the electrical performance of the solar cell. Setting the position of the edge region 414 of the seed layer 4 to be higher than the position of the seed layer 4 away from the edge region 414 can make the edge region of the seed layer 4 form a structure similar to a wall or dam, avoiding direct contact between the transport layer 5 and the opening 3, increasing the diffusion distance of metal ions in the transport layer 5, blocking the diffusion channels, and forming an effective barrier to the transport layer 5.

[0261] Referring further to Figure 30, which is a side cross-sectional view of another embodiment of the solar cell provided by the present invention, a passivation layer 8 can also be provided in the solar cell. The passivation layer 8 can be provided between the doped semiconductor layer 9 and the antireflection layer 3, or between the doped semiconductor layer 9 and the silicon substrate 1. When the opening 3 is formed by opening the film, the passivation layer 8 at the opening 3 is removed together, exposing the doped semiconductor layer 9 of the opening 3. The passivation layer 8 provided between the doped semiconductor layer 9 and the antireflection layer 3 is a first passivation layer 51. The thickness of the first passivation layer 51 can be configured to be 4-10 nm. The material of the first passivation layer 51 can be configured as aluminum oxide. The oxygen-silicon (O-Si) chemical bonds in aluminum oxide can provide chemical passivation capability. The presence of fixed negative charges in aluminum oxide can play a field passivation effect. Through field passivation and chemical passivation, recombination loss in the solar cell can be reduced, and the photoelectric conversion efficiency of the solar cell can be improved. The passivation layer 8 provided between the doped semiconductor layer 9 and the silicon substrate 1 is a second passivation layer 52. The second passivation layer 52 can be configured as silicon dioxide (SiO2). The second passivation layer can also be called the interface layer.

[0262] In this invention, the solar cell includes a silicon substrate, a doped semiconductor layer, an antireflection layer, and an electrode. The electrode includes a seed layer and a transport layer. The seed layer at least covers the opening in the doped semiconductor layer where the antireflection layer is not located, ensuring good ohmic contact between the electrode and the doped semiconductor layer. A transport layer is located on the seed layer to collect current. The height of the edge region of the seed layer is greater than the height of the region away from the edge of the seed layer. When openings are created using a laser, the antireflection layer at the opening edge is prone to cracking due to the heat effect of the laser. The antireflection layer near the opening edge thins, reducing its blocking effect on the transport layer. Metal ions in the transport layer can easily diffuse into the opening of the doped semiconductor layer, causing undesirable metal recombination and weakening the electrical performance of the solar cell. In this invention, the higher edge region of the seed layer allows it to effectively block the transport layer, preventing the main metal ions of the transport layer from diffusing into the doped semiconductor layer through the opening edge, thus avoiding metal recombination and ensuring the electrical performance of the solar cell.

[0263] Optionally, the height difference between the position at the edge region 414 of the seed layer 4 and the position in the seed layer 4 away from the edge region 414 is 20-300nm.

[0264] The height difference between the position at the edge region 414 and the position away from the edge region 414 can be controlled between 20-300 nm. This height difference makes the edge region 414 of the seed layer 4 higher and the middle lower, resulting in a curved or basin-like interface between the seed layer 4 and the transport layer 5. This increases the specific surface area of ​​the contact between the seed layer 4 and the transport layer 5, which not only reduces the contact resistance between the seed layer 4 and the transport layer 5, reducing current loss and improving the conductivity of the electrode 10, but also microscopically increases the unevenness between the seed layer 4 and the transport layer 5, which is beneficial to improving the interfacial bonding force between the two layers and preventing the transport layer 5 from detaching from the surface of the seed layer 4. The height difference range can balance the conductivity and mechanical stability of the electrode 10 of the solar cell, thereby improving the reliability and overall efficiency of the solar cell.

[0265] In the seed layer 4, the height of the seed layer 4 can be gradually varied from the position at the edge region 414 to the position away from the edge region 414. This feature can provide smooth stress changes for the seed layer 4 and the transport layer 5, achieve dynamic balance of mechanical stress, and prevent the seed layer 4 and the transport layer 5 from delamination or cracking.

[0266] For example, in the seed layer 4, the difference between the thickness of the edge region 414 and the thickness of the region away from the edge region 414 can be 20nm, 80nm, 100nm, 155nm, 175nm, 200nm, 220nm, 250nm, 280nm, or 300nm.

[0267] Optionally, referring to Figures 30, 31, 32, 33, 34, 35, and 36, where Figure 31 is a microstructure view of the openings on the surface of the second doped semiconductor (5500x magnification), Figure 8 is a further magnified microstructure view of Figure 7 (20000x magnification), Figure 33 is a top view microstructure view of the seed layer 4 (i.e., the second seed layer 422) disposed on the second doped semiconductor layer 7 (5500x magnification); Figure 34 is a microstructure view of the openings on the surface of the second doped semiconductor layer 7 (5500x magnification), Figure 35 is a further magnified microstructure view of Figure 10 (20000x magnification), and Figure 36 is a top view microstructure view of the seed layer 4 (i.e., the first seed layer 421) disposed on the first doped semiconductor layer 6 of the doped semiconductor layer 9 (5500x magnification). Second seed layer 422

[0268] The first doped semiconductor layer 91 is an N-type doped semiconductor layer, and the second doped semiconductor layer 92 is a P-type semiconductor layer. From the position at the edge region 414 to the position away from the edge region 414, the rate of change of the height of the first seed layer 421 is less than the rate of change of the height of the second seed layer 422; or, the height difference between the position of the first seed layer 421 at the edge region 414 and the position away from the edge region 414 is less than the height difference between the position of the second seed layer 422 at the edge region 414 and the position away from the edge region 414.

[0269] From the position of edge region 414 to the direction away from edge region 414, the height change rate of the first seed layer 421 is less than that of the second seed layer 422. The slower height change of the first seed layer 421 provides a smoother stress transition at the contact surface between the first seed layer 421 and the transport layer 5, reducing stress accumulation at the contact surface and preventing cracks or gaps. Compared to the N-type doped semiconductor layer, the P-type semiconductor layer has weaker carrier separation and transport capabilities, requiring reinforcement of the carrier transport channel. Therefore, this application designs a larger height change rate for the second seed layer 422, which increases the volume of the recessed structure formed on the surface of the second seed layer 422, accommodating more transport layer 5 paste and expanding the transport channel of the transport P region. At the same time, the larger contact area between the second seed layer 422 and the transport layer 5 reduces contact resistance and improves the electrical performance of the electrode 10 composed of the second seed layer 422 and the transport layer 5.

[0270] Alternatively, the height difference between the position of the first seed layer 421 at the edge region 414 and the position away from the edge region 414 is less than the height difference between the position of the second seed layer 422 at the edge region 414 and the position away from the edge region 414.

[0271] Similarly, the smaller height difference of the first seed layer 421 provides a smoother stress transition at the contact surface between the first seed layer 421 and the transport layer 5, reducing stress accumulation at the contact surface and preventing cracks or gaps. Compared to the N-type doped semiconductor layer, the P-type semiconductor layer has weaker carrier separation and transport capabilities, requiring reinforcement of the carrier transport channels. Therefore, this application designs a larger height difference for the second seed layer 422, which increases the volume of the recessed structure formed on the surface of the second seed layer 422, accommodating more transport layer 5 paste and expanding the transport channels in the P-region. At the same time, the larger contact area between the second seed layer 422 and the transport layer 5 reduces contact resistance and improves the electrical performance of the electrode 10 composed of the second seed layer 422 and the transport layer 5.

[0272] The height difference can be verified as follows: First, in the first seed layer 421, calculate the average height of the edge region 414 and the average height of the position away from the edge region 414, and use the difference between these two average heights as the height difference of the first seed layer 421; then, in the second seed layer 422, calculate the average height of the edge region 414 and the average height of the position away from the edge region 414, and use the difference between these two average heights as the height difference of the second seed layer 422; when sampling, the sample size and relative position in the first seed layer 421 should be consistent with the sample size and relative position in the second seed layer 422 (the relative position here can be the position relative to a certain anchor point, for example, the anchor point can be the geometric center of the seed layer 4).

[0273] Optionally, the surface of the doped semiconductor layer 9 in the opening 3 has a first protrusion structure 61, and the height of the seed layer 4 in the opening 3 is positively correlated with the density of the first protrusion structure 61 on the surface of the doped semiconductor layer 9.

[0274] The formation of the seed layer 4 depends on the deposition of the preparation material on the surface of the doped semiconductor layer 9. In areas with a higher density of the first protrusion structure 61, the metal deposition rate is faster, resulting in a higher metal film layer (seed layer 4). That is, the height of the seed layer 4 is positively correlated with the density of the first protrusion structure on the surface of the doped semiconductor layer 9. For the doped semiconductor layer 9 located in the opening 3, since the density of the first protrusion structure 61 of the doped semiconductor layer 9 near the edge of the opening 3 is greater than that of the first protrusion structure 61 of the doped semiconductor layer 9 far away from the edge of the opening 3, the deposition rate of the seed layer 4 on the surface of the doped semiconductor layer 9 near the edge of the opening 3 is faster. This makes the height of the seed layer 4 in this region higher than that of the seed layer 4 away from the edge of the opening 3. Ultimately, the height of the edge region 414 in the seed layer 4 is greater than the height of the region away from the edge region 414.

[0275] It should be noted that the process for seed layer 4 obtained in this application may include, but is not limited to, the following examples:

[0276] For example, in one embodiment, the opening 3 is formed by laser ablation, and the laser spot size is smaller than the opening 3 size. When forming the opening 3, the power of the laser spot edge can be set to be less than the power of the center, such as reducing the edge power by 10%-20%, so that the laser power is greater when removing the antireflection layer 3 in the center of the opening 3. The lower the laser power, the longer the removal time of the antireflection layer 3, and the longer the time window for the doped semiconductor layer 9 to generate unsaturated bonds or structural defects. Therefore, in the opening 3, the first protrusion structure 61 is more likely to be formed at the edge position of the opening 3 irradiated by the lower power laser. That is, the density of the first protrusion structure 61 at this position is higher or the surface roughness at this position is greater. The material for preparing the seed layer 4 is more likely to be deposited at this position, resulting in the height of the seed layer 4 in the opening 3 near the edge of the opening 3 being greater than the height of the position far away from the edge of the opening 3.

[0277] Furthermore, in the above embodiment, as the laser spot moves from a position far away from the edge of the aperture 3 to a position closer to the edge of the aperture 3, the power of the laser can be gradually reduced (for example, the laser spot initially illuminates the geometric center of the aperture 3, and the laser power decreases by 5% for every 100nm moved outward). This can also result in the height of the seed layer 4 in the aperture 3 being closer to the edge of the aperture 3 being greater than the height of the position far away from the edge of the aperture 3.

[0278] For example, when preparing the antireflection layer 3 on the surface of the doped semiconductor layer 9, the height of the antireflection layer 3 near the edge of the opening 3 can be made greater than the height of the antireflection layer 3 in other areas. For example, when preparing the antireflection layer 3 by plasma-enhanced chemical vapor deposition (PEVCD), a shielding plate is placed at a certain distance directly above the opening 3. The size of the shielding plate is slightly smaller than the size of the opening 3 (for example, if the opening is rectangular, the shielding plate is also rectangular, and the length and width are reduced by 10% proportionally). The shielding plate can disturb the gas flow direction, making the vapor deposition flux at the edge of the opening and outside the opening higher than inside the opening. This results in more material for preparing the antireflection layer being deposited near the edge of the opening 3 than inside the opening 3, making the height of the antireflection layer 3 near the edge of the opening 3 greater than the height of the antireflection layer 3 in other areas. During the laser film-forming process, when the laser energy is roughly equal, the antireflection layer 3 near the edge of the opening 3 is higher and more resistant to laser etching, which makes the time window for the doped semiconductor layer 9 to generate unsaturated bonds or structural defects longer. Therefore, the first protrusion structure 61 is more likely to be formed at the edge of the opening 3, that is, the density of the first protrusion structure 61 at this location is higher or the surface roughness is greater. The material for preparing the seed layer 4 is more likely to be deposited at this location, resulting in the height of the seed layer 4 near the edge of the opening 3 being greater than the height of the location far away from the edge of the opening 3.

[0279] Alternatively, the structure of the seed layer 4 located in the opening 3 can be directly changed during the preparation of the seed layer 4.

[0280] For example, in another embodiment, after a sufficiently high (e.g., 1300 nm) and relatively flat seed layer 4 is deposited in the aperture 3, a mask is covered on the surface of the seed layer 4. This mask is configured as an annular opening, wherein the inner diameter of the annulus extends slightly inward from the edge of the aperture 3 (e.g., 2 μm). The seed layer 4 is then etched using a small amount of a special reagent for the seed layer preparation material. Finally, the mask is removed using a special reagent for the mask. For the seed layer 4 in the aperture 3, the position near the edge of the aperture 3 is protected by the mask and has a small height change, while the position away from the edge of the aperture 3 is exposed and etched by the special reagent for the seed layer 4, resulting in a large height change. Consequently, after removing the mask, for the seed layer 4 in the aperture 3, the height near the edge of the aperture 3 is greater than the height of the position far from the edge of the aperture 3.

[0281] As shown in Figure 30, in one embodiment, the first doped semiconductor layer 6 and the second doped semiconductor layer 7 can be alternately disposed on the same side of the silicon substrate 1. In this case, a transition region 11 is provided between the first doped semiconductor layer 6 and the second doped semiconductor layer 7. During the fabrication of the solar cell, the doped semiconductor layer 9 in the transition region 11 located on the surface of the silicon substrate 1 is removed, leaving only the antireflection layer 3 on the surface of the transition region 11. The transition region 11 can block the lateral (along the surface extension direction of the silicon substrate 1) diffusion of impurities in the first doped semiconductor layer 6 and the second doped semiconductor layer 7, block lateral leakage between the first doped semiconductor layer 6 and the second doped semiconductor layer 7, provide a certain process tolerance margin, and ensure that the opening 3 in the first doped semiconductor layer 6 and the opening 3 in the second doped semiconductor layer 7 avoid each other. In addition, the fact that the first doped semiconductor layer 6 and the second doped semiconductor layer 7 are disposed on the same side of the silicon substrate 1 can avoid flipping the solar cell during the fabrication of the electrode 10, thereby improving the fabrication efficiency.

[0282] Optionally, referring to Figures 33 and 36, the seed layer 4 has a plurality of second protrusion structures 413 on the side near the transport layer 5.

[0283] During the formation of the seed layer 4, multiple spaced second protrusion structures 413 are formed on the upper surface (i.e. the side facing the transport layer 5). These second protrusion structures 413 can further increase the contact area between the seed layer 4 and the transport layer 5, reduce the contact resistance between the seed layer 4 and the transport layer 5, and improve the electrical performance of the electrode 10.

[0284] Optionally, the number of second protrusions 413 on the side of the first seed layer 421 near the transmission layer 5 is greater than the number of second protrusions 413 on the side of the second seed layer 422 near the transmission layer 5.

[0285] For the seed layer 4 on the surface of the first doped semiconductor layer 6, the impurity ions (e.g., phosphorus ions) added therein have the same charge as the impurity ions doped in the first doped semiconductor layer 6, making it easier for the impurity ions in the seed layer 4 to accumulate on the side of the seed layer 4 away from the doped semiconductor layer 9, thereby forming more second protrusion structures 413. That is, for the seed layer 4 located on the surface of the first doped semiconductor layer 6, the number of second protrusion structures 413 on its upper surface is greater than that for the seed layer 4 located on the surface of the second doped semiconductor layer 7. The first seed layer 421 has more second protrusion structures 413, which can enhance the interfacial bonding force between the first seed layer 421 and the transport layer 5 and ensure the mechanical strength of the electrode 10 itself.

[0286] Optionally, along the thickness direction of the solar cell, the projection of the second protrusion structure 413 in the opening 3 coincides with at least a portion of the first protrusion structure 61.

[0287] The second protrusion structure 413 is projected into the opening 3 along the thickness direction of the solar cell. The projection of the second protrusion structure 413 can coincide with at least a portion of the first protrusion structure 61. When viewed along the thickness direction of the silicon substrate 1, the size of the first protrusion structure 61 is smaller than that of the second protrusion structure 413. Therefore, among the multiple first protrusion structures 61, at least a portion of the first protrusion structures 61 coincide with the projection of the second protrusion structure 413.

[0288] The first protrusion structure 61 and the second protrusion structure 413 can respectively enhance the interfacial bonding force on the opposite sides of the seed layer 4. At least part of the projection of the first protrusion structure 61 and the second protrusion structure 413 coincides, which can ensure that the material on the opposite sides applies force to the seed layer 4 at roughly the same position, so that the stress on the opposite sides of the seed layer 4 is more similar. This avoids the tearing or shearing force of the doped semiconductor layer 9 and the transport layer 5 on the seed layer 4 due to different force application positions on both sides, which would damage the structure of the seed layer 4.

[0289] Optionally, referring to Figures 25 and 29, the height of the seed layer 4 is greater than the height of the anti-reflection layer 3, and the seed layer 4 extends beyond the opening 3 to cover part of the anti-reflection layer 3.

[0290] As shown in Figure 25, in one embodiment, the thickness of the seed layer 4 is greater than the thickness of the anti-reflection layer 3, causing a portion of the seed layer 4 to extend beyond the opening 3 along the anti-reflection layer 3, forming an eave-like overflow area that covers the anti-reflection layer 3, also known as the overflow portion. The significance of this arrangement is that the overflow area can cover the anti-reflection layer 3 around the opening 3, enhancing the isolation effect between the doped semiconductor layer 9 and the transport layer 5, and strengthening the blocking effect of the seed layer 4 on the transport layer 5. The overflow area can also eliminate the sharp step structure between the opening 3 and the anti-reflection layer 3, achieving a smooth transition between the electrode 10 and the anti-reflection layer 3, preventing mechanical breakage or large pores in the seed layer 4 or the transport layer 5 coated on the seed layer 4. The overflowing seed layer 4 can contact and connect with the anti-reflection layer 3, improving the connection strength of the electrode 10 on the solar cell. Furthermore, the overflowing seed layer 4 can increase its contact area with the transport layer 5, further reducing the contact resistance between the seed layer 4 and the transport layer 5, reducing current loss, and improving the conductivity of the electrode 10.

[0291] Optionally, referring to Figure 37, which is a schematic diagram of the side cross-sectional structure of a solar cell, the thickness of the seed layer 4 located in the opening 3 and close to the edge of the opening 3 is the first thickness D1, the thickness of the seed layer 4 extending outward from the opening 3 is the second thickness D2, and the thickness of the anti-reflection layer 3 is the third thickness D3. Then, we have: D1≥D2+D3.

[0292] The thickness of seed layer 4 refers to the distance along the height direction from the contact surface between seed layer 4 and doped semiconductor layer 9 to the contact surface between seed layer 4 and transport layer 5. The contact surface between seed layer 4 and doped semiconductor layer 9 can be a flat surface and / or an uneven surface, and the contact surface between seed layer 4 and transport layer 5 can be a flat surface and / or an uneven surface. If either of the two contact surfaces is an uneven surface, the vertex of the protrusion 52 or the concave portion 415 in the uneven surface can be selected as the endpoint for measuring the thickness of seed layer 4 in that contact surface. If both contact surfaces are uneven surfaces, and there are multiple protrusions 52 or concave portions 415 on the uneven surface, the highest point and / or the lowest point in the two contact surfaces can be selected as the endpoint for measuring the thickness of seed layer 4, or the average of multiple thickness measurements can be selected as the thickness of seed layer 4.

[0293] For example, both of the above contact surfaces are uneven. For the contact surface between the seed layer 4 and the transport layer 5, multiple sampling points can be selected, and the distance between these sampling points and their projection points on the contact surface between the seed layer 4 and the doped semiconductor layer 9 can be measured. After obtaining multiple sampling distances, the average value of these sampling distances is taken as the thickness of the seed layer 4.

[0294] For the seed layer 4 located in the opening 3, the first thickness D1 near the edge of the opening 3 can be measured at multiple sampling points and the average value can be taken as its thickness.

[0295] The thickness of the antireflection layer 3 refers to the distance along the height direction from the contact surface between the antireflection layer 3 and the doped semiconductor layer 9 to the contact surface between the antireflection layer 3 and the transport layer 5 (or the epitaxial seed layer 4); the method for determining its value can refer to the above-mentioned method for determining the thickness of the seed layer 4, and will not be repeated here.

[0296] Referring to Figure 37, which is a side cross-sectional view of another solar cell, the seed layer 4, which is thicker than the anti-reflection layer 3, extends along the direction of the silicon substrate 1, covering part of the anti-reflection layer 3. The side of the overflow portion facing away from the anti-reflection layer 3 contacts the transport layer 5. This contact surface can be considered as an extension of the contact surface between the seed layer 4 and the transport layer 5 in the opening 3. That is, for the contact surface between the seed layer 4 and the transport layer 5 near the edge of the opening 3, the contact surface inside the opening 3 is flush with the contact surface outside the opening 3. The thickness of the portion of the seed layer 4 located in the opening 3 and near the edge of the opening 3 is the first thickness D1, and the thickness of the portion of the seed layer 4 overflowing the anti-reflection layer 3 is the second thickness D2. The specific value range can be 200nm-600nm. The thickness of the antireflection layer 3 is the third thickness D3. During the laser film opening process, the laser etches the surface of the doped semiconductor layer 9, which reduces the thickness of the doped semiconductor layer 9 located in the opening 3. Thus, there is a height difference between the doped semiconductor layer 9 inside and outside the opening 3 along the direction away from the silicon substrate 1. This means that when measuring the first thickness D1, the endpoints near the doped semiconductor layer 9 are not on the same reference plane as when measuring the third thickness D3. In addition, the heat-affected zone of the laser spot will thin the antireflection layer 3 outside the opening, ultimately making D1≥D2+D3, as shown in Figure 37.

[0297] Since the first thickness D1 is greater than the sum of the second thickness D2 and the third thickness D3, the seed layer 4 in the opening 3 can extend towards the doped semiconductor layer 9 in the direction close to the doped semiconductor. On the one hand, this can increase the contact area between the seed layer 4 and the doped semiconductor layer 9 and reduce the contact resistance between the electrode 10 and the doped semiconductor layer 9. On the other hand, this arrangement can also ensure that the seed layer 4 and the anti-reflection layer 3 are in full contact and improve the peel strength of the electrode 10.

[0298] It should be noted that transport layer 5 should completely cover seed layer 4, that is, transport layer 5 should cover any overflowing seed layer 4.

[0299] Optionally, referring to Figure 37, the first thickness D1 and the second thickness D2 satisfy: D1:D2=4:(1~3).

[0300] For the edge region 414 of the seed layer 4, the ratio between the first thickness D1 of the portion located in the opening 3 and close to the edge of the opening 3 and the second thickness D2 of the portion extending outside the opening 3 can satisfy: 4:(1~3). Setting the ratio of D1 to D2 to 4:(1~3) can enhance the physical blocking effect of the seed layer 4 on the transport layer 5, ensuring that the thickness of the entire edge region 414 can meet the requirements for isolating the transport layer 5 and the doped semiconductor layer 9.

[0301] For example, the ratio of the first thickness D1 to the second thickness D2 can be 4:1, or the ratio of the first thickness D1 to the second thickness D2 can be 2:1.

[0302] Optionally, referring to Figure 37, in the seed layer 4, the thickness extending beyond the opening 3 is the second thickness D2, and the width extending beyond the opening 3 is the first width W1, then: D2:W1 = 0.25:(1~3).

[0303] In the seed layer 4, for the portion extending out of the opening 3, the aspect ratio D2:W1 can be in the range of 0.25:(1~3), for example, D2:W1 = 0.25:1, 0.75:1, 1:1, 1:1.5, 1:1.75, 1:2, 1:2.5, 1:3. When the seed layer 4 extends outward from the opening 3 in different directions, the extension distance in each direction may be different, and the extension distance at different positions in the same direction may be different, resulting in a variety of values ​​for W1. For example, the specific value range of W1 can be 50nm-400nm, but it basically satisfies D2:W1 = 0.25:(1~3). When measuring the first width W1, it is preferable to use the extension distance along the direction perpendicular to the electrode 10 as the first width W1 extending outward from the opening 3 in the seed layer 4.

[0304] The ratio of the second thickness D2 to the first width W1 is in the range of 0.25:(1~3), which can ensure the blocking effect of the seed layer 4 on the transport layer 5 in the epitaxial direction. It can not only block the anti-reflection layer 3 at the edge of the transport layer 5 and the opening 3 in the epitaxial direction, preventing the metal ions in the transport layer 5 from diffusing laterally into the opening 3, but also ensure that the seed layer 4 has sufficient contact area and interfacial bonding force with the transport layer 5 in any direction, preventing the peeling between the transport layer 5 and the seed layer 4.

[0305] Optionally, referring to FIG37, in seed layer 4, along the direction perpendicular to the extension of electrode 10, located at

[0306] If the width of the portion in the opening 3 is the second width W2, then along the extension direction perpendicular to the electrode 10, we have: W1:W2=1:(25~900).

[0307] Observing along the direction of electrode 10's extension, the width of the seed layer 4 located in the opening 3 is W2. Therefore, the ratio of W1 to W2 can be 1:(25~900), for example, W1:W2 = 1:25, 1:40, 1:80, 1:160, 1:280, 1:360, 1:480, 1:600, 1:700, 1:800. The specific value range of W2 can be 10μm-50μm. Since the shape of the opening is not restricted, the size of the seed layer 4 in the opening 3 can be different along different directions. Taking a common rectangular opening as an example, the length direction of this rectangle is the direction of electrode 10's extension. Therefore, the size of the seed layer 4 in the width direction of this rectangle, i.e., the size of the cross-section shown in Figure 37, is the second width W2. By controlling the ratio of W1 to W2, the seed layer 4 can extend further out of the opening 3.

[0308] This allows for the coverage of more antireflection layers 3, enhancing the blocking effect of the seed layer 4 on the transport layer 5, as well as the isolation effect on the transport layer 5 and the doped semiconductor layer 9, thereby improving the electrical performance of the solar cell.

[0309] Optionally, the antireflection layer 3 has a thickness of 50-150 nm, and / or the seed layer 4 has a thickness of 300-1200 nm, and / or the doped semiconductor layer 9 located outside the opening 3 has a thickness of 50-250 nm.

[0310] The thickness of the antireflection layer 3 can be set to 50-150nm. On the one hand, it ensures its insulation ability and reduces light reflection. For example, a sufficiently thick antireflection layer 3 can prevent the transport layer 5 from burning through the antireflection layer 3 and causing a short circuit when the transport layer 5 is coated. On the other hand, it ensures that the seed layer 4 has sufficient contact space with the antireflection layer 3 in the lateral direction, thus maintaining the stability of the electrode 10.

[0311] The thickness of the seed layer 4 can be set to 300-1200nm, so that the thickness of the seed layer 4 is greater than the thickness of the anti-reflection layer 3, thereby forming effective overflow at the edge of the opening 3. The thickness of the seed layer 4 is set to less than 1200nm to avoid the overflow part being too thick and causing stress cracks, or affecting the coating stability of the transport layer 5.

[0312] The doped semiconductor layer 9 can be set to 50–250 nm. The doped semiconductor layer 9 outside the aperture 3 is unaffected by the laser etching process and remains at 50–250 nm. The doped semiconductor layer 9 within the aperture 3 is affected by the laser etching process and is thinner than the doped semiconductor layer 9 outside the aperture 3; that is, the thickness of the doped semiconductor layer 9 within the aperture 3 is less than the thickness of the doped semiconductor layer 9 outside the aperture 3. A feasible thickness for the doped semiconductor layer 9 is 50–250 nm. This prevents excessive etching of the silicon substrate 1, avoiding the formation of deep trench defects, while a sufficiently thick doped semiconductor layer 9 can provide sufficient charge to meet the photoelectric conversion requirements of the solar cell.

[0313] Optionally, the antireflection layer 3 is silicon nitride; the seed layer 4 is prepared from a material including nickel and zinc; and the transport layer 5 is prepared from a material including a silver-coated copper paste, a copper paste, and a nickel paste.

[0314] The antireflection layer 3 can be silicon nitride (SiNx), which can be formed on the surface of the doped semiconductor layer 9 using plasma-enhanced chemical vapor deposition (PECVD). This process involves reacting silane and ammonia under plasma-enhanced reaction conditions. In addition to its insulating and antireflection properties, silicon nitride also possesses a certain amount of positive charge, which can form field passivation, thereby improving the photoelectric conversion efficiency of the solar cell.

[0315] The seed layer 4 can be prepared using either nickel or zinc, preferably nickel metal. This method has a lower process cost. The seed layer 4 can be prepared by chemical precipitation using a redox reaction. For example, nickel metal in a compound can be reduced and deposited using a phosphorus-containing reducing agent. During this process, the phosphorus content in the seed layer 4 should be controlled to ensure that the phosphorus content is within the range of 2-8 wt%. If the phosphorus content is higher than this range, it may reduce the contact performance between the seed layer 4 and the doped semiconductor layer 9, thereby affecting the electrical performance of the solar cell. If the phosphorus content is lower than this range, the amount of reducing agent participating in the reaction is too low, the triggering conditions for the redox reaction are harsh and the reaction is slow, reducing the preparation efficiency of the seed layer 4.

[0316] The transport layer 5 can be any one of silver-coated copper paste, copper paste, and nickel paste. Using silver-coated copper paste, copper paste, or nickel paste offers lower costs compared to silver paste in related technologies, and the processes are also more mature. In the copper paste used to prepare the transport layer, the copper mass fraction exceeds 85%; in the nickel paste used to prepare the transport layer, the nickel mass fraction exceeds 60%; in the silver-coated copper paste used to prepare the transport layer, the silver mass fraction can be 20%-40%, and the copper mass fraction can be 40%-60%. The materials used to prepare the transport layer 5 require lower coating temperatures than silver paste, which can reduce energy consumption during solar cell fabrication.

[0317] The materials used to prepare the transport layer 5 and the seed layer 4 are metals with lower costs than silver. Compared with conventional silver paste screen printing and high-temperature sintering, the above materials not only avoid the price and supply disadvantages of silver paste products, but also save the resource consumption brought about by high-temperature technology, which can effectively reduce the production and preparation costs.

[0318] In this invention, the solar cell includes a silicon substrate, a doped semiconductor layer, an antireflection layer, and an electrode. The electrode includes a seed layer and a transport layer. The seed layer at least covers the opening in the doped semiconductor layer where the antireflection layer is not located, ensuring good ohmic contact between the electrode and the doped semiconductor layer. A transport layer is located on the seed layer to collect current. The height of the edge region of the seed layer is greater than the height of the region away from the edge of the seed layer. When openings are created using a laser, the antireflection layer at the edge of the opening is prone to cracking due to the heat effect of the laser. The antireflection layer near the edge of the opening thins, reducing its blocking effect on the transport layer. Metal ions in the transport layer can easily diffuse into the opening of the doped semiconductor layer, causing undesirable metal recombination and weakening the electrical performance of the solar cell. In this invention, the higher edge region of the seed layer allows it to effectively block the transport layer, preventing the main metal ions of the transport layer from diffusing into the doped semiconductor layer through the opening edge, thus avoiding metal recombination and ensuring the electrical performance of the solar cell.

[0319] Referring to FIG38, the present invention provides a photovoltaic module in a second aspect, the photovoltaic module including a cover plate, a back sheet, and a battery string disposed between the cover plate and the back sheet, the battery string including a plurality of solar cells connected in series by interconnecting members; the solar cells including the solar cells as described in any one of the claims of the first aspect above.

[0320] This photovoltaic module has the same or similar beneficial effects as the aforementioned solar cells, and will not be described in detail here.

[0321] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0322] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0323] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A solar cell, comprising: The battery body includes a first surface and a second surface that are disposed opposite to each other; A passivation layer is provided at least on the first surface, and the passivation layer has a plurality of openings that penetrate its thickness; The seed layer includes a portion disposed corresponding to the opening and an overflow portion extending from the opening to the passivation layer on the side away from the battery body. The ratio of the width of the overflow portion along the first direction to the thickness of the overflow portion along the thickness direction of the battery body is 0.5 to 10; the first direction is parallel to the first surface.

2. The solar cell according to claim 1, wherein, The ratio of the width of the overflow portion along the first direction to the thickness of the overflow portion along the thickness direction of the battery body is 0.5 to 1.

3. The solar cell according to claim 1, wherein, The ratio of the width of the overflow portion along the first direction to the thickness of the overflow portion along the thickness direction of the battery body is 1 to 10.

4. The solar cell according to any one of claims 1, wherein, Along the direction from the center of the opening to the edge, the edge thickness of the overflow gradually decreases.

5. The solar cell according to claim 1, wherein, The seed layer fills the opening and protrudes from the opening.

6. The solar cell according to claim 1, wherein, Along the length or width direction of the battery body, the width of the overflow portion on the first side of the opening is greater than the width of the overflow portion on the second side.

7. The solar cell according to claim 1, wherein, Along the thickness direction of the battery body, the thickness of the overflow portion is 60 nm to 1200 nm; and / or, Along the first direction, the width of the overflow portion is 60nm to 1200nm.

8. The solar cell according to claim 1, wherein, Along the first direction, the ratio of the width of the overflow portion to the maximum width of the seed layer projected onto the first surface is 0.05-0.

2.

9. The solar cell according to claim 1, wherein, Along the thickness direction of the battery body, the ratio of the thickness of the overflow portion to the thickness of the seed layer corresponding to the opening is 50%-96%.

10. The solar cell according to any one of claims 1-9, wherein, The battery body includes a silicon substrate, a first doped semiconductor layer, and a second doped semiconductor layer. The first doped semiconductor layer is disposed on a first surface of the silicon substrate, and the second doped semiconductor layer is disposed on either the first or second surface of the silicon substrate. The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. The passivation layer covers the side of the first doped semiconductor layer and the second doped semiconductor layer away from the silicon substrate. The passivation layer has a first opening corresponding to the first doped semiconductor layer and a second opening corresponding to the second doped semiconductor layer. Along the first direction, the equivalent width of the first opening is different from the equivalent width of the second opening. The number of the first openings is multiple and they are arranged along the second direction; the number of the second openings is multiple and they are arranged along the second direction. Wherein, the equivalent width is the ratio of the area of ​​the first opening to the distance between two adjacent first openings, or the ratio of the area of ​​the second opening to the distance between two adjacent second openings.

11. The solar cell according to claim 10, wherein, The second doped semiconductor layer is a P-type doped semiconductor layer; Along the first direction, the equivalent width of the first opening is smaller than the equivalent width of the second opening.

12. The solar cell according to any one of claims 1-9, wherein, The battery body includes a silicon substrate, a first doped semiconductor layer, and a second doped semiconductor layer. The first doped semiconductor layer is disposed on a first surface of the silicon substrate, and the second doped semiconductor layer is disposed on either the first or second surface of the silicon substrate. The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. The passivation layer covers the side of the first doped semiconductor layer and the second doped semiconductor layer away from the silicon substrate, and the passivation layer has a first opening corresponding to the first doped semiconductor layer and a second opening corresponding to the second doped semiconductor layer; The total area of ​​the first opening is different from the total area of ​​the second opening.

13. The solar cell according to claim 1, wherein, The battery body includes a silicon substrate, a first doped semiconductor layer, and a second doped semiconductor layer. The first doped semiconductor layer is disposed on a first surface of the silicon substrate, and the second doped semiconductor layer is disposed on either the first or second surface of the silicon substrate. The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. The passivation layer covers the side of the first doped semiconductor layer and the second doped semiconductor layer away from the silicon substrate, and the passivation layer has a first opening corresponding to the first doped semiconductor layer and a second opening corresponding to the second doped semiconductor layer; The seed layer includes a first seed layer and a second seed layer. The first seed layer includes a portion disposed at the first opening and a first overflow portion extending from the first opening to the side of the passivation layer away from the battery body. The second seed layer includes a portion disposed at the second opening and a second overflow portion extending from the second opening to the side of the passivation layer away from the battery body. Along the first direction, the width of the first overflow portion and the width of the second overflow portion are different.

14. The solar cell according to any one of claims 1-9, wherein, The solar cell further includes an electrode disposed on the side of the seed layer away from the cell body, the electrode covering at least a portion of the surface of the seed layer away from the cell body.

15. The solar cell according to claim 14, wherein, The electrode covers the surface and sides of the seed layer away from the battery body; and / or, the width of the electrode is 40 μm to 200 μm.

16. A solar cell, wherein, include: A silicon substrate, the silicon substrate including opposing first and second surfaces, the first surface having a first doped semiconductor layer; An antireflection layer covers at least the side of the first doped semiconductor layer that is away from the silicon substrate; A first seed layer is electrically connected to the first doped semiconductor layer through the antireflection layer. The first seed layer includes a plurality of first metal particles and a plurality of second metal particles deposited on at least a portion of the surface of the first metal particles. The particle size of the first metal particles is a, and the particle size of the second metal particles is b, where ab ≥ 40 nm and / or a ≥ 1.5 b. Multiple first transport layers extend along a first direction and are spaced apart along a second direction, with at least a portion of each first transport layer disposed on the side of the first seed layer away from the silicon substrate.

17. The solar cell according to claim 16, wherein, 100nm ≥ a ≥ 1000nm; and / or, 10nm ≥ b ≥ 60nm; and / or, ab ≤ 990nm; and / or, a ≤ 100b.

18. The solar cell according to claim 16, wherein, The antireflection layer has a plurality of first openings exposing the first doped semiconductor layer; The first seed layer includes a portion disposed corresponding to the first opening, and a second overflow portion located on the side of the passivation layer away from the silicon substrate.

19. The solar cell according to claim 18, wherein, The second overflow portions around at least two adjacent first openings are at least partially connected.

20. The solar cell according to claim 18, wherein, The second overflow portion is dispersed around the first opening.

21. The solar cell according to claim 18, wherein, The first doped semiconductor layer is an N-type doped semiconductor layer, and the width of the first opening is 3 μm to 20 μm; or, the first doped semiconductor layer is a P-type doped semiconductor layer, and the width of the first opening is 5 μm to 30 μm; and / or, The particle size of the first metal particle in the first seed layer is a1, and the particle size of the second metal particle in the first seed layer is b1; the particle size of the first metal particle in the second seed layer is a2, and the particle size of the second metal particle in the first seed layer is b2. a1≥a2; and / or, b1≥b2; and / or, the number of first metal particles contained in the first seed layer is greater than the number of first metal particles contained in the second seed layer; and / or, the number of second metal particles contained in the first seed layer is greater than the number of second metal particles contained in the second seed layer.

22. A solar cell, wherein, The solar cell includes: Silicon substrate, doped semiconductor layer, antireflection layer, and electrodes; The electrode includes a seed layer and a transport layer; The doped semiconductor layer is disposed on at least one surface of the silicon substrate; at least a portion of the doped semiconductor layer on the side opposite to the silicon substrate is provided with the anti-reflection layer; the surface of the doped semiconductor layer includes openings where the anti-reflection layer is not disposed. The seed layer is disposed on the side of the doped semiconductor layer opposite to the silicon substrate, and the seed layer at least covers the opening; the transport layer is disposed on the side of the seed layer opposite to the doped semiconductor layer. The height of the edge region of the seed layer is greater than the height of the seed layer that is away from the edge region.

23. The solar cell according to claim 22, wherein, The height difference between the position at the edge region of the seed layer and the position in the seed layer away from the edge region is 20-300 nm.

24. The solar cell according to claim 22, characterized in that... in, The doped semiconductor layer includes a first doped semiconductor layer and a second doped semiconductor layer; The first doped semiconductor layer is an N-type semiconductor layer, and the second doped semiconductor layer is a P-type semiconductor layer; The seed layer of the opening on the surface of the first doped semiconductor layer is the first seed layer, and the seed layer of the opening on the surface of the second doped semiconductor layer is the second seed layer. From the position in the edge region to the position away from the edge region, the rate of change of the height of the first seed layer is less than the rate of change of the height of the second seed layer. Alternatively, the height difference between the position of the first seed layer in the edge region and the position away from the edge region is less than the height difference between the position of the second seed layer in the edge region and the position away from the edge region.

25. The solar cell according to claim 22, wherein, The surface of the doped semiconductor layer located in the opening has a first protrusion structure; For the seed layer located in the opening, the height of the seed layer is positively correlated with the density of the first protrusion structure on the surface of the doped semiconductor layer.

26. The solar cell according to any one of claims 22-25, wherein, On the side of the seed layer near the transport layer, there are multiple second protrusion structures.

27. The solar cell according to claim 26, wherein, The number of second protrusions on the side of the first seed layer closest to the transport layer is greater than the number of second protrusions on the side of the second seed layer closest to the transport layer.

28. The solar cell of claim 26, wherein, along the thickness direction of the solar cell, the projection of the second protrusion structure in the opening coincides with at least a portion of the first protrusion structure.

29. The solar cell according to claim 22, wherein, The height of the seed layer is greater than the height of the antireflection layer, and the seed layer extends beyond the opening to cover part of the antireflection layer.

30. The solar cell according to claim 29, wherein, In the seed layer, the thickness located in the opening and close to the edge of the opening is the first thickness D1, the thickness extending outward from the opening in the seed layer is the second thickness D2, and the thickness of the anti-reflection layer is the third thickness D3. Therefore, D1≥D2+D3.

31. The solar cell according to claim 30, wherein, The first thickness D1 and the second thickness D2 satisfy: D1:D2=4:(1~3).

32. The solar cell according to claim 31, wherein, In the seed layer, the thickness extending outward from the opening is the second thickness D2, and the width extending outward from the opening is the first width W1, then: D2:W1 = 0.25:(1~3).

33. The solar cell according to claim 32, wherein, In the seed layer, the width of the portion located in the opening along the extension direction perpendicular to the electrode is the second width W2. Then, along the extension direction perpendicular to the electrode, we have: W1:W2 = 1:(25~900).

34. A photovoltaic module, wherein, The photovoltaic module includes a cover plate, a back sheet, and a battery string disposed between the cover plate and the back sheet, the battery string including a plurality of solar cells connected in series by interconnecting elements; the solar cells include the solar cells as described in any one of claims 23 to 34; The solar cell includes a silicon substrate, the silicon substrate including a first surface and a second surface disposed opposite to each other; A passivation layer is provided on the first surface at least, and the passivation layer has a plurality of openings that penetrate its thickness; A seed layer, the seed layer including a portion disposed corresponding to the opening, and an overflow portion extending from the opening to the side of the passivation layer away from the silicon substrate; The ratio of the width of the overflow portion along the first direction to the thickness of the overflow portion along the thickness direction of the silicon substrate is 0.5 to 10; the first direction is parallel to the first surface.

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