Detection device

Abstract

This detection device comprises a photoelectric conversion element electrically connected to a first node, and a first transistor electrically connected between the first node and a second node and controlled in terms of switching by a first control signal line. The photoelectric conversion element includes a second p-type semiconductor layer and a first semiconductor layer that comes into contact with the second p-type semiconductor layer. The first transistor includes a second semiconductor layer electrically connected between the first node and the second node, and a gate electrode electrically connected to the first control signal line. The second semiconductor layer includes a first portion electrically connected to the second node, a second portion overlapping the gate electrode, and a fourth portion electrically connected to the second portion and directly connected to the first semiconductor layer. The impurity concentration of the fourth portion is lower than the impurity concentration of the first portion.

Description

Detection device

[0001] One embodiment of the present invention relates to a detection device.

[0002] In recent years, detection devices for non-destructive inspection of objects have become widespread. Examples of such detection devices include imaging devices, X-ray detectors, and fingerprint detectors used in fields such as medical technology and transportation technology.

[0003] Conventionally, various imaging or detection devices have been proposed that incorporate a photoelectric conversion element (e.g., a photodiode) in each pixel. For example, Patent Document 1 discloses an imaging device having a sensor substrate that includes a photoelectric conversion element capable of improving the image quality of captured images. The imaging device disclosed in Patent Document 1 includes a photoelectric conversion element and a driving element for the photoelectric conversion element, and the photoelectric conversion element is electrically connected to the drain electrode of the driving element, which includes a conductive material. Also, for example, Patent Document 2 discloses a detection device capable of improving detection accuracy. The detection device disclosed in Patent Document 2 includes a photoelectric conversion element (PIN photodiode) and a driving element for the photoelectric conversion element, and the upper conductive layer of the photoelectric conversion element is electrically connected to the driving element. On the other hand, conventionally, in detection devices, suppressing noise has been a challenge when seeking to improve image quality and detection accuracy.

[0004] Japanese Patent Publication No. 2013-165109 Japanese Patent Publication No. 2023-028605

[0005] This invention has been made in view of the above problems, and one of the objectives of this invention is to provide a detection device capable of suppressing noise.

[0006] A detection device according to one embodiment of the present invention includes a photoelectric conversion element electrically connected to a first node and capable of receiving light, and a first transistor electrically connected between the first node and a second node and whose switching is controlled by a first control signal line, wherein the photoelectric conversion element includes a second p-type semiconductor layer and a first semiconductor layer in contact with the second p-type semiconductor layer, the first transistor includes a second semiconductor layer electrically connected between the first node and the second node and a gate electrode electrically connected to the first control signal line, the second semiconductor layer includes a first portion electrically connected to the second node, a second portion superimposed on the gate electrode, and a fourth portion electrically connected to the second portion and directly connected to the first semiconductor layer, wherein the impurity concentration of the fourth portion is smaller than the impurity concentration of the first portion.

[0007] This is a plan view showing the configuration of a detection device according to the first embodiment of the present invention. This is a plan view showing the configuration of a detection device according to the first embodiment of the present invention. This is a circuit diagram showing a pixel circuit according to the first embodiment of the present invention. This is an end view showing an example of a partial end face structure of a pixel according to the first embodiment of the present invention. This is a timing chart showing an example of a pixel driving method according to the first embodiment of the present invention. This is a plan view showing a partial layout of a pixel an end view showing an example of a partial end face structure of a pixel according to a modified example of the present invention.

[0008] The embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different ways, and is not limited to the embodiments described below. In addition, the drawings may schematically represent the width, thickness, shape, and configuration of each part compared to the actual embodiments in order to make the explanation clearer, but these are merely examples and do not limit the interpretation of the present invention. The letters "First," "Second," etc., attached to each element are convenient indicators used to distinguish each element and have no further meaning unless specifically explained.

[0009] Furthermore, in the specification of this application, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C unless otherwise explicitly stated. Moreover, these expressions do not exclude cases where α includes other elements.

[0010] In the specification of this application, the first direction D1 intersects the second direction D2, and the third direction D3 intersects the first direction D1 and the second direction D2 (the D1D2 plane). For example, the first direction D1, the second direction D2, and the third direction D3 correspond to the X direction, the Y direction, and the Z direction. The first direction D1 may be perpendicular to the second direction D2, the first direction D1 may be perpendicular to the third direction D3, and the second direction D2 may be perpendicular to the third direction D3.

[0011] In the specification of this application, when the terms parallel, orthogonal, identical, and coincident are used, these terms may include errors within the scope of design.

[0012] For example, a detection device according to one embodiment of the present invention includes a device for detecting biological information such as fingerprints, a device for detecting X-rays, or a solid-state imaging device. For example, a solid-state imaging device is a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a CCD (Charge Coupled Device) image sensor, or the like.

[0013] One example of an embodiment of the present invention described below is a solid-state imaging device. The imaging data described later may also be referred to as detection data.

[0014] [1. First Embodiment] [1-1. Overview of Solid State Imaging Device 100] An overview of the solid state imaging device 100 will be described with reference to Figures 1 to 4. Figures 1 and 2 are plan views showing the configuration of the solid state imaging device 100 including a plurality of pixels 502. Figure 3 is a circuit diagram showing the pixel circuit 60. Figure 4 is an end view showing an example of a part of the end face structure of the pixel 502.

[0015] As will be described in detail later, as shown in Figures 1 and 2, the solid-state imaging device 100 includes a plurality of pixels 502, each of which includes a photoelectric conversion element 110, a plurality of transistors (e.g., a data transfer transistor T1, a reset transistor T2, a drive transistor T3, and a selection transistor T4), and capacitive elements (e.g., capacitive elements SC1 and SC2).

[0016] Furthermore, as will be described in more detail later, for example, as shown in Figure 3, each of the pixel circuits 60 includes a photoelectric conversion element 110 electrically connected to node N1 (first node) and capable of receiving light, a data transfer transistor (first transistor) T1 electrically connected between node N1 and node N2 (second node) and whose switching is controlled by a data transfer signal TX(n) supplied to a data transfer signal line (first control signal line) 412, and a capacitive element SC2 electrically connected to node N2. Furthermore, as will be described in more detail later, the data transfer transistor T1 has the function of conducting between node N1 and node N2 and supplying a potential based on the photovoltaic power generated by the light received by the photoelectric conversion element 110 when the pixel 502 is exposed, from node N1 to node N2.

[0017] For example, in order for the photoelectric conversion element 110 to efficiently transfer the potential based on the photovoltaic power from node N1 to node N2 as a result of exposure of pixel 502, it is important to suppress noise that is superimposed on the photovoltaic power (for example, kTC noise pd (reset noise)) and noise during potential transfer from node N1 to node N2 (kTC noise fd).

[0018] As shown in Figure 3 or Figure 4, the photoelectric conversion element 110 includes a second p-type semiconductor layer 144 and a semiconductor layer (first semiconductor layer) 143 in contact with the second p-type semiconductor layer 144. The photoelectric conversion element 110 may also include a conductive layer 145. The photoelectric conversion element 110 may also include a first p-type semiconductor layer 140, the first p-type semiconductor layer 140 may be in contact with the semiconductor layer (first semiconductor layer) 143, and the semiconductor layer (first semiconductor layer) 143 may be sandwiched between the first p-type semiconductor layer 140 and the second p-type semiconductor layer 144. For example, the photoelectric conversion element 110 is a photodiode, and the semiconductor layer 143 is a so-called intrinsic semiconductor layer (i-layer).

[0019] Furthermore, as shown in Figure 3 or Figure 4, the data transfer transistor T1 includes an oxide semiconductor layer (first oxide semiconductor layer) 122B electrically connected between node N1 and node N2, and a gate electrode 127B. The oxide semiconductor layer 122B includes a first portion 113 electrically connected to node N2, a second portion 111 superimposed on the gate electrode 127B, a third portion 112 electrically connected between the first portion 113 and the second portion 111, and a fourth portion 114 electrically connected to the second portion 111 and directly connected to the semiconductor layer 143. The gate electrode 127B is a gate electrode 612 (see Figure 3) electrically connected to a data transfer signal line 412 (see Figure 3).

[0020] For example, the first portion 113 contains impurities and functions as a conductive layer and drain region (drain electrode), and functions as the second electrode 616 of the data transfer transistor T1. The first portion 113 may also be the second electrode 616.

[0021] For example, the second portion 111 superimposed on the gate electrode 612 includes an intrinsic semiconductor and functions as a semiconductor layer (channel) of the data transfer transistor T1. The second portion 111 is switched between a conductive state and a non-conductive state depending on the potential supplied to the gate electrode 127B.

[0022] For example, the third portion 112 functions as an LDD (Light Doped Drain) region containing a smaller amount of impurities than the first portion 113. That is, the concentration of impurities in the third portion 112 (impurity concentration) is smaller than the concentration of impurities in the first portion 113.

[0023] For example, the fourth portion 114 functions as an LDD region containing a smaller amount of impurities than the first portion 113, and also functions as a source region (source electrode) and as the first electrode 614 of the data transfer transistor T1. The fourth portion 114 may also be the first electrode 614. The concentration of impurities in the fourth portion 114 (impurity concentration) may be smaller than the concentration of impurities in the first portion 113, and may be a concentration that is very close to an intrinsic semiconductor and contains almost no impurities, or it may be the same as the concentration of impurities in the third portion 112. Furthermore, since the fourth portion 114 is directly connected to the semiconductor layer 143, it may function as an n-type semiconductor layer of the photoelectric conversion element 110, it may function as the cathode electrode of the photoelectric conversion element 110, or it may be the cathode electrode of the photoelectric conversion element 110.

[0024] For example, when a data transfer signal TX(n) with a high (H) level potential is supplied to the gate electrode 127B (gate electrode 612) and the data transfer transistor T1 turns on, the first portion 113, the third portion 112, the second portion 111, and the fourth portion 114 become conductive, and a potential corresponding to the photovoltaic power generated based on the light received by the photoelectric conversion element 110 is supplied from node N1 to node N2. That is, the potential supplied to nodes N1 and N2 changes according to the photovoltaic power. At this time, the fourth portion 114, which is very close to an intrinsic semiconductor and contains almost no impurities, is directly connected to the semiconductor layer 143 without passing through an impurity region or conductive layer like the first portion, so the fourth portion 114 and its surroundings are depleted to a state close to complete depletion.

[0025] For example, in the conventional detection circuit, the fourth portion 114 is electrically connected to the semiconductor layer 143 via an impurity region or conductive layer like the first portion, so the fourth portion 114 and its surroundings never become completely depleted or nearly completely depleted. As a result, in the conventional detection circuit, the photovoltaic power generated by the photoelectric conversion element 110 includes the potential due to kTC noise pd, so when the data transfer transistor T1 is turned on, the potential supplied to the cathode electrode electrically connected to node N1 and node N2 includes the potential due to kTC noise pd. Therefore, the conventional detection circuit cannot suppress noise.

[0026] On the other hand, when the data transfer transistor T1 in the solid-state imaging device 100 is turned on, the fourth portion 114 and its surroundings are depleted to a state close to complete depletion. Therefore, the potential supplied to the fourth portion 114 and its surroundings (including the cathode electrode) electrically connected to node N1 and to node N2 is a potential in which the potential due to kTC noise pd is suppressed. Thus, the solid-state imaging device 100 can suppress the effects of kTC noise pd.

[0027] Furthermore, as will be described in detail later, as shown in Figure 2, the solid-state imaging device 100 includes a readout circuit 600 electrically connected to the output signal lines (OUT(1) to OUT(m)). The readout circuit 600 includes at least a correlated double sampling (CDS) circuit 610. By including the CDS circuit 610, the solid-state imaging device 100 can sample a first output potential output to the output signal line in accordance with the reset potential VRES (see Figure 3), and a second output potential output to the output signal line in accordance with the photovoltaic power generated based on the light received by the photoelectric conversion element 110, and calculate the potential difference between the first output potential and the second output potential. At this time, the kTC noise fd due to the potential supplied from node N1 to node N2 is canceled out by calculating the potential difference between the first output potential and the second output potential. In other words, the solid-state imaging device 100 can suppress the effects of kTC noise fd.

[0028] As a result, the solid-state imaging device 100 can suppress the effects of both kTC noise pd and fd, which were difficult to achieve with conventional detection circuits, and can generate imaging data with high color reproducibility of the subject with the effects of noise suppressed. Furthermore, because the solid-state imaging device 100 can suppress the effects of noise, it can suppress the degradation of pixels 502 (pixel circuits 60) due to noise, and the long-term reliability of the solid-state imaging device 100 is improved compared to conventional detection circuits.

[0029] [1-2. Configuration of the Solid-State Imaging Device 100] The configuration of the solid-state imaging device 100 will be described in detail with reference to Figures 1 to 3.

[0030] As shown in Figure 1 or Figure 2, the solid-state imaging device 100 includes a power supply circuit 200, a drive timing control circuit 300, a row selection circuit 400, a pixel unit 504, a readout circuit 600, and a signal processing circuit 700. The pixel unit 504 includes a plurality of pixels 502.

[0031] Multiple pixels 502 are arranged in a matrix in a first direction D1 (row direction) and a second direction D2 (column direction) intersecting the first direction D1. As described in "1-1. Overview of the Solid State Imaging Device 100", each of the multiple pixels 502 includes a pixel circuit 60, which includes multiple transistors, multiple capacitive elements and a light-receiving element, and the light-receiving element is a photoelectric conversion element 110 that generates photovoltaic power. For example, the photoelectric conversion element 110 is a photodiode. The pixels 502 can image a subject using the pixel circuit 60.

[0032] The power supply circuit 200 is electrically connected to the drive timing control circuit 300, the signal processing circuit 700, the readout circuit 600, and the row selection circuit 400. For example, the power supply circuit 200 includes a logic circuit (not shown) and a potential generation circuit (not shown). The power supply circuit 200 uses the logic circuit and the potential generation circuit to generate a signal or power supply potential, and supplies the generated signal, power supply potential, or power to the drive timing control circuit 300, the signal processing circuit 700, the readout circuit 600, and the row selection circuit 400. For example, the generated signal, power supply potential, or power is a reference potential VSS, a drive potential VPP, and a reset potential VRES.

[0033] The drive timing control circuit 300 is electrically connected to the signal processing circuit 700, the readout circuit 600, and the row selection circuit 400. For example, the drive timing control circuit 300 generates timing signals required for signal processing of each circuit and supplies the generated timing signals to each circuit. For example, the timing control signals are a clock signal and a start pulse that control the row selection of the row selection circuit 400 and the like.

[0034] For example, the row selection circuit 400 is arranged at a position adjacent to the pixel section 504 in the first direction D1. For example, the row selection circuit 400 is connected to a data transfer signal line 412 (see FIG. 3), a reset signal line 414 (see FIG. 3), and a readout signal line 410 (see FIG. 3). The data transfer signal line 412, the reset signal line 414, and the readout signal line 410 are connected to a plurality of pixels 502 arranged in the same row. The row selection circuit 400 generates a data transfer signal TX(n), a reset signal RS(n), a readout signal RD(n), etc. using the timing signal from the drive timing control circuit 300 and the power supply potential received from the power supply circuit 200 and the like. The data transfer signal TX(n) is supplied to the data transfer signal line 412, the reset signal RS(n) is supplied to the reset signal line 414, and the readout signal RD(n) is supplied to the readout signal line 410.

[0035] The readout circuit 600 is connected to the signal processing circuit 700. For example, the readout circuit 600 is arranged at a position adjacent to the pixel section 504 in the second direction D2. A plurality of output signal lines 420 (see FIG. 3) are connected to the readout circuit 600. The output signal lines 420 are connected to a plurality of pixels 502 arranged in the same column.

[0036] For example, the readout circuit 600 includes a CDS circuit 610, an analog-to-digital (AD) conversion circuit 620, and a horizontal transfer scanning circuit (not shown). As will be described in detail later, the output signal OUT(m) (see Figure 3) is a signal whose potential changes over time and is supplied to the output signal line 420 and also to the CDS circuit 610. As explained in "1-1. Overview of the Solid State Imaging Device 100", the CDS circuit 610 samples a first output signal (including the first output potential) output to the output signal line 420 in accordance with the reset potential VRES (see Figure 3), and a second output signal (including the second output potential) output to the output signal line 420 in accordance with the photovoltaic power generated based on the light received by the photoelectric conversion element 110, calculates the potential difference between the first output potential and the second output potential, and suppresses kTC noise fd. The AD conversion circuit 620 can receive the potential difference between a first output potential and a second output potential, which are analog potentials, and convert it into a digital signal. Furthermore, for example, the horizontal transfer scanning circuit holds the output signal OUT(m) corresponding to each of the multiple pixels 502 connected to the row selected using the row selection circuit 400 as a digital signal, and reads out the held digital signals column by column. In other words, the readout circuit 600 can receive the output signal OUT(m), which is an analog signal, as input and output a digital signal.

[0037] The signal processing circuit 700 includes an image processing circuit (not shown). For example, the image processing circuit performs image processing such as gamma correction and noise reduction on a plurality of digital signals output from the readout circuit 600 to generate image data. For example, the image data is imaging data of the subject being photographed. Although not shown, the signal processing circuit 700 and the image processing circuit each include an arithmetic processing circuit and a memory circuit. For example, the arithmetic processing circuit in one embodiment of the present invention is a processor, CPU, etc., and the memory circuit in one embodiment of the present invention is a volatile memory, non-volatile memory.

[0038] For example, the drive timing control circuit 300, row selection circuit 400, readout circuit 600, and signal processing circuit 700 in the solid-state imaging device 100 may each be referred to as a control circuit, or two or more circuits may be collectively referred to as a control circuit.

[0039] As shown in FIG. 2, the row selection circuit 400 commonly supplies a reset signal RS(n), a readout signal RD(n), and a data transfer signal TX(n) to each of the plurality of pixels 502 (pixel circuits 60) located in the n-th row within the pixel section 504. The power supply circuit 200 supplies a reference potential VSS, a drive potential VPP, and a reset potential VRES to each of the pixel circuits 60 of the plurality of pixels 502 located in the m-th column within the pixel section 504. For example, the plurality of pixels 502 are arranged in m in the first direction D1 and n in the second direction D2. The numerical values m and n are each natural numbers. For example, the pixels 502 arranged in 3 rows and 5 columns are referred to as pixels 502 of 3 rows and 5 columns or pixels 502 at coordinates (3, 5).

[0040] Each of the plurality of pixels 502 may include a plurality of sub-pixels. For example, one pixel 502 has three sub-pixels, and each of the three sub-pixels may include a pixel circuit 60. The three sub-pixels may include color filters that exhibit different colors. For example, among the three pixels, the first sub-pixel may include a color filter that exhibits red, the second sub-pixel may include a color filter that exhibits green, and the third sub-pixel may include a color filter that exhibits blue. Also, for example, one pixel 502 may include sub-pixels that include color filters that exhibit four or more different colors. For example, the solid-state imaging device 100 can generate imaging data with high color reproducibility of the subject by including pixels or sub-pixels that include color filters that exhibit four or more different colors.

[0041] Also, for example, the arrangement of the plurality of pixels 502 in the solid-state imaging device 100 is a stripe arrangement. Note that there is no limitation on the configuration of the plurality of pixels 502, and it can be appropriately selected based on the application or specifications of the solid-state imaging device 100.

[0042] Furthermore, the signals, potentials, and powers that form the basis of each signal, potential, and power may be supplied from an external circuit (not shown) to the power supply circuit 200, the drive timing control circuit 300, and the signal processing circuit 700. Based on the supplied signals, potentials, and powers, the power supply circuit 200, the drive timing control circuit 300, and the signal processing circuit 700 may generate and supply the desired signals, desired potentials, and desired powers corresponding to the row selection circuit 400, the pixel unit 504, and the readout circuit 600.

[0043] [1-3. Circuit Configuration of Pixel 502] Referring to Figure 3, the pixel circuit 60 included in the pixel 502 will be described in detail. Each of the multiple pixels 502 has multiple transistors, a capacitive element, and a photoelectric conversion element that constitute the pixel circuit 60. Figure 3 shows the components that constitute the pixel circuit 60 of the n x m pixel 502 shown in Figure 2. The configuration of the pixel circuit 60 shown in Figure 3 is an example, and the configuration of the pixel circuit 60 is not limited to the configuration shown in Figure 3. Configurations identical or similar to those in Figures 1 and 2 will be described as necessary.

[0044] As shown in Figure 3, the pixel circuit 60 includes a data transfer transistor T1 (first transistor), a reset transistor T2 (second transistor), a drive transistor T3 (third transistor), a selection transistor T4 (fourth transistor), a photoelectric conversion element 110, a capacitive element SC1, and a capacitive element SC2. Each transistor includes a gate electrode and a pair of electrodes consisting of a source electrode and a drain electrode (a pair of electrodes consisting of a first electrode and a second electrode). Each capacitive element includes a pair of electrodes (a first electrode and a second electrode). Note that the function of each electrode as a source and drain may be reversed depending on the potential applied (supplied) to the source electrode and the drain electrode.

[0045] As a power source for driving the pixel 502, the drive potential VPP is supplied to the drive potential line PVDD, and the reference potential VSS is supplied to the reference potential line PVSS. In addition, the reset potential VRES is supplied to the reset potential line SVR. The reset potential VRES is a constant potential that can reset or initialize the pixel 502, and is supplied to node N2 by controlling the reset transistor T2. The reset potential VRES may be a constant potential or a variable potential depending on time. For example, the reset potential VRES of the solid-state imaging device 100 is a constant potential.

[0046] The data transfer transistor T1 has the function of supplying a potential based on the photovoltaic power generated by the light received by the photoelectric conversion element 110 due to the exposure of the pixel 502, by conducting node N1 to node N2. In other words, the data transfer transistor T1 has the function of transferring the potential generated by the photoelectric conversion element 110 from node N1 to node N2. The data transfer transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the data transfer signal line 412. The first electrode 614 is electrically connected to node N1, the second electrode 24 of the capacitive element SC1, and the second electrode 14 of the photoelectric conversion element 110. The second electrode 616 is electrically connected to node N2, the first electrode 624 of the reset transistor T2, the gate electrode 632 of the drive transistor T3, and the second electrode 34 of the capacitive element CS2. A data transfer signal TX(n) is supplied to the data transfer signal line 412. The switching of the data transfer transistor T1 is controlled using the data transfer signal TX(n). In other words, the data transfer transistor T1 is controlled to be either conducting (on) or not conducting (off) by the data transfer signal TX(n). When the signal supplied to the data transfer signal TX(n) is at a low (L) level, the data transfer transistor T1 is in a non-conducting state. When the signal supplied to the data transfer signal TX(n) is at a high level, the data transfer transistor T1 is in a conducting state. Note that a high level is at a higher potential than a low level.

[0047] The reset transistor T2 has the function of supplying a reset potential VRES to node N2 and putting the pixel 502 into a reset or initialization state. The reset transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the reset signal line 414. The second electrode 626 is electrically connected to the reset potential line SVR. The reset signal RS(n) is supplied to the reset signal line 414. The switching of the reset transistor T2 is controlled using the reset signal RS(n). In other words, the conduction state (on state) and non-conduction state (off state) of the reset transistor T2 are controlled by the reset signal RS(n). When the signal supplied to the reset signal RS(n) is low level, the reset transistor T2 is in a non-conduction state. When the signal supplied to the reset signal RS(n) is high level, the reset transistor T2 is in a conduction state.

[0048] The drive transistor T3 adjusts the potential supplied to node N3 in the reset or initialization state to a potential corresponding to node N2 based on the reset potential VREF supplied to the gate electrode 632. Furthermore, the drive transistor T3 adjusts the potential supplied to node N3 to a potential corresponding to node N2 based on the photovoltaic power generated by the light received by the photoelectric conversion element 110 upon exposure of pixel 502. In one embodiment of the present invention, exposure of pixel 502 may be rephrased as pixel 502 receiving light or exposure of pixel 502, and light receiving by the photoelectric conversion element 110 may be rephrased as exposure of the photoelectric conversion element 110 or exposure of the photoelectric conversion element 110. The drive transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The first electrode 634 is electrically connected to node N3 and the second electrode 646 of the selection transistor T4. The second electrode 636 is electrically connected to the drive potential line PVDD. For example, the threshold voltage of the drive transistor T3 is the threshold voltage VTH. The drive transistor T3 controls the potential supplied to node N3 to be lower than the potential supplied to node N2 by the threshold voltage VTH, according to the potential difference Vgs between the potential supplied to node N2 and the potential supplied to the first electrode 634, and the potential difference Vds between the potential supplied to the second electrode 636 and the potential supplied to the first electrode 634. For example, if the potential difference Vgs is less than the threshold voltage VTH, the second transistor T2 becomes non-conducting. If the potential difference Vgs is greater than or equal to the threshold voltage VTH and the potential difference Vds is greater than 0V, the drive transistor T3 becomes conductive, and the potential supplied to node N3 becomes the potential corresponding to node N2.

[0049] The selection transistor T4 has the function of connecting node N3 to the output signal line 420 and supplying a potential to the output signal line 420 to supply to node N3 in the reset state or initialization state, according to the reset potential VREF (first potential) supplied to the gate electrode 632. The selection transistor T4 also has the function of connecting node N3 to the output signal line 420 and supplying a potential to the output signal line 420 to supply to node N3 according to the potential (second potential) based on the photovoltaic power generated by the light received by the photoelectric conversion element 110 due to exposure of the pixel 502. In other words, the selection transistor T4 has the function of supplying to the output signal line 420 a potential to supply to node N3 based on the reset potential VREF (first potential) and a potential to supply to node N3 based on the potential (second potential) generated by the photoelectric conversion element 110. The selection transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the read signal line 410. The first electrode 644 is electrically connected to the output signal line 420. A read signal RD(n) is supplied to the read signal line 410. The switching of the selection transistor T4 is controlled using the read signal RD(n). In other words, the select transistor T4 is controlled to be in a conduction state (on state) or a non-conduction state (off state) by the read signal RD(n). When the signal supplied to the read signal RD(n) is low level, the selection transistor T4 is in a non-conduction state. When the signal supplied to the read signal RD(n) is high level, the select transistor T4 is in a conduction state.

[0050] Capacitive element SC1 has the function of holding a charge (potential) corresponding to the photovoltaic power generated based on the light received by the photoelectric conversion element 110 supplied to node N1. Capacitive element SC1 is provided between node N1 and the reference potential line PVSS. Capacitive element SC1 includes a first electrode 22 and a second electrode 24. The second electrode 24 is electrically connected to the reference potential line PVSS. The capacitance value of capacitive element SC1 is capacitance value Cdiode.

[0051] The capacitive element SC2 has the function of holding a charge (potential) corresponding to the reset potential VREF supplied to node N2 and the photovoltaic power generated based on the light received by the photoelectric conversion element 110 supplied to node N2. The capacitive element SC2 is provided between node N2 and the drive potential line PVDD. The capacitive element SC2 includes a first electrode 32 and a second electrode 34. The first electrode 32 is electrically connected to the drive potential line PVDD, and the second electrode 34 is electrically connected to node N2. That is, the potential supplied to the first electrode 32 is fixed to the drive potential VPP, and the potential supplied to the second electrode 34 changes according to the potential supplied to node N2. The capacitance value of the capacitive element SC2 is the capacitance value Css. By having the capacitive element SC2, the solid-state imaging device 100 can suppress the discharge of charge corresponding to the drive potential VPP and maintain the reset state or initialization state of the pixel 502. Furthermore, the solid-state imaging device 100, by having a capacitive element SC2, can suppress the discharge of the reset potential VREF and maintain the reset or initialization state of the pixel 502. Also, by having a capacitive element SC2, the solid-state imaging device 100 can suppress the discharge of charge (potential) corresponding to the photovoltaic power and maintain the exposure state of the pixel 502. As a result, the solid-state imaging device 100 can maintain constant potentials in the reset or initialization state and the exposure state, making it a device with excellent long-term reliability.

[0052] The photoelectric conversion element 110 has the function of generating a photovoltaic power from the light received when the pixel 502 is exposed. The photoelectric conversion element 110 also has the function of supplying a potential based on the generated photovoltaic power to node N1 and capacitive element SC1. The photoelectric conversion element 110 includes a first electrode 12 and a second electrode 14.

[0053] In the solid-state imaging device 100, a conductive state is defined as a state in which the source electrode and drain electrode of a transistor are conductive, indicating that the transistor is ON. Conversely, a non-conductive state in the solid-state imaging device 100 is defined as a state in which the source electrode and drain electrode of a transistor are non-conductive, indicating that the transistor is OFF. Note that in each transistor, the source electrode and drain electrode may be swapped depending on the potential supplied to each electrode. Furthermore, it is easily understood by those skilled in the art that even when a transistor is OFF, a small current may flow, such as leakage current.

[0054] [1-4. End Face Structure of Pixel 502] An example of the end face structure of pixel 502 will be described in detail with reference to Figure 3 or Figure 4. Configurations identical or similar to those in Figures 1 to 3 will be described as necessary.

[0055] The substrate 101 includes a first surface 101A and a second surface 101B opposite to the first surface 101A along the third direction D3. Each layer included in the solid-state imaging device 100 (pixel 502) is stacked on top of the substrate 101 (on the first surface 101A side) along the third direction D3.

[0056] For example, a conductive layer 120 (conductive layer 120B) is provided on the first surface 101A. An insulating layer 121 is provided on the top and side surfaces of the conductive layer 120, and on the first surface 101A where the conductive layer 120 is not provided. An oxide semiconductor layer 122 (oxide semiconductor layer 122B) is provided on the insulating layer 121. A gate insulating layer 125 is provided on the top and side surfaces of the oxide semiconductor layer 122, and on the insulating layer 121 where the oxide semiconductor layer 122 is not provided. A conductive layer 127 (gate electrode 127B) is provided on the gate insulating layer 125. An insulating layer 128 is provided on the top and side surfaces of the conductive layer 127, and on the gate insulating layer 125 where the conductive layer 127 is not provided. A conductive layer 132 (conductive layer 132E) is provided on the insulating layer 128. An insulating layer 131 is provided on the upper and side surfaces of the conductive layer 132, and on an insulating layer 128 on which the conductive layer 132 is not provided. An insulating layer 136 is also provided on an insulating layer 131. For example, insulating layers 131 and 128, and the gate insulating layer 125 may be collectively referred to as the first insulating layer, and insulating layer 136 may be referred to as the second insulating layer.

[0057] The opening 135 (opening 135E) penetrates the insulating layer 128 and the gate insulating layer 125, and exposes the surface of the oxide semiconductor layer 122. Although not shown in the figures, the opening 135 may also penetrate the insulating layer 128 and expose the surface of the conductive layer 127. The opening 135 allows the conductive layer 132 to be electrically connected to the oxide semiconductor layer 122 or the conductive layer 127.

[0058] Furthermore, an insulating layer 141 is provided on insulating layer 136, an insulating layer 151 is provided on insulating layer 141, a conductive layer 149 is provided on insulating layer 151, an insulating layer 152 is provided on conductive layer 149, and an insulating layer 153 is provided on insulating layer 152. In addition, the first p-type semiconductor layer 140, semiconductor layer 143, second p-type semiconductor layer 144, and conductive layer 145 are stacked in this order from the side closest to insulating layer 136 along the third direction D3, and are provided between insulating layer 136 and insulating layer 141.

[0059] More specifically, the first p-type semiconductor layer 140 is provided on top of the insulating layer 136. The semiconductor layer 143 is sandwiched between the first p-type semiconductor layer 140 and the second p-type semiconductor layer 144, and the end 160 of the first p-type semiconductor layer 140 is in contact with the end 161 of the second p-type semiconductor layer 144. The insulating layer 141 is provided on top of the insulating layer 136 where the first p-type semiconductor layer 140 is not provided, on the end 160 of the first p-type semiconductor layer 140, on the end 161 of the second p-type semiconductor layer 144, on the upper and side surfaces of the conductive layer 145, and on top of the second p-type semiconductor layer 144 where the conductive layer 145 is not provided.

[0060] Furthermore, the opening 138 (first opening) penetrates the insulating layer 136 and exposes the surface of the insulating layer 131. The opening 137 (second opening) opens the first p-type semiconductor layer 140, the insulating layers 131 and 128, and the gate insulating layer 125, and exposes the oxide semiconductor layer 122.

[0061] In this case, the diameter W2 of the opening 138 is smaller than the diameter W1 of the opening 137. For example, if the openings 138 and 137 are circular, the diameters W2 and W1 may be the diameters of the circles. If the openings 138 and 137 are not circular, the diameters W2 and W1 may be the diameters obtained by converting the circumference of the opening 138 and the circumference of the opening 137 to the circumference.

[0062] Furthermore, at this time, the first p-type semiconductor layer 140 is in contact with the inside of the opening 138 and also in contact with the insulating layer 131 exposed by the opening 138. The inside of the opening 138 includes a portion in which the first p-type semiconductor layer 140, semiconductor layer 143, and second p-type semiconductor layer 144 are stacked in this order along the third direction D3, and a portion in which the semiconductor layer 143 and second p-type semiconductor layer 144 are stacked in this order inside the opening 138 along the third direction D3.

[0063] Furthermore, at this time, the semiconductor layer 143 is in contact with the inside (side wall) of the opening 137 and is in direct contact with the oxide semiconductor layer 122B exposed by the opening 137. In addition, the semiconductor layer 143 provided inside the opening 137 is in contact with the insulating layers 131 and 128 (and their side walls), and the gate insulating layer 125 (and its side wall), while being separated from the insulating layer 136.

[0064] As described in "1-1. Overview of the Solid State Imaging Device 100", the oxide semiconductor layer 122B includes a first portion 113, a second portion 111, a third portion 112 electrically connected between the first portion 113 and the second portion 111, and a fourth portion 114 electrically connected to the second portion 111. The conductive layer 132E is provided between the insulating layer 136 and the oxide semiconductor layer 122B along the third direction D3 and is connected to the first portion 113 of the oxide semiconductor layer 122B via openings 135E provided in the insulating layer 128 and the gate insulating layer 125.

[0065] The data transfer transistor T1 includes an oxide semiconductor layer 122B, a gate insulating layer 125, and a gate electrode 127B. A first portion 113 of the oxide semiconductor layer 122B is exposed by an opening 135E that penetrates the insulating layer 128 and the gate insulating layer 125, and is electrically connected to a conductive layer 132E. As described in "1-1. Overview of Solid State Imaging Device 100", for example, the first portion 113 may function as a second electrode 616 and drain region, and therefore the conductive layer 132E electrically connected to the first portion 113 may function as a second electrode 616 and drain region. Also, as described in "1-1. Overview of Solid State Imaging Device 100", for example, a fourth portion 114 of the oxide semiconductor layer 122B functions as a first electrode 614 and source region. The gate electrode 127B faces the oxide semiconductor layer 122B, and the gate insulating layer 125 is provided between the oxide semiconductor layer 122B and the gate electrode 127B. The oxide semiconductor layer 122B is provided on the first surface 101A side of the gate electrode 127B. In other words, the data transfer transistor T1 is a so-called top-gate transistor. As an example, each transistor constituting the solid-state imaging device 100 is a top-gate transistor, but each transistor constituting the solid-state imaging device 100 is not limited to a top-gate transistor. For example, each transistor constituting the solid-state imaging device 100 may be a bottom-gate transistor in which the gate electrode 127B is provided on the first surface 101A side of the oxide semiconductor layer 122B, and the positional relationship between the oxide semiconductor layer 122B and the gate electrode 127B is the opposite of that of a top-gate transistor.

[0066] Furthermore, the data transfer transistor T1 includes a conductive layer 120B. The conductive layer 120B is provided between the oxide semiconductor layer 122B and the substrate 101. The conductive layer 120B is superimposed on the gate electrode 127B and the oxide semiconductor layer 122B. For example, a constant potential is supplied to the conductive layer 120B to suppress light incident from the substrate 101 side from reaching the oxide semiconductor layer 122B. Alternatively, the conductive layer 120B may be supplied with a potential similar to that of the gate electrode 127B to control the current flowing through the oxide semiconductor layer 122B. In this case, the conductive layer 120B may be connected to the gate electrode 127B in the peripheral region of the pixel circuit 60.

[0067] The photoelectric conversion element 110 includes at least a first p-type semiconductor layer 140, a semiconductor layer 143, a second p-type semiconductor layer 144, and a conductive layer 145. Furthermore, for example, a portion of the fourth portion 114 that is in direct contact with the semiconductor layer 143 may function as an n-type semiconductor layer and a lower electrode of the photoelectric conversion element 110, and the conductive layer 145 may function as an upper electrode of the photoelectric conversion element 110. Thus, the photoelectric conversion element 110 includes at least a portion of the fourth portion 114 that is in direct contact with the semiconductor layer 143, the first p-type semiconductor layer 140, the semiconductor layer 143, the second p-type semiconductor layer 144, and the conductive layer 145, and functions as a light-emitting diode.

[0068] When distinguishing between conductive layers 120, they are represented by numbers and letters, such as conductive layer 120A, 120B, etc. Similarly, the oxide semiconductor layer 122, conductive layer 132, opening 135, opening 138, conductive layer 139, conductive layer 145, conductive layer 148, conductive layer 149, opening 146, and opening 147 are also represented by numbers followed by letters when distinguishing between them, in the same manner as conductive layer 120.

[0069] [1-5. Driving Method of Solid-State Imaging Device 100] An example of a driving method for the solid-state imaging device 100 will be described with reference to Figure 5. More specifically, an example of a driving method for the solid-state imaging device 100 will be described for driving a plurality of pixels 502 electrically connected to the nth row readout signal line 410. Figure 5 is a timing chart showing an example of a driving method for the solid-state imaging device 100. The driving method shown in Figure 5 is an example of a driving method for the solid-state imaging device 100. Configurations that are the same as or similar to those in Figures 1 to 4 will not be explained here.

[0070] [1-5-1. Overview of the driving method of the solid-state imaging device 100] Figure 5 shows the current frame (nth frame, nthFRAME), a portion of the frame immediately preceding the current frame (n-1st frame, n-1stFRAME), and a portion of the frame immediately following the current frame (n+1st frame, n+1stFRAME). As shown in Figure 5, each frame in the driving method of the solid-state imaging device 100 includes at least an exposure period PEX, a reset period PRS, and an imaging data acquisition period PDT. For example, a blank period is included between the reset period PRS and the imaging data acquisition period PDT, and a blank period is included between the current frame and the next frame.

[0071] For example, the row selection circuit 400 selects each pixel from the multiple pixels 502 in the first row to the multiple pixels 502 in the last row, row by row. For each selected row, the light received by each pixel 502 is converted into an analog signal (photovoltaic) by the photoelectric conversion element 110 corresponding to each pixel 502. Each analog signal converted photoelectrically for each row is output to the output signal line 420 corresponding to each pixel 502.

[0072] The CDS circuit 610 included in the readout circuit 600 samples a first output signal (including the first output potential) output to the output signal line 420 according to the reset potential VRES, and a second output signal (including the second output potential) output to the output signal line 420 according to the photovoltaic power generated based on the light received by the photoelectric conversion element 110, and calculates the potential difference between the first output potential and the second output potential. The calculated third output signal including the potential difference is supplied to the AD conversion circuit 620 included in the readout circuit 600, and is converted into a digital signal by the AD conversion circuit 620. Here, the first output signal, the second output signal, and the third output signal are analog signals. For example, the processing of each signal in the readout circuit 600 is performed sequentially for each row, and the readout circuit 600 can receive an analog output signal OUT(m) as input and output a digital signal. The horizontal transfer scanning circuit included in the readout circuit 600 transmits the digital signal converted for each row to the signal processing circuit 700 for each row.

[0073] The signal processing circuit 700 receives the digital signals converted row by row and generates imaging data of the subject using the digital signals converted row by row.

[0074] The driving method shown in Figure 5 described above is repeated from the multiple pixels 502 in the first row to the multiple pixels 502 in the last row, and the digital signals converted for each row are processed by the signal processing circuit 700. That is, the driving method shown in Figure 5 is repeatedly executed for each of the multiple pixels 502, and the digital signals converted for each row are processed by the signal processing circuit 700. As a result, the signal processing circuit 700 can generate imaging data of the subject. The driving method of the solid-state imaging device 100 for each period in the nth frame will be described in detail below.

[0075] [1-5-2. Exposure Period PEX] The exposure period PEX is the period during which the pixel 502 is exposed and the photoelectric conversion element 110 transfers a potential (second potential) based on the photovoltaic power (second potential) to node N1 (second electrode 14, second electrode 24, first electrode 614) as a result of the exposure of the pixel 502.

[0076] Between time t1 and time t2, the reset signal RS(n) and the data transfer signal TX(n) remain at a low level. Therefore, the data transfer transistor T1 and the reset transistor T2 are in a non-conducting state. Although not shown in the diagram, for example, the read signal RD(n) remains at a low level, and the selection transistor T4 is in a non-conducting state.

[0077] As a result, during the exposure period PEX, current flows from node N1 towards the reference potential line PVSS, and the potential supplied to node N1 gradually decreases from the potential VD. Also, since the data transfer transistor T1 and reset transistor T2 are in a non-conducting state, the potential supplied to node N2 (second electrode 34, second electrode 616, gate electrode 632) maintains the reference potential VSS supplied to node N2 after the imaging data acquisition period PDS in the (n-1)th frame. For example, the reference potential VSS supplied to node N2 is held in the retention capacitor SC2.

[0078] At this time, the potential supplied to node N1 gradually decreases from the potential VD, but because the semiconductor layer 143 of the photoelectric conversion element 110 is directly connected to the fourth part 114 of the data transfer transistor T1, the potential supplied to node N1 is a potential in which the kTC noise pd is suppressed.

[0079] [1-5-3. Reset Period PRS] The reset period PRS is a period during which node N2 of pixel 502 is reset, pixel 502 is put into a reset or initialization state, and the first output signal (including the first output potential) output to the output signal line 420 according to the reset potential VRES is sampled (acquired).

[0080] Between time t2 and time t3, the reset signal RS(n) changes from a low level to a high level and maintains that high level, while the data transfer signal TX(n) maintains a low level. Therefore, the reset transistor T2 changes from a non-conductive state to a conductive state and maintains that conductive state, while the data transfer transistor T1 maintains a non-conductive state. Although not shown in the diagram, for example, the readout signal RD(n) changes from a low level to a high level and maintains that high level, and the selection transistor T4 changes from a non-conductive state to a conductive state and maintains that conductive state.

[0081] As a result, during the reset period PRS, current flows from the reset potential line SVR towards node N2, and the potential supplied to node N2 rises from the reference potential VSS to potential VRES. Also, since the data transfer transistor T1 remains in a non-conductive state, the potential supplied to node N1 decreases further from the potential at time t2. For example, the reset potential VRES supplied to node N2 is held in the holding capacitor SC2. Note that, similar to the exposure period PEX, the potential supplied to node N1 during the reset period PRS is a potential with suppressed kTC noise pd.

[0082] Furthermore, since the reset transistor T2 and the selection transistor T4 are in a conductive state, the potential V(t21) of node N2 at time t21 is supplied to the gate electrode 632. As a result, the drive transistor T3 supplies a potential to node N3 according to the potential V(t21), and the selection transistor T4 supplies an output signal OUT(m) to the output signal line 420, which includes a first output potential corresponding to the potential supplied to node N3. For example, the potential V(t21) is the reset potential VREF.

[0083] Furthermore, the CDS circuit 610 samples and holds the output signal OUT(m), which includes the first output potential output to the output signal line 420.

[0084] [1-5-4. Blank period between reset period PRS and imaging data acquisition period PDT] Between time t3 and time t4, the reset signal RS(n) changes from a high level to a low level and maintains the low level, and the data transfer signal TX(n) maintains the low level. Therefore, the reset transistor T2 changes from a conductive state to a non-conductive state and maintains the non-conductive state, and the data transfer transistor T1 maintains the non-conductive state. In addition, although not shown in the diagram, for example, the readout signal RD(n) may maintain a high level and the selection transistor T4 may maintain a conductive state, or the readout signal RD(n) may change from a high level to a low level and maintain the low level, and the selection transistor T4 may change from a conductive state to a non-conductive state and maintain the non-conductive state.

[0085] As a result, during the blank period between the reset period PRS and the imaging data acquisition period PDT, node N2 is in a floating state, and the potential supplied to node N2 drops from the reset potential VRES to a potential VA that is lower than the reset potential VRES. Also, since the data transfer transistor T1 remains in a non-conductive state, the potential supplied to node N1 decreases further from the potential at time t3 to a potential VC. For example, the potential VA supplied to node N2 is held in the holding capacitor SC2. Note that the potential supplied to node N1 is a potential with suppressed kTC noise pd, and since pixel 502 has been exposed, the potential difference (and the charge based on it) between the potential VD corresponding to the photovoltaic power generated based on the light received by the photoelectric conversion element 110 and the potential VC is held in the capacitive element SC1.

[0086] [1-5-5. Image Data Acquisition Period PDT] The image data acquisition period PDT is the period during which the pixel 502 is set to a state where image data can be acquired, and the second output signal (including the second output potential) output to the output signal line 420 in accordance with the photovoltaic power is sampled (acquired), and is the period during which image data of the subject is acquired.

[0087] Between time t4 and time t5, the reset signal RS(n) remains at a low level, and the data transfer signal TX(n) changes from a low level to a high level and remains at a high level. Therefore, the reset transistor T2 remains in a non-conductive state, and the data transfer transistor T1 changes from a non-conductive state to a conductive state and remains at a conductive state. Although not shown in the diagram, for example, the readout signal RD(n) changes from a low level to a high level and remains at a high level, and the selection transistor T4 changes from a non-conductive state to a conductive state and remains at a conductive state.

[0088] As a result, for example, during the imaging data acquisition period PDT, node N2 is connected to node N1, and the charge (potential) held in capacitive element SC1 is transferred to capacitive element SC2. Therefore, the potential supplied to node N2 gradually decreases from potential VA to potential VB, and the potential supplied to node N1 gradually increases from potential VC to potential VD. At this time, potentials VD and VB are potentials in which the kTC noise pd is suppressed.

[0089] Furthermore, since the data transfer transistor T1 and the selection transistor T4 are in a conductive state, for example, the potential V(t41) of node N2 at time t31 is supplied to the gate electrode 632. As a result, the drive transistor T3 supplies a potential to node N3 according to the potential V(t41), and the selection transistor T4 supplies an output signal OUT(m) to the output signal line 420, which includes a second output potential corresponding to the potential supplied to node N3. For example, the potential V(t41) is potential VB.

[0090] Furthermore, the CDS circuit 610 samples (acquires) and holds the output signal OUT(m) which includes the second output potential output to the output signal line 420. In addition, the CDS circuit 610 calculates the potential difference between the first output potential held during the reset period PRS and the second output potential. As explained in "1-1. Overview of the Solid State Imaging Device 100", the kTC noise fd is canceled out by calculating the potential difference between the first output potential and the second output potential.

[0091] Furthermore, the CDS circuit 610 samples (acquires) and holds the output signal OUT(m) which includes the second output potential output to the output signal line 420. In addition, the CDS circuit 610 calculates the potential difference between the first output potential held during the reset period PRS and the second output potential. As explained in "1-1. Overview of the Solid State Imaging Device 100", the kTC noise fd is canceled out by calculating the potential difference between the first output potential and the second output potential. The potential difference between the first output potential and the second output potential is then transferred to the AD conversion circuit 620, which converts the potential difference between the first output potential and the second output potential into a digital signal. Furthermore, multiple digital signals, including multiple imaging data generated by the readout circuit 600, are transferred to the signal processing circuit 700, which performs image processing on the multiple digital signals to generate image data.

[0092] [1-5-6. Blank period after imaging data acquisition period PDT] Between time t5 and time t6, the reset signal RS(n) remains at a low level, and the data transfer signal TX(n) changes from a high level to a low level and remains at a low level. Therefore, the reset transistor T2 remains in a non-conductive state, and the data transfer transistor T1 changes from a conductive state to a non-conductive state and remains in a non-conductive state. In addition, although not shown in the diagram, for example, the readout signal RD(n) may remain at a high level and the selection transistor T4 may remain in a conductive state, or the readout signal RD(n) may change from a high level to a low level and remain at a low level, and the selection transistor T4 may change from a conductive state to a non-conductive state and remain in a non-conductive state.

[0093] As a result, during the blank period after the imaging data acquisition period PDT, node N2 is in a floating state, and for example, the potential supplied to node N2 drops from potential VB to initialization potential VSS. Also, while the data transfer transistor T1 maintains a conductive state, the potential supplied to node N1 maintains potential VD. When the data transfer transistor T1 changes from a conductive state to a non-conductive state, the pixel 502 is exposed, and the photoelectric conversion element 110 generates a photovoltaic, so the potential supplied to node N1 begins to gradually decrease from potential VD. Note that the potential supplied to node N1 is a potential in which kTC noise pd is suppressed.

[0094] Furthermore, during the blank period after the imaging data acquisition period PDT, the potential difference between the first output potential and the second output potential may be transferred to the AD conversion circuit 620, which converts the potential difference between the first output potential and the second output potential into a digital signal. Multiple digital signals, including multiple imaging data generated by the readout circuit 600, may be transferred to the signal processing circuit 700, which then performs image processing on the multiple digital signals to generate image data.

[0095] As explained above, by using the driving method of the solid-state imaging device 100, imaging data can be obtained in which both kTC noise pd and kTC noise fd are suppressed. Therefore, the solid-state imaging device 100 can generate imaging data with high color reproducibility of the subject in which the effects of noise are suppressed.

[0096] [1-6. Layout of Pixel 502] The layout of pixel 502 will be described in general terms with reference to Figures 4, 6, and 7. Figures 6 and 7 show an example of the layout of pixel 502. Figure 6 is a plan view showing the layout of oxide semiconductor layer 122, conductive layer 127, conductive layer 132, opening 135, opening 137, and opening 138. In Figure 6, the layers above the first p-type semiconductor layer 140, starting from the side closer to the first surface 101A along the third direction D3, are omitted. Figure 7 is a plan view showing the layout of a part of oxide semiconductor layer 122, a part of conductive layer 132, opening 138, opening 137, first p-type semiconductor layer 140, semiconductor layer 143, second p-type semiconductor layer 144, conductive layer 145, conductive layer 148, conductive layer 149, opening 146, and opening 147. In Figure 7, the layers below the first p-type semiconductor layer 140, starting from the side closer to the first surface 101A along the third direction D3, are omitted. Furthermore, to facilitate understanding of the positional relationships between the openings 137 and 138, the oxide semiconductor layer 122D, the first p-type semiconductor layer 140, the conductive layer 145, and the conductive layer 132E, the oxide semiconductor layer 122D and the conductive layer 132E, which are layers below the first p-type semiconductor layer 140, are shown in Figure 7 for reference. The pixel layout 502 shown in Figures 6 and 7 is an example, and the pixel layout 502 is not limited to the example shown in Figures 6 and 7. Configurations identical or similar to those in Figures 1 to 5 will be described as necessary.

[0097] Furthermore, the end view shown in Figure 4, which explains "1-4. End Face Structure of Pixel 502," is an example of the end face structure of a part of pixel 502, and is an end view showing the end face cut along A1-A2 in the layout of pixel 502 shown in Figures 6 and 7.

[0098] First, with reference to Figure 4 or Figure 6, the layout of the layers below the first p-type semiconductor layer 140 will be described.

[0099] The conductive layer 120 includes conductive layers 120A, 120B, 120C, 120D, and 120E. Conductive layers 120A, 120B, 120C, 120D, and 120E are arranged on the same layer, spaced apart from each other. Conductive layer 120A functions as a read signal line 410, conductive layer 120B functions as a data transfer signal line 412, conductive layer 120C functions as a reset signal line 414, conductive layer 120D functions as the first electrode 32 of the capacitive element SC2, and conductive layer 120E functions as a light-shielding layer or gate electrode of the drive transistor T3. Conductive layers 120A, 120B, and 120E, like conductive layer 120B, are superimposed on the corresponding transistors and function as light-shielding layers or gate electrodes of the corresponding transistors. Conductive layer 120 may sometimes be referred to as the lower gate electrode.

[0100] The oxide semiconductor layer 122 includes oxide semiconductor layers 122A, 122B, 122C, and 122D. The oxide semiconductor layers 122A, 122B, 122C, and 122D are arranged in the same layer, spaced apart from each other. The conductive layer 127 includes gate electrodes 127A, 127B, 127C, 127D, and 127E. The gate electrodes 127A, 127B, 127C, 127D, and 127E are arranged in the same layer, spaced apart from each other.

[0101] The oxide semiconductor layer 122A, like the oxide semiconductor layer 122B, includes a first portion (not shown), a second portion (not shown), a third portion (not shown), and a fourth portion (not shown). The oxide semiconductor layer 122A also includes a fifth portion (not shown) electrically connected to the fourth portion and located on the opposite side from the third portion. The fifth portion contains the same amount of impurities as the first portion. In a plan view, the oxide semiconductor layer 122A in the region overlapping with the gate electrode 127A (gate electrode 642) functions as a semiconductor layer (channel) of the selection transistor T4 and switches between a conductive state and a non-conductive state depending on the potential supplied to the gate electrode 127A. For example, in a plan view, the oxide semiconductor layer 122A in the region not overlapping with the gate electrode 127C functions as a conductive layer of the selection transistor T4 and functions as the first electrode 644 and the second electrode 646. That is, the oxide semiconductor layer 122C functions as both a semiconductor layer and a conductive layer.

[0102] For example, the impurities contained in the first portion 113, the third portion 112, and the fourth portion 114 include elements such as boron (B), phosphorus (P), and argon (Ar). For example, the impurities are implanted into the first portion 113, the third portion 112, and the fourth portion 114 by an impurity implantation process. By implanting impurities into the first portion 113, the third portion 112, and the fourth portion 114, oxygen vacancies are formed in the oxide semiconductor layer 122. The amount of impurities implanted in the third portion 112 and the amount of impurities implanted in the fourth portion 114 is less than the amount of impurities implanted in the first portion 113. For example, the resistance of the first portion 113 is reduced by the impurities implanted in the first portion 113. On the other hand, the amount of impurities implanted in the fourth portion 114 is such that the fourth portion 114 becomes completely depleted or very close to completely depleted.

[0103] The oxide semiconductor layer 122C has the same configuration as the oxide semiconductor layer 122A and is formed in the same manner. The region of the oxide semiconductor layer 122C that overlaps with the gate electrode 127C (gate electrode 632) in a plan view functions as a semiconductor layer (channel) of the drive transistor T3 and is switched between a conductive state and a non-conductive state depending on the potential supplied to the gate electrode 127C. For example, the region of the oxide semiconductor layer 122C that does not overlap with the gate electrode 127C in a plan view functions as a conductive layer of the drive transistor T3 and functions as the first electrode 634 and the second electrode 636. In other words, the oxide semiconductor layer 122C functions as both a semiconductor layer and a conductive layer.

[0104] The oxide semiconductor layer 122D has the same configuration as the oxide semiconductor layer 122A and is formed in the same manner. The region of the oxide semiconductor layer 122D that overlaps with the gate electrode 127D (gate electrode 622) in a plan view functions as a semiconductor layer (channel) of the reset transistor T2 and is switched between a conductive state and a non-conductive state depending on the potential supplied to the gate electrode 127D. For example, the region of the oxide semiconductor layer 122D that does not overlap with the gate electrode 127D in a plan view functions as a conductive layer of the reset transistor T2 and functions as the first electrode 624 and the second electrode 626. In other words, the oxide semiconductor layer 122D functions as both a semiconductor layer and a conductive layer.

[0105] The opening 135 includes openings 135A to 135S. The opening 135 may penetrate the insulating layer 128 (see Figure 4), may penetrate the insulating layer 128 and the gate insulating layer 125 (see Figure 4), or may penetrate the insulating layer 128, the gate insulating layer 125 and the insulating layer 121 (see Figure 4). The conductive layer 132 also includes conductive layers 132A to 132H. The conductive layers 132A to 132H are arranged in the same layer, spaced apart from each other.

[0106] For example, the opening 135G exposes the conductive layer 120B (data transfer signal line 412). The conductive layer 132G electrically connects the conductive layer 120B and the gate electrode 127B (gate electrode 612) via the openings 135F and 135G. For example, as shown in Figures 4 and 5, the oxide semiconductor layer 122B is sandwiched between the conductive layer 120B and the gate electrode 127B, and the oxide semiconductor layer 122B, the conductive layer 120B, and the gate electrode 127B face each other and overlap, forming a part of the data transfer transistor T1.

[0107] The opening 135N exposes the conductive layer 120C (reset signal line 414), and the opening 135M exposes the gate electrode 127D (gate electrode 622). The conductive layer 132G electrically connects the conductive layer 120C (reset signal line 414) and the gate electrode 127D (gate electrode 622) via the openings 135N and 135M. In a plan view, the oxide semiconductor layer 122D is sandwiched between the conductive layer 120C and the gate electrode 127D. The oxide semiconductor layer 122D, the conductive layer 120C, and the gate electrode 127D face each other and overlap, forming a part of the reset transistor T2.

[0108] The opening 135E exposes the oxide semiconductor layer 122B, the opening 135J exposes the oxide semiconductor layer 122D, the opening 135S exposes the conductive layer 120E, and the opening 135D exposes the gate electrode 127C (gate electrode 632). The conductive layer 132E electrically connects the oxide semiconductor layers 122B and 122D, the conductive layer 120E, and the gate electrode 127C via the openings 135E, 135J, 135S, and 135E. In a plan view, the oxide semiconductor layer 122C is sandwiched between the conductive layer 120E and the gate electrode 127C, and the oxide semiconductor layer 122C, the conductive layer 120E, and the gate electrode 127C face each other and overlap, forming a part of the drive transistor T3.

[0109] Furthermore, node N2, the first electrode 624 of the reset transistor T2, the gate electrode 632 of the drive transistor T3, the second electrode 616 of the data transfer transistor T1, and the second electrode 34 of the capacitive element SC2 are electrically connected, and the conductive layer 132E functions as node N2, the second electrode 34 of the capacitive element SC2, the second electrode 616 of the data transfer transistor T1, and the first electrode 624 of the reset transistor T2.

[0110] The opening 135C exposes the conductive layer 120A (read signal line 410), and the opening 135O exposes the gate electrode 127A (gate electrode 642). The conductive layer 132C electrically connects the conductive layer 120A and the gate electrode 127A via the openings 135C and 135O. In a plan view, the oxide semiconductor layer 122A is sandwiched between the conductive layer 120A and the gate electrode 127A, and the oxide semiconductor layer 122A, the conductive layer 120A, and the gate electrode 127A face each other and overlap, forming a part of the selection transistor T4.

[0111] The opening 135R exposes the oxide semiconductor layer 122C, and the opening 135K exposes the gate electrode 127E (the first electrode 32 of the capacitive element SC2). The conductive layer 132F (driving potential line PVDD) is electrically connected to the oxide semiconductor layer 122C via the opening 135R and to the gate electrode 127E via the opening 135K. In other words, the conductive layer 132F (driving potential line PVDD) is electrically connected to the driving transistor T3 and the capacitive element SC2.

[0112] The opening 135A exposes the oxide semiconductor layer 122A. The conductive layer 132A (output signal line 420) is electrically connected to the oxide semiconductor layer 122A via the opening 135A. That is, the conductive layer 132A (output signal line 420) is electrically connected to the selection transistor T4.

[0113] The opening 135L exposes the conductive layer 120D, the opening 135I exposes the conductive layer 120D, and the opening 132K exposes the oxide semiconductor layer 122D. The conductive layer 132D (reset potential line SVR) is electrically connected to the conductive layer 120D via the opening 135L, and the conductive layer 132H is electrically connected to the oxide semiconductor layer 122D via the openings 135I and 135H. That is, the conductive layer 132A (output signal line 420) is electrically connected to the selection transistor T4.

[0114] Although a detailed explanation is omitted, the other openings 135 also expose the corresponding insulating layer, conductive layer, gate electrode, or oxide semiconductor layer, thereby creating electrical conductivity between the conductive layer and the gate electrode, or between the conductive layer and the oxide semiconductor layer.

[0115] Next, with reference to Figure 4 or Figure 7, the layout of the layers above the first p-type semiconductor layer 140 will be described.

[0116] After the insulating layer 136 is formed so as to overlap the insulating layer 131, the opening 138 penetrates the insulating layer 136, exposing a portion of the surface of the insulating layer 131. After the opening 138 penetrates the insulating layer 136 and a portion of the surface of the insulating layer 131 is exposed, the first p-type semiconductor layer 140 is provided on the insulating layer 136, on the inside (side wall) of the opening 138, and on a portion of the exposed surface of the insulating layer 131.

[0117] After the insulating layer 136 is formed so as to overlap the insulating layer 131, the opening 137 penetrates the insulating layers 131 and 128, as well as the gate insulating layer 125, exposing the oxide semiconductor layer 122D. A portion of the surface of the insulating layer 131 is exposed. After the opening 137 penetrates the insulating layers 131 and 128, as well as the gate insulating layer 125, and exposes the oxide semiconductor layer 122D, the semiconductor layer 143 is provided on the top and side surfaces of the first p-type semiconductor layer 140, the inside (side walls) of the insulating layers 131 and 128, the inside (side walls) of the gate insulating layer 125, and the surface of the exposed oxide semiconductor layer 122D. That is, as shown in Figure 4, the semiconductor layer 143 is directly connected to the surface of the exposed oxide semiconductor layer 122D.

[0118] The first p-type semiconductor layer 140 and the second p-type semiconductor layer 144 are arranged to overlap. In this case, as shown in Figure 4, the end of the semiconductor layer 143 is located inside the end 160 of the first p-type semiconductor layer 140 and the end 161 of the second p-type semiconductor layer 144, and the end 160 of the first p-type semiconductor layer 140 is in contact with the end 161 of the second p-type semiconductor layer 144.

[0119] The conductive layer 145 is superimposed on the second p-type semiconductor layer 144, and is provided at a distance from the openings 137 and 138 so as not to overlap with them. In other words, in a plan view, the conductive layer 145 is superimposed on the second p-type semiconductor layer 144 and is provided so as to surround the openings 137 and 138. For example, the conductive layer 145 functions as the upper electrode constituting the photoelectric conversion element 110. Also, for example, a part of the conductive layer 145 functions as the first electrode 12 of the photoelectric conversion element 110 and functions as the first electrode 22 of the capacitive element SC1.

[0120] Furthermore, as shown in Figure 7, openings 146 and 147 are provided. Opening 146 opens the insulating layer 141 (see Figure 4) and exposes a portion of the surface of the conductive layer 145. Opening 147 opens the insulating layer 151 (see Figure 4) and exposes a portion of the surface of the conductive layer 145, as well as a portion of the surface of the conductive layer 145 exposed by opening 146.

[0121] Furthermore, as shown in Figure 7, a conductive layer 148 is provided. Although not shown, the conductive layer 148 is provided on top of the insulating layer 151. Also, although not shown, in an end view, the conductive layer 148 is separated from the end 160 of the first p-type semiconductor layer 140 and the end 161 of the second p-type semiconductor layer 144 by the insulating layer 151. Also, as shown in Figure 7, in a plan view, the conductive layer 148 overlaps the end 160 of the first p-type semiconductor layer 140 and the end 161 of the second p-type semiconductor layer 144.

[0122] Furthermore, as shown in Figure 7, a conductive layer 149 is provided. The conductive layer 149 is provided so as to be in contact with and covering the conductive layer 148, and is connected to a part of the surface of the exposed conductive layer 145 through openings 146 and 147. For example, the conductive layer 149 and the conductive layer 148 function as a reference potential line PVSS.

[0123] [1-7. Materials of Each Member of Solid-State Imaging Device 100] As the substrate 101, a rigid substrate having no flexibility, such as a glass substrate, a quartz substrate, or a sapphire substrate, can be used. Further, as the substrate 101, a flexible substrate containing a resin and having flexibility, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, may be used.

[0124] As the conductive layers 120, 127, 132, and 148, a metal material can be used. For example, as the metal material, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), or silver (Ag), or an alloy or compound thereof is used. As the members such as the above electrodes, the above metal material may be used in a single layer or in a laminated manner.

[0125] As the insulating layers 121, gate insulating layer 125, insulating layers 128, 131, 141, and 152, and insulating layers 136, 151, and 153, general insulating materials can be used. For example, as the insulating layers 121, gate insulating layer 125, insulating layers 128, 131, 141, and 152, silicon oxide (SiO ｘ ), silicon oxynitride (SiO ｘ N ｙ ), silicon nitride (SiN ｘ ), silicon nitride oxide (SiN ｘ O ｙ ), aluminum oxide (AlO ｘ ), aluminum oxynitride (AlO ｘ N ｙ ), aluminum nitride oxide (AlN ｘ O ｙ ), or aluminum nitride (AlN ｘAn inorganic insulating layer such as ) can be used. As these insulating layers, an insulating layer with few defects can be used. As the insulating layers 136, 151, and 153, an organic insulating material such as a polyimide resin, an acrylic resin, an epoxy resin, a silicone resin, a fluororesin, or a siloxane resin can be used. Note that as the insulating layer 121, the gate insulating layer 125, the insulating layers 128, 131, 141, and 152, the above organic insulating material may be used. As members such as the above insulating layers, the above insulating material may be used as a single layer or in a laminated form.

[0126] SiO ｘ N ｙ and AlO ｘ N ｙ are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio less than that of oxygen (O). SiN ｘ O ｙ and AlN ｘ O ｙ are silicon compounds and aluminum compounds containing oxygen in a ratio less than that of nitrogen (x > y).

[0127] As the oxide semiconductor layer 122, an oxide semiconductor having semiconductor characteristics can be used. The oxide semiconductor layer 122 has translucency.

[0128] The composition of the oxide semiconductor used in the solid-state imaging device 100 is not limited. As the oxide semiconductor, for example, an oxide semiconductor layer for improving mobility may be used. Also, an oxide semiconductor layer for increasing the bandgap and reducing the influence of light irradiation may be used.

[0129] For example, the subthreshold value (S value) of a transistor having an oxide semiconductor with semiconductor properties is close to the theoretical value, the leakage current is extremely small, and according to the electrical properties of the transistor having an oxide semiconductor with semiconductor properties (dependence of drain current on gate-drain voltage), the transistor having an oxide semiconductor with semiconductor properties is depleted to a state of complete depletion or close to complete depletion. Therefore, the electrical properties of a transistor formed using the oxide semiconductor layer 122 in the solid-state imaging device 100 (for example, a data transfer transistor T1) are depleted to a state of complete depletion or close to complete depletion, and the solid-state imaging device 100 has a configuration that can suppress kTC noise ped.

[0130] In addition, as an example, an example is shown in which oxide semiconductors are used for the semiconductor layer (second semiconductor layer) of the reset transistor T2 (second transistor), the semiconductor layer (third semiconductor layer) of the drive transistor T3 (third transistor), and the semiconductor layer (fourth semiconductor layer) of the selection transistor T4 (fourth transistor) in the solid-state imaging device 100. However, the semiconductor layer (second semiconductor layer) of the reset transistor T2 (second transistor), the semiconductor layer (third semiconductor layer) of the drive transistor T3 (third transistor), and the semiconductor layer (fourth semiconductor layer) of the selection transistor T4 (fourth transistor) in the solid-state imaging device 100 are not limited to oxide semiconductors. For example, Group 14 elements such as silicon and germanium may be used as the semiconductor layer (second semiconductor layer) of the reset transistor T2 (second transistor), the semiconductor layer (third semiconductor layer) of the drive transistor T3 (third transistor), and the semiconductor layer (fourth semiconductor layer) of the selection transistor T4 (fourth transistor) in the solid-state imaging device 100. For example, crystalline silicon can be used as the channel region having a group 14 element. The crystalline silicon may be low-temperature polysilicon (LTPS) or single-crystal silicon.

[0131] Transparent conductive layers are used as conductive layers 145 and 149. For example, a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO) can be used as the transparent conductive layer. Other materials may also be used as the transparent conductive layer.

[0132] For example, the conductive layer 120, insulating layer 121, oxide semiconductor layer 122, gate insulating layer 125, conductive layer 127, insulating layer 128, opening 135, conductive layer 132, insulating layer 131, and insulating layer 136 are collectively referred to as the array portion 170.

[0133] [2. Modified Examples] Referring to Figure 8, an overview of the modified solid-state imaging device 100 will be described. Figure 8 is an end view showing an example of a part of the end face structure of a pixel 502 according to the modified example. Configurations identical or similar to those in Figures 1 to 7 will be described as necessary.

[0134] The modified pixel 502 includes the following configurations (1) to (3). Configurations (1) to (3) differ from the configuration of the pixel 502 of the solid-state imaging device 100 according to the first embodiment. (1) The fourth portion 114, which is directly connected to the semiconductor layer 143, includes an intrinsic semiconductor, similar to the second portion 111 which is superimposed on the gate electrode 612. (2) The impurity concentration of the fourth portion 114 is the same as the impurity concentration of the second portion 111. (3) The fourth portion 114, which includes an intrinsic semiconductor, functions as a source region (source electrode) and functions as the first electrode 614 of the data transfer transistor T1. The fourth portion 114 may also be the first electrode 614. Furthermore, since the fourth portion 114 is directly connected to the semiconductor layer 143, it may function as an n-type semiconductor layer of the photoelectric conversion element 110, or it may function as a cathode electrode of the photoelectric conversion element 110, or it may be a cathode electrode of the photoelectric conversion element 110.

[0135] Configurations (1) to (3), and configurations other than those related to configurations (1) to (3), are the same as the pixel 502 of the solid-state imaging device 100 according to the first embodiment.

[0136] Therefore, the solid-state imaging device 100 including the pixel 502 according to the modified example provides the same effects and advantages as the solid-state imaging device 100 according to the first embodiment.

[0137] The various configurations of the detection device (solid-state imaging device) illustrated as one embodiment and modification of the present invention can be combined as appropriate, as long as they do not contradict each other. Furthermore, the various configurations of the detection device (solid-state imaging device) illustrated as one embodiment and modification of the present invention can be replaced as appropriate, as long as they do not contradict each other. Based on the detection device (solid-state imaging device) disclosed in this specification and drawings, any additions, deletions, or design changes of components, or additions, omissions, or changes in processes, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0138] Any effects or benefits other than those brought about by the embodiments disclosed herein are to be understood to be brought about by the present invention if they are clear from the description herein or can be easily predicted by a person skilled in the art.

[0139] 12: First electrode, 14: Second electrode, 22: First electrode, 24: Second electrode, 32: First electrode, 34: Second electrode, 60: Pixel circuit, 100: Solid-state imaging device, 101: Substrate, 101A: First surface, 101B: Second surface, 110: Photoelectric conversion element, 111: Second part, 112: Third part, 113: First part, 114: Fourth part, 120: Conductive layer, 120A: Conductive layer, 120B: Conductive layer, 120C: Conductive layer, 120D: Conductive layer, 120E: Conductive layer, 121: Insulating layer, 122: Oxide semiconductor layer, 122A: Oxide semiconductor layer, 122B: Oxide semiconductor layer, 122C: Oxide semiconductor layer, 122D: Oxide semiconductor layer, 125: Gate insulating layer, 127: Conductive layer, 127A: Gate gate, 127B: Gate gate, 127C: Gate gate, 127D: Gate gate, 127E: Gate gate, 128: Insulating layer, 131: Insulating layer, 132: Conductive layer, 132A: Conductive layer, 132B: Conductive layer, 132C: Conductive layer, 132D: Conductive layer, 132E: Conductive layer, 132F: Conductive layer, 132G: Conductive layer, 132H: Conductive layer, 132K: Opening, 135: Opening, 135A: Opening, 135B: Opening, 135C: Opening, 135D: Opening 135E: Opening part, 135F: Opening part, 135G: Opening part, 135H: Opening part, 135I: Opening part, 135J: Opening part, 135K: Opening part , 135L: Opening, 135M: Opening, 135N: Opening, 135O: Opening, 135P: Opening, 135Q: Opening, 135R: Opening part, 135S: opening section, 136: insulating layer, 137: opening section, 138: opening section, 139: conductive layer, 140: first p-type semiconductor layer, 141: absolute Edge layer, 143: Semiconductor layer, 144: Second p-type semiconductor layer, 145: Conductive layer, 146: Opening, 147: Opening, 148: Conductive layer, 149: Conductive Electrode layer, 151: insulating layer, 152: insulating layer, 153: insulating layer, 160: end, 161: end, 170: array section, 200: power supply circuit, 300: drive timing control circuit, 400: row selection circuit, 410: read signal line, 412: data transfer signal line, 414: reset signal line, 420: output signal line, 502: pixel, 504: pixel section, 600: read circuit, 610: CDS circuit, 612: gate electrode, 614: first electrode, 616: second electrode, 620: AD conversion circuit, 622: gate electrode, 624: first electrode, 626: second electrode, 632: gate electrode,634: First electrode, 636: Second electrode, 642: Gate electrode, 644: First electrode, 646: Second electrode, 700: Signal processing circuit,

Claims

1. A detection device comprising: a photoelectric conversion element electrically connected to a first node and capable of receiving light; and a first transistor electrically connected between the first node and a second node, the switching of which is controlled by a first control signal line, wherein the photoelectric conversion element comprises a second p-type semiconductor layer and a first semiconductor layer in contact with the second p-type semiconductor layer; the first transistor comprises a second semiconductor layer electrically connected between the first node and the second node and a gate electrode electrically connected to the first control signal line; the second semiconductor layer comprises a first portion electrically connected to the second node, a second portion superimposed on the gate electrode, and a fourth portion electrically connected to the second portion and directly connected to the first semiconductor layer, wherein the impurity concentration of the fourth portion is smaller than the impurity concentration of the first portion.

2. The detection device according to claim 1, wherein the impurity concentration of the fourth portion is greater than the impurity concentration of the second portion.

3. The detection device according to claim 1, wherein the impurity concentration of the fourth portion is the same as the impurity concentration of the second portion.

4. The detection device according to claim 1, wherein the second semiconductor layer includes a third portion electrically connected between the first portion and the second portion.

5. The detection device according to claim 1, wherein the photoelectric conversion element further includes a first p-type semiconductor layer, and the first semiconductor layer is sandwiched between the first p-type semiconductor layer and the second p-type semiconductor layer.

6. The detection device according to claim 5, wherein the edge of the first p-type semiconductor layer is in contact with the edge of the second p-type semiconductor layer.

7. The detection device according to claim 5, further comprising: a first insulating layer; a second insulating layer formed on the first insulating layer along a third direction perpendicular to a plane including a first direction and a second direction intersecting the first direction in an end view; a first opening in an end view that opens the second insulating layer and exposes the surface of the first insulating layer; and a second opening in an end view that opens the first p-type semiconductor layer and the first insulating layer and exposes the second semiconductor layer.

8. The detection device according to claim 7, wherein the diameter of the first opening is greater than the diameter of the second opening.

9. The detection device according to claim 7, wherein the inside of the first opening is provided with a portion in which the first p-type semiconductor layer, which is in contact with the first opening and the first insulating layer exposed by the first opening, the first semiconductor layer, and the second p-type semiconductor layer are stacked in this order along the third direction, and a portion in which the first semiconductor layer and the second p-type semiconductor layer are stacked in this order along the third direction.

10. The detection device according to claim 7, wherein a first semiconductor layer is provided inside the second opening, in contact with the second opening and in contact with the second semiconductor layer exposed by the second opening, and the first semiconductor layer provided inside the second opening is in contact with the first insulating layer and separated from the second insulating layer.

11. The detection device according to claim 7, further comprising a conductive layer provided between the first insulating layer and the second semiconductor layer along the third direction, wherein, in end view, the second semiconductor layer is provided parallel to the surface, and a first portion of the conductive layer includes the second node and is electrically connected to the first portion of the second semiconductor layer.

12. The detection device according to claim 1, further comprising: a second transistor electrically connected between the second node and a reset potential line to which a reset potential is supplied, and whose switching is controlled by a second control signal line; a wiring to which a predetermined potential to which a drive potential is supplied is supplied; and a capacitive element electrically connected between the second node and the second node, wherein the second transistor comprises a third semiconductor layer electrically connected between the second node and the reset potential line, and a gate electrode electrically connected to the second control signal line, and the third semiconductor layer comprises silicon or an oxide semiconductor.

13. The detection device according to claim 12, further comprising a third transistor having a gate electrode electrically connected between the wiring and the third node and electrically connected to the second node, wherein the third transistor includes a fourth semiconductor layer electrically connected between the wiring and the third node, and the fourth semiconductor layer comprises silicon or an oxide semiconductor.

14. The detection device according to claim 13, further comprising a fourth transistor electrically connected between the third node and an output signal line for outputting a potential to be detected by the detection device, the switching of which is controlled by a third control signal line, wherein the fourth transistor comprises a fifth semiconductor layer electrically connected between the third node and the output signal line, and a gate electrode electrically connected to the third control signal line, the fifth semiconductor layer comprising silicon or an oxide semiconductor.

15. The detection device according to claim 14, further comprising a control circuit electrically connected to the output signal line, wherein the control circuit is configured to control: controlling a first potential which the third transistor flows to the third node and the fourth transistor outputs to the output signal line based on a first potential supplied to the second node in accordance with the reset potential, and sampling a first output potential corresponding to the first potential; controlling a second potential which the third transistor flows to the third node and the fourth transistor outputs to the output signal line based on a second potential supplied to the second node in accordance with the photovoltaic power generated based on light received by the photoelectric conversion element, and sampling a second output potential corresponding to the second potential; and calculating the potential difference between the first output potential and the second output potential.

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