Controlled etching using pulsed plasma

Abstract

Exemplary semiconductor processing methods may include providing a halogen-containing precursor and an inert gas to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A layer of silicon-containing material may overlie the substrate. The methods may include contacting the layer of silicon-containing material with the halogen-containing precursor and the inert gas for a first period of time to form a halogenated portion of the layer of silicon-containing material. The methods may include, subsequent to the first period of time, applying a source power and a bias power or a bias voltage while continuing to contact the layer of silicon-containing material with the halogen-containing precursor and the inert gas for a second period of time to desorb the halogenated portion of the layer of silicon-containing material.

Description

PCT / US25 / 10733 08 January 2025 (08.01.2025)PATENT KTS No.: 080042-44025460WO01-1473621CONTROLLED ETCHING USING PULSED PLASMATECHNICAL FIELD

[0001] The present technology relates to semiconductor processes and equipment. More 5 specifically, the present technology relates to etching silicon-containing materials.BACKGROUND

[0002] Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate requires controlled methods for removal of exposed material. Chemical etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers, thinning layers, or thinning lateral dimensions of features already present on the surface. Often it is desirable to have an etch process that etches one material faster than another facilitating, for example, a pattern transfer process. Such an etch process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etch processes have been developed with a selectivity towards a variety of materials.

[0003] Etch processes may be termed wet or dry based on the materials used in the process. A wet HF etch preferentially removes silicon oxide over other dielectrics and materials. However, wet processes may have difficulty penetrating some constrained trenches and also may sometimes deform the remaining material. Dry etches produced in local plasmas formed within the substrate processing region can penetrate more constrained trenches and exhibit less deformation of delicate remaining structures. However, local plasmas may damage the substrate through the production of electric arcs as they discharge.

[0004] Thus, there is a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are addressed by the present 25 technology.SUMMARY

[0005] Exemplary semiconductor processing methods may include i) providing a halogencontaining precursor and an inert gas to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A layer of silicon-PCT / US25 / 10733 08 January 2025 (08.01.2025)containing material may overlie the substrate. The methods may include n) contacting the layer of silicon-containing material with the halogen-containing precursor and the inert gas for a first period of time to form a halogenated portion of the layer of silicon-containing material. The methods may include iii) subsequent to the first period of time, applying a source power and a bias power or a bias voltage while continuing to contact the layer of silicon-containing material with the halogen-containing precursor and the inert gas for a second period of time to desorb the halogenated portion of the layer of silicon-containing material. The methods may include iv) repeating operations ii and iii to etch a feature into the layer of silicon-containing material.[00061 In embodiments, the halogen-containing precursor may be or include a chlorine-containing precursor. The halogen-containing precursor may be or include diatomic chlorine (Ch). The inert gas may be or include argon (Ar). A flow rate of the halogen-containing precursor may be less than or about 300 seem. A flow rate ratio of the halogen-containing precursor relative to the inert gas may be less than or about 1:1. The layer of silicon-containing material may be or include amorphous silicon or polycrystalline silicon. The source power may be applied at less than or about 750 W. The bias power may be applied at less than or about 1,000 W or the bias voltage is applied at less than or about 2.0 kV. The first period of time may be greater than the second period of time. The first period of time may be greater than or about 20 milliseconds. A temperature within the processing region may be maintained at greater than or about 0 °C. A pressure within the processing region may be maintained at less than or about 1 Torr.

[0007] Some embodiments of the present technology may encompass semiconductor processing methods. The methods may include providing a halogen-containing precursor and an inert gas to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A layer of silicon-containing material may overlie the substrate. The methods may include contacting the layer of silicon-containing material with the halogen-containing precursor and the inert gas while pulsing a source power and a bias power or a bias voltage. The source power and the bias power or the bias voltage may be off while chemisorbing the halogen-containing precursor to form a halogenated portion of the layer of silicon-containing material. The source power and the bias power or the bias voltage may be on while desorbing halogenated portion of the layer of silicon-containing material.PCT / US25 / 10733 08 January 2025 (08.01.2025)

[0008] In embodiments, the source power and the bias power or the bias voltage are synchronized. A duty cycle of each of the source power and the bias power or the bias voltage may be less than or about 40%. A pulsing frequency of each of the source power and the bias power may be less than or about 1 kHz.5

[0009] Some embodiments of the present technology may encompass semiconductor processing methods. The methods may include i) providing a chlorine-containing precursor and an inert gas to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A layer of silicon material may overlie the substrate. The methods may include ii) contacting the layer of silicon material with the 10 chlorine-containing precursor and the inert gas without applying a source power and a bias power or a bias voltage for a first period of time to form a halogenated portion of the layer of silicon material. The methods may include iii) subsequent to the first period of time, applying the source power and the bias power or the bias voltage while continuing to contact the layer of silicon material with the chlorine-containing precursor and the inert gas for a second period of time to desorb the halogenated portion of the layer of silicon material. The methods may include iv) repeating operations ii and iii to etch a feature into the layer of silicon material. The source power and the bias power or the bias voltage may be pulsed between an OFF state during the first period of time and an ON state during the second period of time.20

[0010] In embodiments, the halogenated portion of the layer of silicon material may be characterized by a thickness of less than or about 1.7 A. A temperature within the processing region may be maintained at greater than or about 25 °C.

[0011] Such technology may provide numerous benefits over conventional systems and techniques. For example, the processes may etch silicon-containing materials, such as features into silicon-containing materials, within semiconductor structures. Additionally, the processes may etch materials on an atomic layer etching (ALE)-type basis without the intermittent purging of the processing region, effectively reducing processing times. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the below description and attached figures.30PCT / US25 / 10733 08 January 2025 (08.01.2025)BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings.

[0013] FIG. 1 shows a top plan view of one embodiment of an exemplary processing 5 system according to some embodiments of the present technology.

[0014] FIG. 2 shows a schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology.

[0015] FIG. 3A shows exemplary operations in a method according to some embodiments of the present technology.10

[0016] FIG. 3B shows an exemplary pulsing scheme in a method according to some embodiments of the present technology.

[0017] FIGS.4A-4D show cross-sectional views of substrates being processed according to some embodiments of the present technology.

[0018] Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes, and are not to be considered of scale unless specifically stated to be of scale. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes.

[0019] In the appended figures, similar components and / or features may have the same 20 reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter.DETAILED DESCRIPTION

[0020] In transitioning from 2D NAND to 3D NAND (or to 3D DRAM), many process operations are modified from vertical to horizontal operations. Additionally, as structures grow in the number of cells or transistors being formed, such as in transitioning from a gate- all-around (GAA) transistor to a complementary field-effect transistors (CFET), the aspect 30 ratios of holes, trenches, and other structures increase, sometimes dramatically. During 3DPCT / US25 / 10733 08 January 2025 (08.01.2025)NAND, 3D DRAM, GAA, and / or CFET processing, or other memory and / or logic processing, layers silicon-containing materials may be present in intermediate structures. These silicon-containing materials may have a variety of operations performed to fabricate final devices. For example, one or more holes or trenches may be etched into the silicon-containing materials.[00211 Some conventional technologies utilize an etch process that removes silicon-containing materials on an atomic layer basis. These technologies, often referred to as atomic layer etching (ALE) operations, include sequentially providing a first precursor to react with silicon-containing material, purging the processing region, providing a second precursor to react with a treated portion of the silicon-containing material, purging the processing region, and repeating the operations for a number of cycles. However, each purging of the processing region may continue for a number of seconds, oftentimes greater than 30 seconds. The repeated and necessary purging of the processing region may result in a cycle commonly longer than a minute to etch a single monolayer, or fraction thereof.

[0022] The present technology overcomes these issues by etching materials on an atomic layer ALE-type basis without the intermittent purging of the processing region. Instead, the present technology may utilize a pulsing scheme to transition between a first period of time without apply source power and bias power or bias voltage and a second period of time while applying source power and bias power or bias voltage. The first period of time may predominantly chemisorb the etchant precursor to, for example, halogenate a portion of the silicon-containing material to be etched. The second period of time, conversely, may predominantly bombard the previously formed halogenated portion of the silicon-containing material, thereby etching the portion of the silicon-containing material. Without intermittent purging of the processing region, the present technology may more quickly and more efficiently remove silicon-containing materials on an ALE-type basis, such that precise control of the etch is maintained.

[0023] Although the remaining disclosure will routinely identify specific etching processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to deposition and cleaning processes as may occur in the described chambers. Accordingly, the technology should not be considered to be so limited as for use with etching processes or chambers alone. Moreover, although an exemplary chamber is described to provide foundation for the present technology, it is to be understood that thePCT / US25 / 10733 08 January 2025 (08.01.2025)present technology can be applied to virtually any semiconductor processing chamber that may allow the single-chamber operations described.

[0024] FIG. 1 shows a top plan view of one embodiment of a processing system 10 of deposition, etching, baking, and / or curing chambers according to embodiments. The tool or 5 processing system 10 depicted in FIG. 1 may contain a plurality of process chambers, 24a-d, a transfer chamber 20, a service chamber 26, an integrated metrology chamber 28, and a pair of load lock chambers 16a-b. The process chambers may include any number of structures or components, as well as any number or combination of processing chambers.

[0025] To transport substrates among the chambers, the transfer chamber 20 may contain a 10 robotic transport mechanism 22. The transport mechanism 22 may have a pair of substrate transport blades 22a attached to the distal ends of extendible arms 22b, respectively. The blades 22a may be used for carrying individual substrates to and from the process chambers. In operation, one of the substrate transport blades such as blade 22a of the transport mechanism 22 may retrieve a substrate W from one of the load lock chambers such as chambers 16a-b and carry substrate W to a first stage of processing, for example, a treatment process as described below in chambers 24a-d. The chambers may be included to perform individual or combined operations of the described technology. For example, while one or more chambers may be configured to perform a deposition or etching operation, one or more other chambers may be configured to perform a pre-treatment operation and / or one or more 20 post-treatment operations described. Any number of configurations are encompassed by the present technology, which may also perform any number of additional fabrication operations typically performed in semiconductor processing.

[0026] If the chamber is occupied, the robot may wait until the processing is complete and then remove the processed substrate from the chamber with one blade 22a and may insert a new substrate with a second blade. Once the substrate is processed, it may then be moved to a second stage of processing. For each move, the transport mechanism 22 generally may have one blade carrying a substrate and one blade empty to execute a substrate exchange. The transport mechanism 22 may wait at each chamber until an exchange can be accomplished.30

[0027] Once processing is complete within the process chambers, the transport mechanism 22 may move the substrate W from the last process chamber and transport the substrate W to a cassette within the load lock chambers 16a-b. From the load lock chambers 16a-b, thePCT / US25 / 10733 08 January 2025 (08.01.2025)substrate may move into a factory interface 12. The factory interface 12 generally may operate to transfer substrates between pod loaders 14a-d in an atmospheric pressure clean environment and the load lock chambers 16a-b. The clean environment in factory interface 12 may be generally provided through air filtration processes, such as HEPA filtration, for example. Factory interface 12 may also include a substrate orienter / aligner that may be used to properly align the substrates prior to processing. At least one substrate robot, such as robots 18a-b, may be positioned in factory interface 12 to transport substrates between various positions / locations within factory interface 12 and to other locations in communication therewith. Robots 18a-b may be configured to travel along a track system within factory interface 12 from a first end to a second end of the factory interface 12.

[0028] The processing system 10 may further include an integrated metrology chamber 28 to provide control signals, which may provide adaptive control over any of the processes being performed in the processing chambers. The integrated metrology chamber 28 may include any of a variety of metrological devices to measure various film properties, such as thickness, roughness, composition, and the metrology devices may further be capable of characterizing grating parameters such as critical dimensions, sidewall angle, and feature height under vacuum in an automated manner.

[0029] Each of processing chambers 24a-d may be configured to perform one or more process steps in the fabrication of a semiconductor structure, and any number of processing chambers and combinations of processing chambers may be used on multi-chamber processing system 10. For example, any of the processing chambers may be configured to perform a number of substrate processing operations including any number of deposition processes including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, as well as other operations including etch, pre-clean, pre-treatment, post-treatment, anneal, plasma processing, degas, orientation, and other substrate processes. Some specific processes that may be performed in any of the chambers or in any combination of chambers may be metal deposition, surface cleaning and preparation, thermal annealing such as rapid thermal processing, and plasma processing. Any other processes may similarly be performed in specific chambers incorporated into multichamber processing system 10, including any process described below, as would be readily appreciated by the skilled artisan.PCT / US25 / 10733 08 January 2025 (08.01.2025)

[0030] FIG. 2 illustrates a schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer disposed on a substrate 302 in the processing chamber 100. The exemplary processing chamber 100 is suitable for performing a patterning process, although it is to be understood that aspects of the present technology may be performed in any number of chambers, and substrate supports according to the present technology may be included in etching chambers, deposition chambers, treatment chambers, or any other processing chamber. The plasma processing chamber 100 may include a chamber body 105 defining a chamber volume 101 in which a substrate may be processed. The chamber body 105 may have sidewalls 112 and a bottom 118 which are coupled with ground 126. The sidewalls 112 may have a liner 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and related components of the plasma processing chamber 100 are not limited and generally may be proportionally larger than the size of the substrate 302 to be processed therein. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter and 450 mm diameter, among others, such as display or solar cell substrates as well.

[0031] The chamber body 105 may support a chamber lid assembly 110 to enclose the chamber volume 101. The chamber body 105 may be fabricated from aluminum or other suitable materials. A substrate access port 113 may be formed through the sidewall 112 of the chamber body 105, facilitating the transfer of the substrate 302 into and out of the plasma processing chamber 100. The access port 113 may be coupled with a transfer chamber and / or other chambers of a substrate processing system as previously described. A pumping port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber volume 101. A pumping device may be coupled through the pumping port 145 to the chamber volume 101 to evacuate and control the pressure within the processing volume. The pumping device may include one or more pumps and throttle valves.

[0032] A gas panel 160 may be coupled by a gas line 167 with the chamber body 105 to supply process gases into the chamber volume 101. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164 and may additionally include inert gases, non-reactive gases, and reactive gases, as may be utilized for any number of processes. Examples of process gases that may be provided by the gas panel 160 include, but are not limited to, hydrocarbon containing gas including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon containing gas, argon gas, chlorine, nitrogen,PCT / US25 / 10733 08 January 2025 (08.01.2025)helium, or oxygen gas, as well as any number of additional materials. Additionally, process gasses may include nitrogen, chlorine, fluorine, oxygen, and hydrogen containing gases such as H2, NH3, H2O, H2O2, NF3, HF, F2, Ch, CF4, CHF3, C2F6, C2F4, C3F6, C4F6, C4F8, BrF3, CIF3, SF6, XeF2, CH3F, CH2F2, PF3, BCh, SiCh, SiCl4, ClF3.H2SiCl2.PH3, COS, and SO2, among any number of additional precursors.

[0033] Valves 166 may control the flow of the process gases from the sources 161, 162, 163, 164 from the gas panel 160 and may be managed by a controller 165. The flow of the gases supplied to the chamber body 105 from the gas panel 160 may include combinations of the gases form one or more sources. The lid assembly 110 may include a nozzle 114. The nozzle 114 may be one or more ports for introducing the process gases from the sources 161, 162, 164, 163 of the gas panel 160 into the chamber volume 101. After the process gases are introduced into the plasma processing chamber 100, the gases may be energized to form plasma. An antenna 148, such as one or more inductor coils, may be provided adjacent to the plasma processing chamber 100. An antenna power supply 142 may power the antenna 148 through a match circuit 141 to inductively couple energy, such as RF energy, to the process gas to maintain a plasma formed from the process gas in the chamber volume 101 of the plasma processing chamber 100. Alternatively, or in addition to the antenna power supply 142, process electrodes below the substrate 302 and / or above the substrate 302 may be used to capacitively couple RF power to the process gases to maintain the plasma within the chamber volume 101. The operation of the power supply 142 may be controlled by a controller, such as controller 165, that also controls the operation of other components in the plasma processing chamber 100.

[0034] A substrate support pedestal 135 may be disposed in the chamber volume 101 to support the substrate 302 during processing. The substrate support pedestal 135 may include an electrostatic chuck (“ESC”) 122 for holding the substrate 302 during processing. The electrostatic chuck 122 may use the electrostatic attraction to hold the substrate 302 to the substrate support pedestal 135. The ESC 122 may be powered by an RF power supply 125 integrated with a match circuit 124. The ESC 122 may include an electrode 121 embedded within a dielectric body. The electrode 121 may be coupled with the RF power supply 125 and may provide a bias which attracts plasma ions, formed by the process gases in the chamber volume 101, to the ESC 122 and substrate 302 seated on the pedestal. The RF power supply 125 may cycle on and off, or pulse, during processing of the substrate 302. The ESC 122 may have an isolator 128 for the purpose of making the sidewall of the ESC 122PCT / US25 / 10733 08 January 2025 (08.01.2025)less attractive to the plasma to prolong the maintenance life cycle of the ESC 122.Additionally, the substrate support pedestal 135 may have a cathode liner 136 to protect the sidewalls of the substrate support pedestal 135 from the plasma gases and to extend the time between maintenance of the plasma processing chamber 100.

[0035] Electrode 121 may be coupled with a power source 150. The power source 150 may provide a chucking voltage of about 500 volts to about 15,000 volts to the electrode 121. The power source 150 may also include a system controller for controlling the operation of the electrode 121 by directing a DC current to the electrode 121 for chucking and dechucking the substrate 302. For example, similar to the RF power supply 125, power supply 150 may provide a bias which attracts plasma ions, formed by the process gases in the chamber volume 101, to the ESC 122 and substrate 302 seated on the pedestal. The power supply 150 may cycle on and off, or pulse, during processing of the substrate 302. In embodiments, the power supply 150 may supply RF power, DC current or voltage for chucking and / or bias, or a combination thereof. In additional embodiments, multiple power supplies may be configured to supply RF power and DC current or voltage for chucking and / or bias. The ESC 122 may include heaters disposed within the pedestal and connected to a power source for heating the substrate, while a cooling base 129 supporting the ESC 122 may include conduits for circulating a heat transfer fluid to maintain a temperature of the ESC 122 and substrate 302 disposed thereon. The ESC 122 may be configured to perform in the temperature range required by the thermal budget of the device being fabricated on the substrate 302. For example, the ESC 122 may be configured to maintain the substrate 302 at a temperature of about -150 °C or lower to about 500 °C or higher depending on the process being performed.

[0036] The cooling base 129 may be provided to assist in controlling the temperature of the substrate 302. To mitigate process drift and time, the temperature of the substrate 302 may be maintained substantially constant by the cooling base 129 throughout the time the substrate 302 is in the cleaning chamber. In some embodiments, the temperature of the substrate 302 may be maintained throughout subsequent cleaning processes at temperatures between about -150 °C and about 500 °C, although any temperatures may be utilized. A cover ring 130 may be disposed on the ESC 122 and along the periphery of the substrate support pedestal 135. The cover ring 130 may be configured to confine etching gases to a desired portion of the exposed top surface of the substrate 302, while shielding the top surface of the substrate support pedestal 135 from the plasma environment inside the plasmaPCT / US25 / 10733 08 January 2025 (08.01.2025)processing chamber 100. Lift pins may be selectively translated through the substrate support pedestal 135 to lift the substrate 302 above the substrate support pedestal 135 to facilitate access to the substrate 302 by a transfer robot or other suitable transfer mechanism as previously described.5

[0037] The controller 165 may be utilized to control the process sequence, regulating the gas flows from the gas panel 160 into the plasma processing chamber 100, and other process parameters. Software routines, when executed by the CPU, transform the CPU into a specific purpose computer such as a controller, which may control the plasma processing chamber 100 such that the processes are performed in accordance with the present disclosure. The 10 software routines may also be stored and / or executed by a second controller that may be associated with the plasma processing chamber 100.

[0038] The chamber discussed previously may be used in performing exemplary methods, including etching methods, although any number of chambers may be configured to perform one or more aspects used in embodiments of the present technology. Turning to FIG. 3A, exemplary operations in a method 300 according to embodiments of the present technology are shown. Method 300 may include one or more operations prior to the initiation of the method, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The methods may include a number of optional operations, which may or may not be specifically associated 20 with some embodiments of methods, according to embodiments of the present technology.For example, many of the operations are described in order to provide a broader scope of the processes performed, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below. Method 300 may describe operations show n schematically in FIGS. 4A-4D, the illustrations of which will be described in conjunction with the operations of method 300. It is to be understood that the figures illustrate only partial schematic views, and a substrate may contain any number of additional materials and features having a variety of characteristics and aspects as illustrated in the figures.

[0039] Method 300 may or may not involve optional operations to develop the30 semiconductor structure for a particular fabrication operation. It is to be understood that method 300 may be performed on any number of semiconductor structures 400 or substrates 405, as illustrated in FIG. 4A, including exemplary structures on which a silicon-containingPCT / US25 / 10733 08 January 2025 (08.01.2025)material (e.g., amorphous silicon, poly crystalline silicon, silicon-and-oxy gen-containing material, silicon-containing material, silicon-and-carbon-containing material, or any other silicon-containing material) etching operation may be performed. As illustrated in FIG. 4A, substrate 405 may include a layer of silicon-containing material 410. The layer of silicon-containing material 410 may overlie the substrate 405. Additionally, to allow for one or more holes or trenches to be formed through the layer of silicon-containing material 410, a mask material 415 may overlie the layer of silicon-containing material 410. The mask material 415 may be patterned to form one or more apertures 420, exposing a portion of the underlying layer of silicon-containing material 410. Although only a single aperture 420 is illustrated, it is to be understood that exemplary structure 400 may include any number of apertures across the substrate 405. Some or all of these operations may be performed in chambers or system tools as previously described, or may be performed in different chambers on the same system tool, which may include the chamber in which the operations of method 300 are performed.

[0040] Method 300 may be performed to etch or otherwise remove portions of the layer of silicon-containing material 410, which may form holes or trenches in the structure 400 as illustrated. The method 300 may be performed to facilitate control of the profile through the structure, and improve etch characteristics, such as uniformity of the holes or trenches as the etch progresses into the layer of silicon-containing material 410. Method 300 may include providing a halogen-containing precursor and an inert gas into a processing region of the semiconductor processing chamber in which the substrate 405 is housed at operation 305. The substrate 405, including the layer of silicon-containing material 410, may be contacted with the halogen-containing precursor and the inert gas at operation 310. As illustrated in FIG. 4B, the contacting at operation 310 may form a halogenated portion of the layer of silicon-containing material 425. Subsequent a first period of time, operation 315 of method 300 may include applying a source power and a bias power or a bias voltage while continuing to contact the layer of silicon-containing material 410 with the halogen-containing precursor and the inert gas for a second period of time. As illustrated in FIG. 4C, the contacting at operation 315 to desorb the halogenated portion of the layer of silicon-containing material 425. Method 300 may include cycling operations 310 and 315, by pulsing the source power and the bias power or the bias voltage, such as synchronously, to etch a feature 430 into the layer of silicon-containing material 410. The cycling of operations 310 and 315 may be repeated any number of times to etch a desired amount of the layer of silicon-containingPCT / US25 / 10733 08 January 2025 (08.01.2025)material 410. For example, and as illustrated in FIG. 4D, operations 310 and 315 may be cycled until the feature 430 extends to the substrate 405.

[0041] Halogen-containing precursors provided at operation 305 may include any halogen, and may be or include a fluorine-containing precursor, a chlorine-containing precursor, a 5 bromine-containing precursor, or any other halogen-containing precursor. In an exemplary embodiment, the halogen-containing precursor may be a chlorine-containing precursor. For example, the chlorine-containing precursor may be or include atomic chlorine (C), diatomic chlorine (Cb), chlorine trifluoride (CIF3), di chlorosilylene (SiCh), dichlorosilane (H2SiCh), silicon tetrachloride (SiCU), or any other chlorine-containing precursor used or useful in 10 semiconductor processing. Other halogen-containing precursors may be or include, for example, hydrogen fluoride (HF), nitrogen trifluoride (NF3), diatomic fluorine (F2), bromine trifluoride (BrFs). sulfur hexafluoride (SFe), xenon difluoride (XeF2), carbon tetrafluoride (CF4), or any organofluoride, or any other halogen-containing precursor used or useful in semiconductor processing.

[0042] A flow rate of the halogen-containing precursor may be between about 5 seem and about 500 seem. While higher flow rates of the halogen-containing precursor, such as greater than or about 500 seem, are contemplated, these higher flow rates may result in increased halogenation and / or halogen incorporation in the structure 400. As such, the flow rate of the halogen-containing precursor may be less than or about 500 seem, and may be less than or 20 about 450 seem, less than or about 400 seem, less than or about 350 seem, less than or about 300 seem, less than or about 275 seem, less than or about 250 seem, less than or about 225 seem, less than or about 200 seem, less than or about 175 seem, less than or about 150 seem, less than or about 140 seem, less than or about 130 seem, less than or about 125 seem, less than or about 120 seem, less than or about 110 seem, less than or about 100 seem, less than or about 75 seem, less than or about 50 seem, less than or about 25 seem, or less. However, at reduced flow rates, halogenation may be reduced and may increase the number of cycles needed to etch the layer of silicon-containing material 410. As such, the flow rate of the halogen-containing precursor may be greater than or about 5 seem, and may be greater than or about 25 seem, greater than or about 50 seem, greater than about 60 seem, greater than or 30 about 70 seem, greater than about 80 seem, greater than or about 90 seem, greater than about 100 seem, or more.PCT / US25 / 10733 08 January 2025 (08.01.2025)

[0043] Inert gases provided with the halogen-containing precursor at operation 305 may include nitrogen (N2), argon (Ar), helium (He), xenon (Xe), or other noble gases, or any chemically inert material used or useful in semiconductor processing. The inert gas may be provided to dilute and / or distribute the halogen-containing precursor, which may reduce 5 halogenation of the silicon-containing material at operation 310. At operation 315, an increased amount of the inert gas relative to the halogen-containing precursor may result in efficient desorption of the halogenated portion of the layer of silicon-containing material 425.

[0044] A flow rate of the inert gas may be between about 5 seem and about 1,000 seem. For example, the flow rate of the inert gas may be greater than or about 5 seem, and may be greater than or about 25 seem, greater than or about 50 seem, greater than or about 75 seem, greater than or about 100 seem, greater than or about 125 seem, greater than or about 150 seem, greater than or about 200 seem, greater than or about 250 seem, greater than about 500 seem, greater than or about 750 seem, greater than or about 1,000 seem, or more. However, at increased flow rates of the inert gas, halogenation may be reduced and may increase the 15 number of cycles needed to etch the layer of silicon-containing material 410. As such, the flow rate of the halogen-containing precursor may be less than or about 500 seem, and may be less than or about 400 seem, less than or about 300 seem, less than about 250 seem, less than or about 200 seem, less than about 150 seem, less than or about 125 seem, less than about 100 seem, or less.20

[0045] In embodiments, a flow rate ratio of the halogen-containing precursor relative to the inert gas may be controlled to balance halogenation and subsequent desorption that results in etching. For example, the flow rate ratio of the halogen-containing precursor relative to the inert gas is less than or about 5:1, and may be less than or about 4:1, less than or about 3:1, less than or about 2.5:1, less than or about 2:1, less than or about 1.5:1, less than or about 1:1, less than or about 0.95: 1, less than or about 0.9: 1, less than or about 0.85: 1, less than or about 0.8:1, less than or about 0.75:1, less than or about 0.7:1, less than or about 0.65:1, less than or about 0.6:1, less than or about 0.55:1, less than or about 0.5:1, less than or about 0.45:1, less than or about 0.4:1, less than or about 0.35: 1, less than or about 0.3:1, less than or about 0.25: 1, or less. At these reduced flow rate ratios of the halogen-containing precursor relative 30 to the inert gas, halogenation may be reduced and may result in an atomic layer etching (ALE)-type removal of the layer of silicon-containing material 410, such that a monolayer or a fractional monolayer (i.e., less than an entire or continuous monolayer) may be halogenated and subsequently removed.PCT / US25 / 10733 08 January 2025 (08.01.2025)

[0046] The contacting at operation 310 may continue the first period of time, which be sufficient to at least partially halogenate a portion of the layer of silicon-containing material 410. As illustrated in FIG. 4B, the contacting may form the halogenated portion of the layer of silicon-containing material 425. The first period of time may proceed without any 5 application of source power, bias power, and / or bias voltage. Without application of source power, bias power, and / or bias voltage, ion bombardment may be limited. Instead, the first period of time at operation 310 may mainly result in chemisorption of the halogen-containing precursor to form the halogenated portion of the layer of silicon-containing material 425. In subsequent cycles of operations 310 and 315, the first period of time may be referred to as an 10 afterglow state (or OFF state), such as after the second period of time in which source power, bias power, and / or bias voltage are applied. Ions from the second period of time may quickly decay, while radicals may more slowly decay. As such, even though the first period of time may proceed without any application of source power, bias power, and / or bias voltage, some residual ions and / or radicals may be present during the first period of time.

[0047] The first period of time may be between about 1 ms and about 100 ms. In embodiments, a duration of the first period of time may be related to a timing of radical decay. As the first period of time may be driven by the chemisorption of halogen-containing radicals to the layer of silicon-containing material 410, once the halogen-containing radicals have decayed, chemisorption may reduce and / or even halt. As such, the first period of time 20 may be greater than or about 4 ms, and may be greater than or about 6 ms, greater than or about 8 ms, greater than or about 10 ms, greater than or about 12 ms, greater than or about 14 ms, greater than or about 16 ms, greater than or about 18 ms, greater than or about 20 ms, or more. Conversely, the first period of time may be less than or about 55 ms, and may be less than or about 45 ms, less than or about 40 ms, less than or about 35 ms, less than or about 30 ms, less than or about 28 ms, less than or about 26 ms, less than or about 24 ms, less than or about 22 ms, less than or about 20 ms, or less.

[0048] The halogenated portion of the layer of silicon-containing material 425 may be characterized by a thickness of less than or about 2 A. In embodiments, the halogenation and subsequent removal may proceed on an ALE-type basis. As such, the halogenated portion of 30 the layer of silicon-containing material 425 may be a monolayer or a fractional monolayer of the layer of silicon-containing material 410. In embodiments, the halogenated portion of the layer of silicon-containing material 425 may be characterized by a thickness of less than or about 1.9 A, and may be characterized by a thickness of less than or about 1.8 A, less than orPCT / US25 / 10733 08 January 2025 (08.01.2025)about 1.7 A, less than or about 1.6 A, less than or about 1.5 A, less than or about 1.4 A, or less. Additionally, with efficient halogenation, the halogenated portion of the layer of silicon-containing material 425 may be characterized by a thickness of greater than or about 0.9 A, and may be characterized by a thickness of greater than or about 1 A, greater than or 5 about 1.1 A, greater than or about 1.2 A, greater than or about 1.3 A, greater than or about 1.4 A, or more.

[0049] Subsequent to halogenation a portion of the layer of silicon-containing material 410, and as illustrated in FIG. 4C, operation 315 of method 300 may include desorbing the halogenated portion of the layer of silicon-containing material 425 over the second period of 10 time. At operation 315, method 300 may include applying a source power and either a bias power or bias voltage. The application of source power may form plasma effluents, including both ions and radicals, of the halogen-containing precursor and / or the inert precursor. The second period of time may be referred to as an activeglow state (or ON state). The application of bias power or bias voltage may draw the plasma effluents, such as ions, of the halogen-containing precursor and / or the inert precursor to the substrate 405. By drawing the plasma effluents of the halogen-containing precursor and / or the inert precursor to the substrate 405, ions in the plasma effluents may bombard the substrate 405, including the halogenated portion of the layer of silicon-containing material 425. This bombardment may result in the halogenated portion of the layer of silicon-containing material 425 being 20 desorbed, such that a portion of the layer of silicon-containing material 410 is etched from the structure 400.

[0050] The duration of the second period of time may be less than the duration of the first period of time. The bombardment during the second period of time may desorb the halogenated portion of the layer of silicon-containing material 425 relatively quickly compared to halogenation during the first period of time. At increased durations of the second period of time, the halogenated portion of the layer of silicon-containing material 425 may be removed, and the plasma effluents, including ions in the plasma effluents, may continue to bombard the structure 400 and may damage other materials. As such, the second period of time may be between about 0.1 ms and about 5 ms. For example, the second period 30 of time may be less than or about 4.5 ms, and may be less than or about 4 ms, less than or about 3.5 ms, less than or about 3 ms, less than or about 2.5 ms, less than or about 2 ms, less than or about 1.5 ms, less than or about 1 ms, less than or about 0.8 ms, less than or about 0.6 ms, less than or about 0.4 ms, less than or about 0.2 ms, or less. Conversely, to ensure thePCT / US25 / 10733 08 January 2025 (08.01.2025)halogenated portion of the layer of sih con-containing material 425 is desorbed, the second period of time may be greater than or about 0.2 ms, and may be greater than or about 0.4 ms, greater than or about 0.6 ms, greater than or about 0.8 ms, greater than or about 1 ms, greater than or about 1.5 ms, greater than or about 2 ms, greater than or about 2.5 ms, greater than or 5 about 3 ms, greater than or about 3.5 ms, greater than or about 4 ms, greater than or about 4.5 ms, greater than or about 5 ms, or more.

[0051] The source power applied during operation 315 may be selected to control dissociation while maintaining a desired radical density. While reduced source powers may limit dissociation, increased source powers may increase radical density. As previously 10 discussed, an increased radical density may improve halogenation during the first periods of time at operation 310. As such, the source power may be applied at between about 10 W and about 1,000 W. For example, to control dissociation, the source power may be applied at less than or about 1,000 W, and may be applied at less than or about 750 W, less than or about 500 W, less than or about 400 W, less than or about 300 W, less than or about 250 W, less than or about 200 W, less than or about 175 W, less than or about 150 W, less than or about 125 W, less than or about 100 W, or less. Conversely, to maintain a desired radical density, the source power may be applied at greater than or about 10 W, and may be applied at greater than or about 25 W, greater than or about 50 W, greater than or about 60 W, greater than or about 70 W, greater than or about 80 W, greater than or about 90 W, greater than or about 20 100 W, greater than or about 125 W, greater than or about 150 W, greater than or about 175 W, greater than or about 200 W, or more.

[0052] Together with the source power, the bias power and / or bias voltage may be applied during operation 315. The bias power and / or bias voltage applied during operation 315, similar to the source power, may be selected to control bombardment. More specifically, the bias power and / or bias voltage may be selected to balance removal of the halogenated portion of the layer of silicon-containing material 425 while limiting damage, such as through sputtering, of other materials in structure 400. In embodiments, the bias power may be applied as, for example, a 2 MHz frequency to the pedestal or substrate support. The bias power may be applied at between about 100 W and about 1,000 W. For example, the bias 30 power may be applied at less than or about 900 W, less than or about 800 W, less than about 750 W, less than about 700 W, less than or about 650 W, less than or about 600 W, less than or about 550 W, less than or about 500 W, less than or about 450 W, less than or about 400 W, or less. Conversely, the bias power may be applied at greater than or about 100 W, andPCT / US25 / 10733 08 January 2025 (08.01.2025)may be applied at greater than or about 200 W, greater than or about 250 W, greater than or about 300 W, greater than or about 350 W, greater than or about 400 W, greater than or about 450 W, greater than or about 500 W, or more.

[0053] In embodiments, the bias voltage may be a voltage applied to the pedestal or substrate support at a frequency of between about 100 kHz and about 500 kHz. The bias voltage may be applied at between about 0.1 kV and about 2.0 kV. For example, the bias voltage may be applied at less than or about 2.0 kV, and may be applied at less than or about 1.9 kV, less than or about 1.8 kV, less than or about 1.7 kV, less than or about 1.6 kV, less than or about 1.5 kV, less than or about 1.4 kV, less than or about 1.3 kV, or less.Conversely, the bias voltage may be applied at greater than or about 0.1 kV, and may be applied at greater than or about 0.2 kV, greater than or about 0.3 kV, greater than or about 0.4 kV, greater than or about 0.5 kV, greater than or about 0.6 kV, greater than or about 0.7 kV, greater than or about 0.8 kV, greater than or about 0.9 kV, greater than or about 1.0 kV, greater than or about 1.1 kV, greater than or about 1.2 kV, greater than or about 1.3 kV, greater than or about 1.4 kV, greater than or about 1.5 kV, or more.

[0054] As previously discussed, operations 310 and 315 may be cycled to provide an amount of halogenation to form the halogenated portion of the layer of silicon-containing material 425 followed by desorption of the halogenated portion of the layer of silicon-containing material 425 to iteratively etch the layer of silicon-containing material 410. In embodiments, the cycling may be achieved by pulsing the source power and the bias power or bias voltage. As such, the source power and the bias power or bias voltage may be synchronized, such that when the source power is on, the bias power or bias voltage is also on, or while the source power is off, the bias power or bias voltage is also off. When the source power (and bias power or bias voltage) is off, the halogen-containing precursor and inert gas may be contacting the substrate 405, including the layer of silicon-containing material 410, during the first period of time at operation 310. Conversely, when the source power (and bias power or bias voltage) is on, plasma effluents of the halogen-containing precursor and inert gas may be contacting the substrate 405, including the halogenated portion of the silicon-containing material 425, during the second period of time at operation 315. While the source power and the bias power or bias voltage may be synchronized, it is also contemplated that the source power and the bias power (or bias voltage) may be operated independently and without the other.PCT / US25 / 10733 08 January 2025 (08.01.2025)

[0055] In embodiments, the first period of time at operation 310 and the second period of time at operation 315 may be dictated by a duty cycle of the source power and the bias power (or bias voltage). Duty cycle may refer to a portion of time in which the source power and the bias power (or bias voltage) are on or in the second period of time. As the chemisorption 5 of halogen material may occur at a relatively decreased rate compared to the subsequent desorption, the duty cycle may be relatively low to allow for adequate halogenation. In embodiments, the duty cycle may be between about 0.1% and about 40%. For example, the duty cycle may be less than or about 35%, and may be less than or about 30%, less than or about 25%, less than or about 20%, less than or about 15%, less than or about 10%, less than 10 or about 8%, less than or about 6%, less than or about 5%, less than or about 4%, less than or about 3%, less than or about 2%, less than or about 1%, less than or about 0.8%, less than or about 0.6%, less than or about 0.4%, less than or about 0.2%, or less.

[0056] Pulsing frequency of the source power and / or the bias power (or bias voltage) may be less than or about 1 kHz. In embodiments, the pulsing frequency may be less than or about 750 Hz, and may be less than or about 500 Hz, less than or about 250 Hz, less than or about 100 Hz, less than or about 75 Hz, less than or about 50 Hz, less than or about 40 Hz, less than or about 30 Hz, less than or about 25 Hz, less than or about 20 Hz, less than or about 15 Hz, less than or about 10 Hz, or less. Pulsing frequency, in combination with duty cycle, may dictate the duration of activeglow and afterglow states. As such, the pulsing frequency, 20 in combination with duty cycle, may control chemisorption of halogen-containing radicals to the layer of silicon-containing material 410 and desorption of the halogenated portion of the layer of silicon-containing material 425.

[0057] Operations 310 and 315 may be repeated for any number of cycles. With an increased number of cycles, a depth of the resultant feature 430 may increase. In embodiments, operations 310 and 315 may be repeated for two cycles, ten cycles, twenty-five cycles, fifty cycles, one hundred cycles, five hundred cycles, or more.

[0058] FIG. 3B illustrates an exemplary pulsing scheme 350 that may be utilized in method 300. Periods of time between ti and t2, t3 and t4, ts and t6, and so on may correspond with operation 315 of method 300, such as the activeglow state (or ON state). More30 specifically, between ti and t2, 13 and U, and ts and te, source power and either bias power or bias voltage may be applied. As previously discussed, application of source power may form plasma effluents, including both ions and radicals, of the halogen-containing precursor and / orPCT / US25 / 10733 08 January 2025 (08.01.2025)the inert precursor. The application of bias power or bias voltage may draw the plasma effluents, such as ions, of the halogen-containing precursor and / or the inert precursor to the substrate 405. By drawing the plasma effluents of the halogen-containing precursor and / or the inert precursor to the substrate 405, ions in the plasma effluents may bombard the 5 substrate 405, including the halogenated portion of the layer of silicon-containing material 425. This bombardment may result in the halogenated portion of the layer of silicon- containing material 425 being desorbed, such that a portion of the layer of silicon-containing material 410 is etched from the structure 400.

[0059] Conversely, periods of time between t2 and ts, t4 and ts, and so on may correspond with operation 310 of method 300, such as the afterglow state (or OFF state) of method 300. More specifically, between t2 and t3 and t4 and ts, source power and either bias power or bias voltage may not be applied. As previously discussed, without application of source power, bias power, and / or bias voltage, ion bombardment may be limited. With limited ion bombardment, the halogen-containing precursor may be chemisorbed to form the halogenated 15 portion of the layer of silicon-containing material 425.

[0060] While illustrated with the source power and bias power (or bias voltage) initially being in the ON state, it is also contemplated, such as previously discussed, that the source power and bias power (or bias voltage) may initially be in the OFF state. In such embodiments, limited or not etching of the layer of silicon-containing material 410 may 20 result, as there is no halogenated portion of the layer of silicon-containing material 425 to be desorbed.

[0061] Finally, while FIG. 3B illustrates the source power and the bias power (or bias voltage) being synchronized, such that the two are either both in the ON state or OFF state, it is contemplated that the source power and the bias power (or bias voltage) may not be perfectly synchronized, such that one of the source power or the bias power (or bias voltage) may be in the ON state while the other is in the OFF state.

[0062] The resultant feature 430 may be characterized by any depth or aspect ratio as desired. As previously discussed, and as illustrated in FIG. 4D, embodiments may include etching the feature 430 to expose the underlying substrate 405, or an underlying material. In 30 embodiments, a depth of the feature 430 may be greater than or about 20 nm, and may be greater than or about 30 nm, greater than or about 40 nm, greater than or about 50 nm, greater than or about 75 nm, greater than or about 100 nm, greater than or about 150 nm, greater thanPCT / US25 / 10733 08 January 2025 (08.01.2025)or about 200 nm, or more. An aspect ratio, or ratio of length to width of the feature 430, may be greater than or about 2: 1 , and may be greater than or about 3:1, greater than or about 4: 1 , greater than or about 5:1, greater than or about 6:1, greater than or about 7:1, greater than or about 8:1, greater than or about 9:1, greater than or about 10:1, or more.

[0063] In embodiments, the layer of silicon-containing material 410 may be etched at a rate of greater than or about 2 nm / min, and may be etched at a rate of greater than or about 2.2 nm / min, greater than or about 2.4 nm / min, greater than or about 2.6 nm / min, greater than or about 2.8 nm / min, greater than or about 3.0 nm / min, greater than or about 3.1 nm / min, greater than or about 3.2 nm / min, greater than or about 3.3 nm / min, greater than or about 3.4 nm / min, or more. Conversely, conventional ALE technologies may only be able to etch silicon-containing material at a rate of, for example, less than or about 0.3 nm / min, such as 0.25 nm / min, or less.

[0064] Process conditions may also impact the operations performed in method 300. Each of the operations of method 300 may be performed during a constant temperature in embodiments, while in some embodiments the temperature may be adjusted during different operations. Temperatures may be maintained in any range, however, at reduced temperatures, etch byproduct redeposition may increase. Conversely, at increased temperatures, byproduct redeposition may be reduced. As such, during any or all operations of the method 300, a temperature within the processing region may be maintained between about 0 °C and about 250 °C. For example, the temperature within the processing region may be maintained at greater than or about 0 °C, and may be maintained at greater than or about 10 °C, greater than or about 20 °C, greater than or about 30 °C, greater than or about 40 °C, greater than or about 50 °C, greater than or about 75 °C, greater than or about 100 °C, greater than or about 150 °C, greater than or about 200 °C, greater than or about 250 °C, or more. Conversely, the temperature within the processing region may be maintained at less than or about 250 °C, and may be maintained at less than or about 200 °C, less than or about 150 °C, less than or about 100 °C, less than or about 90 °C, less than or about 80 °C, less than or about 70 °C, less than or about 60 °C, less than or about 50 °C, less than or about 25 °C, or less.

[0065] Each of the operations of method 300 may be performed during a constant pressure. However, it is also contemplated that the pressure may be adjusted during different operations. Pressures may be maintained in any range, however, at reduced pressures, radicalPCT / US25 / 10733 08 January 2025 (08.01.2025)density of the plasma effluents formed during the second periods of time may reduce.Conversely, at increased pressures, radical density of the plasma effluents formed during the second period of time may increase, which may better halogenate a portion of the layer of silicon-containing material 410 during the subsequent first periods of time. As such, a pressure within the processing region may be maintained at between about 1 mTorr and about 1 Torr. For example, the pressure within the processing region may be maintained at greater than or about 1 mTorr, and may be maintained at greater than or about 3 mTorr, greater than or about 5 mTorr, greater than or about 7 mTorr, greater than or about 10 mTorr, greater than or about 12 mTorr, greater than or about 15 mTorr, greater than or about 20 mTorr, greater than or about 30 mTorr, greater than or about 40 mTorr, greater than or about 50 mTorr, greater than or about 75 mTorr, greater than or about 100 mTorr, greater than or about 250 mTorr, or more. Conversely, the pressure within the processing region may be maintained at less than or about 1 Torr, and may be maintained at less than or about 750 mTorr, less than or about 500 mTorr, less than or about 250 mTorr, less than or about 100 mTorr, less than or about 75 mTorr, less than or about 50 mTorr, less than or about 40 mTorr, less than or about 30 mTorr, less than or about 25 mTorr, less than or about 20 mTorr, less than or about 18 mTorr, less than or about 16 mTorr, less than or about 15 mTorr, or less.

[0066] In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details.

[0067] Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology. Additionally, methods or processes may be described as sequential or in steps, but it is to be understood that the operations may be performed concurrently, or in different orders than listed.

[0068] Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed.PCT / US25 / 10733 08 January 2025 (08.01.2025)Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller 5 ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0069] As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “a precursor” includes a plurality of such precursors, and reference to “the layer” includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth. “About” and / or “approximately” as used herein when referring to a measurable value such as an amount, a temporal duration, and the like, encompasses variations of ±20% or ±10%, ±5%, or ±0.1% from the specified value, as such variations are appropriate to in the context of the systems, devices, circuits, methods, and other implementations described herein. “Substantially” as used herein when referring to a measurable value such as an amount, a temporal duration, a physical attribute (such as frequency), and the like, also encompasses variations of ±20% or ±10%, ±5%, or ±0.1% from the specified value, as such variations are appropriate to in the context of the systems, devices, circuits, methods, and other implementations described herein.

[0070] Also, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, 25 components, operations, acts, or groups.

Claims

PCT / US25 / 10733 08 January 2025 (08.01.2025)CLAIMS:

1. A semiconductor processing method comprising:i) providing a halogen-containing precursor and an inert gas to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein a layer of silicon-containing material overlies the substrate;ii) contacting the layer of silicon-containing material with the halogencontaining precursor and the inert gas for a first period of time to form a halogenated portion of the layer of silicon-containing material;iii) subsequent to the first period of time, applying a source power and a bias power or a bias voltage while continuing to contact the layer of silicon-containing material with the halogen-containing precursor and the inert gas for a second period of time to desorb the halogenated portion of the layer of silicon-containing material; andiv) repeating operations ii and iii to etch a feature into the layer of silicon-containing material.

2. The semiconductor processing method of claim 1, wherein the halogen-containing precursor comprises a chlorine-containing precursor.

3. The semiconductor processing method of claim 1, wherein the halogen-containing precursor comprises diatomic chlorine (Ch).

4. The semiconductor processing method of claim 1, wherein the inert gas comprises argon (Ar).

5. The semiconductor processing method of claim 1, wherein a flow rate of the halogen-containing precursor is less than or about 300 seem.

6. The semiconductor processing method of claim 1, wherein a flow rate ratio of the halogen-containing precursor relative to the inert gas is less than or about 1:1.

7. The semiconductor processing method of claim 1, wherein the layer of silicon-containing material comprises amorphous silicon or poly crystalline silicon.

8. The semiconductor processing method of claim 1, wherein the source power is applied at less than or about 750 W.PCT / US25 / 10733 08 January 2025 (08.01.2025)9. The semiconductor processing method of claim 1, wherein the bias power is applied at less than or about 1,000 W or the bias voltage is applied at less than or about 2.0 kV.

10. The semiconductor processing method of claim 1, wherein the first period of time is greater than the second period of time.

11. The semiconductor processing method of claim 1, wherein the first period of time is greater than or about 20 milliseconds.

12. The semiconductor processing method of claim 1, wherein a temperature within the processing region is maintained at greater than or about 0 °C.

13. The semiconductor processing method of claim 1, wherein a pressure within the processing region is maintained at less than or about 1 Torr.

14. A semiconductor processing method comprising:providing a halogen-containing precursor and an inert gas to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein a layer of silicon-containing material overlies the substrate; andcontacting the layer of silicon-containing material with the halogen-containing precursor and the inert gas while pulsing a source power and a bias power or a bias voltage, wherein:the source power and the bias power or the bias voltage are off while chemisorbing the halogen-containing precursor to form a halogenated portion of the layer of silicon-containing material; andthe source power and the bias power or the bias voltage are on while desorbing halogenated portion of the layer of silicon-containing material.

15. The semiconductor processing method of claim 14, wherein the source power and the bias power or the bias voltage are synchronized.

16. The semiconductor processing method of claim 14, wherein a duty cycle of each of the source power and the bias power or the bias voltage is less than or about 40%.PCT / US25 / 10733 08 January 2025 (08.01.2025)17. The semiconductor processing method of claim 14, wherein a pulsing frequency of each of the source power and the bias power is less than or about 1 kHz.

18. A semiconductor processing method comprising:i) providing a chlorine-containing precursor and an inert gas to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein a layer of silicon material overlies the substrate;ii) contacting the layer of silicon material with the chlorine-containing precursor and the inert gas without applying a source power and a bias power or a bias voltage for a first period of time to form a halogenated portion of the layer of silicon material;iii) subsequent to the first period of time, applying the source power and the bias power or the bias voltage while continuing to contact the layer of silicon material with the chlorine-containing precursor and the inert gas for a second period of time to desorb the halogenated portion of the layer of silicon material; andiv) repeating operations ii and iii to etch a feature into the layer of silicon material, wherein the source power and the bias power or the bias voltage are pulsed between an OFF state during the first period of time and an ON state during the second period of time.

19. The semiconductor processing method of claim 18, wherein the halogenated portion of the layer of silicon material is characterized by a thickness of less than or about 1.7 A.

20. The semiconductor processing method of claim 18, wherein a temperature within the processing region is maintained at greater than or about 25 °C.

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