Display device

Abstract

A display device, comprising a plurality of stages of cascaded gate driving sub-circuits, at least one stage of redundant driving sub-circuit (Dummy GOA), a plurality of metal pads, a plurality of metal lines, and at least one power supply line. A first gate driving signal output terminal (Pout[n]), a second gate driving signal output terminal (Nout[n]), and a cascade signal output terminal (Pc[n]) of the redundant driving sub-circuit (Dummy GOA) are electrically connected to a first metal pad (B1), a second metal pad (B2), and a third metal pad (B3) via a first metal line (A1), a second metal line (A2), and a third metal line (A3), respectively. At least one of the first metal line (A1) and the second metal line (A2) forms a capacitor with the power supply line (VDD / VGH / VSS / VGL). Thus, the reliability of testing for the display device is improved.

Description

Display device Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] In the field of display technology, complementary metal-oxide-semiconductor (CMOS) gate-driver-on-array (GOA) technology can achieve segmentation and frequency division. Compared with traditional gate-driver circuits, CMOS gate-driver circuits output three signals: one stage-transfer signal and two gate-drive signals. The stage-transfer signal serves as the trigger signal for the upper and lower stage gate-driver circuits, while the two gate-drive signals are used to drive the pixels.

[0003] However, when measuring the high and low voltage margins of the complementary metal-oxide-semiconductor (CMOS) gate drive circuit, the inventors discovered that the waveform output by the non-redundant gate drive circuit was normal, while the waveform output by the redundant gate drive circuit was abnormal. This anomaly occurred because the redundant gate drive circuit had no actual pixel load, only being connected to the metal traces used for testing, and the load of these metal traces was much lower than the load of the lines connected to the display area by the non-redundant gate drive circuit. This difference in load caused the output waveforms of the redundant and non-redundant gate drive circuits to be inconsistent. Furthermore, traditional gate drive circuit output testing methods can only test the gate drive signal output by the redundant gate drive circuit using a gate drive circuit output test pad, and cannot test the stage transmission signal. Because the stage transmission signal cannot be tested, even if the stage transmission signal of the redundant gate drive circuit is abnormal, it cannot be detected through testing, which may lead to misjudgment of the test results for the gate drive circuit. Invention Overview

[0004] The purpose of this application is to provide a display device that aims to improve the reliability of tests conducted on the display device.

[0005] Embodiments of this application provide a display device, including: a display panel, the display panel including: a multi-level cascaded gate driving sub-circuit for providing gate driving signals to pixels of the display panel; at least one level of redundant driving sub-circuit disposed on one side of the arrangement direction of the multi-level gate driving sub-circuit, the at least one level of redundant driving sub-circuit being cascaded with the at least one level of gate driving sub-circuit; a plurality of metal pads disposed on the edge of the display panel, the plurality of metal pads including at least a first metal pad, a second metal pad, and a third metal pad; and a plurality of metal lines, the plurality of metal lines including at least a first metal line, a second metal line, and a third metal line; wherein, the redundant driving sub-circuit includes a first gate driving signal output terminal, a second gate driving signal output terminal, and a cascade signal output terminal, the first gate driving signal output terminal being electrically connected to the first metal pad through the first metal trace, the second gate driving signal output terminal being electrically connected to the second metal pad through the second metal trace, and the cascade signal output terminal being electrically connected to the third metal pad through the third metal trace. Beneficial effects

[0006] In the display device provided by the present invention, by adding a third metal pad for testing the stage transmission signal at the edge of the display panel, and electrically connecting the stage transmission signal output terminal of the redundant drive sub-circuit to the third metal pad through a third metal wire, not only the gate drive signal output by the redundant drive sub-circuit can be tested, but also the stage transmission signal output by the redundant drive sub-circuit can be tested. This allows for comprehensive monitoring of the operating status of the gate drive circuit, avoids misjudgment of test results due to the inability to test the stage transmission signal, and significantly improves the reliability of testing for the display device.

[0007] Furthermore, by forming capacitors between the first and second metal lines and the power supply traces, the load on the first and second metal lines is increased, bringing them closer to the load on the lines connected to the display area of ​​the gate driver sub-circuit. Simultaneously, by adjusting the line width and thickness of the metal lines farther from the power supply traces to be smaller than those closer to the power supply traces, the parasitic capacitance difference caused by the distance difference with the power supply traces is compensated. This ensures that the load ratio of the first and second metal lines is within the range of 80% to 120%, allowing the test signal to accurately reflect the operating state of the gate driver circuit.

[0008] In addition, by making the load on the third metal line less than that on the first and second metal lines, the normal transmission of the stage signal is ensured, so that the test signal can truly reflect the working state of the gate drive circuit and avoid misjudgment of the test results. Attached Figure Description

[0009] Figure 1 is a schematic diagram of a display device provided in an embodiment of this application.

[0010] Figure 2 is a schematic diagram of the gate driving circuit in the display device provided in an embodiment of this application.

[0011] Figure 3 is a schematic diagram of the connection between the gate drive circuit and the metal pad shown in Figure 2.

[0012] Figure 4 is a circuit diagram of a first-stage gate driver sub-circuit or a first-stage redundant driver sub-circuit in the gate driver circuit shown in Figure 2. Embodiments of the present invention

[0013] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0014] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0015] The display device provided in the embodiments of this application may be, for example, an OLED display device, a Mini-LED display device, or a Micro-LED display device. The embodiments of this application will be described using an OLED display device as an example.

[0016] As shown in Figure 1, the display device provided in the embodiments of this application includes a display panel, a timing controller, a source drive circuit, and a power management chip (the power management chip can be integrated with the timing controller into the same chip). The display panel is an organic light-emitting diode (OLED) display panel.

[0017] The display panel includes a display area AA and a non-display area. The display area AA has an array of m×n pixel units PX, where m and n are integers greater than 1. The non-display area is located around the display area AA and is used to arrange driving circuits and various signal lines. The display panel also includes multiple scan lines (SCAN), multiple data lines (DATA), and a gate driving circuit. The multiple scan lines (SCAN) extend along a first direction and are arranged along a second direction, and the multiple data lines (DATA) extend along the second direction and are arranged along the first direction, with the first direction perpendicular to the second direction. The gate driving circuit is located in the non-display area and is electrically connected to the multiple scan lines (SCAN). The source driving circuit is electrically connected to the multiple data lines (DATA) via a flexible circuit board. A timing controller is electrically connected to both the gate driving circuit and the source driving circuit.

[0018] The display panel includes an organic light-emitting diode (OLED) array substrate and an encapsulation layer. The OLED array substrate includes a substrate, a buffer layer disposed on the substrate, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a first metal layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the first metal layer, a second metal layer disposed on the interlayer insulating layer, a planarization layer disposed on the second metal layer, a first electrode layer disposed on the planarization layer, a pixel defining layer disposed on the first electrode layer, an organic light-emitting layer disposed within an opening area defined by the pixel defining layer, and a second electrode layer disposed on the organic light-emitting layer. The first metal layer includes scan lines (SCAN), a gate electrode, etc. The second metal layer includes data lines (DATA), a source electrode, a drain electrode, etc. The encapsulation layer is sealed to the OLED array substrate to prevent moisture and oxygen from penetrating the organic light-emitting layer.

[0019] Each pixel unit (PX) includes a pixel driving circuit and an organic light-emitting diode (OLED). The pixel driving circuit includes at least two thin-film transistors (TFTs) and a storage capacitor. One TFT acts as a switching transistor, with its gate electrically connected to the corresponding scan line and its source electrically connected to the corresponding data line. The other TFT acts as a driving transistor, with its gate electrically connected to the drain of the switching transistor, its source electrically connected to a first power supply voltage line, and its drain electrically connected to the anode of the OLED. One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end is electrically connected to either the source or drain of the driving transistor. The cathode of the OLED is electrically connected to a second power supply voltage line.

[0020] The gate driving circuit includes n cascaded gate driving sub-circuits, each electrically connected to a scan line. Under the control of the timing controller, the gate driving sub-circuits sequentially output gate driving signals, scanning each row of pixel units PX in the display area AA line by line. The source driving circuit, under the control of the timing controller, generates and outputs data signals based on the image data. The timing controller receives and processes externally input image data and timing signals, generates control signals, and transmits the image data to the source driving circuit. The power management chip (PMIC) provides operating voltages to various parts of the display device, including providing a second power supply voltage VSS to the cathode of the organic light-emitting diode (OLED), a first power supply voltage VDD to the first power supply line, and gate driving voltages VGH / VGL to the gate driving circuit.

[0021] As shown in Figures 2 and 3, the present invention provides a display device comprising a display panel, the display panel including a plurality of pixels, a gate driving circuit, a plurality of metal pads, and a plurality of metal lines. The gate driving circuit includes multiple cascaded gate driving sub-circuits (e.g., GOA1, GOA2, ..., GOA[n-1]) and at least one redundant driving sub-circuit, a dummy GOA (e.g., GOA[n]). The gate driving circuit is electrically connected to a plurality of clock signal inputs (CK1, CK2, CK3, CK4) and a start signal input STV.

[0022] The multi-level cascaded gate driving sub-circuits are used to provide gate driving signals (e.g., Nout1, Nout2, ..., Nout[n-1], Pout1, Pout2, ..., Pout[n-1]) to the pixels of the display panel, and to provide cascade signals (e.g., Pc1, Pc2, ..., Pc[n-1]) to the lower-level gate driving sub-circuits / redundant driving sub-circuits; at least one level of redundant driving sub-circuit Dummy GOA is disposed on one side of the arrangement direction of the multi-level gate driving sub-circuits, that is, located at the edge of the display panel, and at least one level of redundant driving sub-circuit Dummy GOA is cascaded with at least one level of gate driving sub-circuit; a plurality of metal pads are disposed at the edge of the display panel, including at least a first metal pad B1, a second metal pad B2 and a third metal pad B3; a plurality of metal lines include at least a first metal line A1, a second metal line A2 and a third metal line A3.

[0023] The gate driving circuit is fabricated using complementary metal-oxide-semiconductor (CMOS) technology. Each stage of the gate driving sub-circuit includes a stage transmission unit 302 and a driving unit 301. The stage transmission unit 302 outputs a stage transmission signal, which serves as a trigger signal for the adjacent stage of the gate driving sub-circuit. The driving unit 301 outputs a first gate driving signal and a second gate driving signal to drive the pixels in the display area AA. This separation of the stage transmission unit 302 and the driving unit 301 enables the gate driving circuit to achieve frequency division and segmentation functions.

[0024] The redundant drive sub-circuit Dummy GOA has the same structure as the gate drive sub-circuit, also including a cascade unit 302 and a drive unit 301. The redundant drive sub-circuit Dummy GOA includes a first gate drive signal output terminal Pout[n], a second gate drive signal output terminal Nout[n], and a cascade signal output terminal Pc[n]. The first gate drive signal output terminal Pout[n] is electrically connected to the first metal pad B1 through a first metal line A1, the second gate drive signal output terminal Nout[n] is electrically connected to the second metal pad B2 through a second metal line A2, and the cascade signal output terminal Pc[n] is electrically connected to the third metal pad B3 through a third metal line A3.

[0025] In this embodiment, to further improve the reliability of the test, the first metal wire A1 and the second metal wire A2 are arranged in parallel, and the third metal wire A3 is parallel to both the first metal wire A1 and the second metal wire A2. The distance between the first metal wire A1 and the second metal wire A2 is set to a first preset distance, which is used to ensure that the first metal wire A1 and the second metal wire A2 do not interfere with each other. The distance between the third metal wire A3 and the closer one of the first metal wire A1 and the second metal wire A2 is set to a second preset distance, which is greater than the first preset distance, in order to reduce the parasitic capacitance between the third metal wire A3 and the first metal wire A1 and the second metal wire A2.

[0026] In this embodiment, the second preset distance is at least three times the first preset distance. This effectively reduces the parasitic capacitance between the third metal line A3 and the first metal line A1 and the second metal line A2, preventing interference with the cascaded signal.

[0027] Multiple metal pads are arranged in a direction perpendicular to the arrangement direction of the gate driver circuit.

[0028] As shown in Figure 4, the i-th stage gate driver sub-circuit in the multi-stage gate driver sub-circuit includes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. i is a positive integer, and i is not greater than n.

[0029] The first transistor T1, the fourth transistor T4, the tenth transistor T10, the thirteenth transistor T13, the fourteenth transistor T14, the seventeenth transistor T17, and the twenty-first transistor T21 are N-type transistors.

[0030] The second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the fifteenth transistor T15, the sixteenth transistor T16, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24, and the twenty-fifth transistor T25 are P-type transistors.

[0031] The first transistor T1, the fourth transistor T4, the tenth transistor T10, the thirteenth transistor T13, the fourteenth transistor T14, the seventeenth transistor T17, and the twenty-first transistor T21 are dual-gate transistors, with the two gates of each transistor electrically connected.

[0032] Transistors T2, T3, T5, T6, T7, T8, T9, T11, T12, T15, T16, T18, T19, T20, T22, T23, T24, and T25 are single-gate transistors.

[0033] One of the source and drain of the first transistor T1 is electrically connected to the first low-level signal input terminal PVGL. The first transistor T1 includes two gates that are electrically connected. The gate of the first transistor T1 is electrically connected to node K. One of the source and drain of the first transistor T1 is electrically connected to node P[i].

[0034] The gate of the second transistor T2 is electrically connected to the first clock signal input terminal XCK. One of the source and drain of the second transistor T2 is electrically connected to node O, and the other of the source and drain of the second transistor T2 is electrically connected to node K.

[0035] The gate of the third transistor T3 is electrically connected to node K, one of the source and drain of the third transistor T3 is electrically connected to the first high-level signal input terminal PVGH, and the other of the source and drain of the third transistor T3 is electrically connected to node P[i].

[0036] The fourth transistor T4 includes two gates that are electrically connected. The gate of the fourth transistor T4 is electrically connected to the first clock signal input terminal XCK. One of the source and drain of the fourth transistor T4 is electrically connected to node K.

[0037] The gate of the fifth transistor T5 is electrically connected to node P[i]. One of the source and drain of the fifth transistor T5 is electrically connected to the first high-level signal input terminal PVGH. The other of the source and drain of the fifth transistor T5 is electrically connected to the other of the source and drain of the fourth transistor T4.

[0038] The gate of the sixth transistor T6 is electrically connected to node Q1, one of the source and drain of the sixth transistor T6 is electrically connected to the second clock signal CK1, and the other of the source and drain of the sixth transistor T6 is electrically connected to the first gate drive signal output terminal Pout[i].

[0039] The gate of the seventh transistor T7 is electrically connected to node P[i]. One of the source and drain of the seventh transistor T7 is electrically connected to the first high-level signal input terminal PVGH. The other of the source and drain of the seventh transistor T7 is electrically connected to the first gate drive signal output terminal Pout[i].

[0040] The gate of the eighth transistor T8 is electrically connected to node P[i-2] in the (i-2)th stage gate driver sub-circuit. One of the source and drain of the eighth transistor T8 is electrically connected to node M, and the other of the source and drain of the eighth transistor T8 is electrically connected to node Q1.

[0041] The gate of the ninth transistor T9 is electrically connected to node W. One of the source and drain of the ninth transistor T9 is electrically connected to the second high-level signal input terminal NVGH. The other of the source and drain of the ninth transistor T9 is electrically connected to the second gate drive signal output terminal Nout[i].

[0042] The gate of the tenth transistor T10 is electrically connected to node K. One of the source and drain of the tenth transistor T10 is electrically connected to the second low-level signal input terminal NVGL. The other of the source and drain of the tenth transistor T10 is electrically connected to the second gate drive signal output terminal Nout[i]. The tenth transistor T10 includes two gates, which are electrically connected.

[0043] One of the source and drain of the eleventh transistor T11 is electrically connected to node K, and the other of the source and drain of the eleventh transistor T11 is electrically connected to node W.

[0044] The gate of the twelfth transistor T12 is electrically connected to the start signal input terminal STV. One of the source and drain of the twelfth transistor T12 is electrically connected to the first high-level signal input terminal PVGH. The other of the source and drain of the twelfth transistor T12 is electrically connected to node O.

[0045] The gate of the thirteenth transistor T13 is electrically connected to the start signal input terminal STV. One of the source and drain of the thirteenth transistor T13 is electrically connected to the second low-level signal input terminal NVGL. The other of the source and drain of the thirteenth transistor T13 is electrically connected to node O.

[0046] The gate of the fourteenth transistor T14 is electrically connected to node P[i]. The fourteenth transistor T14 includes two gates, which are electrically connected. One of the source and drain of the fourteenth transistor T14 is electrically connected to the second low-level signal input terminal NVGL, and the other of the source and drain of the fourteenth transistor T14 is electrically connected to node K.

[0047] The gate of the fifteenth transistor T15 is electrically connected to the control signal input terminal Ctrl. One of the source and drain of the fifteenth transistor T15 is electrically connected to the first high-level signal input terminal PVGH. The other of the source and drain of the fifteenth transistor T15 is electrically connected to node K.

[0048] The gate of the sixteenth transistor T16 is electrically connected to node P[i]. One of the source and drain of the sixteenth transistor T16 is electrically connected to the first partition allocation control signal input terminal NLF. The other of the source and drain of the sixteenth transistor T16 is electrically connected to the gate of the eleventh transistor T11.

[0049] The gate of the seventeenth transistor T17 is electrically connected to the first clock signal input terminal XCK. The seventeenth transistor T17 includes two gates, which are electrically connected. One of the source and drain of the seventeenth transistor T17 is electrically connected to node W.

[0050] The gate of the eighteenth transistor T18 is electrically connected to node P[i]. One of the source and drain of the eighteenth transistor T18 is electrically connected to the first high-level signal input terminal PVGH. The other of the source and drain of the eighteenth transistor T18 is electrically connected to the other of the source and drain of the seventeenth transistor T17.

[0051] One of the source and drain of the nineteenth transistor T19 is electrically connected to node K, and the other of the source and drain of the nineteenth transistor T19 is electrically connected to node M.

[0052] The gate of the twentieth transistor T20 is electrically connected to node P[i]. One of the sources and drains of the twentieth transistor T20 is electrically connected to the second partition allocation control signal input terminal PLF. The other of the sources and drains of the twentieth transistor T20 is electrically connected to the gate of the nineteenth transistor T19.

[0053] The gate of the twenty-first transistor T21 is electrically connected to the first clock signal input terminal XCK. The twenty-first transistor T21 includes two gates, which are electrically connected. One of the source and drain of the twenty-first transistor T21 is electrically connected to node M.

[0054] The gate of the twenty-second transistor T22 is electrically connected to node P[i]. One of the source and drain of the twenty-second transistor T22 is electrically connected to the first high-level signal input terminal PVGH. The other of the source and drain of the twenty-second transistor T22 is electrically connected to the other of the source and drain of the twenty-first transistor T21.

[0055] The gate of the 23rd transistor T23 is electrically connected to node P[i-2] in the (i-2)th stage gate driver sub-circuit. One of the source and drain of the 23rd transistor T23 is electrically connected to node M, and the other of the source and drain of the 23rd transistor T23 is electrically connected to node Q2.

[0056] The gate of the 24th transistor T24 is electrically connected to node Q2. The source of the 24th transistor T24 is electrically connected to one of its source and drain terminals to the third clock signal CK2. The other of the source and drain terminals of the 24th transistor T24 is electrically connected to the stage signal output terminal Pc[i].

[0057] The gate of the 25th transistor T25 is electrically connected to node P[i]. One of the source and drain of the 25th transistor T25 is electrically connected to the first high-level signal input terminal PVGH. The other of the source and drain of the 25th transistor T25 is electrically connected to the stage signal output terminal Pc[i].

[0058] One plate of the first capacitor C1 is electrically connected to node Q1, and the other plate is electrically connected to the first gate drive signal output terminal Pout[i]. One plate of the second capacitor C2 is electrically connected to node W, and the other plate is electrically connected to the gate of the eleventh transistor T11. One plate of the third capacitor C3 is electrically connected to node M, and the other plate is electrically connected to the gate of the nineteenth transistor T19. One plate of the fourth capacitor C4 is electrically connected to node Q2, and the other plate is electrically connected to the stage transmission signal output terminal Pc[i].

[0059] The first transistor T1 to the twenty-second transistor T22 and the first capacitor C1 to the third capacitor C3 constitute the driving unit 301, and the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25 and the fourth capacitor C4 constitute the transmission unit 302.

[0060] To address the issue of inaccurate test signals in existing technologies, this invention adds a third metal pad B3 at the edge of the display panel for testing the stage transmission signal. By testing the signal on the third metal pad B3, the normality of the stage transmission signal of the redundant drive sub-circuit Dummy GOA can be monitored, thereby avoiding misjudgments of test results due to the inability to test the stage transmission signal.

[0061] As shown in Figure 3, at least one of the first metal line A1 and the second metal line A2 forms a capacitor with the power supply traces VDD / VGH / VSS / VGL of the display panel. In this way, the load of at least one of the first metal line A1 and the second metal line A2 is increased, bringing it close to the load of the line located in the display area AA connected to the gate driver circuit. The parasitic capacitance of the conventional display area AA's lines is approximately 20 picofarads, and the parasitic capacitance of the metal lines without adding a capacitor is only 7-10 picofarads. Therefore, by forming a capacitor between the first and second metal traces and the power supply traces VDD / VGH / VSS / VGL, the load of the first and second metal traces can be made to reach a level comparable to the load of the lines located in the display area AA.

[0062] To ensure accurate load matching, the ratio of the load of the first metal wire A1 to the load of the second metal wire A2 is within the range of 80% to 120%, for example, this ratio can be 80%, 85%, 90%, 95%, 100%, 105%, 110%, 115%, or 120%. Preferably, the load of the first metal wire A1 is equal to the load of the second metal wire A2. Because one of the first metal wire A1 and the second metal wire A2 has a large parasitic capacitance due to its proximity to the power supply traces VDD / VGH / VSS / VGL, while the other has a smaller parasitic capacitance due to its distance from the power supply traces VDD / VGH / VSS / VGL, in order to ensure that the load ratio of the two is within the aforementioned range, the line width of the metal wire farther from the power supply traces VDD / VGH / VSS / VGL is set to be smaller than that of the metal wire closer to the power supply traces VDD / VGH / VSS / VGL, and / or the thickness of the metal wire farther from the power supply traces VDD / VGH / VSS / VGL is set to be smaller than that of the metal wire closer to the power supply traces VDD / VGH / VSS / VGL. By reducing the cross-sectional area of ​​the metal wire farther from the power supply traces VDD / VGH / VSS / VGL, its own resistance value can be increased, thereby compensating for its smaller parasitic capacitance value and achieving load matching between the two metal wires. Specifically, the trace width of the metal traces away from the power traces VDD / VGH / VSS / VGL can be set to 50% to 80% of the trace width of the metal traces close to the power traces VDD / VGH / VSS / VGL, and / or the thickness of the metal traces away from the power traces VDD / VGH / VSS / VGL can be set to 50% to 80% of the thickness of the metal traces close to the power traces VDD / VGH / VSS / VGL.

[0063] Meanwhile, the ratio of the load of either the first metal line A1 or the load of the second metal line A2 to the load of the output terminal of the gate drive sub-circuit should also be in the range of 80% to 120%. For example, the ratio can be 80%, 85%, 90%, 95%, 100%, 105%, 110%, 115% or 120%.

[0064] The load of the third metal line A3 is set to be less than either the load of the first metal line A1 or the load of the second metal line A2. Specifically, the load of the third metal line A3 is 30% to 50% of the load of the first metal line A1, for example, 30%, 35%, 40%, 45%, and 50%. This is because the stage transmission signal is mainly used to trigger the adjacent stage gate driver sub-circuit and does not need to drive pixels, so its load does not need to be equivalent to the load of the lines in the display area AA. Conversely, if the load of the third metal line A3 is too large, it will affect the test results.

[0065] The power traces can be high-level power traces VDD / VGH or low-level power traces VSS / VGL. At least one of the first metal line A1 and the second metal line A2 is arranged parallel to the power traces VDD / VGH / VSS / VGL to form the required capacitor. Furthermore, at least one of the first metal line A1 and the second metal line A2 forms multiple capacitors with multiple power traces VDD / VGH / VSS / VGL to obtain the required load size.

[0066] The capacitance of the capacitor between at least one of the first metal line A1 and the second metal line A2 and the power supply trace VDD / VGH / VSS / VGL is greater than the capacitance of the third metal line A3 and the power supply trace VDD / VGH / VSS / VGL.

[0067] The distance between at least one of the first metal line A1 and the second metal line A2 and the power trace VDD / VGH / VSS / VGL is less than the distance between the third metal line A3 and the power trace VDD / VGH / VSS / VGL; the overlap area between at least one of the first metal line A1 and the second metal line A2 and the power trace VDD / VGH / VSS / VGL is greater than the overlap area between the third metal line A3 and the power trace VDD / VGH / VSS / VGL.

[0068] As an improvement, the first metal wire A1, the second metal wire A2, and the third metal wire A3 are bent less than or equal to three times, and the angle of each bend is not less than 45 degrees.

[0069] The bends of the first metal wire A1, the second metal wire A2, and the third metal wire A3 are provided with arc transition sections to avoid excessive charge concentration at the bends.

[0070] The technical solution of the present invention is applicable to all gate drive circuits that design the cascade unit 302 and the drive unit 301 separately.

[0071] In the display device provided by the present invention, by adding a third metal pad B3 for testing the stage transmission signal at the edge of the display panel, and electrically connecting the stage transmission signal output terminal Pc[n] of the redundant drive sub-circuit Dummy GOA to the third metal pad B3 through the third metal line A3, not only can the gate drive signal output by the redundant drive sub-circuit Dummy GOA be tested, but also the stage transmission signal output by the redundant drive sub-circuit Dummy GOA can be tested. This allows for comprehensive monitoring of the working state of the gate drive circuit, avoids misjudgment of test results due to the inability to test the stage transmission signal, and significantly improves the reliability of testing for the display device.

[0072] Furthermore, by forming capacitors between the first metal line A1 and the second metal line A2 and the power supply traces VDD / VGH / VSS / VGL, the load on the first metal line A1 and the second metal line A2 is increased, bringing them closer to the load on the lines connected to the display area AA of the gate driver sub-circuit. Simultaneously, by adjusting the linewidth and thickness of the metal lines farther from the power supply traces VDD / VGH / VSS / VGL to be smaller than those closer to them, the parasitic capacitance difference caused by the distance difference with the power supply traces VDD / VGH / VSS / VGL is compensated. This ensures that the load ratio of the first metal line A1 to the second metal line A2 is within the range of 80% to 120%, allowing the test signal to accurately reflect the operating state of the gate driver circuit.

[0073] In addition, by making the load of the third metal line A3 less than the load of the first metal line A1 and the second metal line A2, the normal transmission of the stage transmission signal is ensured, so that the test signal can truly reflect the working state of the gate drive circuit and avoid misjudgment of the test results.

[0074] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, comprising: The display panel includes: A multi-stage cascaded gate drive sub-circuit is used to provide gate drive signals to the pixels of the display panel; At least one redundant driving sub-circuit is disposed on one side of the arrangement direction of the multiple gate driving sub-circuits, and the at least one redundant driving sub-circuit is cascaded with the at least one gate driving sub-circuit. Multiple metal pads are disposed on the edge of the display panel, and the multiple metal pads include at least a first metal pad, a second metal pad, and a third metal pad; and Multiple metal wires, wherein the multiple metal wires include at least a first metal wire, a second metal wire, and a third metal wire; The redundant drive sub-circuit includes a first gate drive signal output terminal, a second gate drive signal output terminal, and a stage transmission signal output terminal. The first gate drive signal output terminal is electrically connected to the first metal pad through the first metal trace, the second gate drive signal output terminal is electrically connected to the second metal pad through the second metal trace, and the stage transmission signal output terminal is electrically connected to the third metal pad through the third metal trace.

2. The display device according to claim 1, wherein, At least one of the first metal trace and the second metal trace forms a capacitor with the power trace of the display panel.

3. The display device according to claim 2, wherein, The power supply trace can be a high-level power supply trace or a low-level power supply trace.

4. The display device according to claim 2, wherein, The load of the third metal trace is less than the load of the first metal trace or the load of the second metal trace.

5. The display device according to claim 2, wherein, The load ratio of the first metal trace to the load ratio of the second metal trace is in the range of 80% to 120%.

6. The display device according to claim 2, wherein, The ratio of the load of either the first metal trace or the load of the second metal trace to the load at the output of the gate driver sub-circuit is in the range of 80% to 120%.

7. The display device according to claim 2, wherein, At least one of the first metal trace and the second metal trace is parallel to the power trace.

8. The display device according to claim 2, wherein, The capacitance value of the capacitor between at least one of the first metal trace and the second metal trace and the power trace is greater than the capacitance value between the third metal trace and the power trace.

9. The display device according to claim 2, wherein, The distance between at least one of the first metal trace and the second metal trace and the power trace is less than the distance between the third metal trace and the power trace.

10. The display device according to claim 2, wherein, The line width of the first metal line and the second metal line that are farther away from the power trace is smaller than the line width of the other one that is closer to the power trace, and / or the thickness of the first metal line and the second metal line that are farther away from the power trace is smaller than the thickness of the other one that is closer to the power trace.

11. The display device according to claim 2, wherein, The first metal wire, the second metal wire, and the third metal wire are arranged in parallel.

12. The display device according to claim 11, wherein, The distance between the first metal wire and the second metal wire is a first preset distance, and the distance between the third metal wire and the closer of the first metal wire and the second metal wire is a second preset distance, which is greater than the first preset distance.

13. The display device according to claim 12, wherein, The second preset distance is at least three times the first preset distance.

14. The display device according to claim 2, wherein, The plurality of metal pads are arranged perpendicular to the arrangement direction of the gate driver sub-circuit.

15. The display device according to claim 2, wherein, The first metal wire, the second metal wire, and the third metal wire are bent less than or equal to three times.

16. The display device according to claim 15, wherein, The bending angle of the first metal wire, the second metal wire, and the third metal wire is not less than 45 degrees each time.

17. The display device according to claim 15, wherein, The first metal wire, the second metal wire, and the third metal wire are provided with arc transition sections at their bends.

18. The display device according to claim 2, wherein, One end of the first metal wire, the second metal wire, and the third metal wire is electrically connected to the corresponding metal pad, and the other end is electrically connected to the corresponding signal output terminal.

19. The display device according to claim 2, wherein, The load of the third metal wire is 30% to 50% of the load of the first metal wire.

20. The display device according to claim 2, wherein, The redundant driving sub-circuit is located at the edge of the display panel.

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