Display device and method for producing same

Abstract

The present invention comprises: a base substrate (10); a TFT layer (20) provided on the base substrate (10); a light-emitting element layer (40a) provided on the TFT layer (20) and including a plurality of first electrodes (32), a common first charge transport layer (34), a plurality of light-emitting layers (35a), a common second charge transport layer (36), and a common second electrode (37) stacked in order, the plurality of first electrodes (32) and the plurality of light-emitting layers (35a) corresponding to a plurality of sub-pixels forming a display region (D); and a sealing film (45) provided on the light-emitting element layer (40a). In at least one sub-pixel among the plurality of sub-pixels, a base layer (31) on which the corresponding first electrode (32) is placed is provided on the TFT layer (20) side of the first electrode (32).

Description

Display device and method for manufacturing the same

[0001] The present invention relates to a display device and a method for manufacturing the same.

[0002] In recent years, self-emissive display devices using, for example, organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) have attracted attention as alternatives to liquid crystal displays.

[0003] For example, Patent Document 1 discloses a method for manufacturing a display device in which a photosensitive resin material layer, a charge transport material layer, and a light-emitting material layer are formed sequentially on a substrate equipped with electrodes, and then the photosensitive resin material layer, charge transport material layer, and light-emitting material layer are partially lifted off to form the photosensitive resin layer, charge transport layer, and light-emitting layer.

[0004] International Publication No. 2022 / 113179

[0005] By the way, as described in Patent Document 1 above, when a resist pattern with multiple through holes is formed on a substrate, and a light-emitting material is applied to cover the resist pattern, and then the light-emitting material is lifted off to form a light-emitting layer, the light-emitting material tends to accumulate in the corners of each through hole, so the peripheral edges of the light-emitting layer tend to protrude in a angular shape. As a result, the peripheral edges of the light-emitting layer become relatively thicker, causing uneven light emission in those subpixels.

[0006] The present invention has been made in view of the above, and its purpose is to suppress the protrusion of the peripheral edge of the light-emitting layer and thereby suppress the occurrence of uneven light emission.

[0007] To achieve the above objective, the present invention provides a display device comprising: a base substrate; a thin film transistor layer provided on the base substrate; a light-emitting layer provided on the thin film transistor layer, wherein a plurality of first electrodes, a common first charge transport layer, a plurality of light-emitting layers, a common second charge transport layer, and a common second electrode are sequentially stacked corresponding to a plurality of subpixels constituting a display area; and a sealing film provided on the light-emitting layer, wherein in at least one of the plurality of subpixels, a base layer for supporting the first electrode is provided on the thin film transistor layer side of the corresponding first electrode.

[0008] Furthermore, the method for manufacturing the display device according to the present invention is a method for manufacturing the above-described display device, wherein the plurality of subpixels include a first subpixel, a second subpixel, and a third subpixel that emit light of different colors from each other, and the step of forming the plurality of light-emitting layers is to apply a resist to the surface of a substrate on which the first charge transport layer is formed, then expose and develop the resist to form a first resist pattern having through-holes that expose portions that overlap with the first electrodes formed on the base layer corresponding to the first subpixels, a flat bottom around the through-holes, and an inclined portion around the bottom; apply a first light-emitting material so as to cover the first resist pattern formed in the first resist pattern formation step, then lift off the first resist pattern to form a first light-emitting layer with the first light-emitting material; and apply a resist to the surface of a substrate on which the first light-emitting layer is formed in the first light-emitting layer formation step, then expose and develop the resist to expose portions that overlap with the first electrodes formed on the base layer corresponding to the second subpixels. A second resist pattern forming step is performed to form a second resist pattern having a through portion, a flat bottom portion around the through portion, and an inclined inclined portion around the bottom portion; a second light-emitting layer forming step is performed to apply a second light-emitting material so as to cover the second resist pattern formed in the second resist pattern forming step, then lift off the second resist pattern to form a second light-emitting layer with the second light-emitting material; and after applying a resist to the substrate surface on which the second light-emitting layer was formed in the second light-emitting layer forming step, the resist is exposed and developed. The present invention is characterized by comprising: a third resist pattern forming step of forming a third resist pattern having through portions that expose portions that overlap with the first electrode formed on the base layer corresponding to the third subpixel, a flat bottom portion around the through portions, and an inclined portion around the bottom portion; and a third light-emitting layer forming step of applying a third light-emitting material so as to cover the third resist pattern formed in the third resist pattern forming step, then lifting off the third resist pattern to form a third light-emitting layer with the third light-emitting material.

[0009] According to the present invention, protrusions at the peripheral edges of the light-emitting layer can be suppressed, thereby suppressing the occurrence of uneven light emission.

[0010] Figure 1 is a plan view showing a schematic configuration of a QLED display device according to the first embodiment of the present invention. Figure 2 is a plan view of the display area of ​​a QLED display device according to the first embodiment of the present invention. Figure 3 is a cross-sectional view of the display area of ​​a QLED display device according to the first embodiment of the present invention. Figure 4 is an equivalent circuit diagram of the TFT layers constituting the QLED display device according to the first embodiment of the present invention. Figure 5 is a first cross-sectional view showing a part of the manufacturing process of a QLED display device according to the first embodiment of the present invention. Figure 6 is a second cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 5. Figure 7 is a third cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 6. Figure 8 is a fourth cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 7. Figure 9 is a fifth cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 8. Figure 10 is a sixth cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 9. Figure 11 is a seventh cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 10. Figure 12 is an eighth cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 11. Figure 13 is a ninth cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 12. Figure 14 is a tenth cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 13. Figure 15 is an eleventh cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 14. Figure 16 is a twelfth cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 15. Figure 17 is a thirteenth cross-sectional view showing a part of the manufacturing process of a QLED display device following Figure 16. Figure 18 is a first cross-sectional view showing a part of the second resist pattern formation process in the manufacturing process of a QLED display device according to the first embodiment of the present invention. Figure 19 is a second cross-sectional view showing a part of the second resist pattern formation process following Figure 18. Figure 20 is a third cross-sectional view showing a part of the second resist pattern formation process following Figure 19. Figure 21 is a cross-sectional view showing a modified example of the second resist pattern formation process in the manufacturing process of a QLED display device according to the first embodiment of the present invention. Figure 22 is a cross-sectional view of the display area of ​​a QLED display device according to the second embodiment of the present invention, and corresponds to Figure 3.

[0011] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the following embodiments.

[0012] 《First Embodiment》 Figures 1 to 21 show a first embodiment of the display device and its manufacturing method according to the present invention. In the following embodiments, a QLED display device equipped with a QLED element layer is exemplified as a display device equipped with a light-emitting element layer. Here, Figure 1 is a plan view showing the schematic configuration of the QLED display device 50a of this embodiment. Figures 2 and 3 are a plan view and a cross-sectional view of the display area D of the QLED display device 50a. Figure 4 is an equivalent circuit diagram of the TFT layer 20 constituting the QLED display device 50a.

[0013] As shown in Figure 1, the QLED display device 50a includes, for example, a rectangular display area D for displaying images and a frame-shaped frame area F surrounding the display area D. In this embodiment, a rectangular display area D is used as an example, but this rectangular shape also includes substantially rectangular shapes such as shapes with arc-shaped sides, shapes with arc-shaped corners, and shapes with notches in part of the sides.

[0014] In the display area D, as shown in Figure 2, a plurality of subpixels P are arranged in a matrix. The plurality of subpixels P include a first subpixel Pr, a second subpixel Pg, and a third subpixel Pb, each displaying a different color. In the display area D, as shown in Figure 2, for example, a first subpixel Pr having a red light-emitting region Lr for displaying red, a second subpixel Pg having a green light-emitting region Lg for displaying green, and a third subpixel Pb having a blue light-emitting region Lb for displaying blue are arranged adjacent to each other. In the display area D, for example, one pixel is composed of three adjacent first subpixels Pr, second subpixel Pg, and third subpixel Pb, each having a red light-emitting region Lr, a green light-emitting region Lg, and a blue light-emitting region Lb, respectively, and displaying different colors.

[0015] A terminal portion T is provided at the positive end of the frame region F in the Y direction in Figure 1, extending in one direction (the X direction in Figure 1). Furthermore, between the display region D and the terminal portion T, as shown in Figure 1, a bendable portion B is provided on the display region D side of the terminal portion T in the frame region F, extending in one direction (the X direction in the figure), which can be bent, for example, 180° (in a U shape) with the X direction in the figure as the axis of bending.

[0016] As shown in Figure 3, the QLED display device 50a comprises a resin substrate 10 provided as a base substrate, a TFT layer 20 provided on the resin substrate 10, a QLED element layer 40a provided on the TFT layer 20 as a light-emitting layer, and a sealing film 45 provided on the QLED element layer 40a.

[0017] The resin substrate 10 is made of, for example, polyimide resin.

[0018] As shown in Figure 3, the TFT layer 20 comprises a base coat film 11 provided on a resin substrate 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c provided on the base coat film 11, and a planarization film 19 provided on each of the first TFTs 9a, second TFTs 9b, and capacitors 9c. Here, as shown in Figure 2, the TFT layer 20 is provided with a plurality of gate lines 14g extending parallel to each other in the X direction in the figure. Also, as shown in Figure 2, the TFT layer 20 is provided with a plurality of source lines 18f extending parallel to each other in a direction that intersects (orthogonal to) the plurality of gate lines 14g, i.e., in the Y direction in the figure. Also, as shown in Figure 2, the TFT layer 20 is provided with a plurality of power lines 18g extending parallel to each other in the Y direction in the figure. And, as shown in Figure 2, each power line 18g is provided adjacent to each source line 18f. Furthermore, in the TFT layer 20, as shown in Figure 4, a first TFT 9a, a second TFT 9b, and a capacitor 9c are provided in each subpixel P. In the TFT layer 20, as shown in Figure 3, a base coat film 11, a semiconductor film which will become a semiconductor layer 12a (described later), a first metal film which will become a gate insulating film 13, a gate line 14g, a first interlayer insulating film 15, a second metal film which will become an upper conductive layer 16c (described later), a second interlayer insulating film 17, a third metal film which will become a source line 18f or power line 18g, and a planarization film 19 are stacked in that order on the resin substrate 10.

[0019] The base coat film 11, gate insulating film 13, first interlayer insulating film 15, and second interlayer insulating film 17 are composed of, for example, single-layer or multilayer films of inorganic insulating films such as silicon nitride, silicon oxide, or silicon oxynitride.

[0020] As shown in Figure 4, the first TFT 9a is electrically connected to the corresponding gate line 14g, source line 18f, and second TFT 9b at each subpixel P. Here, as shown in Figure 3, the first TFT 9a comprises a semiconductor layer 12a provided on a base coat film 11, a gate electrode 14a provided on the semiconductor layer 12a via a gate insulating film 13, and a source electrode 18a and a drain electrode 18b provided spaced apart from each other on the second interlayer insulating film 17.

[0021] The semiconductor layer 12a and the semiconductor layer 12b, described later, are formed from a semiconductor film made of polysilicon such as LTPS (low temperature polysilicon), and include a source region and a drain region defined to be spaced apart from each other, and a channel region defined between the source region and the drain region.

[0022] The gate electrode 14a is provided so as to overlap the channel region of the semiconductor layer 12a and is configured to control conductivity between the source region and the drain region of the semiconductor layer 12a. Here, the gate electrode 14a is formed of a first metal film, similar to the gate wire 14g, etc.

[0023] As shown in Figure 3, the source electrode 18a and the drain electrode 18b are electrically connected to the source region and drain region of the semiconductor layer 12a, respectively, via contact holes formed in the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. Here, the source electrode 18a and the drain electrode 18b are formed from a third metal film, similar to the source wire 18f and the power supply wire 18g.

[0024] As shown in Figure 4, the second TFT 9b is electrically connected to the corresponding first TFT 9a, power line 18g, and QLED element 39 (described later) at each subpixel P. Here, as shown in Figure 3, the second TFT 9b comprises a semiconductor layer 12b provided on the base coat film 11, a gate electrode 14b provided on the semiconductor layer 12b via a gate insulating film 13, and a source electrode 18c and a drain electrode 18d provided spaced apart from each other on the second interlayer insulating film 17.

[0025] The gate electrode 14b is provided so as to overlap the channel region of the semiconductor layer 12b and is configured to control conductivity between the source region and the drain region of the semiconductor layer 12b. Here, the gate electrode 14b is formed of a first metal film, similar to the gate wire 14g, etc.

[0026] As shown in Figure 3, the source electrode 18c and drain electrode 18d are electrically connected to the source region and drain region of the semiconductor layer 12b, respectively, through contact holes formed in the laminated film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. Here, the source electrode 18c and drain electrode 18d are formed from a third metal film, similar to the source wire 18f and power supply wire 18g.

[0027] In this embodiment, semiconductor layers 12a and 12b formed from a semiconductor film made of polysilicon are exemplified, but semiconductor layers 12a and 12b may be formed from a semiconductor film made of an oxide semiconductor such as In-Ga-Zn-O. Furthermore, the TFT layer 20 may have a hybrid structure in which a TFT having a semiconductor layer made of polysilicon and a TFT having a semiconductor layer made of an oxide semiconductor are provided.

[0028] As shown in Figure 4, the capacitor 9c is electrically connected to the corresponding first TFT 9a and power line 18g at each sub-pixel P. Here, as shown in Figure 3, the capacitor 9c comprises a lower conductive layer 14c formed of a first metal film, an upper conductive layer 16c formed of a second metal film, and a first interlayer insulating film 15 provided between the lower conductive layer 14c and the upper conductive layer 16c. The upper conductive layer 16c is electrically connected to the power line 18g via a contact hole formed in the second interlayer insulating film 17, as shown in Figure 3.

[0029] The planarized film 19 has a flat surface in the display area D and is made of an organic resin material such as polyimide resin.

[0030] As shown in Figure 3, the QLED element layer 40a comprises a plurality of first electrodes 32, a common edge cover 33, a common hole transport layer 34, a plurality of light-emitting layers 35a, a common electron transport layer 36, and a common second electrode 37, which are stacked sequentially to correspond to a plurality of subpixels P. Here, in each subpixel P, the first electrode 32, hole transport layer 34, light-emitting layer 35a, electron transport layer 36, and second electrode 37 constitute a QLED element 39, as shown in Figure 3, and in the QLED element layer 40a, a plurality of QLED elements 39 corresponding to a plurality of subpixels P are arranged in a matrix.

[0031] As shown in Figure 3, the first electrode 32 is electrically connected to the drain electrode 18d of the second TFT 9b of each subpixel P via a contact hole formed in the planarization film 19 and the inclined side surface of the base layer 31, which will be described later. The first electrode 32 also has the function of injecting holes into the light-emitting layer 35a. Furthermore, to improve the hole injection efficiency into the light-emitting layer 35a, it is more preferable to form the first electrode 32 from a material with a large work function. Here, the first electrode 32 is formed from a laminated film in which transparent conductive films such as an indium tin oxide (ITO) film or an indium zinc oxide (IZO) film, a metal film such as a silver film or a silver alloy film, and transparent conductive films such as an ITO film or an IZO film are sequentially stacked and have light reflectivity. Furthermore, as shown in Figure 3, a base layer 31 on which the first electrode 32 is placed is provided on the TFT layer 20 side of the first electrode 32.

[0032] The base layer 31 is formed to a thickness of approximately 1 μm using, for example, an organic resin material or an inorganic insulating film. When the base layer 31 is formed of an organic resin material, for example, the base layer 31 can be easily formed by simply applying a photosensitive organic resin material, followed by exposure, development, and firing. When the base layer 31 is formed of an inorganic insulating film, it becomes unnecessary to consider the effects of degassing from the base layer 31, thereby improving reliability. In this embodiment, a configuration in which the base layer 31 is provided on the TFT layer 20 side of each of the multiple first electrodes 32 is illustrated, but a configuration in which the base layer 31 is provided on the TFT layer 20 side of at least one of the multiple first electrodes 32 is also possible.

[0033] The edge cover 33 is provided in a grid pattern across the entire display area D, and as shown in Figure 3, it is provided to cover the peripheral edge of the first electrode 32. Here, the edge cover 33 is composed of a single layer or multilayer film of a transparent inorganic insulating film such as silicon nitride, silicon oxide, or silicon oxynitride.

[0034] The hole transport layer 34 is provided as a first charge transport layer and has the function of improving the efficiency of hole transport from the first electrode 32 to the light-emitting layer 35a. Examples of materials constituting the hole transport layer 34 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, zinc selenide, and the like. Furthermore, examples of materials that constitute the hole transport layer 34 include functional polymer materials such as poly[(9,9-dioctylfluorenyl-2,7-diyl)-co-(4,4'-(N-(4-sec-butylphenyl))diphenylamine)] (abbreviated as "TFB"), poly[N,N'-bis(4-butylphenyl)-N,N'-bis(phenyl)-benzidine] (abbreviated as "poly-TPD"), and polyvinylcarbazole (abbreviated as "PVK"). The hole transport layer 34 may consist of only one of the above-mentioned materials, or it may consist of two or more as appropriate. Also, as shown in Figure 17, the hole transport layer 34 is provided in common for multiple subpixels P, but it may also consist of multiple layers corresponding to multiple subpixels P.

[0035] Furthermore, a hole injection layer may be provided between the first electrode 32 and the hole transport layer 34, which has the function of bringing the energy levels of the first electrode 32 and the light-emitting layer 35a closer together and improving the hole injection efficiency from the first electrode 32 to the light-emitting layer 35a. Here, examples of materials constituting the hole injection layer include, as organic materials, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, etc., and as inorganic materials, it includes at least one nanoparticle. The nanoparticle includes, for example, nickel oxide (NiO) and further contains nitrate ions (NO). ３ － It includes ).

[0036] The light-emitting layer 35a is a region where holes and electrons are injected from the first electrode 32 and the second electrode 37, respectively, when voltage is applied by the first electrode 32 and the second electrode 37, and where holes and electrons recombine. As shown in Figure 3, the light-emitting layer 35a is provided so as to cover the upper surface of the first electrode 32 via the hole transport layer 34, and its peripheral edge is positioned to coincide with the peripheral edge of the base layer 31 in a plan view, or to be positioned inward from the peripheral edge of the base layer 31. The light-emitting layer 35a also includes a red light-emitting layer 35ar provided on the first sub-pixel Pr that displays red, a green light-emitting layer 35ag provided on the second sub-pixel Pg that displays green, and a blue light-emitting layer 35ab provided on the third sub-pixel Pb that displays blue (see Figure 17). Here, the light-emitting layer 35a is formed of a material with high luminescence efficiency. The light-emitting layer 35a includes, for example, multiple quantum dots as the light-emitting material. Furthermore, each quantum dot constituting the light-emitting layer 35a may have a core / shell structure including a core that emits light when excitons are activated and a shell formed around the core to protect it. In addition, in this embodiment, the light-emitting layer 35a may contain organic or inorganic ligands that coordinate to each quantum dot by forming coordination bonds with the outermost surface of each quantum dot.

[0037] Note that in this embodiment, the "quantum dot" means a dot with a maximum width of 100 nm or less. Also, the shape of the quantum dot may be within the range that satisfies the above maximum width, and is not particularly limited, and is not limited to a spherical three-dimensional shape (circular cross-sectional shape). Furthermore, the shape of the quantum dot may be, for example, a polygonal cross-sectional shape, a rod-shaped three-dimensional shape, a branched three-dimensional shape, a three-dimensional shape having irregularities on the surface, or a combination thereof.

[0038] The quantum dot is typically preferably made of a semiconductor. Here, the semiconductor preferably has a certain bandgap. Also, the semiconductor may be any material that can emit light, and preferably contains at least the materials described below. Also, the semiconductor preferably can emit blue, green, and red light respectively. Also, the semiconductor contains, for example, at least one selected from the group consisting of II-VI group compounds, III-V group compounds, chalcogenides, and perovskite compounds. Note that the II-VI group compound means a compound containing a group II element and a group VI element, and the III-V group compound means a compound containing a group III element and a group V element. Also, the group II element包含 the group 2 element and the group 12 element, the group III element包含 the group 3 element and the group 13 element, the group V element包含 the group 5 element and the group 15 element, and the group VI element may包含 the group 6 element and the group 16 element.

[0039] The II-VI group compound contains, for example, at least one selected from the group consisting of MgS, MgSe, MgTe, CaS, CaSe, CaTe, SrS, SrSe, SrTe, BaS, BaSe, BaTe, ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, and HgTe.

[0040] The III-V group compound contains, for example, at least one selected from the group consisting of GaAs, GaP, InN, InAs, InP, and InSb.

[0041] The chalcogenide is a compound containing a group VIA (16) element, and contains, for example, CdS or CdSe. Also, the chalcogenide may contain mixed crystals thereof.

[0042] It should be noted that in the translation of the text in item , the expression "包含" is used instead of the more appropriate "includes" for better semantic understanding in Chinese-English conversion. You can adjust it according to actual needs.The perovskite compound has, for example, a composition represented by the general formula CsPbX ３ and contains at least one element X selected from the group consisting of Cl, Br, and I.

[0043] Note that the notation of the group number of elements using Roman numerals is based on the old IUPAC (International Union of Pure and Applied Chemistry) system or the old CAS (Chemical Abstracts Service) system, and the notation of the group number of elements using Arabic numerals is based on the current IUPAC system.

[0044] In addition, in this embodiment, each of the plurality of light-emitting layers 35a includes quantum dots, but at least one of the plurality of light-emitting layers 35a may include quantum dots.

[0045] The electron transport layer 36 is provided as a second charge transport layer and has a function of efficiently moving electrons to the light-emitting layer 35a. Here, examples of the material constituting the electron transport layer 36 include, as organic compounds, oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, metal oxynoid compounds, etc., and inorganic materials can be used. Further, the material constituting the electron transport layer 36 may contain zinc oxide (ZnO), magnesium zinc oxide (MgZnO), etc. Furthermore, the material constituting the electron transport layer 36 may contain only one type of the above-described materials, or may contain two or more types as appropriate. Also, as shown in FIG. 17, the electron transport layer 36 is provided in common corresponding to the plurality of sub-pixels P, but a plurality of electron transport layers 36 may be provided corresponding to the plurality of sub-pixels P.

[0046] Note that an electron injection layer having a function of reducing the energy level difference between the second electrode 37 and the light-emitting layer 35a and improving the efficiency of injecting electrons from the second electrode 37 into the light-emitting layer 35a may be provided between the electron transport layer 36 and the second electrode 37. Here, examples of the material constituting the electron injection layer include inorganic alkali compounds such as lithium fluoride (LiF), magnesium fluoride (MgF ２ ), calcium fluoride (CaF ２ ), strontium fluoride (SrF ２ ), barium fluoride (BaF ２ ), aluminum oxide (Al ２ O ３ ), strontium oxide (SrO), and the like.

[0047] As shown in FIG. 3, the second electrode 37 is provided so as to cover the electron transport layer 36. The second electrode 37 has a function of injecting electrons into the light-emitting layer 35a. Further, the second electrode 37 is preferably made of a material having a small work function in order to improve the electron injection efficiency into the light-emitting layer 35a. Here, the second electrode 37 is formed of, for example, a transparent conductive film such as an ITO film or an IZO film and has high light transmittance.

[0048] As shown in FIG. 3, the encapsulation film 45 is provided so as to cover the second electrode 37 and includes a first inorganic encapsulation film 41, an organic encapsulation film 42, and a second inorganic encapsulation film 43 laminated in this order on the second electrode 37, and has a function of protecting the light-emitting layer 35a of the QLED element 39 from moisture, oxygen, and the like. Here, the first inorganic encapsulation film 41 and the second inorganic encapsulation film 43 are made of, for example, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. The organic encapsulation film 42 is made of, for example, an organic resin material such as an acrylic resin, an epoxy resin, a silicone resin, a polyurea resin, a parylene resin, a polyimide resin, or a polyamide resin.

[0049] The QLED display device 50a described above is configured such that, at each subpixel P, a gate signal is input to the first TFT 9a via the gate line 14g, thereby turning on the first TFT 9a, and a voltage corresponding to the source signal is written to the gate electrode 14b and capacitor 9c of the second TFT 9b via the source line 18f. A current from the power line 18g, defined based on the gate voltage of the second TFT 9b, is supplied to the QLED element 39, causing the light-emitting layer 35a of the QLED element 39 to emit light and display an image. In addition, in the QLED display device 50a, even if the first TFT 9a is turned off, the gate voltage of the second TFT 9b is maintained by the capacitor 9c, so the light emission from the light-emitting layer 35a is maintained until the gate signal for the next frame is input.

[0050] Next, the manufacturing method of the QLED display device 50a of this embodiment will be described. The manufacturing method of the QLED display device 50a of this embodiment comprises a TFT layer formation step, a QLED element layer formation step including a light-emitting layer formation step for forming a plurality of light-emitting layers 35a, and a sealing film formation step. Here, Figures 5 to 17 are the first to thirteenth cross-sectional views showing a part of the manufacturing process of the QLED display device 50a (the QLED element layer formation step) in sequence. Figures 18 to 20 are the first to third cross-sectional views showing a part of the second resist pattern formation step in the QLED element layer formation step in sequence. Figure 21 is a cross-sectional view showing a modified example of the second resist pattern formation step in the QLED element layer formation step.

[0051] ~TFT layer formation process~ First, for example, a non-photosensitive polyimide resin (approximately 6 μm thick) is applied to a glass substrate, and then a resin substrate 10 is formed by performing pre-baking and post-baking on the applied film.

[0052] Next, a base coat film 11 is formed on the substrate surface on which the resin substrate 10 is formed by sequentially depositing a silicon oxide film (approximately 500 nm thick) and a silicon nitride film (approximately 100 nm thick) using, for example, a plasma CVD (chemical vapor deposition) method.

[0053] Subsequently, an amorphous silicon film (approximately 50 nm thick) is deposited on the substrate surface on which the base coat film 11 is formed by plasma CVD, and the amorphous silicon film is crystallized by laser annealing or the like to form a polysilicon semiconductor film. After that, the semiconductor film is patterned to form semiconductor layers 12a and 12b, etc.

[0054] Furthermore, a silicon oxide film (approximately 100 nm) is formed on the substrate surface on which the semiconductor layer 12a is formed, for example, by plasma CVD, to form a gate insulating film 13 that covers the semiconductor layer 12a.

[0055] Next, a first metal film, such as a molybdenum film (approximately 250 nm thick), is formed on the substrate surface on which the gate insulating film 13 is formed, for example, by sputtering. Then, the first metal film is patterned to form the gate wire 14g, gate electrodes 14a and 14b, lower conductive layer 14c, etc.

[0056] Subsequently, using gate electrodes 14a and 14b as masks, impurity ions are doped to make a portion of the semiconductor layers 12a and 12b conductive.

[0057] Furthermore, a first interlayer insulating film 15 is formed on the substrate surface, where a portion of the semiconductor layer 12a or the like is made conductive, by depositing a silicon nitride film (approximately 100 nm thick) using, for example, a plasma CVD method.

[0058] Next, a second metal film, such as a molybdenum film (approximately 250 nm thick), is deposited on the substrate surface on which the first interlayer insulating film 15 is formed, for example, by sputtering. After that, the second metal film is patterned to form an upper conductive layer 16c, etc.

[0059] Subsequently, a second interlayer insulating film 17 is formed on the substrate surface on which the upper conductive layer 16c etc. is formed, by sequentially depositing a silicon oxide film (approximately 300 nm thick) and a silicon nitride film (approximately 200 nm thick) using, for example, a plasma CVD method.

[0060] Furthermore, contact holes are formed by appropriately patterning the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17.

[0061] Next, a third metal film is formed on the substrate surface where the contact holes are formed, for example by sputtering, by sequentially depositing a titanium film (approximately 50 nm thick), an aluminum film (approximately 600 nm thick), and a titanium film (approximately 50 nm thick). After that, the third metal film is patterned to form source electrodes 18a and 18c, drain electrodes 18b and 18d, source wire 18f, power line 18g, etc.

[0062] Finally, a photosensitive polyimide resin (approximately 2.5 μm thick) is applied to the substrate surface on which the source electrode 18a, etc., is formed, for example, by a spin coating method or a slit coating method. Then, a planarization film 19 is formed by pre-baking, exposure, development, and post-baking of the coated film.

[0063] In this manner, the TFT layer 20 can be formed.

[0064] ~QLED element layer formation process~ <Base layer formation process> After applying a photosensitive polyimide resin (approximately 1 μm thick) to the substrate surface on which the TFT layer 20 was formed in the above TFT layer formation process, for example, by a spin coating method or a slit coating method, the base layer 31 is formed by pre-baking, exposure, development and post-baking of the coated film.

[0065] <First Electrode Formation Process> On the substrate surface on which the base layer 31 has been formed in the base layer formation process described above, a transparent conductive film such as an ITO film (approximately 10 nm thick), a metal film such as an Ag film (approximately 100 nm thick), and a transparent conductive film such as an ITO film (approximately 10 nm thick) are sequentially deposited by, for example, a sputtering method, and then the laminated films are patterned to form the first electrode 32.

[0066] <Edge Cover Formation Process> On the substrate surface on which the first electrode 32 was formed in the first electrode formation process described above, an inorganic insulating film such as a silicon nitride film (approximately 300 nm thick) is deposited, for example, by plasma CVD. After that, the inorganic insulating film is patterned to form the edge cover 33 as shown in Figure 5.

[0067] <Hole Transport Layer Formation Process> On the substrate surface where the edge cover 33 has been formed in the edge cover formation process described above, a solution (dispersion) in which the constituent materials of the hole transport layer 34 described above have been dissolved (dispersed) is applied, for example, by a spin coating method or a slit coating method. After that, the coated film is dried to form a hole transport layer 34 with a thickness of about 30 nm, as shown in Figure 6.

[0068] <Light-emitting layer formation process> First, a resist is applied to the substrate surface on which the hole transport layer 34 was formed in the hole transport layer formation process described above, for example, by a spin coating method or a slit coating method. Then, the resist is exposed and developed to form a first resist pattern Ra, as shown in Figure 7, which has a through portion H that exposes the portion that overlaps with the first electrode 32 formed on the base layer 31 corresponding to the first subpixel Pr, a flat bottom portion E around the through portion H, and an inclined portion G around the bottom portion E (first resist pattern formation process). Note that the specific formation methods (exposure methods) for the first resist pattern Ra, the second resist pattern Rb and the third resist pattern Rc, which will be described later, are substantially the same and will be explained in detail in the formation method of the second resist pattern Rb using Figures 18 to 21, which will be described later.

[0069] Next, to cover the first resist pattern Ra formed in the first resist pattern formation step described above, a first light-emitting material 35r, consisting of a solution (dispersion) in which the constituent materials of the red light-emitting layer 35ar described above are dissolved (dispersed), is applied by, for example, a spin coating method or a slit coating method, as shown in Figure 8, and after drying, the first resist pattern Ra is lifted off, thereby forming a red light-emitting layer 35ar with a thickness of about 30 nm using the first light-emitting material 35r, as shown in Figure 9 (first light-emitting layer formation step).

[0070] Furthermore, after applying a resist R (see Figure 18) to the substrate surface on which the red light-emitting layer 35ar was formed in the first light-emitting layer formation step, for example, by a spin coating method or a slit coating method, the resist R is exposed and developed to form a second resist pattern Rb as shown in Figure 10, which has a through portion H that exposes the portion that overlaps with the first electrode 32 formed on the base layer 31 corresponding to the second subpixel Pg, a flat bottom portion E around the through portion H, and an inclined portion G around the bottom portion E (second resist pattern formation step).

[0071] Here, when forming the second resist pattern Rb, first, as described above, a positive-type resist R is applied to the substrate surface on which the red light-emitting layer 35ar was formed in the first light-emitting layer formation step to a thickness of about 1 μm, for example, by a spin coating method or a slit coating method, as shown in Figure 18. Next, as shown in Figure 19, the resist R is exposed to a relatively large exposure amount through a photomask Ma to create a latent image of the through-part H (see Figure 10). Furthermore, as shown in Figure 20, the resist R is exposed to a relatively small exposure amount through a photomask Mb to create a latent image of the bottom part E and the inclined part G (see Figure 10). Finally, the resist R on which the through-part H, bottom part E and inclined part G are latently imagined is developed to form the second resist pattern Rb (see Figure 10). Alternatively, instead of exposing the resist R in two stages as described above, the second resist pattern Rb may be formed by exposing the resist R in one stage through a halftone or graytone photomask Mc, as shown in Figure 21.

[0072] Subsequently, to cover the second resist pattern Rb formed in the second resist pattern formation step described above, a second light-emitting material 35g, consisting of a solution (dispersion) in which the constituent materials of the green light-emitting layer 35ag described above are dissolved (dispersed), is applied by, for example, a spin coating method or a slit coating method, as shown in Figure 11, and after drying, the second resist pattern Rb is lifted off, thereby forming a green light-emitting layer 35ag with a thickness of approximately 30 nm using the second light-emitting material 35g, as shown in Figure 12 (second light-emitting layer formation step).

[0073] Furthermore, after applying a resist to the substrate surface on which the green light-emitting layer 35ag was formed in the second light-emitting layer formation step, for example by a spin coating method or a slit coating method, the resist is exposed and developed to form a third resist pattern Rc as shown in Figure 13, which has a through portion H that exposes the portion that overlaps with the first electrode 32 formed on the base layer 31 corresponding to the third subpixel Pb, a flat bottom portion E around the through portion H, and an inclined portion G around the bottom portion E (third resist pattern formation step).

[0074] Finally, to cover the third resist pattern Rc formed in the third resist pattern formation step described above, a third light-emitting material 35b, which consists of a solution (dispersion) in which the constituent materials of the blue light-emitting layer 35ag described above are dissolved (dispersed), is applied by, for example, a spin coating method or a slit coating method, as shown in Figure 14, and after drying, the third resist pattern Rc is lifted off, thereby forming a blue light-emitting layer 35ab with a thickness of about 30 nm using the third light-emitting material 35b, as shown in Figure 15 (third light-emitting layer formation step).

[0075] <Electron Transport Layer Formation Process> On the substrate surface in which the blue light-emitting layer 35ab has been formed in the third light-emitting layer formation process described above, a solution (dispersion) in which the above-mentioned constituent materials have been dissolved (dispersed) is applied, for example, by a spin coating method or a slit coating method. After drying the coated film, an electron transport layer 36 is formed to a thickness of approximately 100 nm, as shown in Figure 16.

[0076] <Second Electrode Formation Process> On the substrate surface on which the electron transport layer 36 was formed in the above electron transport layer formation process, a transparent conductive film such as an ITO film (approximately 100 nm thick) is deposited using a mask, for example, by sputtering, to form the second electrode 37 as shown in Figure 17.

[0077] As described above, the QLED element layer 40a can be formed.

[0078] ~Encapsulation Film Formation Process~ First, on the substrate surface on which the QLED element layer 40a was formed in the above QLED element layer formation process, a silicon nitride film (approximately 50 nm), a silicon oxynitride film (approximately 1500 nm), and a silicon oxide film (approximately 50 nm) are sequentially deposited using a film deposition mask, for example, by plasma CVD, to form a first inorganic encapsulation film 41.

[0079] Next, an organic encapsulation film 42 is formed on the substrate surface on which the first inorganic encapsulation film 41 is formed by applying, for example, an acrylic resin (about 10 μm thick) using an inkjet method.

[0080] Furthermore, a second inorganic encapsulation film 43 is formed on the substrate surface on which the organic encapsulation film 42 is formed by depositing a silicon nitride film (approximately 500 nm thick) or the like using a film-forming mask, for example, by plasma CVD, thereby forming an encapsulation film 45.

[0081] Finally, after attaching a protective sheet (not shown) to the substrate surface on which the sealing film 45 is formed, the glass substrate is peeled off from the bottom surface of the resin substrate 10 by irradiating the resin substrate 10 with laser light from the glass substrate side, and then a protective sheet (not shown) is attached to the bottom surface of the resin substrate 10 from which the glass substrate has been peeled off.

[0082] As described above, the QLED display device 50a of this embodiment can be manufactured.

[0083] As described above, according to the QLED display device 50a and its manufacturing method of this embodiment, in the base layer formation step of the QLED element layer formation step, a base layer 31 on which the first electrode 32 is placed is formed on the TFT layer 20 side of the corresponding first electrode 32 in each subpixel P. Then, in the first resist pattern formation step of the QLED element layer formation step, a first resist pattern Ra is formed in the first subpixel Pr having a through portion H that exposes the portion overlapping with the first electrode 32, a flat bottom portion E around the through portion H, and an inclined portion G around the bottom portion E. Furthermore, in the first light-emitting layer formation step of the QLED element layer formation step, a thin portion of the first light-emitting material 35r can be formed on the flat bottom portion E of the first resist pattern Ra by applying the first light-emitting material 35r so as to cover the first resist pattern Ra. Furthermore, when the first resist pattern Ra is lifted off, the first light-emitting material 35r is divided at the thin portion of the first light-emitting material 35r, so that a red light-emitting layer 35ar with suppressed protrusion at the peripheral edge can be formed. Similarly, in the second resist pattern formation step (third resist pattern formation step) of the QLED element layer formation step, a second resist pattern Rb (third resist pattern Rc) having substantially the same configuration as the first resist pattern Ra is formed in the second sub-pixel Pg (third sub-pixel Pb). Therefore, in the second light-emitting layer formation step (third light-emitting layer formation step) of the QLED element layer formation step, a thin portion of the second light-emitting material 35g (third light-emitting material 35b) can be formed on the flat bottom E of the second resist pattern Rb (third resist pattern Rc) by applying the second light-emitting material 35g (third light-emitting material 35b) so as to cover the second resist pattern Rb (third resist pattern Rc). Furthermore, when the second resist pattern Rb (third resist pattern Rc) is lifted off, the second light-emitting material 35g (third light-emitting material 35b) is divided at the thin portion of the second light-emitting material 35g (third light-emitting material 35b), so that a green light-emitting layer 35ag (blue light-emitting layer 35ab) with suppressed protrusion at the peripheral edge can be formed. As a result, the protrusion at the peripheral edge of the red light-emitting layer 35ar, the green light-emitting layer 35ag, and the blue light-emitting layer 35ab is suppressed, and the protrusion at the peripheral edge of the light-emitting layer 35a can be suppressed, thereby suppressing the occurrence of uneven light emission.Furthermore, since the protrusion of the peripheral edge of the light-emitting layer 35a can be suppressed, the QLED element layer 40a including the light-emitting layer 35a can be more easily covered by the sealing film 45, thereby improving the sealing performance of the sealing film 45.

[0084] 《Second Embodiment》 Figure 22 shows a second embodiment of the display device and its manufacturing method according to the present invention. Here, Figure 22 is a cross-sectional view of the display area D of the QLED display device 50b of this embodiment, and corresponds to Figure 3. In the following embodiments, the same reference numerals are used for parts that are the same as in Figures 1 to 21, and their detailed descriptions are omitted.

[0085] In the first embodiment described above, a QLED display device 50a was illustrated that included a QLED element layer 40a with a relatively small light-emitting layer 35a in a plan view. However, in this embodiment, a QLED display device 50b is illustrated that includes a QLED element layer 40b with a relatively large light-emitting layer 35c in a plan view.

[0086] The QLED display device 50b, like the QLED display device 50a of the first embodiment described above, includes, for example, a rectangular display area D and a frame-shaped frame area F surrounding the display area D. Furthermore, as shown in Figure 22, the QLED display device 50b includes a resin substrate 10, a TFT layer 20 provided on the resin substrate 10, a QLED element layer 40b provided on the TFT layer 20 as a light-emitting element layer, and a sealing film 45 provided on the QLED element layer 40b.

[0087] As shown in Figure 22, the QLED element layer 40b comprises a plurality of first electrodes 32 stacked sequentially corresponding to a plurality of subpixels P, a common edge cover 33, a common hole transport layer 34, a plurality of light-emitting layers 35c, a common electron transport layer 36, and a common second electrode 37. Here, in each subpixel P, the first electrode 32, hole transport layer 34, light-emitting layer 35c, electron transport layer 36, and second electrode 37 constitute a QLED element 39, as shown in Figure 22, and in the QLED element layer 40b, a plurality of QLED elements 39 provided corresponding to a plurality of subpixels P are arranged in a matrix. Furthermore, in the QLED element layer 40b, similar to the QLED element layer 40a of the first embodiment described above, as shown in Figure 22, a base layer 31 on which the first electrode 32 is placed is provided on the TFT layer 20 side of the first electrode 32.

[0088] The light-emitting layer 35c is a region in which holes and electrons are injected from the first electrode 32 and the second electrode 37, respectively, when voltage is applied by the first electrode 32 and the second electrode 37, and where holes and electrons recombine. As shown in Figure 22, the light-emitting layer 35c is provided so as to cover the upper surface of the first electrode 32 via the hole transport layer 34, and its peripheral edge is positioned outside the peripheral edge of the base layer 31 in a plan view. The light-emitting layer 35c also includes a red light-emitting layer provided on the first sub-pixel Pr that displays red, a green light-emitting layer provided on the second sub-pixel Pg that displays green, and a blue light-emitting layer provided on the third sub-pixel Pb that displays blue. Here, the light-emitting layer 35c is formed of a material with high luminescence efficiency, similar to the light-emitting layer 35a in the first embodiment. Furthermore, similar to the light-emitting layer 35a in the first embodiment, the light-emitting layer 35c contains, for example, a plurality of quantum dots as the light-emitting material. Furthermore, each quantum dot constituting the light-emitting layer 35c may have a core / shell structure including a core that emits light when excitons are activated and a shell formed around the core to protect it, similar to the light-emitting layer 35a in the first embodiment. In addition, in this embodiment, the light-emitting layer 35c may also contain an organic or inorganic ligand that coordinates to each quantum dot by forming a coordination bond with the outermost surface of each quantum dot, similar to the light-emitting layer 35a in the first embodiment.

[0089] The QLED display device 50b described above is configured to display an image by appropriately emitting light from the light-emitting layer 35c of the QLED element 39 via the first TFT 9a and the second TFT 9b at each subpixel P.

[0090] The QLED display device 50b of this embodiment can be manufactured by changing the pattern shape of the light-emitting layer 35a in the QLED element layer formation process of the first embodiment described above.

[0091] As described above, according to the QLED display device 50b and its manufacturing method of this embodiment, in the base layer formation step of the QLED element layer formation step, a base layer 31 on which the first electrode 32 is placed is formed on the TFT layer 20 side of the corresponding first electrode 32 in each subpixel P. Then, in the first resist pattern formation step of the QLED element layer formation step, a first resist pattern is formed in the first subpixel Pr having a through portion that exposes the portion overlapping with the first electrode 32, a flat bottom portion around the through portion, and an inclined portion around the bottom portion. Furthermore, in the first light-emitting layer formation step of the QLED element layer formation step, a thin portion of the first light-emitting material can be formed on the flat bottom portion of the first resist pattern by applying the first light-emitting material so as to cover the first resist pattern. Then, when the first resist pattern is lifted off, the first light-emitting material is divided at the thin portion of the first light-emitting material, so that a red light-emitting layer with suppressed protrusion at the peripheral edge can be formed. Similarly, in the second resist pattern formation step (third resist pattern formation step) of the QLED element layer formation step, a second resist pattern (third resist pattern) with substantially the same configuration as the first resist pattern is formed in the second sub-pixel Pg (third sub-pixel Pb). Therefore, in the second light-emitting layer formation step (third light-emitting layer formation step) of the QLED element layer formation step, a thin portion of the second light-emitting material (third light-emitting material) can be formed on the flat bottom of the second resist pattern (third resist pattern) by applying the second light-emitting material (third light-emitting material) so as to cover the second resist pattern (third resist pattern). When the second resist pattern (third resist pattern) is lifted off, the second light-emitting material (third light-emitting material) is divided at the thin portion, so that a green light-emitting layer (blue light-emitting layer) with suppressed protrusion at the peripheral edge can be formed. As a result, protrusion at the peripheral edges of the red, green, and blue light-emitting layers is suppressed, thereby suppressing the protrusion at the peripheral edge of the light-emitting layer 35c and preventing uneven light emission. Furthermore, since the protrusion at the peripheral edge of the light-emitting layer 35c is suppressed, the QLED element layer 40b including the light-emitting layer 35c is more easily covered by the sealing film 45, thereby improving the sealing performance of the sealing film 45.

[0092] <Other Embodiments> In the above embodiments, a QLED display device in which the first electrode is the anode and the second electrode is the cathode was illustrated. However, the present invention can also be applied to a QLEDEL display device in which the stacked structure of the QLED element is reversed, with the first electrode being the cathode and the second electrode being the anode.

[0093] Furthermore, while the above embodiments illustrate QLED display devices in which the electrode of the TFT connected to the first electrode is used as the drain electrode, the present invention can also be applied to QLED display devices in which the electrode of the TFT connected to the first electrode is called the source electrode.

[0094] Furthermore, although the above embodiments have described a QLED display device as an example, the present invention can be applied to a display device equipped with a plurality of light-emitting elements driven by electric current, and can be applied to an organic EL display device using OLEDs, for example.

[0095] As described above, the present invention is useful for self-illuminating display devices.

[0096] D Display area E Bottom G Slanted area H Through area Ma First photomask Mb Second photomask Mc Third photomask P Subpixel Pr First subpixel Pg Second subpixel Pb Third subpixel R Resist Ra First resist pattern Rb Second resist pattern Rc Third resist pattern 10 Resin substrate (base substrate) 20 TFT layer (thin film transistor layer) 31 Base layer 32 First electrode 34 Hole transport layer (first charge transport layer) 35a, 35c Light-emitting layer 35ab Blue light-emitting layer (third light-emitting layer) 35ag Green light-emitting layer (second light-emitting layer) 35ar Red light-emitting layer (first light-emitting layer) 35b Third light-emitting material 35g Second light-emitting material 35r First light-emitting material 36 Electron transport layer (second charge transport layer) 37 Second electrode 40a, 40b QLED element layer (light-emitting element layer) 45 Encapsulation film 50a, 50b QLED display device

Claims

1. A display device comprising: a base substrate; a thin film transistor layer provided on the base substrate; a light-emitting layer provided on the thin film transistor layer, wherein a plurality of first electrodes, a common first charge transport layer, a plurality of light-emitting layers, a common second charge transport layer, and a common second electrode are sequentially stacked corresponding to a plurality of subpixels constituting a display area; and a sealing film provided on the light-emitting layer, wherein in at least one of the plurality of subpixels, a base layer for supporting the first electrode is provided on the thin film transistor layer side of the corresponding first electrode.

2. A display device according to claim 1, characterized in that the base layer is formed of an organic resin material.

3. A display device according to claim 1, characterized in that the base layer is formed of an inorganic insulating film.

4. A display device according to any one of claims 1 to 3, wherein in at least one subpixel of the plurality of subpixels, the corresponding light-emitting layer is provided so as to cover the upper surface of the corresponding first electrode via the first charge transport layer, and the peripheral edge of the light-emitting layer is positioned inward from or coincides with the peripheral edge of the base layer in a plan view.

5. A display device according to any one of claims 1 to 3, characterized in that, in at least one subpixel of the plurality of subpixels, the corresponding light-emitting layer is provided so as to cover the upper surface of the corresponding first electrode via the first charge transport layer, and the peripheral edge of the light-emitting layer is positioned outside the peripheral edge of the base layer in a plan view.

6. A display device according to any one of claims 1 to 5, characterized in that at least one of the plurality of light-emitting layers includes a quantum dot.

7. A method for manufacturing a display device according to any one of claims 1 to 6, wherein the plurality of subpixels include a first subpixel, a second subpixel, and a third subpixel that display different colors from each other, and the step of forming the plurality of light-emitting layers is: a first resist pattern forming step of applying a resist to the surface of a substrate on which the first charge transport layer is formed, then exposing and developing the resist to form a first resist pattern having through portions that expose portions that overlap with the first electrodes formed on the base layer corresponding to the first subpixels, a flat bottom portion around the through portions, and an inclined inclined portion around the bottom portion; and a first light-emitting layer forming step of applying a first light-emitting material so as to cover the first resist pattern formed in the first resist pattern forming step, then lifting off the first resist pattern to form a first light-emitting layer with the first light-emitting material. A second resist pattern formation step, in which, after applying a resist to the substrate surface on which the first light-emitting layer is formed in the first light-emitting layer formation step, the resist is exposed and developed to form a second resist pattern having through-holes that expose the portion that overlaps with the first electrode formed on the base layer corresponding to the second subpixel, a flat bottom around the through-holes, and an inclined portion around the bottom; a second light-emitting layer formation step, in which, after applying a second light-emitting material so as to cover the second resist pattern formed in the second resist pattern formation step, the second resist pattern is lifted off to form a second light-emitting layer with the second light-emitting material; a third resist pattern formation step, in which, after applying a resist to the substrate surface on which the second light-emitting layer is formed in the second light-emitting layer formation step, the resist is exposed and developed to form a third resist pattern having through-holes that expose the portion that overlaps with the first electrode formed on the base layer corresponding to the third subpixel, a flat bottom around the through-holes, and an inclined portion around the bottom; A method for manufacturing a display device, comprising: a third light-emitting layer formation step, in which a third light-emitting material is applied so as to cover the third resist pattern formed in the third resist pattern formation step described above, and then the third resist pattern is lifted off to form a third light-emitting layer with the third light-emitting material.

8. A method for manufacturing a display device according to claim 7, characterized in that the resist is exposed in two stages in the first resist pattern formation step, the second resist pattern formation step, and the third resist pattern formation step.

9. A method for manufacturing a display device according to claim 7, characterized in that in the first resist pattern formation step, the second resist pattern formation step, and the third resist pattern formation step, the resist is exposed with a halftone photomask.

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