Semiconductor device

Abstract

This semiconductor device comprises: an electrode; a pull-up circuit and a pull-down circuit that control a voltage of the electrode in accordance with input data; an internal circuit that outputs data; a control circuit that can execute an operation of the internal circuit and a calibration operation of the pull-up circuit and the pull-down circuit; and a clock signal control circuit that supplies a first clock signal to the control circuit in a state in which the calibration operation is executed. The clock signal control circuit comprises: a clock signal generation circuit that outputs a second clock signal in a state in which at least one of the operation of the internal circuit and the calibration operation is executed; a clock signal output circuit that outputs the second clock signal as the first clock signal in response to a gate signal; and a gate signal output circuit that outputs a signal indicating an execution state of the calibration operation as a gate signal in response to switching of the second clock signal.

Description

Semiconductor equipment

[0001] This embodiment relates to a semiconductor device.

[0002] A semiconductor device is known that includes electrodes, pull-up and pull-down circuits that control the voltage of the electrodes according to input data, and an internal circuit that outputs the data supplied to the pull-up and pull-down circuits.

[0003] Japanese Patent Publication No. 2021-034084

[0004] To provide a semiconductor device that operates optimally.

[0005] A semiconductor device according to one embodiment includes electrodes, a pull-up circuit and a pull-down circuit that control the voltage of the electrodes according to input data, an internal circuit that outputs data supplied to the pull-up circuit and the pull-down circuit, a control circuit capable of performing a calibration operation that adjusts the operation of the internal circuit and the output impedance of the pull-up circuit and the pull-down circuit, and a clock signal control circuit that supplies a first clock signal to the control circuit while the calibration operation is being performed. The clock signal control circuit includes a clock signal generation circuit that outputs a second clock signal while at least one of the operation of the internal circuit and the calibration operation is being performed, a clock signal output circuit that outputs the second clock signal as a first clock signal according to a gate signal, and a gate signal output circuit that outputs a signal indicating the execution status of the calibration operation as a gate signal according to the switching of the second clock signal.

[0006] This is a schematic block diagram showing the configuration of the memory system 10. This is a schematic side view showing an example of the configuration of the memory system 10. This is a schematic top view showing an example of the configuration of the memory system 10. This is a schematic circuit diagram showing a part of the configuration of the memory die MD. This is a schematic perspective view showing a part of the configuration of the memory cell array MCA. This is a schematic cross-sectional view for explaining the read operation. This is a schematic cross-sectional view for explaining the write operation. This is a schematic cross-sectional view for explaining the erase operation. This is a schematic block diagram showing the configuration of the peripheral circuit PC. This is a schematic circuit diagram showing the configuration of the termination resistance adjustment circuit in the input / output control circuit I / O. This is a table for explaining the termination resistance adjustment circuit in the input / output control circuit I / O. This is a schematic circuit diagram showing the configuration of the calibration circuit. This is a schematic circuit diagram showing the configuration of the calibration circuit. This is a timing chart for explaining the timing at which the calibration operation can be performed. This is a timing chart for explaining the timing at which the calibration operation can be performed. This is a schematic circuit diagram showing the configuration of the clock signal control circuit according to the first embodiment. This is a schematic circuit diagram showing a part of the configuration of the clock signal control circuit according to the first embodiment. This is a schematic circuit diagram showing a part of the configuration of the clock signal control circuit according to the first embodiment. This is a schematic waveform diagram illustrating the operation of the clock signal control circuit according to the first embodiment. This is a schematic waveform diagram illustrating the operation of the clock signal control circuit according to the first embodiment. This is a schematic waveform diagram illustrating the operation of the clock signal control circuit according to the first embodiment. This is a schematic circuit diagram showing the configuration of the clock signal control circuit according to the second embodiment. This is a schematic circuit diagram showing a part of the configuration of the clock signal control circuit according to the second embodiment. This is a schematic waveform diagram illustrating the operation of the clock signal control circuit according to the second embodiment. This is a timing chart illustrating the timing at which calibration operations can be performed in the semiconductor device according to the third embodiment.

[0007] Next, a semiconductor device according to an embodiment will be described in detail with reference to the drawings. It should be noted that the following embodiments are merely examples and are not intended to limit the scope of the present invention.

[0008] Furthermore, in this specification, the term "semiconductor device" may refer to semiconductor memory devices, or it may refer to other devices such as integrated circuits for computing, integrated circuits for communication, etc.

[0009] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die (memory chip), or to a memory system including a controller die, such as a memory card or SSD. It may also refer to a configuration including a host computer, such as a smartphone, tablet, or personal computer. In this specification, NAND flash memory is used as an example of a semiconductor memory device. However, the semiconductor memory device may be a memory other than NAND flash memory.

[0010] Furthermore, in this specification, the term "internal circuitry" may refer to memory cell arrays, or it may refer to arithmetic circuits, communication circuits, etc.

[0011] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0012] Furthermore, in this specification, when it is said that the first configuration is "electrically connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and the second configuration is electrically connected to the third configuration via the first configuration.

[0013] Furthermore, in this specification, when it is said that a circuit "makes two wires conductive," it may mean, for example, that the circuit includes a transistor, that the transistor is located in the current path between the two wires, and that the transistor is in the ON state.

[0014] [First Embodiment] [Memory System 10] Figure 1 is a schematic block diagram showing the configuration of the memory system 10.

[0015] The memory system 10 performs operations such as reading, writing, and erasing user data in response to signals transmitted from the host computer 20. The memory system 10 is, for example, a memory card, SSD, or other system capable of storing user data. The memory system 10 comprises a plurality of memory dies MD for storing user data, and a controller die CD connected to these plurality of memory dies MD and the host computer 20. The controller die CD includes, for example, a processor, RAM, etc., and performs operations such as logical address-to-physical address conversion, bit error detection / correction, garbage collection (compaction), and wear leveling.

[0016] Figure 2 is a schematic side view showing an example configuration of the memory system 10. Figure 3 is a schematic top view showing the same configuration. For the sake of explanation, some components are omitted in Figures 2 and 3.

[0017] As shown in Figure 2, the memory system 10 according to this embodiment comprises a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory dies MD. Pad electrodes P are provided on the upper surface of the mounting substrate MSB at the Y-direction end region, and some other regions are bonded to the lower surface of the memory dies MD via adhesive or the like. Pad electrodes P are provided on the upper surface of the memory dies MD at the Y-direction end region, and other regions are bonded to the lower surface of other memory dies MD or controller die CD via adhesive or the like. Pad electrodes P are provided on the upper surface of the controller die CD at the Y-direction end region.

[0018] As shown in Figure 3, the mounting substrate MSB, the multiple memory dies MD, and the controller die CD each have multiple pad electrodes P arranged in the X direction. The multiple pad electrodes P provided on the mounting substrate MSB, the multiple memory dies MD, and the controller die CD are each connected to one another via bonding wires B.

[0019] Note that the configurations shown in Figures 2 and 3 are merely examples, and the specific configuration can be adjusted as appropriate. For example, in the examples shown in Figures 2 and 3, controller dies CD are stacked on multiple memory dies MD, and these components are connected by bonding wires B. In such a configuration, multiple memory dies MD and controller dies CD are contained within a single package. However, the controller die CD may be contained in a separate package from the memory dies MD. Also, multiple memory dies MD and controller dies CD may be connected to each other via through-electrodes or the like, instead of bonding wires B.

[0020] [Memory Die MD Configuration] Figure 4 is a schematic circuit diagram showing a part of the configuration of the memory die MD. As shown in Figure 4, the memory die MD comprises a memory cell array MCA that stores user data and a peripheral circuit PC connected to the memory cell array MCA.

[0021] [Configuration of Memory Cell Array MCA] The memory cell array MCA comprises multiple memory blocks BLK. Each of these memory blocks BLK comprises multiple string units SU. Each of these string units SU comprises multiple memory strings MS. One end of each of these memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other end of each of these memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0022] The memory string MS comprises drain-side selection transistors STDT and STD, multiple memory cells MC (memory cell transistors), and source-side selection transistors STS and STSB, all connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistors STDT and STD and the source-side selection transistors STS and STSB may simply be referred to as selection transistors STDT, STD, STS, and STSB, etc.

[0023] A memory cell MC is a field-effect transistor comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge storage film. The memory cell MC stores one or more bits of user data. A word line WL is connected to the gate electrode of each of the multiple memory cell MCs corresponding to one memory string MS. These word lines WL are provided corresponding to each memory block BLK and are commonly connected to all memory string MS in the memory block BLK.

[0024] The selection transistors STDT, STD, STS, and STSB are field-effect transistors comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the selection transistors STDT, STD, STS, and STSB are connected to selection gate lines SGDT, SGD, SGS, and SGSB, respectively. The drain-side selection gate line SGD is provided corresponding to the string unit SU and is commonly connected to all memory strings MS in the string unit SU. The drain-side selection gate line SGDT and the source-side selection gate lines SGS and SGSB are provided corresponding to the memory block BLK and are commonly connected to all memory strings MS in the memory block BLK.

[0025] Figure 5 is a schematic perspective view showing a part of the configuration of the memory cell array MCA. The memory cell array MCA is provided above the semiconductor substrate 100. In addition, a plurality of transistors Tr that constitute the peripheral circuit PC are provided on the upper surface of the semiconductor substrate 100. Each of these plurality of transistors Tr comprises a channel region which is part of the upper surface of the semiconductor substrate 100, a gate insulating film formed on the upper surface of the semiconductor substrate 100, and a gate electrode which faces the channel region via the gate insulating film.

[0026] The memory cell array MCA comprises multiple memory blocks BLK arranged in the Y direction. An interblock insulating layer ST, such as silicon oxide (SiO2), is provided between two adjacent memory blocks BLK in the Y direction. Furthermore, multiple bit lines BL are provided above the memory cell array MCA, arranged in the X direction and extending in the Y direction.

[0027] The memory block BLK comprises a plurality of conductive layers 110 aligned in the Z direction, a plurality of semiconductor columns 120 extending in the Z direction, and a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor columns 120, respectively.

[0028] The conductive layer 110 is a substantially plate-shaped conductive layer that extends in the X direction. The conductive layer 110 may contain a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between a plurality of conductive layers 110 arranged in the Z direction.

[0029] Of the multiple conductive layers 110, one or more conductive layers 110 located in the bottom layer function as the gate electrodes of the source-side selection gate line SGSB (Figure 4) and the multiple source-side selection transistors STSB (Figure 4) connected thereto.

[0030] Furthermore, one or more conductive layers 110 located above this function as gate electrodes for the source-side selection gate line SGS (Figure 4) and the multiple source-side selection transistors STS (Figure 4) connected thereto.

[0031] Furthermore, the multiple conductive layers 110 located above this function as gate electrodes for the word line WL (Figure 4) and the multiple memory cells MC (Figure 4) connected thereto.

[0032] Furthermore, one or more conductive layers 110 located above this function as gate electrodes for the drain-side selection gate wire SGD (Figure 4) and the multiple drain-side selection transistors STD (Figure 4) connected thereto.

[0033] Furthermore, one or more conductive layers 110 located above this function as gate electrodes for the drain-side selection gate wire SGDT (Figure 4) and the multiple drain-side selection transistors STDT (Figure 4) connected thereto.

[0034] A semiconductor layer 112 is provided below the multiple conductive layers 110. The semiconductor layer 112 may contain, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P). An insulating layer 101, such as silicon oxide (SiO2), is provided between the semiconductor layer 112 and the conductive layers 110.

[0035] The semiconductor layer 112 functions as a source line SL (Figure 4). The source line SL is provided in common for all memory blocks BLK included in the memory cell array MCA, for example.

[0036] The semiconductor columns 120 are arranged in a predetermined pattern in the X and Y directions. The semiconductor columns 120 function as channel regions for multiple memory cells MC and selection transistors STDT, STD, STS, and STSB included in one memory string MS (Figure 4). The semiconductor columns 120 are, for example, semiconductor layers such as polycrystalline silicon (Si). The semiconductor columns 120 have, for example, a substantially cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central portion. The outer surfaces of the semiconductor columns 120 are each surrounded by conductive layers 110 and face the conductive layers 110.

[0037] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the end of the semiconductor column 120 on the bit line BL side. The impurity region 121 is connected to the bit line BL via contact electrodes Ch and Cb.

[0038] The gate insulating film 130 has a substantially cylindrical shape that covers the outer surface of the semiconductor column 120. The gate insulating film 130 includes, for example, a tunnel insulating film, a charge storage film, and a block insulating film laminated between the semiconductor column 120 and the conductive layer 110. The tunnel insulating film and the block insulating film are insulating films such as silicon oxide (SiO2). The charge storage film is a charge-storing film such as silicon nitride (SiN). The tunnel insulating film, the charge storage film, and the block insulating film have a substantially cylindrical shape and extend in the Z direction along the outer surface of the semiconductor column 120, excluding the contact portion between the semiconductor column 120 and the semiconductor layer 112.

[0039] Furthermore, the gate insulating film 130 may include a floating gate made of, for example, polycrystalline silicon containing N-type or P-type impurities.

[0040] Multiple contact electrodes CC are connected to multiple conductive layers 110. The multiple conductive layers 110 are electrically connected to the peripheral circuit PC via these multiple contact electrodes CC. As shown in Figure 5, these multiple contact electrodes CC extend in the Z direction and are connected to the conductive layer 110 at their lower ends. The contact electrodes CC may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0041] Furthermore, the memory cell array MCA may be formed upside down. For example, the bit line BL may be provided below multiple memory blocks BLK. Also, the semiconductor layer 112 may be provided above multiple conductive layers 110.

[0042] [Operation of Memory Cell Array MCA] Next, the operation of the memory cell array MCA will be described. The memory cell array MCA according to the present embodiment is configured to be capable of executing a read operation, a write operation, and an erase operation. In the following description, the read operation, the write operation, and the erase operation of the memory cell array MCA may be referred to as "core operations".

[0043] FIG. 6 is a schematic cross-sectional view for explaining the read operation. In the following description, the word line WL that is the target of the operation is called the selected word line WL SRC , SRC , SG and the other word lines WL are called non-selected word lines WL U in some cases. ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​The voltage difference is greater than the threshold voltage of the source-side selection transistors STS and STSB. Therefore, an electron channel is formed in the channel region of the source-side selection transistors STS and STSB, and the voltage V SRC It will be forwarded.

[0047] Furthermore, during the read operation, the non-selected word line WL U Read path voltage V READ It supplies the read path voltage V. READ The operating voltage is V DD and voltage V SRC It is larger than that. Also, the read path voltage V READ and operating voltage V DD and voltage V SRC The voltage difference is greater than the threshold voltage of the memory cell MC, regardless of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, and the operating voltage V is applied to the selected memory cell MC. DD and voltage V SRC It will be forwarded.

[0048] Furthermore, during the reading operation, the selected word line WL S Readout voltage V CGR It supplies the read voltage V. CGR The read path voltage V READ Smaller than. Readout voltage V CGR and voltage V SRC The voltage difference is greater than the threshold voltage of the memory cell MC where some data has been recorded. Therefore, the memory cell MC where some data has been recorded turns ON. Consequently, current flows through the bit line BL connected to such a memory cell MC. On the other hand, the read voltage V CGR and V SRC The voltage difference is smaller than the threshold voltage of the memory cell MC where some data has been recorded. Therefore, the memory cell MC where some data has been recorded is in the OFF state. Consequently, no current flows through the bit line BL connected to such a memory cell MC.

[0049] Furthermore, during the read operation, the sense amplifier SA (described later) detects the current or voltage of each bit line BL, stores it as user data, and outputs it to the cache memory CM (described later).

[0050] Figure 7 is a schematic cross-sectional view illustrating the writing operation.

[0051] In the writing operation, for example, the bit line BL connected to the one among the multiple selected memory cells MC that adjusts the threshold voltage. W Voltage V SRC It supplies the bit line BL connected to the memory cell MC that does not have its threshold voltage adjusted. P Operating voltage V DD This supplies the following. Below, among the multiple selectable memory cells (MCs), those that adjust the threshold voltage are sometimes referred to as "write memory cells (MCs)," and those that do not adjust the threshold voltage are sometimes referred to as "prohibition memory cells (MCs)."

[0052] Furthermore, during the writing operation, a voltage V is applied to the drain-side selected gate lines SGDT and SGD. SGD It will be supplied.

[0053] Voltage V SGD is the voltage V SRC It is larger than that. Also, voltage V SGD and voltage V SRC The voltage difference is greater than the threshold voltage of the drain-side selection transistors STDT and STD. Therefore, the bit line BL W In the channel region of the drain-side selection transistors STDT and STD connected to the voltage V, an electron channel is formed, and the voltage V SRC It will be forwarded.

[0054] On the other hand, voltage V SGD and operating voltage V DD The voltage difference is smaller than the threshold voltage of the drain-side selection transistors STDT and STD. Therefore, the bit line BL P The drain-side selection transistors STDT and STD connected to it will be in the OFF state.

[0055] Furthermore, during the writing operation, a voltage V is applied to the source line SL. SRCA ground voltage V is supplied to the source-side selected gate lines SGS and SGSB. SS This is supplied. As a result, the source-side selection transistors STS and STSB are turned OFF.

[0056] Furthermore, during the writing operation, the non-selected word line WL U Write path voltage V PASS It supplies the write path voltage V. PASS The read path voltage V READ It is greater than. Also, the write path voltage V PASS and voltage V SRC The voltage difference is greater than the threshold voltage of the memory cell MC, regardless of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the unselected memory cell MC, and the voltage V is applied to the written memory cell MC. SRC It will be forwarded.

[0057] Furthermore, during the writing operation, the selected word line WL S Program voltage V PGM It supplies the program voltage V. PGM The write path voltage V PASS It is larger than that.

[0058] Here, bit line BL W The channels of the semiconductor column 120 connected to it have a voltage V SRC Such a semiconductor column 120 and a selected word line WL are supplied. S A relatively large electric field is generated between the two. As a result, electrons in the channel of the semiconductor column 120 tunnel into the charge storage film in the gate insulating film 130 (Figure 5). This increases the threshold voltage of the write memory cell MC.

[0059] Meanwhile, bit line BL P The channel of the semiconductor column 120 connected to it is electrically floating, and the potential of this channel is the non-selected word line WL U Capacitive coupling with the write path voltage V PASS It has risen to this extent. Such semiconductor column 120 and selected word line WL SOnly an electric field smaller than the one described above is generated between them. Therefore, electrons in the channel of the semiconductor column 120 do not tunnel into the charge storage film in the gate insulating film 130 (Figure 5). Consequently, the threshold voltage of the disabled memory cell MC does not increase.

[0060] Figure 8 is a schematic cross-sectional view illustrating the erase operation.

[0061] During the erase operation, the erase voltage V is applied to the bit line BL and the source line SL. ERA The following is supplied: Eraser voltage V ERA For example, the program voltage V PGM It can be larger, and the program voltage V PGM It can also be equal to this.

[0062] Furthermore, during the erase operation, a voltage V is applied to the drain-side selected gate line SGDT. SG A voltage V is supplied. SG ' is the erasure voltage V ERA It is smaller than this. As a result, GIDL (Gate Induced Drain Leakage) occurs in the drain-side selection transistor STDT, generating electron-hole pairs. Additionally, electrons move to the bit line BL side, and holes move to the memory cell MC side.

[0063] Furthermore, during the erase operation, a voltage V is applied to the drain-side selected gate line SGD. SG '' is supplied. Voltage V SG '' is the erasure voltage V ERA Smaller than, voltage V SG It is larger than '. As a result, a hole channel is formed in the channel region of the drain-side selection transistor STD, and holes are transferred to the memory cell MC side.

[0064] Furthermore, during the erase operation, a voltage V is applied to the source-side selected gate line SGSB. SG A supply of ' is generated. This causes GIDL to occur in the source-side selection transistor STSB, generating electron-hole pairs. The electrons move to the source line SL side, and the holes move to the memory cell MC side.

[0065] Furthermore, during the erase operation, a voltage V is applied to the source-side selected gate line SGS.SG A hole channel is supplied. As a result, a hole channel is formed in the channel region of the source-side selection transistor STS, and holes are transferred to the memory cell MC.

[0066] Furthermore, during the erase operation, the ground voltage V is applied to the word line WL. SS This is supplied. As a result, holes in the channels of the semiconductor pillar 120 tunnel into the charge storage film in the gate insulating film 130 (Figure 5). This reduces the threshold voltage of the memory cell MC.

[0067] [Peripheral Circuit PC Configuration] Figure 9 is a schematic block diagram showing the configuration of the peripheral circuit PC.

[0068] Figure 9 illustrates multiple control terminals. These control terminals may be represented as terminals corresponding to high-active signals (positive logic signals), as terminals corresponding to low-active signals (negative logic signals), or as terminals corresponding to both high-active and low-active signals. In Figure 9, the symbols for control terminals corresponding to low-active signals include an overline. In this specification, the symbols for control terminals corresponding to low-active signals include a slash (" / "). Note that the description in Figure 9 is illustrative, and the specific configuration can be adjusted as appropriate. For example, some or all high-active signals may be treated as low-active signals, or some or all low-active signals may be treated as high-active signals.

[0069] Furthermore, arrows indicating input / output directions are shown next to the multiple control terminals shown in Figure 9. In Figure 9, control terminals with arrows pointing from left to right can be used for inputting data or other signals from the controller die CD to the memory die MD. In Figure 9, control terminals with arrows pointing from right to left can be used for outputting data or other signals from the memory die MD to the controller die CD. In Figure 9, control terminals with arrows pointing in both directions can be used for both inputting data or other signals from the controller die CD to the memory die MD, and outputting data or other signals from the memory die MD to the controller die CD.

[0070] The peripheral circuit PC comprises a row decoder RD and a sense amplifier SA connected to the memory cell array MCA, and a cache memory CM connected to the sense amplifier. The peripheral circuit PC also comprises a voltage generation circuit VG and a sequencer SQC. Furthermore, the peripheral circuit PC comprises an input / output control circuit I / O, a logic circuit CTR, an address register ADR, a command register CMR, and a status register STR.

[0071] The row decoder RD includes, for example, a block decoder that decodes the block address in the row address RA included in the address data Add, and a voltage transfer circuit that, in accordance with the output signal of the block decoder, connects multiple word lines WL (Figure 4) included in one of the multiple memory blocks BLK to multiple voltage supply lines (not shown).

[0072] The sense amplifier SA comprises multiple sense circuits and multiple voltage transfer circuits connected to multiple bit lines BL, and a data latch circuit. The sense circuits latch "0" or "1" data based on the voltage or current of the bit lines BL to the data latch circuit, for example, according to a control signal from the sequencer SQC. The voltage transfer circuits adjust the voltage of the bit lines BL to "H" or "L" based on the "0" or "1" data latched to the data latch circuit, for example, according to a control signal from the sequencer SQC. User data Dat in the data latch circuit is output to the input / output control circuit I / O via the cache memory CM and data bus DB. User data Dat output from the input / output control circuit I / O is latched to the data latch circuit in the sense amplifier SA via the data bus DB and cache memory CM.

[0073] The voltage generation circuit VG includes, for example, a boost circuit such as a charge pump circuit and a buck circuit such as a regulator. These boost and buck circuits each control the power supply voltage V CC and ground voltage V SS These voltage supply lines are connected to the pad electrodes P, as described with reference to Figures 2 and 3. The voltage generation circuit VG generates multiple operating voltages that are applied to the bit line BL, source line SL, word line WL, and selection gate lines SGD and SGS during read, write, and erase operations on the memory cell array MCA, according to a control signal from the sequencer SQC, and supplies these voltages to the bit line BL, source line SL, word line WL, and selection gate lines SGDT, SGD, SGS, and SGSB via multiple voltage supply lines. The operating voltages output from the voltage supply lines are adjusted as appropriate according to the control signal from the sequencer SQC.

[0074] The SQC sequencer outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG, according to the command data Cmd input to the command register CMR. The SQC sequencer also outputs status data Stt, which indicates the state of the memory die MD, to the status register STR as appropriate.

[0075] Furthermore, the sequencer SQC generates a ready / busy signal and outputs it to the terminal RY / / BY. The terminal RY / / BY is in the "L" state when an operation that supplies voltage to the memory cell array MCA is being performed, such as a read operation, write operation, or erase operation, and in the "H" state at all other times. During the period when the terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is basically prohibited. Conversely, during the period when the terminal RY / / BY is in the "H" state (ready period), access to the memory die MD is permitted. The terminal RY / / BY is implemented, for example, by the pad electrode P described with reference to Figures 2 and 3.

[0076] The address register ADR is connected to the input / output control circuit I / O and stores the address data Add input from the input / output control circuit I / O. The address register ADR comprises, for example, multiple 8-bit register sequences. When an internal operation such as a read operation, write operation, or erase operation is performed, the register sequence holds the address data Add corresponding to the internal operation being performed.

[0077] The address data Add includes, for example, the column address CA and the row address RA. The row address RA includes, for example, the block address that identifies the memory block BLK (Figure 4), the page address that identifies the string unit SU and the word line WL, the plane address that identifies the memory cell array MCA, and the chip address that identifies the memory die MD.

[0078] The command register CMR is connected to the input / output control circuit I / O, and command data Cmd is input from the input / output control circuit I / O. When command data Cmd is input to the command register CMR, a control signal is sent to the sequencer SQC.

[0079] The status register STR is connected to the input / output control circuit I / O and stores status data Stt to be output to the input / output control circuit I / O. The status register STR comprises, for example, multiple 8-bit register sequences. The register sequences hold status data Stt related to the internal operation being performed, for example, when an internal operation such as a read operation, write operation, or erase operation is executed. The register sequences also hold, for example, ready / busy information for the memory cell array MCA.

[0080] The input / output control circuit (I / O) comprises data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS and DQS, a plurality of input circuits and driver circuits connected to the data signal input / output terminals DQ0 to DQ7, respectively, and a shift register connected to these plurality of input circuits and output circuits. The input circuits are, for example, receivers such as comparators. The driver circuits function as, for example, OCD (Off Chip Driver) circuits that output data and adjust the output impedance when data is output. They also function as circuits that adjust the input impedance when data is input. In the following description, this driver circuit will be referred to as the termination resistance adjustment circuit.

[0081] Each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS are implemented by, for example, the pad electrodes P described with reference to Figures 2 and 3. Data input via the data signal input / output terminals DQ0 to DQ7 is input to the cache memory CM, address register ADR, or command register CMR in accordance with the internal control signal from the logic circuit CTR. Data output via the data signal input / output terminals DQ0 to DQ7 is output from the cache memory CM or status register STR in accordance with the internal control signal from the logic circuit CTR.

[0082] Signals input via the data strobe signal input / output terminals DQS and / DQS (for example, data strobe signals and their complementary signals) are used when inputting data via the data signal input / output terminals DQ0 to DQ7. The data input via the data signal input / output terminals DQ0 to DQ7 is captured into the shift register in the input / output control circuit I / O at the timing of the rising edge of the voltage at the data strobe signal input / output terminal DQS and the falling edge of the voltage at the data strobe signal input / output terminal / DQS, as well as the falling edge of the voltage at the data strobe signal input / output terminal DQS and the rising edge of the voltage at the data strobe signal input / output terminal / DQS.

[0083] The logic circuit CTR comprises multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE, and logic circuits connected to these multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE. The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and outputs internal control signals to the input / output control circuit I / O accordingly. In the following description, the external control terminal / CE may be referred to as the "chip enable signal input terminal / CE".

[0084] Furthermore, each of the external control terminals / CE, CLE, ALE, / WE, / RE, and RE is implemented by the pad electrode P described with reference to Figures 2 and 3, for example.

[0085] Signals input via the external control terminal / CE (e.g., chip enable signal) are used when selecting the memory die MD. When "L" is input to the external control terminal / CE, the memory die MD becomes capable of inputting and outputting user data Dat, command data Cmd, and address data Add (hereinafter sometimes simply referred to as "data"). When "H" is input to the external control terminal / CE, the memory die MD becomes incapable of inputting and outputting data.

[0086] Signals input via the external control terminal CLE (for example, the command latch enable signal) are used when using the command register CMR. When "H" is input to the external control terminal CLE, data input via the data signal input / output terminals DQ0 to DQ7 is stored as command data Cmd in the buffer memory of the input / output control circuit I / O and transferred to the command register CMR.

[0087] Signals input via the external control terminal ALE (for example, the address latch enable signal) are used when using the address register ADR. When "H" is input to the external control terminal ALE, data input via the data signal input / output terminals DQ0 to DQ7 is stored as address data Add in the buffer memory within the input / output control circuit I / O and transferred to the address register ADR.

[0088] Furthermore, if "L" is input to both external control terminals CLE and ALE, the data input via data signal input / output terminals DQ0 to DQ7 is stored as user data Dat in the shift register within the input / output control circuit I / O. The user data Dat stored in the shift register is transferred to the cache memory CM via the bus DB.

[0089] Signals input via the external control terminal / WE (e.g., write enable signal) are used when inputting data via the data signal input / output terminals DQ0 to DQ7. Data input via the data signal input / output terminals DQ0 to DQ7 is captured into the shift register, command register CMR, or address register ADR within the input / output control circuit I / O at the timing of the rising voltage of the external control terminal / WE (switching of the input signal).

[0090] Furthermore, when inputting data, you may use the external control terminal / WE or the data strobe signal input / output terminals DQS, / DQS.

[0091] External control terminal / RE, signals input via RE (e.g., read enable signal and its complementary signal) are used when outputting data via data signal input / output terminals DQ0 to DQ7. The data input via data signal input / output terminals DQ0 to DQ7 switches at the rising of the voltage of external control terminal RE and the falling of the voltage of external control terminal / RE, as well as at the falling of the voltage of external control terminal RE and the rising of the voltage of external control terminal / RE.

[0092] [Configuration of termination resistance adjustment circuit in input / output control circuit I / O] FIG. 10 is a schematic circuit diagram showing the configuration of the termination resistance adjustment circuit in the input / output control circuit I / O. FIG. 11 is a table for explaining the termination resistance adjustment circuit.

[0093] The termination resistance adjustment circuit includes seven termination resistance adjustment units 210 connected in parallel to data signal input / output terminals DQ0 to DQ7 and data strobe signal input / output terminals DQS, / DQS, and seven termination resistance adjustment unit control circuits 220 connected to these seven termination resistance adjustment units 210.

[0094] The seven termination resistance adjustment units 210 each have an impedance of 240Ω. Also, the seven termination resistance adjustment units 210 are each connected to signal line TRA_EN<6:0>, and the number of termination resistance adjustment units 210 driven according to the signal line TRA_EN<6:0> is controlled. For example, when a signal 0000001 (01 in hexadecimal) is input to the signal line TRA_EN<6:0>, as shown in FIG. 11, the impedance Z of the termination resistance adjustment circuit DRV is set to about 240Ω. Also, for example, when a signal 0011111 (1F in hexadecimal) is input to the signal line TRA_EN<6:0>, the impedance Z of the termination resistance adjustment circuit DRV is set to about 240Ω / 5 = 48Ω. The signal of the signal line TRA_EN<6:0> is controlled by the user, for example.

[0095] The termination resistance adjustment unit 210 is, for example, as shown in FIG. 10, each with a voltage V DDQThe unit includes a pull-up circuit 211 connected between the voltage supply line to which the voltage is supplied and the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS. The termination resistance adjustment unit 210 is connected to the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS, respectively, and the ground voltage V SS It includes a pad electrode P to which a current is supplied, and a pull-down circuit 212 connected between them.

[0096] The pull-up circuit 211 consists of a resistor 213 connected to the data signal input / output terminals DQ0 to DQ7 or the data strobe signal input / output terminals DQS, / DQS, and the resistor 213 and voltage V DDQ The system comprises n+1 (n is a natural number) transistors 214 connected in parallel between the voltage supply lines to which the power is supplied. The transistors 214 are PMOS transistors. Each of the n+1 transistors 214 has at least one of different channel widths and channel lengths, and has n+1 different resistance values. The gate electrodes of the n+1 transistors 214 are connected to signal lines Up*<0> to Up*<n> (where * is one of 0 to 6). The n+1 bits of data input to signal lines Up*<0> to Up*<n> are adjusted so that the impedance when the pull-up circuit 211 is driven is approximately 240Ω.

[0097] The pull-down circuit 212 consists of a resistor 215 connected to data signal input / output terminals DQ0 to DQ7 or data strobe signal input / output terminals DQS, / DQS, and the resistor 215 and the ground voltage V SSThe system comprises m+1 (m is a natural number) transistors 216 connected in parallel between the pad electrodes P to which the current is supplied. The transistors 216 are NMOS transistors. Each of the m+1 transistors 216 has at least one of different channel widths and channel lengths, and has m+1 different resistance values. The gate electrodes of the m+1 transistors 216 are connected to signal lines Dn*<0> to Dn*<m> (where * is one of 0 to 6). The m+1 bits of data input to signal lines Dn*<0> to Dn*<m> are adjusted so that the impedance when driving the pull-down circuit 212 is approximately 240Ω.

[0098] The termination resistance adjustment unit control circuit 220 includes, for example, n+1 OR circuits 221 and m+1 AND circuits 222.

[0099] When outputting data, one input terminal of the n+1 OR circuits 221 receives a "1" or "0" signal output from the data signal input / output terminals DQ0 to DQ7, or a clock signal output from the data strobe signal input / output terminals DQS, / DQS. The other input terminal of the n+1 OR circuits 221 receives the corresponding bit from the n+1 bit data PCODE<n:0> corresponding to the n+1 PMOS transistors included in the pull-up circuit 211.

[0100] Furthermore, when outputting data, one input terminal of the m+1 AND circuits 222 receives a "1" or "0" signal output from data signal input / output terminals DQ0 to DQ7, or a clock signal output from data strobe signal input / output terminals DQS, / DQS. The other input terminal of the m+1 AND circuits 222 receives the corresponding bit from the m+1 bit data NCODE<m:0> corresponding to the m+1 NMOS transistors included in the pull-down circuit 212.

[0101] When inputting data, the signals from one input terminal of the n+1 OR circuits 221 and one input terminal of the m+1 AND circuits 222 are fixed to "1" or "0". The signals from the other input terminal of the n+1 OR circuits 221 and the other input terminal of the m+1 AND circuits 222 are respectively input to the corresponding bits of the n+1 bit data PCODE <n:0> and the m+1 bit data NCODE <m:0>.

[0102] Furthermore, the data PCODE<n:0> used for data input may be different from the data PCODE<n:0> used for data output. Similarly, the data NCODE<m:0> used for data input may be different from the data NCODE<m:0> used for data output.

[0103] [Calibration Circuit Configuration] Figures 12 and 13 are schematic circuit diagrams showing the configuration of the calibration circuit.

[0104] Although not explained in Figure 9, the peripheral circuit PC includes a calibration circuit. The calibration circuit adjusts the data PCODE<n:0> and data NCODE<m:0> so that the impedance when the pull-up circuit 211 and the pull-down circuit 212 are driven is approximately 240Ω.

[0105] As shown in Figure 12, the calibration circuit includes a first replica unit 310 connected to the calibration electrode ZQ, a first replica unit control circuit 320 connected to the first replica unit 310, a second replica unit 330 connected to the calibration electrode ZQ, a second replica unit control circuit 340 connected to the second replica unit 330, a reference voltage generation circuit 350, a data latch circuit 360, and a calibration control circuit 370.

[0106] The first replica unit 310 has a voltage V DDQ The system includes a pull-up circuit 311 connected between a voltage supply line to which a voltage is supplied and a calibration electrode ZQ.

[0107] As shown in FIG. 13, the pull-up circuit 311 includes a resistance element 313 connected to the calibration electrode ZQ, and n + 1 transistors 314 connected in parallel between the resistance element 313 and the voltage supply line to which the voltage V is supplied. The transistor 314 is a PMOS transistor. The n + 1 transistors 314 each have at least one of different channel widths and channel lengths and have n + 1 different resistance values. The gate electrodes of the n + 1 transistors 314 are respectively connected to n + 1 signal lines. The data PCODE<n:0> is input to these n + 1 signal lines. DDQ

[0108] As shown in FIG. 12, the first replica unit control circuit 320 includes a counter 321 that outputs the data PCODE<n:0>, a comparator 322 that controls the counter 321, and an ESD protection circuit 323 connected to the input terminal of the comparator 322.

[0109] The counter 321 adjusts the data PCODE<n:0> in synchronization with the clock signal. For example, when the output signal of the comparator 322 is in the "L" state, 1 is subtracted from the value indicated by the n + 1-bit data PCODE<n:0>. Also, when the output signal of the comparator 322 is in the "H" state, 1 is added to the value indicated by the n + 1-bit data PCODE<n:0>.

[0110] The inverting input terminal of the comparator 322 is connected to the reference voltage generation circuit 350 via the ESD protection circuit 323. The non-inverting input terminal of the comparator 322 is connected to the calibration electrode ZQ via the ESD protection circuit 323. Also, the comparator 322 is controlled by the calibration control circuit 370. <​​​​​​The second replica unit 330 includes a pull-up circuit 331 connected between the voltage supply line to which the voltage is supplied and the calibration electrode ZQ. SS It includes an electrode that supplies the gas and a pull-down circuit 332 connected between them.

[0113] As shown in Figure 13, the pull-up circuit 331 consists of a resistor 333 connected to the calibration electrode ZQ, and the resistor 333 and voltage V DDQ The system comprises n+1 transistors 334 connected in parallel between the voltage supply lines to which the power is supplied. The transistors 334 are PMOS transistors. Each of the n+1 transistors 334 has at least one of different channel widths and channel lengths, and has n+1 different resistance values. The gate electrodes of each of the n+1 transistors 334 are connected to n+1 signal lines. Data PCODE<n:0> is input to these n+1 signal lines.

[0114] As shown in Figure 13, the pull-down circuit 332 consists of a resistive element 335 connected to the calibration electrode ZQ, and the resistive element 335 and the ground voltage V SS The system comprises m+1 transistors 336 connected in parallel between electrodes supplying a signal. The transistors 336 are NMOS transistors. Each of the m+1 transistors 336 has at least one of different channel widths and channel lengths, and has m+1 different resistance values. The gate electrodes of each of the m+1 transistors 336 are connected to m+1 signal lines. The data NCODE<m:0> is input to these m+1 signal lines.

[0115] As shown in Figure 12, the second replica unit control circuit 340 includes a counter 341 that outputs data NCODE<m:0>, a comparator 342 that controls the counter 341, and an ESD protection circuit 343 connected to the input terminal of the comparator 342.

[0116] The counter 341 adjusts the data NCODE<m:0> in synchronization with the clock signal. For example, when the output signal of the comparator 342 is in the "L" state, 1 is added to the value indicated by the m+1 bit data NCODE<m:0>. Also, when the output signal of the comparator 342 is in the "H" state, the counter 341 subtracts 1 from the value indicated by the n+1 bit data NCODE<m:0>.

[0117] The inverting input terminal of comparator 342 is connected to the reference voltage generation circuit 350 via the ESD protection circuit 343. The non-inverting input terminal of comparator 342 is connected to the calibration electrode ZQ via the ESD protection circuit 343. Furthermore, comparator 342 is controlled by the calibration control circuit 370.

[0118] The ESD protection circuit 343 protects the comparator 342 from rapid charging and discharging caused by static electricity, etc.

[0119] The reference voltage generation circuit 350 includes, for example, a voltage divider circuit. The voltage divider circuit generates voltage V DDQ The voltage supply line that provides the voltage, and the ground voltage V SS The device comprises an electrode that supplies voltage, two resistive elements connected in series between them, and an output terminal connected between these two resistive elements. The two resistive elements have the same resistance value, and the voltage at the output terminal is voltage V. DDQ The voltage supplied will be half the voltage of the voltage supply line.

[0120] The data latch circuit 360 holds the PCODE<n:0> output from the first replica unit control circuit 320 and the NCODE<m:0> output from the second replica unit control circuit 340, and outputs them to the termination resistance adjustment circuit.

[0121] The calibration control circuit 370 controls the first replica unit control circuit 320 and the second replica unit control circuit 340. For example, it controls the first replica unit control circuit 320 to adjust PCODE<n:0>, and then controls the second replica unit control circuit 340 to adjust NCODE<m:0>.

[0122] [Operation of the Calibration Circuit] In the calibration operation of the semiconductor device according to this embodiment, the first replica unit control circuit 320 is controlled to adjust the data PCODE <n:0>. Here, the calibration electrode ZQ is connected to a pull-up circuit 311 with a voltage V DDQ The external ground voltage V is supplied to the semiconductor device via a series resistor 300 having a resistance of approximately 240 Ω, connected to a voltage supply line. SS It is connected to the electrode that supplies the voltage. Also, when the first replica unit control circuit 320 is controlled, the voltage of the calibration electrode ZQm of the memory die MD0 is set to the reference voltage (1 / 2V). DDQ The data PCODE<n:0> is adjusted to approximately 240Ω. This adjusts the data PCODE<n:0> so that the impedance when the pull-up circuit 311 is driven is approximately 240Ω. Subsequently, the data latch circuit 360 holds the PCODE<n:0> output from the first replica unit control circuit 320.

[0123] Next, the second replica unit control circuit 340 is controlled to adjust the data NCODE<m:0>. Here, the calibration electrode ZQ is connected to the pull-up circuit 331 via a voltage V DDQ It is connected to a voltage supply line to which the ground voltage V is supplied via the pull-down circuit 332. SS It is connected to the electrode that supplies the voltage. The impedance of the pull-up circuit 331 is adjusted to approximately 240Ω. Furthermore, when the second replica unit control circuit 340 is controlled, the voltage of the calibration electrode ZQ changes to the reference voltage (1 / 2V). DDQ The data NCODE<m:0> is adjusted to approximately 240Ω. This adjusts the data NCODE<m:0> so that the impedance when the pull-down circuit 332 is driven is approximately 240Ω. Subsequently, the data latch circuit 360 holds the NCODE<m:0> output from the second replica unit control circuit 340.

[0124] [Acquisition of two types of data PCODE<n:0> and NCODE<m:0>] The calibration circuit may include two sets of first replica units 310 and first replica unit control circuits 320 in order to adjust both the data PCODE<n:0> used when outputting data and the data PCODE<n:0> used when inputting data. Similarly, the calibration circuit may include two sets of second replica units 330 and second replica unit control circuits 340 in order to adjust both the data NCODE<m:0> used when outputting data and the data NCODE<m:0> used when inputting data.

[0125] Furthermore, for example, the data PCODE<n:0> and NCODE<m:0> used when inputting data may be the same as the data PCODE<n:0> and NCODE<m:0> used when outputting data, or they may be calculated based on the data PCODE<n:0> and NCODE<m:0> used when outputting data.

[0126] [Timing for Calibration Operation] The impedances of the pull-up circuit 211 and pull-down circuit 212 in the termination resistance adjustment circuit fluctuate in response to changes in power supply voltage, temperature, etc. Therefore, it is preferable to perform the calibration operation as appropriate in response to changes in operating conditions.

[0127] In this embodiment, the semiconductor device is configured to perform calibration operations in parallel with core operations. With such a configuration, it is possible to provide a semiconductor device that operates optimally without spending time on calibration operations.

[0128] The following describes the timing at which calibration operations can be performed. Figures 14 and 15 are timing charts illustrating the timing at which calibration operations can be performed.

[0129] Figure 14 illustrates the command sets input to the memory die MD during read operations, etc. The first command set corresponds to normal read operations. The second command set corresponds to cache read operations. The third command set corresponds to data-out operations.

[0130] Normal read operations and cache read operations are performed in almost the same way. However, when a normal read operation is performed, the memory die MD remains busy until the read operation is completed. On the other hand, when a cache read operation is performed, the memory die MD becomes cache-ready before the read operation is completed. The data-out operation is the operation of outputting user data, which has been read from the memory cell array MCA by the read operation and output to the cache memory CM, to the controller die CD via the data signal input / output terminals DQ0 to DQ7.

[0131] In the illustrated example, at the time the first command set is input, the memory die MD is in a ready state and the terminal RY / / BY is in a "H" state.

[0132] The first command set includes data CR0, CR1, Add, and CR2.

[0133] Specifically, the controller die CD (Figure 1) inputs data CR0 and CR1 to the memory die MD as command data Cmd. That is, the voltages of the data signal input / output terminals DQ0 to DQ7 are set to "H" or "L" according to each bit of data CR0 and CR1, "H" is input to the external control terminal CLE, and "L" is input to the external control terminal ALE, and the external control terminal / WE is raised from "L" to "H". Data CR0 and CR1 are commands that are input at the start of the read operation.

[0134] Next, the controller die CD inputs the address data Add to the memory die MD. Specifically, it sets the voltages of the data signal input / output terminals DQ0 to DQ7 to "H" or "L" according to each bit of the address data Add, inputs "L" to the external control terminal CLE, inputs "H" to the external control terminal ALE, and raises the external control terminal / WE from "L" to "H". The address data Add is input five times.

[0135] Next, the controller die CD inputs data CR2 to the memory die MD as command data Cmd. Data CR2 is a command that indicates the completion of inputting the command set related to normal read operations.

[0136] When the first command set is entered, the memory die MD becomes busy, and the RY / / BY terminal changes from "H" to "L". Consequently, access to the memory die MD is prohibited. At the same time, a read operation is initiated on the memory die MD.

[0137] Once the read operation is complete, the memory die MD enters a ready state, and the RY / / BY terminal changes from the "L" state to the "H" state. Consequently, access to the memory die MD is permitted. In the illustrated example, the second command set is input at this state.

[0138] The second command set is basically the same as the first command set. However, in the second command set, data CR3 is entered instead of data CR2. Data CR3 is a command that indicates that the input of the command set related to cache read operations has finished.

[0139] When the second command set is entered, the memory die MD becomes busy, and the RY / / BY terminal changes from "H" to "L". Consequently, access to the memory die MD is prohibited. At the same time, a read operation is initiated on the memory die MD.

[0140] After a certain period has elapsed since the second command set was input, the memory die MD enters a cache-ready state, and the RY / / BY terminal changes from the "L" state to the "H" state. Consequently, access to the memory die MD is permitted. In the illustrated example, the third command set is input in this state.

[0141] The third command set includes data CR4, Add, and CR5. Data CR4 is the command entered at the start of the data-out operation. CR5 is a command that indicates that the input of the command set related to the data-out operation has finished.

[0142] When the third command set is input, the controller die CD causes the memory die MD to output user data via the data signal input / output terminals DQ0 to DQ7. That is, the voltages of the data signal input / output terminals DQ0 to DQ7 are set to "H" or "L" according to each bit corresponding to the user data by the termination resistor adjustment unit 210, as explained with reference to Figure 10. In addition, the data output from the data signal input / output terminals DQ0 to DQ7 is switched by switching the signals of the external control terminals / RE, RE. Therefore, the controller die acquires the data output from the data signal input / output terminals DQ0 to DQ7 while sequentially switching the data output from the external control terminals / RE, RE.

[0143] In this embodiment, the semiconductor device can initiate calibration operations in both the ready state and the cache-ready state. In the example shown in Figure 14, the state before the input of the first command set and the state from the end of the normal read operation until the input of the second command set correspond to the ready state. Furthermore, the state from when the RY / / BY terminal rises after the input of the second command set until the input of the third command set corresponds to the cache-ready state.

[0144] Note that core operations are not performed in the ready state, while read operations are performed in the cache-ready state illustrated in Figure 14. Therefore, if a calibration operation is started in this cache-ready state, the calibration operation will be performed in parallel with the read operation.

[0145] Figure 15 illustrates the command sets input to the memory die MD during write operations, etc. The first command set corresponds to cache write operations. The second command set corresponds to normal write operations.

[0146] Normal write operations and cache write operations are performed in almost the same way. However, when a normal write operation is performed, the memory die MD remains busy until the write operation is completed. On the other hand, when a cache write operation is performed, the memory die MD becomes cache-ready before the write operation is completed.

[0147] In the illustrated example, at the time the first command set is input, the memory die MD is in a ready state and the terminal RY / / BY is in a "H" state.

[0148] The first command set includes data CW0, CW1, Add, DIN, and CW2.

[0149] Specifically, the controller die CD (Figure 1) inputs data CW0 and CW1 as command data Cmd to the memory die MD. Data CW0 and CW1 are commands that are input at the start of the write operation.

[0150] Next, the controller die CD inputs the address data Add to the memory die MD.

[0151] Next, the controller die CD inputs data DIN to the memory die MD as user data Dat. That is, the voltages of the data signal input / output terminals DQ0 to DQ7 are set to "H" or "L" according to each bit of data DIN, "L" is input to the external control terminal CLE, and with "L" input to the external control terminal ALE, the input signals of the data strobe signal input / output terminals DQS and / DQS are switched. At this time, the input impedance of the data signal input / output terminals DQ0 to DQ7 is adjusted by the termination resistor adjustment unit 210, which was explained with reference to Figure 10.

[0152] Next, the controller die CD inputs data CW2 to the memory die MD as command data Cmd. Data CW2 is a command that indicates the completion of inputting the command set related to the cache write operation.

[0153] When the first command set is entered, the memory die MD becomes busy, and the RY / / BY terminal changes from "H" to "L". Consequently, access to the memory die MD is prohibited. At the same time, a write operation is initiated on the memory die MD.

[0154] After a certain period has elapsed since the first command set was input, the memory die MD enters a cache-ready state, and the RY / / BY terminal changes from the "L" state to the "H" state. Consequently, access to the memory die MD is permitted. In the illustrated example, the second command set is input in this state.

[0155] The second command set is basically the same as the first command set. However, in the second command set, data CW3 is entered instead of data CW2. Data CW3 is a command that indicates that the input of the command set related to normal write operations has finished.

[0156] When the second command set is input, the memory die MD becomes busy, and the RY / / BY terminal changes from the "H" state to the "L" state. Consequently, access to the memory die MD is prohibited. Note that the write operation corresponding to the second command set starts immediately after the write operation corresponding to the first command set is completed.

[0157] In this embodiment of the semiconductor device, calibration operation can be initiated in both the ready state and the cache-ready state. In the example shown in Figure 15, the state before the input of the first command set corresponds to the ready state. Furthermore, the state after the input of the first command set, when the RY / / BY terminal rises, and before the input of the second command set, corresponds to the cache-ready state.

[0158] Note that core operations are not performed in the ready state, while write operations are performed in the cache-ready state illustrated in Figure 15. Therefore, if a calibration operation is started in this cache-ready state, the calibration operation will be performed in parallel with the write operation.

[0159] [Configuration of the clock signal control circuit] When performing the calibration operation, a clock signal for the calibration operation is generated and input to the sequencer SQC (Figure 9).

[0160] In this case, if the calibration operation is started while the core operation is not running, the generation of the clock signal will begin at the time the calibration operation starts.

[0161] On the other hand, when starting a calibration operation while the core operation is running, one might consider using the same clock signal used for the core operation for the calibration operation as well. However, with this method, the waveform of the clock pulse used for the calibration operation may be distorted depending on the relationship between the timing of starting the calibration operation and the phase in the clock signal, which could lead to malfunctions in the calibration operation.

[0162] To prevent this, one could consider, for example, providing a separate clock signal generation circuit for calibration operations. However, such a method would lead to an increase in the overall circuit area of ​​the semiconductor device.

[0163] Therefore, the semiconductor device according to this embodiment is equipped with a clock signal control circuit that can stably generate clock pulses for calibration operation even while the core operation is being performed. Such a clock signal control circuit will be described below with reference to the drawings.

[0164] Figure 16 is a schematic circuit diagram showing the configuration of the clock signal control circuit. Figures 17 and 18 are schematic circuit diagrams showing a part of the configuration of the clock signal control circuit.

[0165] As shown in Figure 16, the sequencer SQC (Figure 9) inputs signals S101 and S103 to the clock signal control circuit. Signal S101 is a signal indicating the execution status of the core operation, and is in the "H" state when the core operation is in progress and in the "L" state otherwise. Signal S103 is a signal indicating the execution status of the calibration operation, and is in the "H" state when the calibration operation is in progress and in the "L" state otherwise.

[0166] The clock signal control circuit includes a clock signal generation circuit 401 that generates a clock signal as signal S105 in response to input signals S101, S103, etc., and an AND circuit 402 (clock signal output circuit) that outputs signal S105 as signal S109 in response to gate signal S108. The clock signal control circuit also includes an adjustment circuit 403 and an OR circuit 404 that modulate signal S103.

[0167] The clock signal generation circuit 401 outputs signal S105 and signal OSC. When a "H" signal is input to the clock signal generation circuit 401, the clock signal is output as signal S105 and the clock signal is output as signal OSC. When a "L" signal is input to the clock signal generation circuit 401, the "L" signal is output as signal S105 and the "L" signal is output as signal OSC. Signal OSC can be used as a clock signal for core operation. The frequency of signal OSC may be different from the frequency of signal S105.

[0168] The AND circuit 402 outputs signal S105 as signal S109 when the gate signal S108 is in the "H" state. Also, when the gate signal S108 is in the "L" state, the AND circuit 402 outputs a signal in the "L" state as signal S109. Signal S109 can be used as a clock signal for calibration operation.

[0169] The adjustment circuit 403 receives signals S103 and OSC. The adjustment circuit 403 delays signal S103 by the equivalent of several pulses in the clock signal output from the clock signal generation circuit 401 and then outputs it.

[0170] The OR circuit 404 outputs the logical OR of signal S103 and the output signal of the adjustment circuit 403. Therefore, the output signal of the OR circuit 404 rises in accordance with the rising edge of signal S103 and falls after a time interval equivalent to several pulses has elapsed since the falling edge of signal S103.

[0171] Next, we will describe the circuit that generates the signal S104, which is input to the clock signal generation circuit 401.

[0172] The clock signal control circuit includes OR circuits 411 and 412 provided in the signal path between signal S101 and signal S104.

[0173] The OR gate 411 receives the signal S101 as input. The OR gate 411 also receives the output signal from the AND gate 413 as input. The AND gate 413 outputs a logical AND of the signal OSC and the inverted signal of the gate signal S108.

[0174] OR gate 412 outputs signal S104. The output signal of OR gate 411 is input to OR gate 412. In addition, the signal OSC is input to OR gate 412.

[0175] Furthermore, a falling edge detection circuit 414, a latch circuit 415, and an AND circuit 416 are provided in the signal path between the output terminal of the OR circuit 411 and one of the input terminals of the OR circuit 412. This configuration makes it possible to temporarily supply a "L" state signal to the clock signal generation circuit 401.

[0176] The falling edge detection circuit 414 includes, for example, a NOR circuit 501 and an even number of dependent NOT circuits 502, as shown in Figure 17. The output signal of the OR circuit 411 is input to one input terminal of the NOR circuit 501. The inverted signal of the output signal of the OR circuit 411, delayed by the even number of NOT circuits 502, is input to the other input terminal of the NOR circuit 501.

[0177] When the output signal of OR circuit 411 is in the "H" state, "H" is input to one input terminal of NOR circuit 501, so NOR circuit 501 outputs "L". For a certain period of time after the output signal of OR circuit 411 switches from the "H" state to the "L" state, "L" is input to one input terminal of NOR circuit 501 and "L" is also input to the other input terminal of NOR circuit 501, so NOR circuit 501 outputs "H". After a certain period of time has elapsed since the output signal of OR circuit 411 switches to the "L" state, "H" will be input to the other input terminal of NOR circuit 501, so NOR circuit 501 outputs "L".

[0178] The latch circuit 415 (Figure 16) holds and outputs the output signal of the falling edge detection circuit 414 when the gate signal S108 is in the "L" state. The latch circuit 415 also maintains the held data and output signal when the gate signal S108 is in the "H" state.

[0179] The latch circuit 415 basically outputs a signal in the "L" state. However, when the gate signal S108 is in the "L" state (for example, when calibration operation is not being performed) and the output signal of the OR circuit 411 switches from the "H" state to the "L" state (for example, when core operation is completed), the latch circuit 415 temporarily outputs a signal in the "H" state.

[0180] Furthermore, even if the output signal of the OR circuit 411 switches from the "H" state to the "L" state when the gate signal S108 is in the "H" state (for example, during calibration operation), the output signal of the latch circuit 415 remains in the "L" state (for example, even after the core operation is completed).

[0181] One input terminal of the AND circuit 416 receives the inverted signal of signal S102 output from the latch circuit 415. The other input terminal of the AND circuit 416 receives the output signal of the OR circuit 404.

[0182] The AND circuit 416 basically outputs an "H" signal when signal S103 is in the "H" state, and during the interval of several pulses after signal S103 switches to the "L" state. However, while the latch circuit 415 is outputting an "H" signal, it outputs an "L" signal.

[0183] Next, we will describe the circuit that generates the gate signal S108.

[0184] The clock signal control circuit includes a latch circuit 421, a flip-flop 422 (gate signal output circuit), a switch circuit 423, and a latch circuit 424, all located in the signal path between signal S103 and gate signal S108.

[0185] A delay circuit 425 is connected to the input terminal of the latch circuit 421. The latch circuit 421 holds and outputs signal 103 when the output signal of the delay circuit 425 is in the "L" state. The latch circuit 421 also maintains the held data and output signal when the output signal of the delay circuit 425 is in the "H" state. The delay circuit 425 delays and outputs the output signal of the OR circuit 404.

[0186] The output signal of the latch circuit 421 becomes "H" in accordance with the rising edge of signal S103. Furthermore, after a time equivalent to several pulses has elapsed since the falling edge of signal S103, and after the delay time set by the delay circuit 425 has elapsed, it becomes "L".

[0187] The output signal of the flip-flop 422 switches to the output signal of the latch circuit 421 in accordance with the rising edge of signal S105.

[0188] A delay signal addition circuit 426 is connected to the switch circuit 423. The delay signal addition circuit 426 comprises, for example, an OR circuit 511 and an even number of NOT circuits 512 connected to it, as shown in Figure 18. The output signal of the OR circuit 411 is input to one input terminal of the OR circuit 511. The output signal of the OR circuit 411, delayed by the even number of NOT circuits 502, is input to the other input terminal of the OR circuit 511.

[0189] When the output signal of OR circuit 411 is in the "H" state, "H" is input to one of the input terminals of OR circuit 511, so OR circuit 511 outputs "H". For a certain period of time after the output signal of OR circuit 411 switches from the "H" state to the "L" state, "H" is input to the other input terminal of OR circuit 511, so OR circuit 511 outputs "H". After a certain period of time has elapsed since the output signal of OR circuit 411 switches to the "L" state, "L" is input to one of the input terminals of OR circuit 511, and "L" is also input to the other input terminal of OR circuit 511, so OR circuit 511 outputs "L".

[0190] The switch circuit 423 (Figure 16) outputs the output signal of the flip-flop 422 when the output signal of the delay signal addition circuit 426 is in the "H" state (when the output signal of the OR circuit 411 is in the "H" state, or for a certain period of time after the output signal of the OR circuit 411 switches to the "L" state). The switch circuit 423 also outputs the output signal of the latch circuit 421 when the output signal of the delay signal addition circuit 426 is in the "L" state (after a certain period of time has elapsed after the output signal of the OR circuit 411 switches to the "L" state).

[0191] The latch circuit 424 outputs a gate signal S108. When signal 105 is in the "L" state, the latch circuit 424 holds and outputs the signal S107 output from the switch circuit 423. Also, when signal 105 is in the "H" state, the latch circuit 424 maintains the held data and output signal.

[0192] [Operation of the Clock Signal Control Circuit] Figures 19 to 21 are schematic waveform diagrams illustrating the operation of the clock signal control circuit.

[0193] Figure 19 shows what happens when the calibration operation is started while the core operation is running.

[0194] In the illustrated example, the core operation is being performed, so signal S101 is in the "H" state. Therefore, signal S104 is also in the "H" state, and the clock signal is output as signal S105. Also, signal S106 is in the "H" state, and the switch circuit 423 outputs the output signal of the flip-flop 422 as signal S107.

[0195] In this state, at timing t101, when signal S103 rises from the "L" state to the "H" state, at timing t102, when signal S105 rises, the output signal of flip-flop 422 becomes "H", and accordingly, signal S107 output from switch circuit 423 also becomes "H". Also, at timing t103, when signal S105 falls, gate signal S108 becomes "H". Furthermore, at timings after this, a clock signal for calibration operation is output as signal S109.

[0196] Figure 20 shows what happens when the calibration operation is started while the core operation is not running.

[0197] In the illustrated example, since the core operation is not being performed, signal S101 is in the "L" state. Also, signal S104 is in the "L" state, and no clock signal is output from the clock signal generation circuit 401. Furthermore, signal S106 is in the "L" state, and the switch circuit 423 outputs the output signal of the latch circuit 421 as signal S107.

[0198] In this state, at timing t111, when signal S103 rises from the "L" state to the "H" state, gate signal S108 becomes "H". Also, at timing t112, signal S104 becomes "H" via OR circuit 404, AND circuit 416, and OR circuit 412, and the clock signal is output as signal S105. Furthermore, at a timing after this, the clock signal for calibration operation is output as signal S109.

[0199] Figure 21 shows the process when the calibration operation starts at the time the core operation ends.

[0200] In the illustrated example, at timing t121, signal S101 switches to the "L" state, and signal S104 also switches to the "L" state. At this timing, the output signal of the falling edge detection circuit 414 rises, and since the gate signal S108 is in the "L" state, signal S102 output from the latch circuit 415 rises to the "H" state. As a result, the output signal of the AND circuit 416 becomes "L", the OR circuit 412 outputs a "L" signal, and the output of the clock signal from the clock signal generation circuit 401 stops.

[0201] Furthermore, for a certain period of time after the output signal of the OR circuit 411 falls to the "L" state, the signal S106 output from the delay signal addition circuit 426 is maintained in the "H" state. Therefore, the signal S107 output from the switch circuit 423 is maintained at the output signal of the flip-flop 422 ("L" state).

[0202] In this state, even if signal S103 rises from the "L" state to the "H" state at timing t121, signal S104 remains in the "L" state because signal S102 is in the "H" state, and the output of the clock signal from the clock signal generation circuit 401 does not start.

[0203] At timing t122, a certain period of time has elapsed since signal S101 switched to the "L" state, signal S102 falls to the "L" state, signal S104 rises to the "H" state, and the output of the clock signal from the clock signal generation circuit 401 begins.

[0204] Furthermore, the signal S106 output from the delay signal addition circuit 426 falls to the "L" state, and the signal S107 output from the switch circuit 423 becomes the output signal of the latch circuit 421 ("H" state). As a result, the gate signal S108 becomes "H" and the clock signal for calibration operation is output as signal S109.

[0205] [Effects of the First Embodiment] The clock signal control circuit according to this embodiment includes a flip-flop 422 provided in the signal path between signal S103 and gate signal S108. The output signal of the flip-flop 422 switches to the output signal of the latch circuit 421 in accordance with the rising edge of signal S105.

[0206] With this configuration, as explained with reference to Figure 19, for example, it becomes possible to stably perform the calibration operation by adjusting the relationship between the phase of the clock signal output as signal S109 and the timing of the rise of the gate signal S108.

[0207] Furthermore, the clock signal control circuit according to this embodiment includes a switch circuit 423 connected between the output terminal of the flip-flop 422 and the input terminal of the gate signal S108. The switch circuit 423 outputs the output signal of the flip-flop 422 when the signal S106 is in the "H" state, and outputs the signal S103 input via the latch circuit 421 when the signal S106 is in the "L" state.

[0208] With this configuration, when signal S106 is in the "H" state, the stable calibration operation described above can be achieved, and when signal S106 is in the "L" state, the clock signal as signal S109 can be output immediately, as explained with reference to Figure 20, for example.

[0209] Furthermore, for example, if signal S106 falls in accordance with the falling edge of signal S101, and signal S103 rises at the same time, a clock signal may be output from the switch circuit 423 at an inappropriate timing while the clock signal is being output from the clock signal generation circuit 401. This can cause the pulse waveform in the clock signal (signal S109) to become distorted, potentially leading to malfunctions in the calibration operation.

[0210] Therefore, in the clock signal control circuit according to this embodiment, the switch circuit 423 outputs the output signal of the flip-flop 422 for a certain period of time after the output signal of the OR circuit 411 falls.

[0211] Furthermore, the clock signal control circuit according to this embodiment includes an OR circuit 412 having an output terminal connected to the clock signal generation circuit 401. The output signal of OR circuit 411 is input to one of the input terminals of OR circuit 412. The signal input to the other input terminal of OR circuit 412 becomes "H" after a certain period of time has elapsed since the output signal of OR circuit 404 was in the "H" state and the output signal of OR circuit 411 switched to the "L" state, and remains "L" otherwise.

[0212] With this configuration, as explained with reference to Figure 21, for example, the gate signal S108 is maintained in the "L" state for a certain period after the falling edge of signal S101. Furthermore, after a certain period has elapsed since the falling edge of signal S101, the output of the clock signal as signal S109 begins. This allows for stable calibration operation by adjusting the relationship between the phase of the clock signal output as signal S109 and the timing of the rising edge of the gate signal S108. In addition, it is possible to suitably suppress distortion of the pulse waveform initially output from the AND circuit 402.

[0213] [Second Embodiment] Next, a semiconductor device according to the second embodiment will be described. In the following description, parts the same as those in the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0214] The semiconductor device according to the second embodiment is basically configured in the same way as the semiconductor device according to the first embodiment. However, the clock signal control circuit according to the second embodiment is different from the clock signal control circuit according to the first embodiment.

[0215] Figure 22 is a schematic circuit diagram showing the configuration of the clock signal control circuit according to the second embodiment. Figure 23 is a schematic circuit diagram showing a part of the configuration of the same clock signal control circuit.

[0216] As shown in Figure 22, the clock signal control circuit according to the second embodiment is basically configured in the same way as the clock signal control circuit according to the first embodiment.

[0217] However, in the second embodiment, the AND circuit 402 outputs signal S205 as signal S109 when the gate signal S204 is in the "H" state. Also, when the gate signal S204 is in the "L" state, the AND circuit 402 outputs a signal in the "L" state as signal S109.

[0218] In the first embodiment, the signal S105 output from the clock signal generation circuit 401 is directly input to the AND circuit 402. In the second embodiment, however, delay circuits 701 and 702 are provided in the signal path between the output signal of the clock signal generation circuit 401 and the input signal of the AND circuit 402. The output signal of the clock signal generation circuit 401 is delayed by the delay circuits 701 and 702 to generate the signal S205, which is then input to the AND circuit 402.

[0219] Furthermore, in the second embodiment, the configuration of the circuit that generates the signal S104 input to the clock signal generation circuit 401 differs from that of the first embodiment. For example, the clock signal control circuit according to the second embodiment does not include a falling edge detection circuit 414, a latch circuit 415, and an AND circuit 416. Also, one of the input terminals of the OR circuit 412 receives the output signal of the OR circuit 404, rather than the output signal of the AND circuit 416.

[0220] Furthermore, in the second embodiment, the configuration of the circuit that generates the gate signal S204 differs from that of the first embodiment. For example, the clock signal control circuit according to the second embodiment does not include a switch circuit 423. Instead, the clock signal control circuit according to the second embodiment includes a rising edge delay circuit 703 and a latch circuit 704, which are provided between the output signal of the latch circuit 421 and the input signal of the flip-flop 422.

[0221] The rising edge delay circuit 703 includes, for example, an AND circuit 711 and an even number of NOT circuits 712 connected in a dependent configuration, as shown in Figure 23. The output signal of the latch circuit 421 (Figure 22) is input to one input terminal of the AND circuit 711. The output signal of the latch circuit 421, delayed by the even number of NOT circuits 712, is input to the other input terminal of the AND circuit 711.

[0222] When the output signal of the latch circuit 421 is in the "L" state, "L" is input to one of the input terminals of the AND circuit 711, so the AND circuit 711 outputs "L". For a certain period of time after the output signal of the latch circuit 421 switches from the "L" state to the "H" state, "L" is input to the other input terminal of the AND circuit 711, so the AND circuit 711 outputs "L". After a certain period of time has elapsed since the output signal of the latch circuit 421 switches to the "H" state, "H" is input to one of the input terminals of the AND circuit 711, and "H" is also input to the other input terminal of the AND circuit 711, so the AND circuit 711 outputs "H".

[0223] The latch circuit 704 (Figure 22) holds and outputs the signal S103' output from the rising edge delay circuit 703 when the signal S201 output from the clock signal generation circuit 401 is in the "H" state. The latch circuit 704 also maintains the held data and output signal when the signal S201 is in the "L" state.

[0224] In the second embodiment, the output signal of the flip-flop 422 switches to the output signal of the latch circuit 704 in accordance with the rising edge of the signal output from the delay circuit 701.

[0225] The latch circuit 424 according to the second embodiment outputs a gate signal S204. When signal S205 is in the "H" state, the latch circuit 424 holds and outputs the signal S203 output from the flip-flop 422. Furthermore, when signal S205 is in the "L" state, the latch circuit 424 maintains the held data and the output signal.

[0226] [Operation of the Clock Signal Control Circuit] Figures 24 and 25 are schematic waveform diagrams illustrating the operation of the clock signal control circuit.

[0227] Figure 24 shows what happens when the calibration operation is started while the core operation is running.

[0228] In the illustrated example, the core operation is being performed, so signal S101 is in the "H" state. Therefore, signal S104 is also in the "H" state, and the clock signal is output as signal S201.

[0229] In this state, at timing t201, when signal S103 rises from the "L" state to the "H" state, after a predetermined delay time has elapsed, at timing t202, signal S103' also rises to the "H" state. Subsequently, at timing t203, when signal S201 rises, signal S202 output from latch circuit 704 becomes "H". After a predetermined delay time has elapsed, at timing t204, when the output signal of delay circuit 701 rises, signal S203 output from flip-flop 422 becomes "H". Furthermore, after another predetermined delay time has elapsed, at timing t205, when signal S205 output from delay circuit 702 rises, gate signal S204 becomes "H". In addition, at timings after this, a clock signal for calibration operation is output as signal S109.

[0230] Figure 25 shows what happens when the calibration operation is started while the core operation is not running.

[0231] In the illustrated example, since the core operation is not being performed, signal S101 is in the "L" state. Also, signal S104 is in the "L" state, and no clock signal is output from the clock signal generation circuit 401.

[0232] In this state, when signal S103 rises from the "L" state to the "H" state at timing t211, signal S104 becomes "H" via OR circuits 404 and 412, and the clock signal is output as signal S201.

[0233] Furthermore, after a predetermined delay time has elapsed, signal S103' also rises to the "H" state at timing S212. Subsequently, at timing t213, when signal S201 rises, signal S202 output from latch circuit 704 becomes "H". Also, after a predetermined delay time has elapsed, at timing t214, when the output signal of delay circuit 701 rises, signal S203 output from flip-flop 422 becomes "H". Furthermore, after another predetermined delay time has elapsed, at timing t215, when signal S205 output from delay circuit 702 rises, gate signal S204 becomes "H". In addition, at timings after this, a clock signal for calibration operation is output as signal S109.

[0234] [Effects of the Second Embodiment] The clock signal control circuit according to this embodiment also includes a flip-flop 422 provided in the signal path between signal S103 and gate signal S204. Furthermore, the output signal of the flip-flop 422 switches to the output signal of the latch circuit 704 in accordance with the rising edge of the signal obtained by delaying signal S201.

[0235] With this configuration, for example, as explained with reference to Figure 24, it is possible to adjust the relationship between the phase of the clock signal output as signal S109 and the timing of the rise of the gate signal S204, thereby enabling stable calibration operation.

[0236] [Third Embodiment] Next, a semiconductor device according to the third embodiment will be described. In the following description, parts the same as those in the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0237] The semiconductor device according to the third embodiment is basically configured the same as the semiconductor device according to the first embodiment. However, the semiconductor device according to the third embodiment includes four memory cell arrays MCA0, MCA1, MCA2, and MCA3. Each of these four memory cell arrays MCA can independently perform core operations.

[0238] Figure 26 is a timing chart illustrating the timing at which a calibration operation can be performed in the semiconductor device according to the third embodiment.

[0239] In the illustrated example, first, a command set for a normal read operation corresponding to the memory cell array MCA0 is input, and the memory cell array MCA0 becomes busy. Consequently, the terminal RY / / BY switches from the "H" state to the "L" state.

[0240] Next, a command set for a normal read operation corresponding to the memory cell array MCA1 is input, and the memory cell array MCA1 becomes busy.

[0241] Next, the normal read operation corresponding to memory cell array MCA0 is completed, and memory cell array MCA0 enters a ready state. However, at this time, the normal read operation corresponding to memory cell array MCA1 is being performed, so the terminal RY / / BY remains in the "L" state.

[0242] Next, a command set for a cache read operation corresponding to memory cell array MCA0 is input, and memory cell array MCA0 becomes busy.

[0243] After a certain period of time has elapsed since the command set for the cache read operation corresponding to memory cell array MCA0 was input, memory cell array MCA0 enters a cache-ready state. At the same time, the normal read operation corresponding to memory cell array MCA1 is completed, and memory cell array MCA1 enters a ready state. Consequently, the RY / / BY terminal switches from the "L" state to the "H" state.

[0244] Next, a command set for a cache read operation corresponding to the memory cell array MCA1 is input, and the memory cell array MCA1 becomes busy. Consequently, the terminal RY / / BY switches from the "H" state to the "L" state.

[0245] After a certain period of time has elapsed since the command set for the cache read operation corresponding to the memory cell array MCA1 was input, the memory cell array MCA1 enters a cache-ready state. Accordingly, the terminal RY / / BY switches from the "L" state to the "H" state.

[0246] In this embodiment, the semiconductor device can start the calibration operation if any of the four memory cell arrays MCA are in a ready state or a cache-ready state. In the example shown in Figure 26, since memory cell arrays MCA2 and MCA3 are always in a ready state, the calibration operation can be started at all timings.

[0247] Furthermore, in this embodiment, the controller die CD can confirm whether or not the calibration operation has been completed by reading the status. In this case, for example, the status data corresponding to one of the four memory cell arrays MCA that is not in use is used as data indicating the execution status of the calibration operation.

[0248] In this embodiment, however, the calibration operation may be permitted only when terminal RY / / BY is in the "H" state (i.e., when memory die MD is in a ready state or cache ready state).

[0249] [Other Embodiments] The semiconductor devices according to the first to third embodiments have been described above. However, these configurations are merely examples, and the specific configurations can be changed as appropriate. For example, in the first to third embodiments, the communication between the memory die MD and the controller die CD may conform to an SDR (Single data rate) interface, a toggle DDR (Double data rate) interface, or ONFI (Open NAND flash interface).

[0250] [Other] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be carried out in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0251] 401...Clock signal generation circuit, 402...AND circuit (clock signal output circuit), 403...Adjustment circuit, 404...OR circuit, 411...OR circuit, 412...OR circuit, 413...AND circuit, 414...Falling edge detection circuit, 415...Latch circuit, 416...AND circuit, 421...Latch circuit, 422...Flip-flop (gate signal output circuit), 423...Switch circuit, 424...Latch circuit, 425...Delay circuit, 426...Delay signal addition circuit.

Claims

1. A semiconductor device comprising: electrodes; a pull-up circuit and a pull-down circuit that control the voltage of the electrodes according to input data; an internal circuit that outputs the data supplied to the pull-up circuit and the pull-down circuit; a control circuit capable of performing a calibration operation that adjusts the operation of the internal circuit and the output impedance of the pull-up circuit and the pull-down circuit; and a clock signal control circuit that supplies a first clock signal to the control circuit while the calibration operation is being performed, wherein the clock signal control circuit comprises: a clock signal generation circuit that outputs a second clock signal while at least one of the operation of the internal circuit and the calibration operation is being performed; a clock signal output circuit that outputs the second clock signal as the first clock signal according to a gate signal; and a gate signal output circuit that outputs a signal indicating the execution status of the calibration operation as the gate signal according to the switching of the second clock signal.

2. The semiconductor device according to claim 1, further comprising a latch circuit provided in the signal path between the output signal of the gate signal output circuit and the input signal of the clock signal output circuit, wherein the latch circuit inputs the input signal to the clock signal output circuit at a timing different from the timing at which the gate signal output circuit outputs the gate signal.

3. The semiconductor device according to claim 2, wherein the gate signal output circuit outputs a signal indicating the execution status of the calibration operation as the gate signal at one of the rising and falling edges of the second clock signal, and the latch circuit inputs an input signal to the clock signal output circuit at the other of the rising and falling edges of the second clock signal.

4. The semiconductor device according to claim 2, further comprising a delay circuit provided in the signal path between the input terminal of the gate signal output circuit to which the second clock signal is input and the input terminal of the latch circuit to which the second clock signal is input.

5. The semiconductor device according to claim 1, further comprising a switch circuit provided in the signal path between the output signal of the gate signal output circuit and the input signal of the clock signal output circuit, wherein the switch circuit inputs the output signal of the gate signal output circuit as the gate signal to the clock signal output circuit when the operation of the internal circuit is being performed, and inputs a signal indicating the execution status of the calibration operation as the gate signal to the clock signal output circuit when the operation of the internal circuit is not being performed.

6. The semiconductor device according to claim 5, wherein the switch circuit inputs the output signal of the gate signal output circuit as the gate signal to the clock signal output circuit for a certain period of time after the completion of the read operation, the write operation, or the erase operation.

7. The semiconductor device according to claim 6, further comprising a logic circuit having an output terminal connected to the clock signal generation circuit, a first input terminal, and a second input terminal, wherein a first signal is input to the first input terminal, which is in a first state when the read operation, the write operation, or the erase operation is being performed, and is in a second state when it is not being performed, and a second signal is input to the second input terminal, which is in a third state when a certain period of time has elapsed since the first signal switched from the first state to the second state and the calibration operation is being performed, and is in a fourth state in all other states, and the logic circuit outputs the second clock signal from the clock signal generation circuit when the first signal is in the first state and when the second signal is in the third state.

8. The semiconductor device according to claim 1, wherein the internal circuit comprises a memory cell for storing data, and the operation of the internal circuit is a read operation, a write operation, or an erase operation on the memory cell.

9. The semiconductor device according to claim 1, wherein the internal circuit further comprises a memory string for storing data, and the memory string comprises a plurality of memory cell transistors connected in series.

10. The semiconductor device according to claim 1, which is capable of initiating the calibration operation when it is in a ready state and a cache-ready state.

11. The semiconductor device according to claim 1, wherein the internal circuit comprises a plurality of memory cell arrays, and the calibration operation can be started when any of the plurality of memory cell arrays is in a ready state or a cache-ready state.

12. The semiconductor device according to claim 11, which is capable of outputting data indicating the execution status of the calibration operation as status data, instead of information indicating the status of which of the plurality of memory cell arrays is in a ready state or a cache ready state.

13. The semiconductor device according to claim 1, wherein communication with the controller conforms to ONFI (Open Nand Flash Interface).

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