Timing adjustment device, timing adjustment method, and sampling receiver

Abstract

A timing adjustment device (3) is configured so as to comprise: a signal provision unit (11) that applies, to a sample-and-hold circuit (1), a signal having a frequency lower than the frequency of a signal to be received; and a timing adjustment unit (12) that, when the sample-and-hold circuit (1) is holding the signal applied by the signal provision unit (11) in synchronization with a clock, adjusts the timing at which the clock is supplied to an ADC (2) so that the signal held by the sample-and-hold circuit (1) is captured by the ADC (2).

Description

Timing adjustment device, timing adjustment method, and sampling receiver

[0001] This disclosure relates to a timing adjustment device, a timing adjustment method, and a sampling receiver.

[0002] There is a sampling receiver that has a function to adjust the timing of the clock supply to an analog-to-digital converter so that the signal held by the sample-and-hold circuit is acquired by the analog-to-digital converter. As such a sampling receiver, for example, Patent Document 1 discloses a sampling receiver that adjusts the timing of the clock supply to an analog-to-digital converter so that when an RF (Radio Frequency) signal received by an antenna is supplied to a sample-and-hold circuit and the sample-and-hold circuit holds the RF signal, the RF signal held by the sample-and-hold circuit is acquired by the analog-to-digital converter.

[0003] International Publication No. 2020-137656

[0004] In the sampling receiver disclosed in Patent Document 1, the sample-and-hold circuit needs to acquire the RF signal received by the antenna in order to adjust the timing of the clock supply to the analog-to-digital converter. Therefore, the sampling receiver disclosed in Patent Document 1 has the problem that it is not possible to adjust the timing of the clock supply to the analog-to-digital converter unless a transmitting system for transmitting RF signals is provided.

[0005] This disclosure was made to solve the above-mentioned problems, and aims to provide a timing adjustment device that can adjust the timing of the clock supply to an analog-to-digital converter without providing a transmission system for transmitting RF signals.

[0006] The timing adjustment device according to this disclosure includes a signal supply unit that supplies a signal with a frequency lower than the frequency of the signal to be received to a sample-and-hold circuit, and a timing adjustment unit that adjusts the timing of the clock supply to the analog-to-digital converter so that when the sample-and-hold circuit holds the signal supplied by the signal supply unit in synchronization with the clock, the signal held by the sample-and-hold circuit is captured by the analog-to-digital converter.

[0007] According to this disclosure, the timing of the clock supply to the analog-to-digital converter can be adjusted without having to prepare a transmission system for transmitting RF signals.

[0008] This is a configuration diagram showing a sampling receiver including a timing adjustment device 3 according to Embodiment 1. This is a hardware configuration diagram showing some of the hardware of the timing adjustment device 3 according to Embodiment 1. This is a hardware configuration diagram of a computer when part of the timing adjustment device 3 is implemented by software or firmware, etc. This is a flowchart showing the timing adjustment method, which is the processing procedure of the timing adjustment device 3. This is an explanatory diagram showing the relationship between the clock delay time and the S / N ratio in the output signal of the ADC2. This is a configuration diagram showing a sampling receiver including another timing adjustment device 3 according to Embodiment 1. This is a configuration diagram showing a sampling receiver including another timing adjustment device 3 according to Embodiment 1. This is a configuration diagram showing a sampling receiver including another timing adjustment device 3 according to Embodiment 1. This is a configuration diagram showing a sampling receiver including a timing adjustment device 3 according to Embodiment 2. This is a hardware configuration diagram showing some of the hardware of the timing adjustment device 3 according to Embodiment 2. This is a configuration diagram showing a differential configuration sampling receiver.

[0009] To provide a more detailed explanation of this disclosure, the forms for implementing this disclosure will be described below with reference to the attached drawings.

[0010] Embodiment 1. Figure 1 is a configuration diagram showing a sampling receiver including a timing adjustment device 3 according to Embodiment 1. Figure 2 is a hardware configuration diagram showing some of the hardware of the timing adjustment device 3 according to Embodiment 1. The sampling receiver shown in Figure 1 comprises a sample-and-hold circuit 1, an analog-to-digital converter (hereinafter referred to as "ADC") 2, and a timing adjustment device 3.

[0011] The signal input terminal 1a of the sample-and-hold circuit 1 is supplied with an RF signal received by an antenna (not shown) or a signal output from the timing adjustment device 3. The RF signal received by the antenna is the signal to be received, and the signal output from the timing adjustment device 3 is a signal with a lower frequency than the frequency of the signal to be received. The clock terminal 1b of the sample-and-hold circuit 1 is supplied with a clock. The sample-and-hold circuit 1 holds the signal supplied to the signal input terminal 1a in synchronization with the clock supplied to the clock terminal 1b. Specifically, the sample-and-hold circuit 1 starts sampling the signal supplied to the signal input terminal 1a when the clock supplied to the clock terminal 1b is, for example, on the rising edge. The sample-and-hold circuit 1 starts holding the signal supplied to the signal input terminal 1a when the clock supplied to the clock terminal 1b is, for example, on the falling edge. The signal sampled by the sample-and-hold circuit 1 or the signal held by the sample-and-hold circuit 1 is output from the signal output terminal 1c of the sample-and-hold circuit 1.

[0012] The signal input terminal 2a of ADC2 is supplied with the signal output terminal 1c of the sample-and-hold circuit 1. The clock terminal 2b of ADC2 is supplied with the clock after timing adjustment by the timing adjustment device 3. Synchronized with the clock, ADC2 acquires the signal output from the signal output terminal 1c of the sample-and-hold circuit 1 and performs analog-to-digital conversion of the acquired signal. Specifically, ADC2 starts acquiring the signal output from the signal output terminal 1c of the sample-and-hold circuit 1 when the clock supplied to the clock terminal 2b falls, for example, and performs analog-to-digital conversion of the acquired signal. The signal after analog-to-digital conversion is output to the timing adjustment device 3 from the signal output terminal 2c of ADC2.

[0013] The timing adjustment device 3 comprises a signal supply unit 11 and a timing adjustment unit 12. The signal supply unit 11 is implemented, for example, by the signal supply circuit 21 shown in Figure 2. When adjusting the timing of the clock supply to the ADC2, the signal supply unit 11 provides a DC voltage V as a signal with a lower frequency than the frequency of the signal to be received, instead of the RF signal which is the signal to be received. ＤＣ This signal is supplied to the signal input terminal 1a of the sample-and-hold circuit 1.

[0014] The timing adjustment unit 12 includes a signal-to-noise ratio (hereinafter referred to as "S / N ratio") calculation unit 12a, a delay control unit 12b, and a delay unit 12c. The timing adjustment unit 12 adjusts the timing of the clock supply to the ADC2 so that when the sample-and-hold circuit 1 holds the signal provided by the signal supply unit 11 in synchronization with the clock, the signal held by the sample-and-hold circuit 1 is captured by the ADC2.

[0015] The S / N ratio calculation unit 12a is implemented, for example, by the S / N ratio calculation circuit 22 shown in Figure 2. The S / N ratio calculation unit 12a calculates the S / N ratio of the signal output from the signal output terminal 2c of the ADC2. The S / N ratio calculation unit 12a outputs the calculated S / N ratio to the delay control unit 12b.

[0016] The delay control unit 12b is implemented, for example, by the delay control circuit 23 shown in Figure 2. The delay control unit 12b delays the clock supplied to the ADC2 compared to the clock supplied to the sample-and-hold circuit 1, based on the signal-to-noise ratio (S / N ratio) calculated by the S / N ratio calculation unit 12a, so that the signal held by the sample-and-hold circuit 1 is captured by the ADC2. That is, the delay control unit 12b controls the delay time of the delay unit 12c based on the S / N ratio calculated by the S / N ratio calculation unit 12a. The delay unit 12c delays the clock supplied to the ADC2 by the delay time after control by the delay control unit 12b.

[0017] In Figure 1, it is assumed that the signal supply unit 11, the S / N ratio calculation unit 12a, and the delay control unit 12b, which are some components of the timing adjustment device 3, are each implemented by dedicated hardware as shown in Figure 2. That is, it is assumed that a part of the timing adjustment device 3 is implemented by the signal supply circuit 21, the S / N ratio calculation circuit 22, and the delay control circuit 23. The signal supply circuit 21, the S / N ratio calculation circuit 22, and the delay control circuit 23 can each be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof.

[0018] Some components of the timing adjustment device 3 are not limited to those implemented by dedicated hardware; some components of the timing adjustment device 3 may be implemented by software, firmware, or a combination of software and firmware. The software or firmware is stored as a program in the computer's memory. The computer refers to the hardware that executes the program, and includes, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, a processor, or a DSP (Digital Signal Processor).

[0019] Figure 3 is a hardware configuration diagram of a computer when a part of the timing adjustment device 3 is implemented by software or firmware. When a part of the timing adjustment device 3 is implemented by software or firmware, a program that causes the computer to execute the respective processing procedures in the signal supply unit 11, the S / N ratio calculation unit 12a, and the delay control unit 12b is stored in memory 31. The computer's processor 32 then executes the program stored in memory 31.

[0020] Furthermore, Figure 2 shows an example in which some components of the timing adjustment device 3 are implemented by dedicated hardware, and Figure 3 shows an example in which some components of the timing adjustment device 3 are implemented by software or firmware, etc. However, this is only one example, and some of the components of the timing adjustment device 3 may be implemented by dedicated hardware, while the remaining components may be implemented by software or firmware, etc.

[0021] Next, the operation of the sampling receiver shown in Figure 1 will be explained. Figure 4 is a flowchart of the timing adjustment method, which is the processing procedure of the timing adjustment device 3. The frequency of the RF signal received by the antenna (not shown) is a high frequency in the RF band. Therefore, the ADC 2 may not be able to perform analog-to-digital conversion of the signal unless the frequency of the RF signal is lowered. The sampling receiver shown in Figure 1 is equipped with a sample-and-hold circuit 1 in front of the ADC 2 so that the ADC 2 can perform analog-to-digital conversion of the signal. The frequency of the signal held by the sample-and-hold circuit 1 in synchronization with the clock is a lower frequency than the frequency of the RF signal.

[0022] When the signal supply unit 11 adjusts the timing of the clock supply to the ADC2, it uses a DC voltage V as a signal with a lower frequency than the frequency of the signal to be received, instead of the RF signal which is the signal to be received. ＤＣ The signal is supplied to the signal input terminal 1a of the sample-and-hold circuit 1 (step ST1 in Figure 4). The clock signal is supplied to the clock terminal 1b of the sample-and-hold circuit 1. The clock signal is output as a leakage component from the signal output terminal 1c of the sample-and-hold circuit 1 via the inside of the sample-and-hold circuit 1.

[0023] When the clock signal supplied to the clock terminal 1b of the sample-and-hold circuit 1 rises, for example, the sample-and-hold circuit 1 receives the DC voltage V supplied to the signal input terminal 1a. ＤＣ Sampling of the clock leakage component is started. When the clock supplied to the clock terminal 1b of the sample-and-hold circuit 1 falls, for example, the sample-and-hold circuit 1 starts sampling the DC voltage V supplied to the signal input terminal 1a. ＤＣ And the holding of the clock leakage component begins. Therefore, the period from the rising edge to the falling edge of the clock is controlled by the DC voltage V ＤＣ The leakage component of the clock is sampled, and the period from the falling edge of the clock to the rising edge of the clock is measured by a DC voltage V ＤＣand the leakage component of the clock are held. The sample hold circuit 1 holds the DC voltage V ＤＣ When the leakage component of the clock is held, the waveform of the signal output from the signal output terminal 1c of the sample hold circuit 1 becomes a rectangular wave in phase with the clock. That is, when the DC voltage V ＤＣ is applied to the signal input terminal 1a of the sample hold circuit 1, and the DC voltage V ＤＣ and the leakage component of the clock are held by the sample hold circuit 1, a rectangular wave in phase with the clock appears at the signal output terminal 1c of the sample hold circuit 1 due to the LO leakage which is the leakage component of the clock. Therefore, when the DC voltage V ＤＣ and the leakage component of the clock are held by the sample hold circuit 1, a rectangular wave in phase with the clock is applied from the signal output terminal 1c of the sample hold circuit 1 to the signal input terminal 2a of the ADC2.

[0024] The ADC2 can capture the signal output from the signal output terminal 1c of the sample hold circuit 1 when the DC voltage V ＤＣ and the leakage component of the clock are held by the sample hold circuit 1. The supply timing of the clock to the ADC2 is adjusted by the timing adjustment device 3.

[0025] When the DC voltage V ＤＣ and the leakage component of the clock are held by the sample hold circuit 1, the S / N ratio in the output signal of the ADC2 is larger than the S / N ratio in the output signal of the ADC2 when the DC voltage V ＤＣ and the leakage component of the clock are sampled by the sample hold circuit 1, as shown in FIG. 5. Also, when the DC voltage V ＤＣEven during the period when the clock leakage component is held, as shown in Figure 5, the S / N ratio of the ADC2 output signal at the timing midway between the falling and rising edges of the clock is greater than the S / N ratio of the ADC2 output signal at the timing immediately after the falling edge of the clock supplied to the clock terminal 1b, or at the timing immediately before the rising edge of the clock, because there is a transition period. Figure 5 is an explanatory diagram showing the relationship between the clock delay time and the S / N ratio of the ADC2 output signal.

[0026] The delay control unit 12b receives a DC voltage V from the signal supply unit 11. ＤＣ When the signal is supplied to the signal input terminal 1a of the sample-and-hold circuit 1, the delay time of the clock supplied to the ADC2 is switched, and the delayed clock is supplied to the clock terminal 2b of the ADC2 (step ST2 in Figure 4). The S / N ratio calculation unit 12a calculates the S / N ratio of the output signal of the ADC2 each time the delay control unit 12b switches the clock delay time (step ST3 in Figure 4). Specifically, the S / N ratio calculation unit 12a acquires the digital value of "0" or "1", which is the output signal of the ADC2, each time the delay control unit 12b switches the clock delay time, and calculates the signal spectrum of the output signal of the ADC2. Then, the S / N ratio calculation unit 12a calculates the S / N ratio based on the signal spectrum. Each time the S / N ratio is calculated, the S / N ratio calculation unit 12a outputs the calculation result of the S / N ratio to the delay control unit 12b.

[0027] The delay control unit 12b obtains multiple S / N ratio calculation results from the S / N ratio calculation unit 12a. The delay control unit 12b compares the multiple calculation results to identify, for example, the clock delay time when the S / N ratio is maximized. The delay control unit 12b determines the clock delay time supplied to the ADC2 to the identified delay time (step ST4 in Figure 4). By controlling the delay time of the delay unit 12c to the identified delay time (step ST5 in Figure 4), the delay control unit 12b supplies a clock to the ADC2's clock terminal 2b that is delayed by the identified delay time compared to the clock supplied to the sample-and-hold circuit 1's clock terminal 1b. This completes the adjustment of the clock supply timing to the ADC2.

[0028] Here, the delay control unit 12b compares multiple calculation results to identify the clock delay time when the signal-to-noise ratio (S / N ratio) is maximized. However, it is not limited to the clock delay time when the S / N ratio is maximized; the delay control unit 12b may also identify the clock delay time when the S / N ratio is smaller than the maximum S / N ratio, within a range that does not pose a practical problem.

[0029] Once the adjustment of the clock supply timing to ADC2 is complete, the signal supply unit 11 supplies a DC voltage V to the signal input terminal 1a of the sample-and-hold circuit 1. ＤＣ The supply of [the signal] will be terminated. From this point onward, the RF signal, which is the signal to be received, will be supplied to the signal input terminal 1a of the sample-and-hold circuit 1. The clock signal will be supplied to the clock terminal 1b of the sample-and-hold circuit 1.

[0030] When the clock signal supplied to the clock terminal 1b of the sample-and-hold circuit 1 rises, for example, the sample-and-hold circuit 1 begins sampling the RF signal supplied to the signal input terminal 1a. When the clock signal supplied to the clock terminal 1b of the sample-and-hold circuit 1 falls, for example, the sample-and-hold circuit 1 begins holding the RF signal supplied to the signal input terminal 1a. Therefore, the RF signal is sampled during the period from the rising edge to the falling edge of the clock, and the RF signal is held during the period from the falling edge to the rising edge of the clock.

[0031] The delay control unit 12b controls the delay time of the delay unit 12c to a specified delay time, thereby supplying a clock to the clock terminal 2b of the ADC2 that is delayed by a specified delay time compared to the clock supplied to the clock terminal 1b of the sample-and-hold circuit 1. The specified delay time is the clock delay time at which the signal-to-noise ratio of the output signal of the ADC2 is maximized, for example, when adjusting the timing of the clock supply to the ADC2.

[0032] The ADC2 starts acquiring the signal output from the signal output terminal 1c of the sample-and-hold circuit 1 when the clock supplied to the clock terminal 2b from the delay control unit 12b falls, for example, and performs analog-to-digital conversion of the acquired signal. The signal output from the signal output terminal 1c of the sample-and-hold circuit 1 when the clock falls is, for example, the signal at which the signal-to-noise ratio of the ADC2's output signal is, for example, maximum. The analog-to-digital converted signal output from the signal output terminal 2c of the ADC2 is output to a device downstream of the sampling receiver shown in Figure 1. Examples of devices downstream of the sampling receiver include a radar device or an image processing device.

[0033] In the above-described Embodiment 1, the timing adjustment device 3 is configured to include a signal providing unit 11 that provides a signal having a frequency lower than the frequency of the signal to be received to the sample-and-hold circuit 1, and a timing adjustment unit 12 that adjusts the supply timing of the clock to the ADC 2 so that when the sample-and-hold circuit 1 holds the signal provided by the signal providing unit 11 in synchronization with the clock, the signal held by the sample-and-hold circuit 1 is captured by the ADC 2. Therefore, the timing adjustment device 3 can adjust the supply timing of the clock to the ADC 2 without preparing a transmission system for transmitting an RF signal.

[0034] Also, in Embodiment 1, the timing adjustment unit 12 is configured to include an S / N ratio calculation unit 12a that calculates the S / N ratio of the signal output from the ADC 2, and a delay control unit 12b that delays the clock supplied to the ADC 2 more than the clock supplied to the sample-and-hold circuit 1 based on the S / N ratio calculated by the S / N ratio calculation unit 12a so that the signal held by the sample-and-hold circuit 1 is captured by the ADC 2. Therefore, the timing adjustment device 3 can automatically adjust the supply timing of the clock to the ADC 2 without preparing a transmission system for transmitting an RF signal.

[0035] In the sampling receiver shown in FIG. 1, either the DC voltage V ＤＣ output from the signal providing unit 11 or the RF signal is supplied to the signal input terminal 1a of the sample-and-hold circuit 1. However, this is merely an example, and as shown in FIG. 6, the timing adjustment device 3 may include a switch 12d, and when the switch 12d is on, the DC voltage V ＤＣ is supplied to the signal input terminal 1a of the sample-and-hold circuit 1, and when the switch 12d is off, the RF signal is supplied to the signal input terminal 1a of the sample-and-hold circuit 1. FIG. 6 is a configuration diagram showing a sampling receiver including another timing adjustment device 3 according to Embodiment 1.

[0036] In the timing adjustment device 3 shown in FIG. 1, the S / N ratio calculation unit 12a calculates the S / N ratio in the signal output from the ADC 2, and the delay control unit 12b adjusts the signal held by the sample and hold circuit 1 to be captured by the ADC 2. Based on the S / N ratio calculated by the S / N ratio calculation unit 12a, the clock supplied to the ADC 2 is delayed with respect to the clock supplied to the sample and hold circuit 1. However, this is merely an example. As shown in FIG. 7, the timing adjustment device 3 may include a waveform detection unit 12e that detects the waveform of the signal output from the signal output terminal 2c of the ADC 2 instead of the S / N ratio calculation unit 12a, and the delay control unit 12b may adjust the signal held by the sample and hold circuit 1 to be captured by the ADC 2. Based on the waveform detected by the waveform detection unit 12e, the clock supplied to the ADC 2 is delayed with respect to the clock supplied to the sample and hold circuit 1. FIG. 7 is a configuration diagram showing a sampling receiver including another timing adjustment device 3 according to Embodiment 1.

[0037] Also in this case, the delay control unit 12b supplies the delayed clock to the clock terminal 2b of the ADC 2 while switching the delay time of the clock supplied to the ADC 2. The delay control unit 12b acquires the waveform detection result from the waveform detection unit 12e every time the waveform detection unit 12e detects a waveform. The delay control unit 12b compares a plurality of waveform detection results obtained by the waveform detection unit 12e. Since the period when the waveform level is low becomes the hold period, for example, the delay time of the clock is specified so that the rising timing of the clock supplied to the clock terminal 2b of the ADC 2 is within that hold period. Even when the timing adjustment device 3 includes the waveform detection unit 12e instead of the S / N ratio calculation unit 12a, the supply timing of the clock to the ADC 2 can be automatically adjusted without preparing a transmission system that transmits an RF signal.

[0038] In the timing adjustment device 3 shown in Figure 1, the timing adjustment unit 12 includes an S / N ratio calculation unit 12a and a delay control unit 12b, enabling automatic adjustment of the clock supply timing to the ADC2. However, this is just one example, and the timing adjustment unit 12 may also be configured to automatically adjust the clock supply timing to the sample-and-hold circuit 1, as shown in Figure 8. Figure 8 is a configuration diagram showing a sampling receiver including another timing adjustment device 3 according to Embodiment 1.

[0039] In this case, the delay control unit 12b switches the delay time of the clock supplied to the sample-and-hold circuit 1 and supplies the delayed clock to the clock terminal 1b of the sample-and-hold circuit 1. The delay control unit 12b obtains the gain detection result from the S / N ratio calculation unit 12a each time the S / N ratio calculation unit 12a detects gain. The delay control unit 12b compares multiple waveform detection results from the S / N ratio calculation unit 12a and, for example, identifies the clock delay time when the gain is maximized. When the timing adjustment unit 12 adjusts the timing of the clock supply to the sample-and-hold circuit 1, the timing of the clock supply to the sample-and-hold circuit 1 can be automatically adjusted without providing a transmission system for transmitting RF signals.

[0040] In the timing adjustment device 3 shown in Figure 1, the timing adjustment unit 12 includes an S / N ratio calculation unit 12a and a delay control unit 12b, enabling automatic adjustment of the clock supply timing to the ADC2. However, this is just one example, and the timing adjustment unit 12 may also be configured without an S / N ratio calculation unit 12a and a delay control unit 12b, allowing the user to manually adjust the delay time using a delay unit 12c.

[0041] Embodiment 2. Embodiment 2 describes a sampling receiver in which the signal supply unit 13 supplies an AC voltage to the sample-and-hold circuit 1 as a signal with a lower frequency than the frequency of the signal to be received.

[0042] Figure 9 is a configuration diagram showing a sampling receiver including a timing adjustment device 3 according to Embodiment 2. In Figure 9, the same reference numerals as in Figures 1 and 6 to 8 indicate the same or corresponding parts, so a detailed explanation is omitted. Figure 10 is a hardware configuration diagram showing some of the hardware of the timing adjustment device 3 according to Embodiment 2. In Figure 10, the same reference numerals as in Figure 2 indicate the same or corresponding parts, so a detailed explanation is omitted. The sampling receiver shown in Figure 9 includes a sample-and-hold circuit 1, an ADC 2, and a timing adjustment device 3.

[0043] The timing adjustment device 3 comprises a signal supply unit 13 and a timing adjustment unit 12. The signal supply unit 13 is implemented, for example, by the signal supply circuit 24 shown in Figure 10. When adjusting the timing of the clock supply to the ADC2, the signal supply unit 13 uses an AC voltage V as a signal with a lower frequency than the frequency of the signal to be received, instead of the RF signal which is the signal to be received. ＡＣ This signal is supplied to the signal input terminal 1a of the sample-and-hold circuit 1.

[0044] The sampling receiver shown in Figure 9 is one in which the signal providing unit 13 is applied to the sampling receiver shown in Figure 1. However, this is merely one example, and the signal providing unit 13 may be applied to any of the sampling receivers shown in Figures 6 to 8.

[0045] In Figure 9, it is assumed that the signal supply unit 13, the S / N ratio calculation unit 12a, and the delay control unit 12b, which are some components of the timing adjustment device 3, are each implemented by dedicated hardware as shown in Figure 10. That is, it is assumed that a part of the timing adjustment device 3 is implemented by the signal supply circuit 24, the S / N ratio calculation circuit 22, and the delay control circuit 23. The signal supply circuit 24, the S / N ratio calculation circuit 22, and the delay control circuit 23 can each be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.

[0046] Some components of the timing adjustment device 3 are not limited to those implemented by dedicated hardware; some components of the timing adjustment device 3 may be implemented by software, firmware, or a combination of software and firmware. When some components of the timing adjustment device 3 are implemented by software or firmware, a program for causing a computer to execute the respective processing procedures in the signal supply unit 13, the S / N ratio calculation unit 12a, and the delay control unit 12b is stored in the memory 31 shown in Figure 3. The processor 32 shown in Figure 3 then executes the program stored in the memory 31.

[0047] Furthermore, Figure 10 shows an example in which some components of the timing adjustment device 3 are implemented by dedicated hardware, and Figure 3 shows an example in which some components of the timing adjustment device 3 are implemented by software or firmware. However, this is only one example, and some of the components of the timing adjustment device 3 may be implemented by dedicated hardware, while the remaining components may be implemented by software or firmware.

[0048] When the signal supply unit 13 adjusts the timing of the clock supply to the ADC2, it uses an AC voltage V as a signal with a lower frequency than the frequency of the signal to be received, instead of the RF signal which is the signal to be received. ＡＣ The AC voltage V is applied to the signal input terminal 1a of the sample-and-hold circuit 1. ＡＣ Because it is a signal with a lower frequency than the frequency of the signal being received, the DC voltage V ＤＣ The ADC2 can perform analog-to-digital conversion of the signal, similar to when the DC voltage V is applied to the signal input terminal 1a of the sample-and-hold circuit 1. Therefore, the timing adjustment device 3 can use the DC voltage V ＤＣ Similar to the case where the signal is supplied to the signal input terminal 1a of the sample-and-hold circuit 1, the timing of the clock supply to the ADC2 can be adjusted without having to prepare a transmitting system that transmits RF signals.

[0049] The sampling receivers according to Embodiments 1 and 2 are shown in which the sample-and-hold circuit 1 and ADC 2 are both single-ended. However, this is merely one example, and for example, as shown in Figure 11, the sample-and-hold circuit 1 may be a differential sample-and-hold circuit and the ADC 2 may be a differential ADC. In this case as well, it will operate in the same way as the sampling receivers according to Embodiments 1 and 2.

[0050] Figure 11 is a configuration diagram showing a differential sampling receiver. In Figure 11, the same reference numerals as in Figure 1 indicate the same or equivalent parts, so a detailed explanation is omitted. In Figure 11, 1a' and 1a'' are differential signal input terminals in the differential sample-and-hold circuit 1. 1c' and 1c'' are differential signal output terminals in the differential sample-and-hold circuit 1. 2a' and 2a'' are differential signal input terminals in the differential ADC 2. 2c' and 2c'' are differential signal output terminals in the differential ADC 2.

[0051] The differential sampling receiver shown in Figure 11 is an application of a differential sample-and-hold circuit 1 and a differential ADC 2 to the sampling receiver shown in Figure 1. However, this is merely one example, and the differential sample-and-hold circuit 1 and the differential ADC 2 may also be applied to any of the sampling receivers shown in Figures 6 to 9.

[0052] Within the scope of this disclosure, it is possible to freely combine the embodiments, modify any component of each embodiment, or omit any component in each embodiment.

[0053] This disclosure includes a signal supply unit that provides a signal at a lower frequency than the frequency of the signal to be received to a sample-and-hold circuit, and a timing adjustment unit that adjusts the timing of the clock supply to the analog-to-digital converter so that when the sample-and-hold circuit holds the signal provided by the signal supply unit in synchronization with the clock, the signal held by the sample-and-hold circuit is captured by the analog-to-digital converter. This allows for adjustment of the timing of the clock supply to the analog-to-digital converter without providing a transmitting system for transmitting RF signals, and is therefore suitable for a timing adjustment device, a timing adjustment method, and a sampling receiver.

[0054] 1 Sample-and-hold circuit, 1a Signal input terminal, 1a', 1a'' Differential signal input terminal, 1b Clock terminal, 1c Signal output terminal, 1c', 1c'' Differential signal output terminal, 2 ADC, 2a Signal input terminal, 2a', 2a'' Differential signal input terminal, 2b Clock terminal, 2c Signal output terminal, 2c', 2c'' Differential signal output terminal, 3 Timing adjustment device, 11 Signal supply unit, 12 Timing adjustment unit, 12a S / N ratio calculation unit, 12b Delay control unit, 12c Delay unit, 12d Switch, 12e Waveform detection unit, 13 Signal supply unit, 21 Signal supply circuit, 22 S / N ratio calculation circuit, 23 Delay control circuit, 24 Signal supply circuit, 31 Memory, 32 Processor.

Claims

1. A timing adjustment device comprising: a signal supply unit that supplies a signal with a frequency lower than the frequency of the signal to be received to a sample-and-hold circuit; and a timing adjustment unit that adjusts the timing of the clock supply to the analog-to-digital converter so that when the sample-and-hold circuit holds the signal supplied by the signal supply unit in synchronization with the clock, the signal held by the sample-and-hold circuit is captured by the analog-to-digital converter.

2. The timing adjustment device according to claim 1, characterized in that the signal supply unit supplies a DC voltage to the sample-and-hold circuit as a signal with a frequency lower than the frequency of the signal to be received.

3. The timing adjustment device according to claim 1, characterized in that the signal supply unit supplies an AC voltage to the sample-and-hold circuit as a signal with a frequency lower than the frequency of the signal to be received.

4. The timing adjustment device according to any one of claims 1 to 3, characterized in that the timing adjustment unit delays the clock supplied to the analog-to-digital converter more than the clock supplied to the sample-and-hold circuit, so that the signal held by the sample-and-hold circuit is acquired by the analog-to-digital converter.

5. The timing adjustment device according to any one of claims 1 to 4, characterized in that the timing adjustment unit comprises a signal-to-noise ratio calculation unit that calculates the signal-to-noise ratio in the signal output from the analog-to-digital converter, and a delay control unit that delays the clock supplied to the analog-to-digital converter more than the clock supplied to the sample-and-hold circuit, based on the signal-to-noise ratio calculated by the signal-to-noise ratio calculation unit, so that the signal held by the sample-and-hold circuit is acquired by the analog-to-digital converter.

6. The timing adjustment device according to any one of claims 1 to 4, characterized in that the timing adjustment unit comprises a waveform detection unit for detecting the waveform of the signal output from the sample-and-hold circuit to the analog-to-digital converter, and a delay control unit for delaying the clock supplied to the analog-to-digital converter more than the clock supplied to the sample-and-hold circuit, based on the waveform detected by the waveform detection unit, so that the signal held by the sample-and-hold circuit is captured by the analog-to-digital converter.

7. The timing adjustment device according to any one of claims 1 to 3, characterized in that, instead of adjusting the timing of supplying the clock to the analog-to-digital converter, the timing adjustment unit adjusts the timing of supplying the clock to the sample-and-hold circuit so that when the sample-and-hold circuit is holding a signal provided by the signal-providing unit in synchronization with the clock, the signal held by the sample-and-hold circuit is captured by the analog-to-digital converter.

8. A timing adjustment method in which a signal supply unit supplies a signal with a frequency lower than the frequency of the signal to be received to a sample-and-hold circuit, and when the sample-and-hold circuit holds the signal supplied by the signal supply unit in synchronization with the clock, the timing adjustment unit adjusts the timing of the clock supply to the analog-to-digital converter so that the signal held by the sample-and-hold circuit is captured by the analog-to-digital converter.

9. A sampling receiver comprising: a sample-and-hold circuit that holds a signal to be received in synchronization with a clock; an analog-to-digital converter that takes in the output signal of the sample-and-hold circuit and performs analog-to-digital conversion of the taken signal in synchronization with the clock; a signal supply unit that provides the sample-and-hold circuit with a signal at a lower frequency than the frequency of the signal to be received, instead of the signal to be received; and a timing adjustment unit that adjusts the timing of the clock supply to the analog-to-digital converter so that when the sample-and-hold circuit is holding the signal provided by the signal supply unit in synchronization with the clock, the signal held by the sample-and-hold circuit is taken in by the analog-to-digital converter.

10. The sampling receiver according to claim 9, characterized in that the signal supply unit supplies a DC voltage to the sample-and-hold circuit as a signal with a frequency lower than the frequency of the signal to be received.

11. The sampling receiver according to claim 9, characterized in that the signal supply unit supplies an AC voltage to the sample-and-hold circuit as a signal with a frequency lower than the frequency of the signal to be received.

12. The sampling receiver according to any one of claims 9 to 11, characterized in that the timing adjustment unit delays the clock supplied to the analog-to-digital converter more than the clock supplied to the sample-and-hold circuit, so that the signal held by the sample-and-hold circuit is acquired by the analog-to-digital converter.

13. The sampling receiver according to any one of claims 9 to 12, characterized in that the timing adjustment unit comprises a signal-to-noise ratio calculation unit that calculates the signal-to-noise ratio in the signal output from the analog-to-digital converter, and a delay control unit that delays the clock supplied to the analog-to-digital converter more than the clock supplied to the sample-to-hold circuit, based on the signal-to-noise ratio calculated by the signal-to-noise ratio calculation unit, so that the signal held by the sample-to-hold circuit is acquired by the analog-to-digital converter.

14. The sampling receiver according to any one of claims 9 to 12, characterized in that the timing adjustment unit comprises a waveform detection unit for detecting the waveform of the signal output from the sample-and-hold circuit to the analog-to-digital converter, and a delay control unit for delaying the clock supplied to the analog-to-digital converter more than the clock supplied to the sample-and-hold circuit, based on the waveform detected by the waveform detection unit, so that the signal held by the sample-and-hold circuit is captured by the analog-to-digital converter.

15. The sampling receiver according to any one of claims 9 to 11, characterized in that the timing adjustment unit adjusts the timing of the supply of the clock to the sample-and-hold circuit, instead of adjusting the timing of the supply of the clock to the analog-to-digital converter, such that when the sample-and-hold circuit is holding a signal provided by the signal supply unit in synchronization with the clock, the signal held by the sample-and-hold circuit is captured by the analog-to-digital converter.

16. The sampling receiver according to any one of claims 9 to 15, characterized in that the sample-and-hold circuit is a differential sample-and-hold circuit and the analog-to-digital converter is a differential analog-to-digital converter.

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