A real-time simulation method, a real-time simulation system, and a readable storage medium.

Abstract

This invention relates to the field of real-time simulation and discloses a real-time simulation method, a real-time simulation system, and a readable storage medium. The real-time simulation method includes: constructing a real-time simulation system, which includes a simulator, a CPU, and an FPGA communicatively connected to the CPU; selecting a clock synchronization mechanism based on the clock accuracy requirements of the real-time simulation, wherein the clock synchronization mechanism includes a soft clock synchronization mechanism and a hard clock synchronization mechanism; the soft clock synchronization mechanism obtains a first clock signal from the CPU operating system as the system clock; the hard clock synchronization mechanism uses a crystal oscillator as the clock source to generate a second clock signal through the FPGA, and the CPU reads the second clock signal using an interrupt strategy as the system clock; and performing real-time simulation of the real-time simulation system using the system clock. The real-time simulation method, real-time simulation system, and readable storage medium provided by this invention can avoid unnecessary resource consumption while ensuring that the clock accuracy requirements are met.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of real-time simulation, and particularly to a real-time simulation method, a real-time simulation system, and a readable storage medium. Background Technology

[0002] With the advancement of science and technology, the research and development of advanced technologies and equipment has gradually attracted widespread attention. However, the research and development of advanced technologies requires significant resource investment, especially in fields such as power grids and military equipment. Their unique characteristics of high voltage, high current, and high risk not only consume substantial resources for experimental equipment in the early stages but also often endanger the safety of researchers. Therefore, employing real-time simulation systems to achieve a safe and reliable research and testing method has become an essential approach to technological development.

[0003] A real-time simulation system refers to running a simulated physical model on a real-time simulator, combining input / output ports with an actual controller to conduct dynamic experiments, making the simulation results more realistic and effective. A real-time simulation system can realize a complete development and design process from purely digital and semi-physical to physical simulation. Clock synchronization, as a core technology of real-time simulation systems, not only determines the accuracy of the system but also the available time resources for the model at a single step size.

[0004] The inventors discovered that while achieving high clock accuracy, related technologies often suffer from excessive time consumption and unnecessary resource depletion. Summary of the Invention

[0005] The purpose of this invention is to provide a real-time simulation method, a real-time simulation system, and a readable storage medium that can avoid unnecessary resource consumption while ensuring that clock accuracy meets requirements.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a real-time simulation method, comprising: constructing a real-time simulation system, the real-time simulation system including a simulator, the simulator including a CPU and an FPGA communicatively connected to the CPU; selecting a clock synchronization mechanism according to the clock accuracy requirements of the real-time simulation, wherein the clock synchronization mechanism includes a soft clock synchronization mechanism and a hard clock synchronization mechanism; the soft clock synchronization mechanism obtains a first clock signal from the CPU operating system as the system clock; the hard clock synchronization mechanism uses a crystal oscillator as the clock source to generate a second clock signal through the FPGA, and the CPU reads the second clock signal as the system clock using an interrupt strategy; and performing real-time simulation of the real-time simulation system using the system clock.

[0007] Embodiments of the present invention also provide a real-time simulation system, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the real-time simulation method as described above.

[0008] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described real-time simulation method.

[0009] Compared to existing technologies, the embodiments of this invention select a clock synchronization mechanism based on the clock accuracy requirements of real-time simulation. This clock synchronization mechanism includes a soft clock synchronization mechanism and a hard clock synchronization mechanism. The soft clock synchronization mechanism obtains a first clock signal from the CPU operating system as the system clock. The hard clock synchronization mechanism uses a crystal oscillator as the clock source and generates a second clock signal through an FPGA. The CPU uses an interrupt strategy to read the second clock signal as the system clock and performs real-time simulation using this system clock. This allows the hard clock synchronization mechanism to obtain a higher-precision system clock to meet simulation requirements when the clock accuracy requirement for real-time simulation is high (e.g., greater than a preset clock accuracy). Conversely, when the clock accuracy requirement is low (e.g., less than or equal to a preset clock accuracy), the soft clock synchronization mechanism is used to obtain a lower-precision system clock. This ensures that the clock accuracy requirement is met while avoiding unnecessary resource consumption. For example, using a soft clock synchronization mechanism for a pure CPU simulation model can prevent the CPU's interrupt strategy from consuming excessive time resources and causing unnecessary resource consumption.

[0010] Furthermore, before selecting the clock synchronization mechanism based on the clock accuracy requirements of real-time simulation, the process includes: when the real-time simulation system includes only one simulator, then the selection of the clock synchronization mechanism based on the clock accuracy requirements of real-time simulation is performed; when the real-time simulation system includes multiple simulators, or one simulator and at least one expansion machine, then the clock signal obtained by any simulator in the real-time simulation system using the hard clock synchronization mechanism is used as the system clock, wherein the expansion machine only includes an FPGA. Because the clock signal generated by the hard clock synchronization mechanism has high clock accuracy, it enables high-precision clock synchronization in multi-machine real-time simulation systems. Simultaneously, since the clock signal is generated by the real-time simulation system itself, it solves the problem in related technologies where receiving clock signals via a Beidou clock server leads to significant dependence on external servers, and the entire real-time simulation system will fail to operate if the external server malfunctions.

[0011] In addition, when the real-time simulation system includes a simulator and at least one expansion machine, the step of using the clock signal obtained by any one of the simulators in the real-time simulation system using the hard clock synchronization mechanism as the system clock includes: the simulator using a crystal oscillator as a clock source to generate a second clock signal through the FPGA as the clock signal of the simulator, and sending the second clock signal to each of the expansion machines; each of the expansion machines receiving the second clock signal sent by the simulator as the clock signal of the expansion machine.

[0012] Additionally, sending the second clock signal to each of the expansion machines includes sending the second clock signal to each of the expansion machines via a direct connection channel between the FPGA of the simulator and the FPGA of the expansion machine.

[0013] Furthermore, when the real-time simulation system includes multiple simulators, using the clock signal obtained by any one of the simulators in the real-time simulation system using the hard clock synchronization mechanism as the system clock includes: configuring any one of the multiple simulators as the master simulator and the other simulators as slave simulators; the master simulator uses a crystal oscillator as the clock source to generate a second clock signal through the FPGA as the master simulator's clock signal, and sends the second clock signal to each slave simulator; each slave simulator receives the second clock signal sent by the master simulator as its own clock signal.

[0014] Furthermore, sending the second clock signal to each of the slave emulators includes: sending the second clock signal to each of the slave emulators through a direct connection channel between the FPGA of the master emulator and the FPGA of the slave emulator. This FPGA-to-FPGA direct connection (without CPU) clock transmission and reception mode effectively reduces system clock synchronization delay and error, improving the overall clock accuracy of the real-time simulation system.

[0015] In addition, each of the emulators includes a pulse transceiver board connected to the FPGA, the pulse transceiver board including a transmit port and a receive interface; the transmit port of each emulator is connected to the receive interface of an adjacent emulator, and the receive port of each emulator is connected to the transmit interface of another adjacent emulator, to form a closed-loop direct connection channel.

[0016] In addition, the CPU communicates with the FPGA via PCIe. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 This is a flowchart of the real-time simulation method provided in the first embodiment of the present invention;

[0019] Figure 2 This is a structural diagram of a real-time simulator;

[0020] Figure 3 This is a flowchart of clock synchronization in a real-time simulation system;

[0021] Figure 4 This is a schematic diagram of single-machine clock synchronization and multi-machine clock synchronization;

[0022] Figure 5 This is a schematic diagram of a distributed master-slave clock strategy.

[0023] Figure 6 This is a schematic diagram of the wiring structure of the pulse transceiver board;

[0024] Figure 7 This is a flowchart of multi-machine master-slave clock synchronization;

[0025] Figure 8 This is a schematic diagram of an electronic device provided in the second embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0027] The inventors discovered that current single-unit real-time simulators use a single clock source. Related technologies utilize the CPU operating system to obtain the clock signal, which is then used as the system model clock. However, due to the CPU's clock accuracy being at the μs level, high-precision, small-step real-time simulation cannot be achieved. Alternatively, an FPGA-based signal generation method can be used to improve clock accuracy. This method uses a crystal oscillator as the clock source, generating the clock through the FPGA. The CPU uses a polling strategy to read this signal as the system model clock, thus initiating a new round of model execution. While this method offers high clock accuracy, the CPU's polling strategy consumes significant time resources, especially for models simulated purely by the CPU, resulting in unnecessary resource consumption.

[0028] The first embodiment of the present invention relates to a real-time simulation method. The core of this embodiment is that the real-time simulation method includes: constructing a real-time simulation system, the real-time simulation system including a simulator, the simulator including a CPU and an FPGA communicatively connected to the CPU; selecting a clock synchronization mechanism according to the clock accuracy requirements of the real-time simulation, wherein the clock synchronization mechanism includes a soft clock synchronization mechanism and a hard clock synchronization mechanism; the soft clock synchronization mechanism obtains a first clock signal from the CPU operating system as the system clock; the hard clock synchronization mechanism uses a crystal oscillator as the clock source to generate a second clock signal through the FPGA, and the CPU reads the second clock signal as the system clock using an interrupt strategy; and using the system clock to perform real-time simulation of the real-time simulation system.

[0029] In other words, in standalone mode, the real-time simulation system selects a clock synchronization mechanism based on the clock accuracy requirements of the real-time simulation. This mechanism includes both soft and hard clock synchronization. The soft clock synchronization mechanism obtains a first clock signal from the CPU operating system as the system clock. The hard clock synchronization mechanism uses a crystal oscillator as the clock source and generates a second clock signal via the FPGA. The CPU then uses an interrupt strategy to read the second clock signal as the system clock. Real-time simulation is performed using this system clock. When the clock accuracy requirement for real-time simulation is high (e.g., greater than a preset clock accuracy), the hard clock synchronization mechanism is used to obtain a higher-precision system clock to meet the simulation requirements. Conversely, when the clock accuracy requirement for real-time simulation is low (e.g., less than or equal to a preset clock accuracy), the soft clock synchronization mechanism is used to obtain a lower-precision system clock. This ensures that the clock accuracy requirements are met while avoiding unnecessary resource consumption.

[0030] The implementation details of the real-time simulation method in this embodiment are described below. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0031] The real-time simulation method in this embodiment, such as Figure 1As shown, the specific steps include:

[0032] S11: Build a real-time simulation system.

[0033] In this step, the real-time simulation system includes a simulator, which includes a CPU and an FPGA that communicates with the CPU. Specifically, the CPU and the FPGA can communicate via PCIe (PCI-Express, peripheral component interconnect express, is a high-speed serial computer expansion bus standard).

[0034] S12: Select a clock synchronization mechanism based on the clock accuracy requirements of real-time simulation.

[0035] In this step, the clock synchronization mechanism includes a soft clock synchronization mechanism and a hard clock synchronization mechanism. When the clock accuracy requirement for real-time simulation is high (e.g., greater than the preset clock accuracy), the hard clock synchronization mechanism is used to obtain a system clock with higher clock accuracy to meet the simulation requirements. When the clock accuracy requirement for real-time simulation is low (e.g., less than or equal to the preset clock accuracy), the soft clock synchronization mechanism is used to obtain a system clock with lower clock accuracy. This ensures that the clock accuracy requirement is met while avoiding unnecessary resource consumption. For example, the soft clock synchronization mechanism is used for pure CPU simulation models to avoid unnecessary resource consumption caused by the CPU interrupt strategy consuming too much time resources.

[0036] S13: Obtain the system clock using the selected clock synchronization mechanism.

[0037] like Figure 2 As shown, in this step, the soft clock synchronization mechanism obtains the first clock signal from the CPU operating system as the system clock, and the hard clock synchronization mechanism uses a crystal oscillator as the clock source to generate a second clock signal through the FPGA, and the CPU uses an interrupt strategy to read the second clock signal as the system clock.

[0038] S14: Real-time simulation of the system using the system clock.

[0039] For a real-time simulation system that includes only one simulator, a clock synchronization mechanism (soft clock synchronization mechanism and hard clock synchronization mechanism) can be selected according to the clock accuracy requirements of the real-time simulation. For example, a soft clock synchronization mechanism is used for models with pure CPU simulation, while a hard clock synchronization mechanism is used for other simulations with higher clock accuracy requirements. This ensures that the clock accuracy requirements are met and avoids unnecessary resource consumption.

[0040] In other words, in the case of a single simulator, the original method of using a single clock source is broken. Instead, a soft clock synchronization mechanism and a hard clock synchronization mechanism based on model resources are adopted. According to the resources occupied by the model simulation, soft clock synchronization under pure CPU simulation and hard clock synchronization under CPU+FPGA co-simulation are achieved, thereby effectively saving system resources.

[0041] Considering the relevant technologies, the clock synchronization strategy for multiple real-time simulators based on external input is suitable for real-time simulation systems composed of multiple real-time simulators. Each simulator is connected to a dedicated clock receiving device via fiber optic cables, serial ports, or other media. This device receives clock signals through a BeiDou clock server and sends them to the other real-time simulators to achieve time synchronization. While this method can solve the clock synchronization problem for multiple simulators, it is highly dependent on an external server. If the server malfunctions, the entire system will fail to operate.

[0042] Optionally, before selecting a clock synchronization mechanism based on the clock accuracy requirements of real-time simulation, the following may be included: when the real-time simulation system includes only one simulator, then the clock synchronization mechanism is selected based on the clock accuracy requirements of real-time simulation; when the real-time simulation system includes multiple simulators, or one simulator and at least one expansion machine, then the clock signal obtained by any simulator in the real-time simulation system using a hard clock synchronization mechanism is used as the system clock, wherein the expansion machine includes only FPGA.

[0043] By proposing a distributed master-slave clock synchronization method, where the clock signal is generated by the real-time simulation system itself, clock synchronization of multiple real-time simulators can be achieved without an external clock source. This solves the problem in related technologies that rely heavily on external servers for clock signals received from Beidou clock servers, and where the entire real-time simulation system will fail if the external server malfunctions. Furthermore, because the clock signal generated by the hard clock synchronization mechanism has high clock accuracy, high-precision clock synchronization can be achieved in multi-machine real-time simulation systems.

[0044] Of course, when the real-time simulation system includes multiple simulators, or one simulator and at least one expansion machine, the clock signal obtained by any simulator in the real-time simulation system using a soft clock synchronization mechanism can also be used as the system clock.

[0045] In practical applications, the clock accuracy can be changed simply by altering the system clock source in the model settings (i.e., switching the simulator to a soft clock synchronization mechanism or a hard clock synchronization mechanism) without changing the hardware connections. This offers high convenience and precise clock accuracy.

[0046] When a real-time simulation system includes a simulator and at least one expansion machine, the clock signal obtained by any simulator in the real-time simulation system using a hard clock synchronization mechanism is used as the system clock. This includes: the simulator using a crystal oscillator as the clock source to generate a second clock signal through the FPGA as the simulator's clock signal, and sending the second clock signal to each expansion machine; each expansion machine receiving the second clock signal sent by the simulator as its own clock signal.

[0047] Furthermore, sending the second clock signal to each expansion unit may include sending the second clock signal to each expansion unit through a direct connection channel between the FPGA of the simulator and the FPGA of the expansion unit.

[0048] When a real-time simulation system includes multiple simulators, the clock signal obtained by any one simulator in the real-time simulation system using a hard clock synchronization mechanism is used as the system clock. This includes: configuring any one simulator among the multiple simulators as the master simulator, and the other simulators as slave simulators; the master simulator uses a crystal oscillator as the clock source to generate a second clock signal through the FPGA as the master simulator's clock signal, and sends the second clock signal to each slave simulator; each slave simulator receives the second clock signal sent by the master simulator as its own clock signal.

[0049] Furthermore, sending the second clock signal to each slave emulator can include: sending the second clock signal to each slave emulator through a direct connection channel between the FPGA of the master emulator and the FPGA of the slave emulator. This FPGA-to-FPGA direct connection (without going through the CPU) clock transceiver mode can effectively reduce system clock synchronization delay and error, and improve the overall clock accuracy of the real-time simulation system.

[0050] In practical applications, each emulator includes a pulse transceiver board connected to the FPGA. The pulse transceiver board includes a transmit port and a receive interface. The transmit port of each emulator is connected to the receive interface of an adjacent emulator, and the receive port of each emulator is connected to the transmit interface of another adjacent emulator to form a closed-loop direct connection channel.

[0051] In one instance, such as Figure 3 As shown, the real-time simulation method can mainly include the following steps:

[0052] Step 1: The real-time simulator adopts a CPU+FPGA co-simulation approach. The system has two clock mechanisms: a soft synchronization mechanism using the CPU's internal clock and a hard synchronization mechanism using clock pulse signals sent by the FPGA.

[0053] In step 1, the real-time simulator consists of a CPU and an FPGA, which communicate via PCIe. The CPU is used for μs-level simulation, while the FPGA is used for ns-level simulation. Depending on the simulation requirements, the simulator provides both soft clock synchronization and hard clock synchronization mechanisms, which can be found in [reference needed]. Figure 2 .

[0054] Specifically, the soft clock synchronization mechanism obtains the clock signal from the operating system in the CPU, with a clock accuracy on the order of μs, suitable for simulations within the CPU. Hard clock synchronization uses a crystal oscillator as the clock source and generates the clock through the FPGA, with a hard clock synchronization accuracy on the order of nanoseconds, suitable for CPU+FPGA co-simulation.

[0055] Step 2: Based on the resources required for simulation (whether the simulation model in the real-time simulation system is a single machine or a multi-machine model), construct a single-machine synchronization mode or a multi-machine synchronization mode in the model.

[0056] like Figure 4 As shown, in step 2, the real-time simulation system is divided into single-machine synchronous mode and multi-machine synchronous mode according to the scale of the simulation system.

[0057] The single-machine synchronous mode operates with a single emulator, using the emulator's internal clock, and is configured as either soft or hard synchronization depending on the resources used.

[0058] The multi-machine synchronous mode involves multiple simulators forming a simulation system for joint simulation. This can be divided into two cases: when the system consists of one CPU+FPGA real-time simulator and multiple expansion machines containing only FPGAs, the clock of the CPU+FPGA real-time simulator is used as the master clock (i.e., the system clock); when the system contains multiple CPU+FPGA real-time simulators, the clock of any one of the CPU+FPGA real-time simulators is used as the master clock (i.e., the system clock). For details, see the section on using the master simulator clock configured in step 3 as the master clock.

[0059] Step 3: Determine the master-slave relationship between the simulators, configure the synchronization signal transmission form of each simulator in the real-time simulation program, and clarify the source of the clock synchronization signal for each simulator.

[0060] like Figure 5 As shown in step 3, when multiple real-time simulators perform joint simulation, each simulator has multiple clock sources, including the internal CPU and FPGA clock sources of the simulator, as well as clock sources from other external simulators. To achieve clock unification and synchronization among the simulators, a multi-agent distributed master-slave configuration strategy is adopted. Without changing the hardware connections, the configuration module in the simulation model is used to configure the clock of any simulator as the system master clock.

[0061] Specifically, the real-time simulator is divided into a leader and a follower, with each real-time simulation system having only one leader. The leader serves as the master clock for the real-time simulation system. It uses the clock signal generated by its own FPGA hard clock synchronization mechanism and transmits this clock signal to the follower via a high-precision pulse transceiver board. The follower uses its own high-precision pulse transceiver board to receive the clock pulse signal sent by the leader, using it as its own clock signal to achieve clock synchronization.

[0062] In addition, the clock signal transmission port (audio or fiber optic) can be set through the configuration module in the simulation model. This module will automatically load the system's underlying driver when the real-time simulation system is running, driving the high-precision pulse transceiver board to receive and send clock pulse signals through different transmission ports.

[0063] Step 4: Place the high-precision pulse transceiver board into the real-time simulator and connect the simulators via audio cables or fiber optic cables.

[0064] like Figure 6 As shown, in step 4, the high-precision pulse transceiver board is placed into the real-time simulator. Each board includes two types: audio input / output ports and fiber optic input / output ports. Audio cables or fiber optic cables are used to connect the simulators. Different transmission cables are adapted according to the different clock synchronization signal sources set in step 3. The audio transmission distance is within 10m.

[0065] In addition, the transmitting port (Tx) of the local sync cable is connected to the receiving interface (Rx) of the lower emulator, while the local receiving interface (Rx) is connected to the transmitting interface (Tx) of the upper emulator, thus forming a closed-loop connection.

[0066] In other words, clock synchronization between the master emulator (leader) and slave emulators is achieved through a high-precision pulse transceiver board, using a direct connection between FPGAs (without CPU involvement). After each slave emulator receives the clock signal from the master emulator (leader), its own FPGA generates a clock pulse.

[0067] By adopting a direct FPGA-to-FPGA clock transceiver mode that bypasses the CPU, the system clock synchronization delay and error can be effectively reduced, and the overall clock accuracy of the system can be improved.

[0068] Step 5: When running the real-time simulation program, adaptively configure the soft or hard synchronization mechanism and generate clock pulse signals.

[0069] In step 5, when running the real-time simulation program, the clock source will be configured as either soft clock synchronization or hard clock synchronization depending on the simulation resources required by the simulation model. When the simulation model only requires CPU resources, soft clock synchronization is used, meaning the clock signal is obtained from the CPU operating system. When the simulation model includes hardware resources such as FPGAs, I / O boards, and high-precision pulse transceiver boards, hard clock synchronization is configured.

[0070] like Figure 7 As shown, under hard clock synchronization, before the model runs, the CPU of the simulation host (leader) sends the simulation run step size to the FPGA via the PCIe line. The FPGA accumulates the count using a counter. When the counter reaches the simulation step size, the FPGA generates a pulse signal as the system clock and sets the counter to zero to start counting again.

[0071] Specifically, within the master emulator, this pulse signal will notify all model subsystems (user model programs) on the target machine (i.e., the emulator host) to begin a new round of operation via a low-level interrupt. Externally, this pulse signal is sent to the slave emulator via a high-precision pulse transceiver board, achieving clock synchronization between the master and slave emulators through direct FPGA-to-FPGA connection.

[0072] Compared to existing technologies, the embodiments of this invention employ both soft and hard clock synchronization strategies based on model resources. One method obtains clock signals from the operating system within the CPU, while the other generates clock signals via a crystal oscillator and FPGA. Depending on the resource requirements of the model, it supports both soft clock synchronization under pure CPU simulation and hard clock synchronization under CPU+FPGA co-simulation, thereby addressing the limitations of existing clock synchronization methods, such as their simplification and high resource consumption, and effectively improving the clock and simulation accuracy of real-time simulation systems.

[0073] The second embodiment of the present invention relates to a real-time simulation system, such as... Figure 8 As shown, it includes: at least one processor 201, and a memory 202 communicatively connected to at least one processor 201, wherein the memory 202 stores instructions that can be executed by at least one processor 201, and the instructions are executed by at least one processor 201 to enable at least one processor 201 to perform the real-time simulation method as described above.

[0074] The memory 202 and processor 201 are connected via a bus, which may include any number of interconnecting buses and bridges, connecting various circuits of one or more processors 201 and memory 202 together. The bus may also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver may be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by processor 201 is transmitted over a wireless medium via an antenna, which further receives data and transmits it to processor 201.

[0075] Processor 201 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory 202 can be used to store data used by processor 201 during operation.

[0076] The third embodiment of the present invention relates to a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described real-time simulation method embodiment.

[0077] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0078] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present invention.

Claims

1. A real-time simulation method, characterized in that, include: A real-time simulation system is constructed, the real-time simulation system including a simulator, the simulator including a CPU and an FPGA communicatively connected to the CPU; The clock synchronization mechanism is selected based on the clock accuracy requirements of real-time simulation, wherein the clock synchronization mechanism includes a soft clock synchronization mechanism and a hard clock synchronization mechanism. The soft clock synchronization mechanism obtains a first clock signal from the CPU operating system as the system clock. The hard clock synchronization mechanism is as follows: a crystal oscillator is used as the clock source to generate a second clock signal through the FPGA, and the CPU uses an interrupt strategy to read the second clock signal as the system clock. The real-time simulation system is performed using the system clock. When the real-time simulation system includes multiple simulators, one of the multiple simulators is configured as the master simulator, and the other simulators are all slave simulators. The master emulator uses a crystal oscillator as its clock source and generates a second clock signal through the FPGA as its clock signal, and sends the second clock signal to each of the slave emulators; wherein, the second clock signal is sent to each of the slave emulators through a direct connection channel between the FPGA of the master emulator and the FPGA of the slave emulator. Each of the slave emulators receives the second clock signal sent by the master emulator as its own clock signal.

2. The real-time simulation method according to claim 1, characterized in that, Before selecting the clock synchronization mechanism based on the clock accuracy requirements of real-time simulation, the following steps are also included: When the real-time simulation system includes only one simulator, the clock synchronization mechanism selected according to the clock accuracy requirements of the real-time simulation is then executed. When the real-time simulation system includes multiple simulators, or one simulator and at least one expansion machine, the clock signal obtained by any simulator in the real-time simulation system using the hard clock synchronization mechanism is used as the system clock, wherein the expansion machine includes only FPGA.

3. The real-time simulation method according to claim 2, characterized in that, When the real-time simulation system includes one simulator and at least one expansion machine, the step of using the clock signal obtained by any of the simulators in the real-time simulation system using the hard clock synchronization mechanism as the system clock includes: The simulator uses a crystal oscillator as its clock source and generates a second clock signal through the FPGA as its clock signal, and sends the second clock signal to each of the expansion machines. Each of the expansion machines receives the second clock signal sent by the simulator as its own clock signal.

4. The real-time simulation method according to claim 3, characterized in that, Sending the second clock signal to each of the expansion units includes: The second clock signal is sent to each of the expansion machines through a direct connection between the FPGA of the simulator and the FPGA of the expansion machine.

5. The real-time simulation method according to claim 1, characterized in that, Each of the emulators includes a pulse transceiver board connected to the FPGA, the pulse transceiver board including a transmit port and a receive interface; Each of the simulators has its transmitting port connected to the receiving interface of an adjacent simulator, and each of the simulators has its receiving port connected to the transmitting interface of another adjacent simulator, to form a closed-loop direct connection channel.

6. The real-time simulation method according to claim 1, characterized in that, The CPU communicates with the FPGA via PCIe.

7. A real-time simulation system, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the real-time simulation method as described in any one of claims 1 to 6.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the real-time simulation method according to any one of claims 1 to 6.

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