Composite substrate, method for manufacturing composite substrate, and device

Abstract

Provided are a composite substrate in which the occurrence of defects in an epitaxial layer caused by voids present at a bonding interface of a bonded substrate can be suppressed, a method for manufacturing the composite substrate, and a device.　This method for manufacturing a composite substrate including a first semiconductor substrate and a second semiconductor substrate comprises: a bonding target surface activation step of activating each of a first bonding target surface in the first semiconductor substrate and a second bonding target surface in a second semiconductor substrate transfer substrate; a bonding step of bonding the first bonding target surface and the second bonding target surface after the bonding target surface activation step to form a bonded semiconductor substrate; a peeling step of peeling a part of the second semiconductor substrate transfer substrate after the bonding step to obtain a composite substrate in which the part of the second semiconductor substrate transfer substrate is transferred to the first semiconductor substrate as the second semiconductor substrate; a polishing step of polishing a peeled surface of the second semiconductor substrate; and a measurement step of measuring a height of a protrusion present on the polished peeled surface after the polishing step.

Description

Composite substrate, method for manufacturing a composite substrate, and device

[0001] The present invention relates to a composite substrate, a method for manufacturing a composite substrate, and a device, and more particularly to a semiconductor substrate in which an epitaxial layer is formed on a bonded substrate consisting of two or more substrates formed by bonding substrates, and which can prevent the occurrence of epitaxial defects caused by voids at the bonding interface of the bonded substrates.

[0002] In recent years, the electrification of automobiles has been promoted as one of the pillars for achieving carbon neutrality in order to prevent global warming, and the demand for SiC single-crystal substrates as low-loss, high-voltage electronic device substrates used in these vehicles has been increasing.

[0003] Until now, the vapor phase growth method utilizing sublimation has been used to grow SiC single crystals. Currently, the method used for growing large SiC single crystals is a sublimation method called the modified Rayleigh process. The basic process of this method is that in a quasi-closed space, vapor consisting of Si and C sublimated from the raw materials is transported in a diffused state through an inert gas, and condenses supersaturated on a seed crystal set to a lower temperature than the raw materials. Therefore, the crystal growth rate is determined by the temperature of the raw materials, the temperature gradient in the system, the pressure, etc.

[0004] The challenge in SiC single crystal growth lies in how to improve both quality and productivity, and other growth methods such as solution-based methods and high-temperature CVD (gas-based) methods are also being developed.

[0005] SiC single crystal substrates, like Si wafers, are manufactured by cutting and polishing a single crystal in a block (ingot). Because SiC single crystals are an ultrahard material, diamond is generally used as the abrasive for processing due to their hardness. The mainstream method used for cutting SiC single crystals is multi-wire saw cutting. Following cutting, the SiC single crystal substrate is polished, first undergoing a multi-stage lapping process using diamond abrasive grains to shape the substrate. In the final polishing stage, to ensure the quality of the substrate surface, chemical polishing, such as chemical mechanical polishing (CMP), is performed using an etching-type polishing solution, rather than diamond abrasive grains. The quality of this final polishing stage greatly influences the quality of the subsequent epitaxial growth stage; therefore, the surface finish of the SiC single crystal requires damage-free and highly flat. (Non-Patent Literature 1).

[0006] As an alternative to the conventional method of manufacturing SiC single crystal substrates described above, a method for manufacturing bonded SiC substrates using a combination of ion implantation exfoliation and direct substrate bonding has been developed. The bonded SiC substrate consists of a SiC single crystal thin film with sufficient thickness for homoepitaxial growth and an inexpensive support substrate to support it. The mechanism for achieving cost reduction lies in dramatically increasing the number of SiC single crystal substrates that can be obtained from an expensive SiC single crystal ingot. By efficiently using expensive SiC single crystals, cost reduction, which was a problem in conventional methods, can be achieved (Non-Patent Literature 2). Furthermore, this method allows for the effective use of rare, high-quality single crystals, enabling the efficient production of high-quality bonded SiC substrates (Patent Literature 1).

[0007] When fabricating power devices, high-frequency devices, etc., using SiC single-crystal substrates, it is common to epitaxially grow SiC thin films on the substrate using a method called thermal CVD (thermochemical vapor deposition) or to directly implant dopants using ion implantation. However, in the latter case, high-temperature annealing is required after implantation, so epitaxial growth is widely used for thin film formation. When epitaxial growth is performed on bonded SiC substrates, there are challenges such as increased interfacial resistance due to voids at the bonding interface and decreased device yield due to defects during epitaxial growth. Below, we will introduce two patent documents that propose methods to avoid these problems.

[0008] After forming a fragile layer by implanting hydrogen ions into a SiC single crystal substrate, a base substrate is attached to the side of the SiC single crystal substrate where hydrogen ions were implanted, and then heat treatment is performed. This causes the SiC single crystal substrate to peel off at the fragile layer, forming a deposition substrate on the base substrate with a SiC single crystal layer composed of a portion of the SiC single crystal substrate. Subsequently, a support (e.g., polycrystalline SiC) is deposited on the peeled surface of the SiC single crystal layer of the deposition substrate, and then the base substrate is removed. By creating a configuration in which the support is deposited on the SiC single crystal layer that will become the active region of the device, a bonded substrate can be provided that does not have voids or oxides at the junction interface between the SiC single crystal layer and the support (Patent Document 2).

[0009] In the technology of bonding a SiC single-crystal substrate to a SiC polycrystalline substrate, an epitaxial layer is grown on the SiC single-crystal substrate bonded to the SiC polycrystalline substrate. Therefore, it was necessary to bond a high-quality SiC single-crystal substrate to the SiC polycrystalline substrate without defects. However, the polishing process required to ensure the surface roughness necessary for bonding the SiC single-crystal substrate to the SiC polycrystalline substrate by room-temperature bonding or diffusion bonding was costly, and defects occurring at the bonding interface sometimes reduced the yield.

[0010] To address the resulting yield reduction, a bonded substrate without voids at the bonding interface can be provided by sequentially forming a first graphene layer, an epitaxial layer, a second graphene layer, and a first SiC polycrystalline layer on the Si surface of a SiC single crystal substrate, then sequentially removing the SiC single crystal substrate and the first graphene layer to form a second SiC polycrystalline layer, and finally removing the second graphene layer and the first SiC polycrystalline layer (Patent Document 3).

[0011] Japanese Patent Publication No. 2012-146695, Japanese Patent Publication No. 2002-280531, International Publication No. 2022 / 123872

[0012] Noboru Otani, "Development Trends of Large-Diameter SiC Single Crystal Substrates," Journal of the Vacuum Society of Japan, Vol. 54, No. 6, pp. 339-345, 2011. Takamitsu Kawahara et al., "Fabrication of Low-Cost SiC Substrates by Fusion of Ion Implantation Delamination and Direct Substrate Bonding," Journal of the Japan Society for Precision Engineering, Vol. 83, No. 9, pp. 833-836, 2017.

[0013] As disclosed in Patent Documents 2 and 3, in order to suppress defects that occur in the epitaxial layer due to voids at the bonding interface, an epitaxial layer is formed on a temporary substrate that will be removed later, and then the temporary substrate is removed and a SiC polycrystal is grown on the epitaxial layer. However, while the generation of voids is suppressed, the number of steps required to prepare the temporary substrate, to bond another substrate to the temporary substrate, to remove the temporary substrate, and to regenerate the temporary substrate increases, resulting in the problem of increased costs for manufacturing a bonded substrate with an epitaxial layer due to the increased number of steps.

[0014] Therefore, the objective is to provide a composite substrate, a method for manufacturing a composite substrate, and a device that can suppress the occurrence of defects in the epitaxial layer caused by voids present at the bonding interface of the bonded substrate, using a simple and low-cost method for manufacturing a bonded substrate as disclosed in Patent Document 1.

[0015] To solve the above problems, the present invention provides a method for manufacturing a composite substrate comprising a first semiconductor substrate and a second semiconductor substrate, including: a bonding target surface activation step of activating a first bonding target surface on a first semiconductor substrate and a second bonding target surface on a second semiconductor substrate transfer substrate; a bonding step of bonding the first bonding target surface and the second bonding target surface after the bonding target surface activation step to form a bonded semiconductor substrate; a peeling step of peeling off a part of the second semiconductor substrate transfer substrate after the bonding step to obtain a composite substrate in which the part of the second semiconductor substrate transfer substrate is transferred to the first semiconductor substrate as a second semiconductor substrate; a polishing step of polishing the peeled surface of the second semiconductor substrate; and a measurement step of measuring the height of the protrusions present on the polished peeled surface after the polishing step.

[0016] Furthermore, in order to solve the above problems, the composite substrate of the present invention comprises a first semiconductor substrate and a second semiconductor substrate laminated on the first semiconductor substrate, wherein a protrusion exists on the surface of the second semiconductor substrate, and the maximum height of the protrusion is less than 0.8 nm.

[0017] Furthermore, in order to solve the above problems, the device of the present invention comprises the composite substrate of the present invention.

[0018] The present invention provides a composite substrate, a method for manufacturing the composite substrate, and a device that can suppress the occurrence of defects in the epitaxial layer caused by voids present at the bonding interface. As a result, an improvement in the yield of devices using the bonded substrate can be expected.

[0019] This is a flow chart showing an example of a method for manufacturing the composite substrate of the present invention. This is a schematic perspective view showing an example of the composite substrate of the present invention. This is a schematic side view showing an example of a single crystal substrate after hydrogen ion implantation. This is a schematic side view showing an example of a bonded semiconductor substrate after the bonding process. This is a schematic side view showing an example of a composite substrate after the delamination process. This is a schematic side view showing an example of the composite substrate of the present invention with an epitaxial layer formed on it. This is a schematic side view showing an example of a void at the bonding interface between the first semiconductor substrate and the second semiconductor substrate. This figure shows the results of AFM observation of a protrusion on the delamination surface of the second semiconductor substrate in the area where the void is located, in a composite substrate having a void at the bonding interface between the first semiconductor substrate and the second semiconductor substrate. This figure shows the results of measuring the stress of the protrusion observed in Figure 8 using a Raman spectroscopic microscope. This figure shows the results of TEM observation of a side cross-section of a composite substrate (void No. 1) having an epitaxial layer. This figure shows the results of TEM observation of a side cross-section of a composite substrate (void No. 2) having an epitaxial layer. This figure shows the results of TEM observation of a side cross-section of a composite substrate (void No. 8) having an epitaxial layer.

[0020] Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

[0021] [Composite Substrate] The composite substrate of the present invention comprises a first semiconductor substrate and a second semiconductor substrate laminated on the first semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are joined via a bonding interface. The composite substrate is formed in a substantially disc shape with a diameter of 4 to 12 inches, for example, having an orientation flat. Furthermore, the composite substrate may have an epitaxial layer laminated on the second semiconductor substrate.

[0022] <Configuration of Composite Substrate> Figure 2 is a schematic perspective view showing an example of a composite substrate of the present invention. The composite substrate 10 is a bonded semiconductor substrate and is formed in a substantially disc shape, for example, with an orientation flat. The semiconductor substrate 10 comprises a support substrate 11, which is an example of a first semiconductor substrate, and a single crystal substrate 13, which is an example of a second semiconductor substrate, with the single crystal substrate 13 bonded to the support substrate 11. Furthermore, an epitaxial layer, which is not shown in Figure 2, may be formed on the single crystal substrate 13.

[0023] An example of a first semiconductor substrate is a support substrate 11, which is a SiC polycrystalline substrate, and an example of a second semiconductor substrate is a SiC single crystal substrate 13, which is a SiC single crystal substrate. These elements are semiconductor materials that can be used to fabricate semiconductor devices. To prevent delamination of the joints due to thermal expansion and warping of the composite substrate during high-temperature heat treatment, it is most desirable that the first and second semiconductor substrates be made of the same material.

[0024] Furthermore, the single crystal substrate 13, which is an example of a second semiconductor substrate, is made of, for example, silicon (Si), gallium nitride (GaN), gallium oxide (Ga ２ O ３ It may be either (a, b, c, or diamond (C)). These elements are semiconductor materials that can be used to fabricate semiconductor devices.

[0025] When using a SiC polycrystalline substrate for the support substrate 11, a substrate containing a mixture of SiC crystals of various polytypes and orientations may be used. Since a SiC polycrystalline substrate containing a mixture of various polytypes and orientations can be manufactured without strict temperature control, it is possible to reduce the cost of manufacturing the support substrate 11.

[0026] The thickness TT1 of the support substrate 11 should be determined so as to provide sufficient mechanical strength to withstand subsequent processing steps such as the formation of an epitaxial layer and the formation of semiconductor elements or semiconductor devices on top of it. For example, if the diameter of the support substrate 11 is 150 mm, the thickness TT1 may be around 350 μm.

[0027] <Protrusions on the surface of the second semiconductor substrate> Protrusions exist on the surface of the second semiconductor substrate. In composite substrates, voids may form at the bonding interface between the first semiconductor substrate and the second semiconductor substrate. When the first and second semiconductor substrates are directly bonded, voids are formed due to particles and irregularities on the bonding surface itself. Then, protrusions may form on the surface of the second semiconductor substrate located directly above the formed voids, due to the influence of the voids.

[0028] When growing an epitaxial layer on the convex portion of the second semiconductor substrate caused by the influence of voids in the bonding interface, the stress is different between the second semiconductor substrate directly above the portion without voids and the convex portion of the second semiconductor substrate affected by the voids. For example, the second semiconductor substrate directly above the void formed by the attachment of particles is curved by the height of the particles and has a convex shape upward to form a convex portion. Therefore, compressive stress is generated in the central portion of the convex portion, and tensile stress is generated in the outer peripheral portion thereof. In addition, in the convex portion of the second semiconductor substrate, the crystal plane orientation is shifted compared to the normal portion of the second semiconductor substrate without the convex portion, so epitaxial defects are likely to occur in the epitaxial layer grown on the convex portion.

[0029] Therefore, in order to suppress the occurrence of epitaxial defects, the maximum height of the convex portion is set to less than 0.8 nm, which is a predetermined specified value. Although details will be described later, there is a correlation between the above epitaxial defects and the height of the convex portion on the surface of the second semiconductor substrate. By setting the height of the convex portion to less than 0.8 nm, which is the specified value, epitaxial defects can be suppressed.

[0030] (Formation of voids in the bonding interface) Regarding the voids formed in the bonding interface between the first semiconductor substrate and the second semiconductor substrate in the bonding step of the composite substrate manufacturing method described later, it will be described using FIG. 7. FIG. 7 is a side schematic view showing an example of a void at the bonding interface between the first semiconductor substrate (support substrate 11 as an example) and the second semiconductor substrate (single crystal substrate 13 as an example). When the two semiconductor substrates are directly bonded in this way, voids 20 are formed in the bonding interface due to particles adhering to the bonding surface of either the support substrate 11 or the single crystal substrate 13 or the unevenness of the bonding surface itself.

[0031] When an epitaxial layer is grown on the convex portion of the single crystal substrate 13 directly above the void 20 of the bonding interface, the stress generated in the single crystal substrate 13 is different between the single crystal substrate 13 above the normal bonding interface and the single crystal substrate 13 directly above the void. For example, when a particle adheres, the single crystal substrate 13 directly above the void 20 "curves" by the height of the void 20 caused by the particle and becomes a convex shape upward. The height of this void 20 is called "void height 21", the portion where the single crystal substrate 13 directly above the void 20 curves and bulges is called "convex portion 30", and the height of the convex portion 30 is called "convex portion height 31".

[0032] In principle, it is considered that the heights of the "void height 21" and the "convex portion height 31" are the same. Although the diameter of the void 20 is about 10 to 100 μm, the void height 21 is extremely low at several nm or less and is difficult to observe visually. Therefore, the shape of the convex portion 30 on the surface of the second semiconductor substrate in the composite substrate was observed by AFM (atomic force microscope). An example of the result is shown in FIG. 8. This convex portion 30 is hemispherical, the diameter in the horizontal direction (direction parallel to the orientation flat) in FIG. 8 is 0.01908 mm, and the convex portion height 31 is 1.155 nm.

[0033] Next, FIG. 9 shows the result of measuring the stress of the convex portion 30 observed in FIG. 8 by a Raman spectroscopic microscope. It was found that compressive stress is generated in the central portion of the convex portion 30 and tensile stress is generated in the outer peripheral portion due to the curvature of the single crystal substrate 13 caused by the void 20. The maximum compressive stress in the central portion of the convex portion 30 calculated from the wave number shift was measured to be -782 MPa. From the results of FIGS. 8 and 9, it was found that the convex portion 30 is hemispherical with compressive stress in the central portion and tensile stress in the outer peripheral portion.

[0034] <Confirmation of the formation state of epitaxial defects in the epitaxial layer 16 formed on the convex portion 30 caused by the void 20> Regarding the epitaxial layer 16 grown on the convex portion 30 directly above the void 20 formed on the bonding interface formed by bonding the bonding target surface 11a of the support substrate 11 and the bonding target surface 13a of the single crystal substrate 13 in the bonding process described later, FIGS. 10A to 10C will be used for explanation.

[0035] First, the results in Figures 8 and 9 prove that the single-crystal substrate 13 is curved and raised by the voids 20, forming a convex portion 30 where stress is generated. In addition, since the crystal plane orientation in the convex portion 30 is shifted compared to the normal part of the single-crystal substrate, it is expected that epitaxial defects due to the shift in crystal orientation caused by the curvature are likely to occur in the epitaxial layer 16 that maintains the crystal structure of the single-crystal substrate 13.

[0036] Based on these predictions, we then grew an epitaxial layer 16 on a single-crystal substrate 13, where the height 31 of the protrusions 30 caused by the voids 20 had been measured in advance, and verified whether epitaxial defects occurred in the epitaxial layer 16 directly above the voids 20.

[0037] As a verification method, semiconductor substrates 10 were prepared in which the diameters of nine voids 20 within the same substrate were measured in advance, as well as the height 31 of the protrusions generated due to the voids 20. Epitaxial layers 16 were grown on these single-crystal substrates 13, and the occurrence of epitaxial defects within the epitaxial layer 16 and the presence or absence of surface irregularities of the epitaxial layer 16 were verified by observing the cross-section using a TEM.

[0038] Table 1 shows the results of observations, including the measured diameter of the voids 20 in the direction parallel to the orientation flat, the height of the protrusions 31, and the presence or absence of epitaxial defects and surface irregularities of the epitaxial layer 16. As shown in Table 1, there is a correlation between the presence or absence of epitaxial defects and the height of the protrusions 31, and it was found that epitaxial defects occur within the epitaxial layer 16 when the height of the protrusions 31 is ≥ 0.8 nm.

[0039] These results support the hypothesis that epitaxial defects are more likely to occur due to two reasons: firstly, the higher the void height 21, the more the single-crystal substrate 13 curves and bulges, forming a stressed convex portion 30; and secondly, the crystal plane orientation in the curved convex portion 30 directly above the void 20 is misaligned with that of the normal portion.

[0040] Based on these results, we found that there is a correlation between epitaxial defects and the height 31 of the protrusion 30 of the single crystal substrate 13 directly above the void 20, and that by setting the protrusion height 31 to <0.8 nm, epitaxial defects inside the epitaxial layer 16 above the protrusion 30 directly above the void 20 can be suppressed.

[0041]

[0042] As an example of images observed using TEM in this verification, Figures 10A to 10C show the results of TEM observation of a side cross-section of a composite substrate equipped with an epitaxial layer 16. Figure 10A is a cross-sectional image of void No. 1, Figure 10B is a cross-sectional image of void No. 2, and Figure 10C is a cross-sectional image of void No. 8. After growing the epitaxial layer 16 on the single crystal substrate 13, the substrate was cut so that the protrusions 30 appeared in the cross-section, and the cross-sectional images were taken.

[0043] In voids No. 1 and 2, where the protrusion height 31 exceeds 0.8 nm, stacking faults in the basal plane direction or dislocations in the C-axis direction were observed in the epitaxial layer 16 above the protrusion 30, and in some cases, multiple defects or dislocations were concentrated. In addition, depressions of C-axis dislocations were observed on the surface of the epitaxial layer 16 (Figures 10A and 10B).

[0044] On the other hand, in void No. 8, where the protrusion height 31 was less than 0.8 nm, no abnormalities were observed within the epitaxial layer 16 or on its surface (Figure 10C).

[0045] [Method for Manufacturing a Composite Substrate] Next, as an example of a method for manufacturing a composite substrate of the present invention, a method for manufacturing a semiconductor substrate 10 in which the support substrate 11, which is an example of a first semiconductor substrate, is a SiC polycrystalline substrate, and the single crystal substrate 13, which is an example of a second semiconductor substrate, is a 4H-SiC single crystal substrate will be described. Here, using the flow diagram shown in Figure 1, etc., a case in which the method for manufacturing a semiconductor substrate 10 is carried out using a technique for peeling off the single crystal substrate 13 by ablation of hydrogen atoms will be described.

[0046] The manufacturing method includes the following steps: activation of the bonding surface, bonding, peeling, polishing (2), and measurement. It may also include a determination step, dopant injection, epitaxial layer formation, heat treatment, and ion implantation.

[0047] <S1: Polishing Process (1)> First, the support substrate 11 and the transfer single crystal substrate 12 are prepared. Next, in the polishing process (1) shown in Figure 1, the support substrate 11 and the transfer single crystal substrate 12 are planarized using polishing processes such as cutting, grinding, LAP processing, and CMP (chemical mechanical polishing). As a guideline for the flatness required to join the support substrate 11 and the transfer single crystal substrate 12, it is desirable that the surface roughness (Sa) of both the joining surfaces 11a and 13a be 0.3 nm or less. However, this guideline is not limited, and depending on the joining method used in the subsequent joining process, the surface roughness may exceed 0.3 nm. Also, if materials with already planarized joining surfaces 11a and 13a are available, the polishing process (1) can be omitted, and the process can proceed directly to the next step.

[0048] <S2: Dopant Injection Process> In the dopant injection process shown in Figure 1, dopants are injected into the bonding surface 13a of the transfer single crystal substrate 12. One guideline for the dopant injection conditions is that the dopant concentration at a depth of 70 nm from the surface of the bonding surface 13a is 3.5 × 10⁻⁶. １９ atoms / cm ３ The dopant injection should be within a certain range. The acceleration voltage for dopant injection is 0.1 to 1000 kV, but it is desirable to adjust the acceleration voltage and injection amount so that the dopant concentration is maximized on the surface of the transfer single crystal substrate 12. Since the diffusion coefficient of phosphorus in SiC is very small, profile control by diffusion is difficult. Therefore, it is effective to use a combination of multiple injection conditions with different acceleration voltages and injection amounts so that the dopant concentration is maximized on the surface of the transfer single crystal substrate 12. Alternatively, the injection peak depth may be adjusted by forming a Si oxide film or the like before dopant injection so that the dopant concentration is maximized on the surface of the transfer single crystal substrate 12.

[0049] As the dopant, a trivalent element or a pentavalent element can be used. For example, at least any one of nitrogen (N), phosphorus (P), boron (B), and aluminum (Al) can be mentioned.

[0050] <S3: Hydrogen Ion Implantation Step> In the hydrogen ion implantation step of FIG. 1, hydrogen ions are implanted from the bonding target surface 13a of the transfer single crystal substrate 12. When hydrogen ions are implanted into the transfer single crystal substrate 12, the hydrogen ions reach a depth corresponding to the incident energy and are distributed at a high concentration. As a result, as shown in the side schematic view of FIG. 3, a hydrogen ion implantation layer 15 indicated by a dotted line is formed at a predetermined depth from the bonding target surface 13a. For example, the hydrogen ion implantation layer 15 is formed at a position about 0.6 μm deep from the bonding target surface 13a. More specifically, as the implantation conditions of hydrogen ions, for example, H ＋ ions may be implanted at 1×10 １７ atoms / cm ２ level.

[0051] Note that even if helium is ion-implanted instead of hydrogen, or hydrogen and helium are alternately ion-implanted, the same effect can be expected.

[0052] <S4: Bonding Target Surface Activation Step> In the bonding target surface activation step of FIG. 1, for example, an argon beam is irradiated onto the bonding target surface 11a and the bonding target surface 13a. The argon beam may be irradiated in the order of the bonding target surface 11a and the bonding target surface 13a.

[0053] Specifically, the transfer single crystal substrate 12 and the support substrate 11 are set in a vacuum chamber, and then the alignment of the relative positions of the transfer single crystal substrate 12 and the support substrate 11 is performed. The alignment is adjusted so that both substrates can be in the correct positional relationship and contact each other in the bonding step described later. The degree of vacuum in the chamber may be, for example, 1×10 －４ to 1×10 －６ Pa.

[0054] Next, a neutral argon beam is irradiated onto the bonding target surface 11a of the support substrate 11 and the bonding target surface 13a of the transfer single crystal substrate 12 using a fast atomic beam gun (FAB gun). The neutral argon beam is irradiated onto the entire surface of the bonding target surface 11a and the entire surface of the bonding target surface 13a. This removes the oxide film and adsorbed layer on the bonding target surface 11a and the bonding target surface 13a, exposing the bonding bonds. This state is called the activated state, and the process of removing the oxide film and adsorbed layer on the bonding target surface 13a to expose the bonding bonds is called the bonding target surface activation process. Furthermore, since the irradiation process, which is an example of the bonding target surface activation process, is performed in a vacuum, the bonding target surface 11a and the bonding target surface 13a can maintain their activated state without oxidation or other damage.

[0055] Alternatively, instead of the activation treatment using a neutral element beam of argon, an irradiation process using atomic-level particles or ions can be employed. Examples of irradiated particles include at least one of atoms, molecules, and ions, which can be irradiated as a beam. More specifically, examples include atoms, molecules, or ions of elements such as He, hydrogen, argon, Si, and C, and mixtures thereof may also be used.

[0056] Generally, in irradiation devices, the amount of irradiation particles or ions can be controlled by controlling the acceleration voltage, current value, and irradiation time of atoms, molecules, or ions.

[0057] Alternatively, instead of the irradiation process described above, a process in which surface contaminants are chemically reacted with a reactive gas and removed by etching can be used as a bonding surface activation process. Furthermore, if the adsorbent is easily sublimated, a sublimation process using heat or light can be employed to remove the adsorbent by sublimation. These processes allow for the removal of oxide films and adsorbent layers from the bonding surface, exposing the bonding bonds.

[0058] <S5: Bonding Process> Next, the activated bonding surfaces are bonded. Following the bonding surface activation process, the bonding surface 11a of the support substrate 11 and the bonding surface 13a of the transfer single crystal substrate 12 are brought into contact in a chamber under vacuum. As a result, the bonding bonds present on the activated bonding surfaces 11a and 13a connect with each other, and as shown in the schematic side view of Figure 4, the support substrate 11 and the transfer single crystal substrate 12 are bonded together to form a bonded semiconductor substrate 14.

[0059] <S6: Peeling Process> This process, which takes place after the bonding process and before the heat treatment process, involves applying heat to the substrate to form a microbubble layer in the hydrogen ion implantation layer 15, and using this microbubble layer as the peeling surface to peel off the transfer single crystal substrate 12. That is, using the hydrogen ion implantation layer 15 on the transfer single crystal substrate 12 where the microbubble layer is formed as the peeling surface, a portion of the transfer single crystal substrate 12 is peeled off as a single crystal substrate 13 and transferred to the bonding target surface 11a of the support substrate 11.

[0060] In the peeling process shown in Figure 1, specifically, the bonded support substrate 11 and the transfer single crystal substrate 12 are heated to approximately 800°C or higher. The peeling atmosphere may be at least one of the following: a gas such as argon or nitrogen, or a vacuum. Peeling may be performed using rapid thermal annealing (RTA) or a furnace. For example, in the case of RTA, heating may be performed at approximately 500°C to 700°C. Similarly, in the case of a furnace, heating may be performed at approximately 500 to 700°C. The peeling atmosphere may be at least one of the following: a gas such as argon or nitrogen, or a vacuum. This allows the transfer single crystal substrate 12 to be separated in the hydrogen ion implantation layer 15. Thus, as shown in the schematic side view of Figure 5, a semiconductor substrate 10 can be formed in which a thin single crystal substrate 13, for example, with a thickness of 0.6 μm, is bonded to the support substrate 11.

[0061] <S7: Heat Treatment Process> This process involves heat treatment of the semiconductor substrate 10, and electrically activates the phosphorus injected into the bonding surface 13a of the single crystal substrate 13 in the phosphorus implantation process. This process is extremely important when the semiconductor substrate 10 is used as a substrate for power devices, as it can reduce the electrical resistance of the bonding interface to the absolute minimum.

[0062] In the heat treatment process shown in Figure 1, the semiconductor substrate 10 formed in the peeling process is heat-treated. The heat treatment temperature may be set to 1100°C to 2200°C (preferably around 1700°C). The atmosphere in the heat treatment process may be at least one of the following: argon, nitrogen, or other gases, or a vacuum. The heating method may be rapid thermal annealing (RTA) or a furnace. The heat treatment process may also be performed immediately following the peeling process in the same furnace where the peeling process was performed.

[0063] <S8: Polishing Process (2)> This process polishes the delamination surface of the thin single-crystal substrate 13 of the semiconductor substrate 10, forming a flat surface (called an epiready) on which epitaxial growth can be carried out in the subsequent epitaxial layer formation process. This process is extremely important in order to completely remove any damage to the substrate caused by phosphorus or hydrogen implantation remaining near the surface of the thin single-crystal substrate 13 of the semiconductor substrate 10, as well as the microbubble layer and its fractured layer generated in the delamination process.

[0064] In polishing step (2), the peeled surface of the thin single-crystal substrate 13 of the semiconductor substrate 10 is polished by CMP processing or the like. Since the single-crystal substrate 13 has a thickness of, for example, 0.6 μm, it is desirable to remove about 0.2 μm in order to completely remove substrate damage caused by phosphorus implantation or hydrogen implantation, and the microbubble layer and its fractured layer generated in the peeling process. One or more of grinding, LAP, and CMP may be used as the polishing method.

[0065] <S9: Measurement process, S10: Judgment process> The measurement process measures the height 31 of the protrusions on the peeled surface of the thin single-crystal substrate 13 of the semiconductor substrate 10 in the polishing process (2). In the manufacturing process of the semiconductor substrate 10, voids 20 may be formed as shown in Figure 7 due to foreign matter adhering to the single-crystal substrate 13 before bonding the support substrate 11. In addition, the formation of the voids 20 causes protrusions 30 to be generated on the surface of the single-crystal substrate 13 directly above the voids 20. The measurement process may include detecting the position of the voids 20, confirming the presence or absence of protrusions 30 on the surface of the thin single-crystal substrate 13 of the bonded semiconductor substrate, and measuring the height 31 of the protrusions.

[0066] After the measurement process, the determination process determines the relationship between the maximum height of the protrusion, which is the protrusion height 31, and a predetermined value of 0.8 nm. For example, if the protrusion height 31 is less than 0.8 nm, the epitaxial layer formation process described later may be performed, and if the protrusion height 31 is not less than 0.8 nm, the epitaxial layer formation process may be canceled.

[0067] The position of the void 20 can be detected, for example, by a Lasertec SICA-88X defect inspection device. The absolute coordinates of each void can be detected as a result of this inspection. Next, according to the detected absolute coordinates of each void, the height of the protrusions on the surface of the thin single-crystal substrate 13 of the bonded semiconductor substrate can be measured, for example, by a ZYGO white light interferometer. The white light interferometer measures the shape of the surface (in this case, the height of the protrusions 31 on the surface of the thin single-crystal substrate 13 of the bonded semiconductor substrate) by analyzing the interference fringes (which occur when there is a difference in the distance of light from the surface of the object to a certain point) that are generated when reflected light from the object and reference light are superimposed.

[0068] <S11: Epitaxial Layer Formation Process> This process involves forming an epitaxial layer 16 on the surface of a thin single-crystal substrate 13 of the semiconductor substrate 10. This process allows for the formation of a 4H-SiC single-crystal layer with a low impurity concentration suitable for a desired power device while maintaining the crystal structure of the single-crystal substrate 13. For example, in SiC epitaxial growth, epitaxial defects such as surface defects caused by downfall and particles, stacking faults, basal plane dislocations, helical dislocations, and edge dislocations are known to occur, and these are highly related to device failure. Therefore, suppressing epitaxial defects is extremely important in this process.

[0069] In the epitaxial layer formation process shown in Figure 1, an epitaxial layer 16 is grown on the surface of a thin single-crystal substrate 13 of the semiconductor substrate 10, as shown in Figure 6. Evaluation indicators for the quality of the epitaxial layer include surface roughness, defect density, and n-type dopant density. Currently, epitaxial defects on the Si surface that are in practical use include surface-exposed defects such as stacking fault complexes (called Carrots), polytype inclusions (called Triangles and Comets), and particle inclusions (called Large Pits), as well as basal plane dislocations (BPDs) and stacking faults (SFs). However, from a device application perspective, the density of epitaxial defects is 1 defect / cm³. ２ The following is preferable. Furthermore, the n-type dopant density is within the range of doping densities typically used in device applications, for example, when the nitrogen concentration is 9 × 10⁻⁶. １５ cm －３ from 1.1 × 10 １６ cm －３　 The degree of this is desirable. The surface roughness of the epitaxial layer is important to prevent pattern defects when the device is miniaturized, and it is preferable that the surface roughness Sa in a 1.5 mm x 1.5 mm area is 0.3 nm or less, preferably 0.2 nm or less. Furthermore, considering the voltage withstand capability of the device, the film thickness of the epitaxial layer should be about 10 μm if a reverse voltage withstand capability of 1200 V is to be achieved.

[0070] The composite substrate of the present invention can be manufactured by the method described above with reference to Figure 1.

[0071] [Effect] In the present invention, in a semiconductor substrate in which an epitaxial layer is formed on a semiconductor substrate consisting of two or more substrates bonded together, it is possible to prevent the occurrence of epitaxial defects caused by voids at the bonding interface.

[0072] [Semiconductor Devices] Examples of semiconductor devices of the present invention include semiconductor devices using the composite substrate of the present invention, which may be semiconductor devices that have circuit patterns as components of the semiconductor element and drain electrodes as back electrodes, or they may be semiconductor devices that have been diced into a chip shape.

[0073] <Modifications> Although one embodiment of the present invention has been described in detail above, these are merely illustrative examples and do not limit the scope of the present invention. For example, as will be described below, the present invention includes various modifications and changes to the specific examples illustrated above.

[0074] In the above manufacturing method, the case described is where the support substrate 11, which is an example of a first semiconductor substrate, is a SiC polycrystalline material, and the single-crystal substrate 13, which is an example of a second semiconductor substrate, is a SiC single crystal. These elements are semiconductor materials that can be used for the fabrication of semiconductor devices.

[0075] To prevent delamination of the joint due to thermal expansion and warping of the semiconductor substrate during high-temperature heat treatment, it is most desirable that the first and second semiconductor substrates be made of the same material, but they are not limited to the same material. An example of the second semiconductor substrate is a single crystal substrate 13, which can be made of silicon (Si), gallium nitride (GaN), gallium oxide (Ga) ２ O ３ It may be either (C) or a diamond.

[0076] These elements are semiconductor materials that can be used to fabricate semiconductor devices, and the channel mobility of SiC is 2-3 cm. ２ Compared to around / Vs, for example, silicon (Si) has a channel mobility of 200-500 cm². ２Because it is high, around / Vs, it has the advantage of allowing the on-resistance of the MOSFET to be low. Also, gallium nitride (GaN) has an electron transfer rate of, for example, about 50,000 cm⁻¹. ２ Because the voltage / Vs is very high, it has the advantage of allowing for a low on-resistance of HEMTs (High Electron Mobility Transistors).

[0077] Gallium oxide (Ga ２ O ３ ) is, for example, the Ga of the β phase ２ O ３ The breakdown field strength is estimated to be approximately 8 MV / cm, which is more than 20 times that of silicon (Si) and more than twice that of SiC and gallium nitride (GaN). This offers the advantage of being able to manufacture MOSFETs with high voltage resistance and low on-resistance.

[0078] Diamond (C) has an even higher fracture field strength (10 ７ V / cm) and high channel mobility (1600 cm) ２ Because it can satisfy both (Vs), it is the most suitable semiconductor material for power devices.

[0079] Furthermore, SiC polycrystalline material, which can be used as a support substrate 11, an example of a first semiconductor substrate, has a thermal conductivity of 300 W / mK or higher, which is the second highest after diamond (C) at 2200 W / mK. In addition, its low manufacturing cost makes it the most effective support substrate 11 for the semiconductor substrate 10.

[0080] Furthermore, in the epitaxial layer formation process, if the single crystal substrate 13 is a Si substrate, the epitaxial layer can be grown on the surface of the Si substrate. Since silicon (Si) epitaxial technology is already highly advanced, the quality evaluation indicators for the epitaxial layer are surface roughness Sa and n-type dopant density. For example, for a 1200V withstand voltage power device, the n-type dopant density is such that the nitrogen concentration is 2 × 10⁻⁶. １３ cm －３ ~5 x 10 １５ cm －３It is desirable that the surface roughness of the epitaxial film is important to prevent pattern defects when the device is miniaturized, and it is required that the surface roughness Sa in a 1.5 mm × 1.5 mm area be 0.3 nm or less, preferably 0.2 nm or less.

[0081] [Summary] Based on the above, the present invention provides a composite substrate, a method for manufacturing a composite substrate, and a device that can suppress the occurrence of epitaxial defects caused by voids present at the bonding interface of semiconductor substrates obtained by bonding, and as a result, is expected to improve device yield, and is therefore industrially useful.

[0082] 10: Semiconductor substrate, 11: Support substrate, 11a: Bonding surface, 12: Transfer single crystal substrate, 13: Single crystal substrate, 13a: Bonding surface, 14: Bonded semiconductor substrate, 15: Hydrogen ion implantation layer, 16: Epitaxial layer, 20: Void, 21: Void height, 30: Protrusion, 31: Protrusion height, TT1: Thickness of support substrate

Claims

1. A method for manufacturing a composite substrate comprising a first semiconductor substrate and a second semiconductor substrate, comprising: a bonding target surface activation step of activating a first bonding target surface on a first semiconductor substrate and a second bonding target surface on a second semiconductor substrate transfer substrate; a bonding step of bonding the first bonding target surface and the second bonding target surface after the bonding target surface activation step to form a bonded semiconductor substrate; a peeling step of peeling off a portion of the second semiconductor substrate transfer substrate after the bonding step to obtain a composite substrate in which the portion of the second semiconductor substrate transfer substrate is transferred to the first semiconductor substrate as a second semiconductor substrate; a polishing step of polishing the peeled surface of the second semiconductor substrate; and a measurement step of measuring the height of the protrusions present on the polished peeled surface after the polishing step.

2. The method for manufacturing a composite substrate according to claim 1, further comprising a determination step for determining the relationship between the maximum height of the protrusion measured in the measurement step and a specified value.

3. The method for manufacturing a composite substrate according to claim 2, comprising an epitaxial layer formation step of forming an epitaxial layer on the peeled surface after the determination step.

4. A method for manufacturing a composite substrate according to claim 1, comprising a heat treatment step of heat treating the composite substrate after the peeling step.

5. A method for manufacturing a composite substrate according to claim 1, comprising: a dopant implantation step of implanting a dopant into the second bonding target surface of the second semiconductor substrate transfer substrate used in the bonding target surface activation step; and an ion implantation step of implanting hydrogen ions or helium ions into the second bonding target surface of the second semiconductor substrate transfer substrate used in the bonding target surface activation step.

6. The method for manufacturing a composite substrate according to claim 1, wherein the first semiconductor substrate is a SiC polycrystalline substrate and the second semiconductor substrate is a SiC single crystal substrate.

7. The first semiconductor substrate is a SiC polycrystalline substrate, and the second semiconductor substrate is silicon (Si), gallium nitride (GaN), gallium oxide (Ga ２ O ３ A method for manufacturing a composite substrate according to claim 1, wherein the composite substrate is one of (C) or diamond (C).

8. A composite substrate comprising a first semiconductor substrate and a second semiconductor substrate laminated on the first semiconductor substrate, wherein a protrusion exists on the surface of the second semiconductor substrate, and the protrusion has a maximum height of less than 0.8 nm.

9. The composite substrate according to claim 8, wherein the first semiconductor substrate is a SiC polycrystalline substrate, the second semiconductor substrate is a SiC single crystal substrate, and the convex portion has a hemispherical shape in which compressive stress is generated in the central part and tensile stress is generated in the outer periphery.

10. A device comprising the composite substrate described in claim 9.

Images