Amplifier circuit, signal processing device, and common mode feedback method

Abstract

The present invention achieves a technology that makes it possible to independently adjust loop gains of a low-frequency path and a high-frequency path of a CMFB circuit, and that improves ease of design.　This technology provides an amplifier circuit comprising: a fully differential amplifier that amplifies a differential signal; and a common mode feedback (CMFB) circuit that stabilizes an output common mode voltage of the fully differential amplifier. The CMFB circuit has a low-frequency path that generates a first feedback signal, and a high-frequency path that generates a second feedback signal. The fully differential amplifier has a differential input transistor pair, and a tail current source that is connected to a common source of the differential input transistor pair. The tail current source is divided into a first current source and a second current source. The low-frequency path supplies the first feedback signal to the first current source and the second current source. The high-frequency path supplies the second feedback signal to the second current source.

Description

Amplifier circuit, signal processing device, and common-mode feedback method

[0001] The technologies disclosed herein (hereinafter also referred to as "the Technologies") relate to amplification circuits, signal processing devices, and common-mode feedback methods.

[0002] Fully differential amplifiers play a crucial role in high-precision analog signal processing and are used in a variety of applications. In fully differential amplifiers, stabilizing the common-mode voltage of the output signal to a desired value is essential, and for this purpose, a common-mode feedback (CMFB) circuit is used. (See Patent Documents 1-3)

[0003] While CMFB circuits generally have one feedback path, a multipath CMFB circuit with two feedback paths has been proposed, where each feedback path operates at a different timing. By designing one feedback path to be highly accurate but slow, and the other to be less accurate but fast, they complement each other, resulting in high-performance common-mode feedback overall.

[0004] Japanese Patent Publication No. 2003-198290, Japanese Patent Publication No. 2006-279377, Japanese Patent Publication No. 2008-067050

[0005] In conventional multipath CMFB circuits with two feedback paths, the low-frequency and high-frequency paths share some paths. Therefore, adjusting the loop gain of one path affects the loop gain of the other path. For example, if you try to reduce the loop gain to ensure a phase margin in the high-frequency path of the CMFB, the main pole frequency of the low-frequency path of the CMFB decreases, resulting in a trade-off where convergence becomes slower.

[0006] In this technical field, there is a demand for higher-performance CMF circuits to stabilize the output common-mode voltage of fully differential amplifiers. In particular, there is a need to improve design flexibility and achieve more stable operation by making the loop gains of the low-frequency and high-frequency paths of the CMF circuit independently adjustable.

[0007] Therefore, the primary objective of this technology is to provide a technique that improves ease of design by enabling independent adjustment of the loop gains of the low-frequency path and high-frequency path of a CMFB circuit.

[0008] This technology provides an amplification circuit comprising: a fully differential amplifier for amplifying differential signals; and a common-mode feedback (CMFB) circuit for stabilizing the common-mode output voltage of the fully differential amplifier, wherein the CMFB circuit has a low-frequency path for generating a first feedback signal and a high-frequency path for generating a second feedback signal; the fully differential amplifier has a differential input transistor pair and a tail current source connected to a common source of the differential input transistor pair, the tail current source is divided into a first current source and a second current source, the low-frequency path supplies the first feedback signal to the first current source and the second current source, and the high-frequency path supplies the second feedback signal to the second current source. The current ratio between the first current source and the second current source may be α:1-α (where 0 < α < 1). The low-frequency path includes a first capacitor, a second capacitor, a plurality of first switches, a second switch, and an amplification circuit, the amplification circuit amplifies the difference between the output common-mode voltage of the fully differential amplifier and a reference voltage to generate a first voltage, the first capacitor holds the first voltage, the plurality of first switches are connected between the first capacitor and the second capacitor, and between the first capacitor and the first current source, the second switch is connected between the first capacitor and the amplification circuit, the first and second switches are switched on and off complementaryly, the second capacitor supplies a second voltage generated by sharing charge with the first capacitor when the first switch is on to the first current source as a first feedback signal, and may also be connected to the second current source. The high-frequency path may be connected to the second current source via a capacitor between the differential outputs of the fully differential amplifier to generate the second feedback signal. The fully differential amplifier may be a ring amplifier. The fully differential amplifier may be a self-biased ring amplifier or a critically damped ring amplifier. The fully differential amplifier may have a Class AB output stage.Furthermore, this technology provides an integrated circuit comprising: an amplification circuit; and an analog-to-digital converter that outputs a digital signal based on the output signal of the amplification circuit. The amplification circuit may be used in an analog front-end circuit. The amplification circuit may be used in a pipeline ADC. The amplification circuit may be used in a ΔΣ ADC. Furthermore, this technology provides a signal processing device comprising the amplification circuit. The signal processing device may be used in audio equipment that processes audio signals. The signal processing device may be used in IoT equipment that processes sensor signals. The signal processing device may be used in LiDAR equipment that processes LiDAR received signals. Furthermore, this technology provides a common-mode feedback method for stabilizing the output common-mode voltage of a fully differential amplifier, comprising: generating a first feedback signal corresponding to the output common-mode voltage of the fully differential amplifier via a low-frequency path; generating a second feedback signal corresponding to the output common-mode voltage of the fully differential amplifier via a high-frequency path; dividing the tail current source of the fully differential amplifier into a first current source and a second current source; supplying the first feedback signal to the first current source and the second current source; and supplying the second feedback signal to the second current source. The current ratio between the first current source and the second current source may be α:1-α (where 0<α<1).Generating the first feedback signal includes: generating a first voltage by amplifying the difference between the output common-mode voltage of the fully differential amplifier and a reference voltage using an amplification circuit; holding the first voltage in a first capacitor; and sharing charge between the first capacitor and the second capacitor using a plurality of first and second switches, wherein the plurality of first switches are connected between the first capacitor and the second capacitor, and between the first capacitor and the first current source, respectively; the second switch is connected between the first capacitor and the amplification circuit; the first and second switches are switched on and off complementaryly; the second capacitor supplies the second voltage generated by sharing charge with the first capacitor when the first switch is on as the first feedback signal to the first current source, and may also be connected to the second current source. Generating the second feedback signal may include feeding it back to the second current source via the capacitor between the differential outputs of the fully differential amplifier.

[0009] This is a circuit diagram showing an example configuration of an amplifier circuit according to one embodiment of this technology. This is a circuit diagram showing an example configuration of an amplifier circuit according to one embodiment of this technology. This is a circuit diagram showing an example configuration of an amplifier circuit according to one embodiment of this technology. This is a circuit diagram showing an example configuration of an amplifier circuit according to one embodiment of this technology. This is a circuit diagram showing an example configuration of an amplifier circuit according to one embodiment of this technology. This is a graph comparing the open-loop frequency characteristics (Bode plot) of the CMFB high-frequency path in a comparative example and in this technology. This is a block diagram showing an example configuration of an integrated circuit according to one embodiment of this technology. This is a schematic diagram showing an example application of an amplifier circuit according to one embodiment of this technology. This is a flowchart showing an example of the CMFB method of this technology. This is a flowchart showing an example of the CMFB method of this technology. This is a circuit diagram showing an example configuration of an amplifier circuit according to a comparative example of this technology. This is a circuit diagram showing an example configuration of an amplifier circuit according to a comparative example of this technology. This is a circuit diagram showing an example configuration of an amplifier circuit according to a comparative example of this technology. This is a circuit diagram showing an example configuration of an amplifier circuit according to a comparative example of this technology. This is a circuit diagram showing the switching operation of a fully differential amplifier and a CMFB circuit. This is a circuit diagram showing the switching operation of a fully differential amplifier and a CMFB circuit. This is a timing chart showing the operating timing of each part in a fully differential amplifier.

[0010] Hereinafter, preferred embodiments for implementing this technology will be described with reference to the drawings. The embodiments described below are merely examples of typical embodiments of this technology and do not limit the scope of this technology. Furthermore, this technology can be implemented by combining any of the following embodiments and their modifications.

[0011] In the following description of embodiments, configurations may be described using terms with "approximately" attached, such as "approximately parallel" and "approximately orthogonal." For example, "approximately parallel" means not only that they are perfectly parallel, but also that they are substantially parallel, that is, that is, they are deviated from a perfectly parallel state by, for example, a few percent. The same applies to other terms with "approximately." Also, each figure is a schematic diagram and is not necessarily a strictly accurate representation. The scale of the drawings is exaggerated to make the technical features easier to understand. Therefore, it should be noted that the scale of the drawings and the scale of the actual device are not necessarily the same.

[0012] Unless otherwise specified, in drawings, "up" means the upper direction or upper side in the drawing, "down" means the lower direction or lower side in the drawing, "left" means the left direction or left side in the drawing, and "right" means the right direction or right side in the drawing. In addition, in drawings, the same or equivalent elements or components are denoted by the same reference numeral, and redundant explanations are omitted.

[0013] The explanation will proceed in the following order: 1. First Embodiment of the Technology (Example 1 of Amplifier Circuit) (1) Overall Configuration of the Comparative Example (2) Fully Differential Amplifier (3) CMFB Circuit (4) Operation Overview (5) Switching Operation (5-1) Input Signal Track (5-2) Short to Common Mode Voltage and Auto Zero (5-3) Charge Share (5-4) Amplification of Input Signal (5-5) Low Frequency Path (5-6) High Frequency Path (5-7) Timing Chart (6) Problems (7) Operation of the Low Frequency Path (8) Operation of the High Frequency Path (9) Overall Configuration of this Embodiment (10) Fully Differential Amplifier (11) Low Frequency Path (12) High Frequency Path 2. Second Embodiment of the Technology (Example 2 of Amplifier Circuit) 3. Third Embodiment of the Technology (Example 3 of Amplifier Circuit) (1) Integrated Circuit (2) Analog Front-End Circuit (3) Pipelined ADC (4) ΔΣ ADC (5) Effects 4. Fourth embodiment of this technology (example of a signal processing device) (1) Signal processing device (2) Audio equipment (3) IoT equipment (4) LiDAR device 5. Fifth embodiment of this technology (example of a common-mode feedback method) (1) Overall flow (2) Generation of the first feedback signal (3) Generation of the second feedback signal

[0014] [1. First Embodiment of the Technology (Example 1 of Amplifier Circuit)] [(1) Overall Configuration of Comparative Example] A comparative example of the Technology will be described with reference to Figures 12 to 14. Figures 12 to 14 are circuit diagrams showing an example configuration of an amplifier circuit related to a comparative example of the Technology.

[0015] As shown in Figure 12, the amplification circuit comprises a fully differential amplifier 1 that amplifies the differential signal, and a common-mode feedback (CMFB) circuit 2 that stabilizes the common-mode voltage of the output of the fully differential amplifier 1.

[0016] [(2) Fully Differential Amplifier] The fully differential amplifier 1 is, for example, a cascade amplifier circuit consisting of three amplification stages 11, 12, and 13. Each amplification stage has an inverter configuration using PMOS transistors and NMOS transistors.

[0017] The first amplification stage 11 consists of a pair of differential input transistors 1b that receive input signals IP and IN, and a single tail current source 1a that supplies current to them. The feedback signal from the CMFB circuit 2 is supplied to this tail current source 1a.

[0018] The second amplification stage 12 consists of a differential pair of transistors that receive the output of the first amplification stage 11, an analog switch (Φ2) that controls the power supply and GND connection to them, and resistors for adjusting the operating point and stability of the amplification stage 13.

[0019] The third amplification stage 13 consists of a differential pair of transistors that receive the output of the second amplification stage 12, and an analog switch (Φ2) that controls the power supply and GND connections to them. The output of the third amplification stage 13 becomes the differential output OP, ON of the fully differential amplifier 1.

[0020] The differential outputs OP and ON each have a load capacitance C. Ｌ It is connected. Typically, the load capacity C Ｌ Since this capacitance is larger than the parasitic capacitance of the other nodes of the fully differential amplifier 1, pole p3 of the output node of this third amplification stage 13 becomes the primary pole.

[0021] [(3) CMFB Circuit] The CMFB circuit 2 detects the output common-mode voltage of the fully differential amplifier 1 and uses it as a reference voltage V ＣＭ The output common-mode voltage is stabilized by applying feedback to bring it closer to the target value. This CMFB circuit 2 has two paths: a low-frequency path that generates the first feedback signal and a high-frequency path that generates the second feedback signal.

[0022] As shown in FIG. 13, the low-pass filter (the shaded part in the CMFB circuit 2) in the CMFB circuit 2 includes a first capacitor C ＳＭＡＬＬ , a second capacitor C ＢＩＧ , a plurality of first switches Φ1 (Φ1a), a second switch Φ2, and an amplifier circuit 2a.

[0023] The amplifier circuit 2a amplifies the difference between the output common-mode voltage of the fully differential amplifier 1 and the reference voltage V ＣＭ to generate a first voltage. In this configuration, the amplifier circuit 2a is a two-stage ring amplifier.

[0024] The capacitor C ＳＥＮＳＥは、 is a capacitor for dividing the output common-mode voltage.

[0025] The first capacitor C ＳＭＡＬＬ and the second capacitor C ＢＩＧ are capacitors for charge accumulation and redistribution. The first capacitor C ＳＭＡＬＬ holds the first voltage generated by the amplifier circuit 2a.

[0026] The first switch Φ1 (Φ1a) and the second switch control the movement of charges between the first capacitor C ＳＭＡＬＬ and the second capacitor C ＢＩＧ and the input to the amplifier circuit 2a. The first switch Φ1 (Φ1a) and the second switch Φ2 turn on and off complementarily. When the first switch Φ(Φ1a) is on, the voltage generated by sharing charges between C ＳＭＡＬＬ and C ＢＩＧ becomes the first feedback signal.

[0027] On the other hand, as shown in FIG. 14, the high-pass filter (the shaded part in the CMFB circuit 2) in the CMFB circuit 2 includes a capacitor C ＦＢ and a capacitor C Ｐ . The high-pass filter is connected to the tail current source of the first amplification stage 11 through the capacitors C ＦＢ and C Ｐ between the differential outputs of the fully differential amplifier, and generates a second feedback signal.

[0028] [(4) Operation Overview] First, the period during which the first switch Φ1 (Φ1a) is ON will be explained. During this period, the differential output OP, ON of the fully differential amplifier 1 is the common mode voltage V ＣＭ It gets short-circuited.

[0029] Next, capacity C ＳＥＮＳＥ The output common-mode voltage, which has been divided by the voltage division, is applied to the input of the amplifier circuit 2a in the CMFB circuit 2, and auto-zero operation is performed.

[0030] Next, the first capacity C ＳＭＡＬＬ The charge that had been stored in the second capacitance C ＢＩＧ It is shared with the second capacity C ＢＩＧ The voltage (first feedback signal) is updated. This voltage is fed back to the tail current source of the first amplification stage 11 of the fully differential amplifier 1.

[0031] On the other hand, the CMFB high-frequency path has capacitance C ＦＢ The settings are reset, and no feedback is provided.

[0032] Next, we will explain the period during which the second switch Φ2 is ON. During this period, the fully differential amplifier 1 becomes active and amplifies the input signals IP and IN.

[0033] The low-frequency path within the CMFB circuit 2 is the first capacitance C ＳＭＡＬＬ This is connected to the output of the amplification circuit 2a, and the output common-mode voltage and V ＣＭ The charge (first voltage) corresponding to the difference is the first capacitance C. ＳＭＡＬＬ It is charged. The CMFB node enters a high impedance state, and capacitance C Ｐ The voltage from the previous day is retained.

[0034] The high-frequency path within the CMFB circuit 2 changes in capacitance C in response to fluctuations in the differential output (OP, ON) of the fully differential amplifier 1. ＦＢ A feedback signal (second feedback signal) is supplied to the CMFB node (tail current source of the first amplification stage 11) via this.

[0035] [(5) Switching Operation] The switching operation of the fully differential amplifier and the CMFB circuit will be explained further with reference to Figures 15 and 16. Figures 15 and 16 are circuit diagrams showing the switching operation of the fully differential amplifier and the CMFB circuit.

[0036] Input capacitance C of fully differential amplifier 1 １ This is the capacitance for sampling the input signal. The integral capacitance C of the fully differential amplifier 1. Ａ This is a capacitor connected between the output and inverting input of a fully differential amplifier, used to determine the amount of feedback.

[0037] The first switch Φ1 (Φ1a) and the second switch Φ2 of the CMFB circuit 2 operate complementaryly (when one is on, the other is off), and Φ1a turns off slightly earlier than Φ1.

[0038] Figure 15 shows the first switch Φ1 (Φ1a) in the ON state. In this state, the following three main operations are performed.

[0039] [(5-1) Input signal track] The first switch Φ1 (Φ1a) is turned on, and the input capacitance C １ This samples (tracks) the input signal.

[0040] [(5-2) Short to Common-Mode Voltage and Auto-Zero] The output of the fully differential amplifier enters a high-impedance (Hi-Z) state, and the differential outputs OP, ON are connected to the reference voltage V via the first switch Φ1. ＣＭ It gets short-circuited.

[0041] At the same time, capacity C ＳＥＮＳＥ Through this, the common-mode voltage output of the fully differential amplifier is applied to the input of the amplification circuit (two-stage ring amplifier) ​​within the CMFB circuit. At this time, the first amplification stage of the amplification circuit (two-stage ring amplifier) ​​performs auto-zero operation via the first switch Φ1, and the common-mode voltage V ＣＭ An operating point is set based on this.

[0042] [(5-3) Charge Share] In the previous second switch Φ2 on period (Amplify-phase), the first capacity C ＳＭＡＬＬThe charge that was stored in the first switch Φ1 is transferred to the second capacitor C ＢＩＧ This short-circuits the circuit, and the charge is redistributed. This creates a second capacitance C. ＢＩＧ The voltage (which becomes the first feedback signal) is updated.

[0043] This updated voltage is fed back to the tail current source of the fully differential amplifier (operating the low-frequency path in the CMFB circuit 2).

[0044] On the other hand, the high-frequency path within the CMFB circuit 2 is capacitance C. ＦＢ The settings are reset, and no feedback is provided.

[0045] Figure 16 shows the second switch Φ2 in the ON state. In this state, the following operations are mainly performed.

[0046] [(5-4) Amplification of the input signal] The fully differential amplifier and the two-stage ring amplifier in the CMFB circuit become active. Input capacitance C １ The input signal charge that was sampled is the integral capacitance C Ａ Voltage amplification occurs through charge transfer.

[0047] [(5-5) Low-frequency path] The CMFB node enters a high-impedance state, and capacitance C Ｐ This ensures that the voltage after charge sharing (the voltage associated with the first feedback signal) is maintained during the period when the first switch Φ1 is ON.

[0048] The common-mode output voltage of a fully differential amplifier in amplification phase is the capacitance C. ＳＥＮＳＥ The voltage is divided and input to the amplification circuit (two-stage ring amplifier) ​​within the CMFB circuit. This input voltage and the reference input voltage V at auto-zero during the ON period of the first switch Φ1 are used. ＣＭ The difference between this and the first capacitance (C) is amplified by the amplification circuit (two-stage ring amplifier). ＳＭＡＬＬ A charge is accumulated (the first voltage is generated and held).

[0049] [(5-6) High-Frequency Path] Capacitance C in response to voltage fluctuations between the differential outputs OP and ON of a fully differential amplifier. ＦＢA feedback signal (second feedback signal) is supplied to the CMFB node (input to the tail current source) via this (high frequency path is activated).

[0050] The main pole of the low-frequency path is the first capacitance C ＳＭＡＬＬ and the second capacity C ＢＩＧ This is determined by the capacitance ratio. Since this main pole can be adjusted independently of the differential characteristics (frequency characteristics of the differential signal) of a fully differential amplifier, the stabilization design of the CMFB circuit is easy.

[0051] [(5-7) Timing Chart] The operation of each switch is summarized with reference to Figure 17. Figure 17 is a timing chart showing the operating timing of each part in a fully differential amplifier. This figure shows the operation of the fully differential amplifier and the CMFB circuit in relation to the control clock signals Φ1 (Φ1a), Φ2 and the operating state of each part.

[0052] Φ1 is a clock signal that controls the first switch Φ1, and is primarily used to control input signal sampling, charge sharing in the CMFB low-frequency path, and auto-zero operation.

[0053] Φ1a is a clock signal that operates at almost the same timing as Φ1, but turns off slightly earlier than Φ1. As will be described later, this is used to reduce the effects of charge injection and improve sampling accuracy.

[0054] Φ2 is a clock signal that controls the second switch Φ2, and is primarily used to control the amplification operation of the fully differential amplifier and the operation of the CMFB high-frequency path. Φ1 and Φ2 operate complementaryly to each other (non-overlapping clocks). That is, when Φ1 (Φ1a) is on, Φ2 is off, and when Φ1 (Φ1a) is off, Φ2 is on.

[0055] Sampling capacity C １ Regarding switching, in the phase when Φ1 (Φ1a) is ON, the input capacitance C １ This samples the input signal (Sample). In the phase when Φ1 (Φ1a) is off, the input capacitance C １The input signal is held, and the charge is integrated into capacitance C. Ａ Transferred to (charge transfer (C) １ →CC Ａ )).

[0056] integral capacity C Ａ Regarding switching, during the phase when Φ1 (Φ1a) is ON, the integrated capacitance C Ａ Both ends are short-circuited, and the charge is reset (C Ａ Charge reset). In the phase when Φ2 is ON, the integral capacitance C Ａ This activates the fully differential amplifier, causing it to perform amplification (feedback path SW ON).

[0057] Regarding output node switching, in the phase when Φ1 (Φ1a) is ON, the output OP, ON of the fully differential amplifier is the common mode voltage V ＣＭ Shorted to (V ＣＭ (Short circuit). When Φ2 is ON, the output of the fully differential amplifier outputs an amplified signal (output path ON).

[0058] For Self-Bias Ringamp, in the phase when Φ1 (Φ1a) is ON, the output of the third amplification stage 1c becomes high impedance (3rd Stage Hi-Z output). In the phase when Φ2 is ON, amplification operation is performed (Amplify).

[0059] In the two-stage Ringamp configuration within the CMFB circuit, when Φ1 (Φ1a) is ON, it performs auto-zero operation. When Φ2 is ON, it performs amplification operation.

[0060] For the CMFB low-frequency path, in the phase when Φ1 (Φ1a) is ON, the first capacitance C in the previous cycle ＳＭＡＬＬ The charge stored in the second capacitance C ＢＩＧ Shared with (Charge Share (C ＢＩＧ and C ＳＭＡＬＬ )). In the phase when Φ2 is ON, the first capacitance C ＳＭＡＬＬ This is connected to the output of a two-stage Ringamp, and the output common-mode voltage and V ＣＭ A charge is accumulated according to the difference between (CＳＭＡＬＬ Charging (CMFB node voltage is held).

[0061] For the CMFB high-frequency path, in the phase when Φ1 (Φ1a) is ON, capacitance C ＦＢ It is reset (C ＦＢ (Reset). In the phase where Φ2 is ON, the CMFB high-frequency path becomes active (CMFB high-frequency path active).

[0062] Φ1a is designed to turn off slightly earlier than Φ1. This is to reduce the effects of charge injection during switching and improve sampling accuracy.

[0063] When the switch is turned off, the charge accumulated in the channel region is released to the source and drain sides. This phenomenon is called charge injection and causes errors in the sampled voltage.

[0064] Φ1a turns off first, causing input capacitance C1 and capacitance C ＳＥＮＳＥ V ＣＭ The side switch turns off first, fixing the amount of charge held in these capacitances. V ＣＭ Since the voltage is constant, the amount of charge shift due to charge injection that occurs when these switches are turned off is also constant.

[0065] In particular, since the input capacitance C1 has a differential configuration, the difference in charge injected into the two capacitances (C1) becomes an in-phase component, and the offset due to charge injection is canceled out. As a result, the impact on sampling accuracy is minimized.

[0066] If Φ1 turns off before Φ1a, the node connected to Φ1 (the input side of C1, C ＳＥＮＳＥ Charge injection occurs depending on the voltage at the output side (Ringamp output). This introduces a signal level-dependent error into the sampled voltage, distorting the signal's frequency characteristics.

[0067] Note that in this diagram, the duty cycles of Φ1 and Φ2 are shown as 50:50, but this is merely an example. Depending on the application and circuit constants (especially the time constant of the CMFB circuit), this duty cycle may be changed from 50:50. For example, by increasing the on-period of Φ2, the amplification time of the fully differential amplifier and the settling time of the CMFB can be increased. Conversely, by increasing the on-period of Φ1, the sampling time of the input signal can be increased. The optimal duty cycle is determined by considering the balance of the required performance (speed, accuracy, power consumption, etc.).

[0068] [(6) Problems] In this comparative example configuration, both the low-frequency path and the high-frequency path in the CMFB circuit are connected to the tail current source of the first amplification stage of the fully differential amplifier. Therefore, attempting to adjust the loop gain of one path will also affect the loop gain of the other path.

[0069] Specifically, in order to ensure the stability of the high-frequency path, it is necessary to set its loop gain appropriately. However, in order to adjust the loop gain of the high-frequency path, capacitance C is required. ＦＢ or capacity C Ｐ Changing this value will also change the loop gain of the low-frequency path.

[0070] Furthermore, since the output node (OP, ON) of the third amplification stage of the fully differential amplifier forms the main pole p3, the main pole of the high-frequency path within the CMFB circuit is dominated by this p3. Normally, to prioritize the differential characteristics (frequency characteristics of the differential signal) of the fully differential amplifier, p3 cannot be freely adjusted solely for the convenience of the high-frequency path within the CMFB circuit.

[0071] Thus, because the low-frequency and high-frequency paths within the CMFB circuit influence each other, and there are also constraints on the main pole p3, it is extremely difficult to ensure the stability of the CMFB circuit in the comparative example.

[0072] [(7) Operation of the Low-Frequency Path] Here, the operation of the low-frequency path of the CMFB circuit will be explained in detail using mathematical formulas. Specifically, the output voltage V of the CMFB circuit ＣＭＦＢis how it changes according to the time variation of the output common-mode voltage V ＣＯＭ and clarifies how the output common-mode voltage V ＣＯＭ converges to the reference voltage V ＣＭ .

[0073] First, a difference equation is established based on the charge conservation law in each phase and solved to derive V ＣＭＦＢ .

[0074] In the phase when the first switch Φ1 is on, sampling of the input signal, auto-zero operation of the amplifier circuit (two-stage ring amplifier), and charge sharing between the first capacitor C ＳＭＡＬＬ and the second capacitor C ＢＩＧ are performed. The total charge Q ＢＩＧ of the CMFB node (top plate side node of the second capacitor C ＣＭＦＢ，Φ１ at this time is expressed by Equation (1).

[0075]

[0076] Here, V ＣＭＦＢ [n] is the voltage of the CMFB node in the phase when the first switch Φ1 is on in the nth cycle. V ＣＭ is the common-mode reference voltage. C ＳＭＡＬＬ , C ＢＩＧ , C<​​​​​​​​​​​​​​​​​​​​​​​​​​[n + 0.5] and V ＯＮ [n + 0.5] is the differential output voltage of the fully differential amplifier in the (n + 0.5)-th cycle (phase when the second switch Φ2 is on). A ２ is the gain of the amplifier circuit (two-stage ring amplifier) in the CMFB circuit.

[0081] The second capacitor C ＢＩＧ The charge Q stored in ＢＩＧ，Φ２ is expressed by Equation (3).

[0082]

[0083] Here, V ＢＩＧ is the voltage across C ＢＩＧ Since the charge in the phase when the first switch Φ1 is on is held, V ＢＩＧ = V ＣＭＦＢ [n].

[0084] The total charge Q ＦＢ with respect to the capacitance of the CMFB node (C Ｐ , C ＣＭＦＢ，Φ２ is expressed by Equation (4) because the charge in the phase when the first switch Φ1 is on is held.

[0085]

[0086] In the state transition from the phase when the first switch Φ1 is on to the phase when the second switch Φ2 is on, the charge is conserved, so the following Equation (5) holds.

[0087]

[0088] Substituting Equations (1) to (4) into Equation (5) and solving for V ＣＭＦＢ [n], Equation (6) is obtained.

[0089]

[0090] Or, when expressed using z-transform, Equation (7) is obtained.

[0091]

[0092] Here, (V ＯＰ [n - 0.5] + V ＯＮ[n-0.5]) / 2 is the output common-mode voltage of the fully differential amplifier at the n-0.5th cycle, and this is V ＣＯＭ When expressed as [n-0.5], equation (7) can be rewritten as equation (8).

[0093]

[0094] Equation (8) shows the voltage V at the CMFB node. ＣＭＦＢ [n] is the voltage V from the previous cycle (n-1). ＣＭＦＢ [n-1] and the output common-mode voltage V of the fully differential amplifier ＣＯＭ and reference voltage V ＣＭ This indicates that it depends on the difference between [the two factors].

[0095] Furthermore, from equation (8), we find the gain of the low-frequency path of the CMFB circuit. We take the difference over one cycle,

[0096] ΔV ＣＭＦＢ，Ｌｏｗ = V ＣＭＦＢ [n+1]-V ＣＭＦＢ [n]

[0097] ΔV ＣＯＭ = V ＣＯＭ [n+0.5]-V Ｃｏｍ [n-0.5]

[0098] Then, we obtain equation (9).

[0099]

[0100] This corresponds to the gain of the low-frequency path in a CMFB circuit (a two-stage ring amplifier).

[0101] Here, the common-mode gain of the fully differential amplifier is A. ＣＯＭ Assuming this, the loop gain A of the entire low-frequency path of the CMFB circuit is... ＣＭＦＢ，Ｌｏｗ This is expressed by equation (10).

[0102]

[0103] The above mathematical derivation has shown the following: First, the output voltage V of the CMFB circuit. ＣＭＦＢ This is expressed by equation (6) or equation (8), and is the output common-mode voltage V of a fully differential amplifier. ＣＯＭ The reference voltage V ＣＭIt is updated every cycle to approach that value.

[0104] Furthermore, the loop gain of the entire low-frequency path of the CMFB circuit is given by equation (10), C ＳＭＡＬＬ , C ＢＩＧ , C ＦＢ , C Ｐ A ２ , and A ＣＯＭ It is determined by [the following].

[0105] In particular, C ＢＩＧ C ＳＭＡＬＬ If it is much larger than V ＣＭＦＢ is V ＣＯＭ V ＣＭ To converge to that.

[0106] This analysis revealed the mechanism by which the low-frequency path of the CMFB circuit acts as a switched-capacitor circuit, stabilizing the output common-mode voltage. Furthermore, equation (10) for the loop gain provides an important guideline for circuit design that takes the stability of the CMFB circuit into consideration.

[0107] [(8) Operation of the High-Frequency Path] Next, the operation of the high-frequency path of the CMFB circuit will be explained in detail using mathematical formulas. Unlike the low-frequency path, the high-frequency path receives continuous-time feedback during the phase when the second switch Φ2 is ON (amplification phase).

[0108] The high-frequency path does not have capacitance to retain the state from the previous cycle. The voltage V determined by the low-frequency path during the phase when the first switch Φ1 is ON (track, auto-zero, charge-share phase) ＣＭＦＢ AC-like feedback is performed using [n] as the reference point (DC operating point).

[0109] The operation of the high-frequency path will be explained below based on the law of conservation of charge. First, the capacitance C in the phase when the first switch Φ1 is ON. ＦＢ，Φ１ and capacity C Ｐ，Φ１ The charges of are expressed by equations (11) and (12), respectively.

[0110]

[0111]

[0112] Here, V ＣＭＦＢ [n] is the voltage at the CMFB node (the voltage determined by the low-frequency path) during the phase when the first switch Φ1 is ON in the nth cycle. ＣＭ This is the common-mode reference voltage. C ＦＢ and C Ｐ These are the capacity values ​​for each capacity.

[0113] Next, in the phase when the second switch Φ2 is ON, the charge Q of the CMFB node ＣＭＦＢ，Φ２ This is expressed by equation (13).

[0114]

[0115] Here, V ＣＭＦＢ [n+0.5] is the voltage V at the CMFB node in the n+0.5th cycle (the phase when the second switch Φ2 is ON). ＯＰ It is [n+0.5]. Also, V ＯＮ [n+0.5] is the differential output voltage of the fully differential amplifier in the n+0.5th cycle (the phase when the second switch Φ2 is ON).

[0116] During the state transition from the phase in which the first switch Φ1 is ON to the phase in which the second switch Φ2 is ON, charge is conserved, and therefore the following equation (14) holds.

[0117]

[0118] Substitute equations (11) to (13) into equation (14), and V ＣＭＦＢ Rearranging for [n+0.5] yields equation (15).

[0119]

[0120] The left side of equation (15) represents the capacitance C in the phase when the second switch Φ2 is ON. ＦＢ This shows how much the voltage at the CMFB node changes. The right-hand side is the output common-mode voltage of the fully differential amplifier (V ＯＰ [n+0.5]+V ＯＮ Common-mode reference voltage V (n + 0.5) / 2) ＣＭ The deviation from is given by the coefficient (2 * C ＦＢ) / (2*C ＦＢ +C Ｐ It is the result of multiplying by ).

[0121] As is clear from equation (15), the voltage change at the CMFB node when transitioning from the phase in which the first switch Φ1 is ON to the phase in which the second switch Φ2 is ON is proportional to the shift in the output common-mode voltage of the fully differential amplifier. Therefore, this proportionality constant (2 * C) ＦＢ ) / (2*C ＦＢ +C Ｐ ), that is, by appropriately adjusting the capacitance ratio, high-speed CMFB can be achieved during the phase when the second switch Φ2 is ON.

[0122] Since this proportionality constant is determined by the capacitance ratio, it is relatively robust to process, voltage, and temperature (PVT) fluctuations. However, the common-mode gain of a fully differential amplifier itself fluctuates under PVT conditions.

[0123] Furthermore, equation (15) merely represents the voltage change at the CMFB node during one period, from the phase when the first switch Φ1 is ON to the phase when the second switch Φ2 is ON. It does not directly show the behavior in which the output common-mode voltage error of a fully differential amplifier converges to zero after multiple cycles. Therefore, a high-frequency path alone is incomplete as a CMFB circuit for a fully differential amplifier, and steady-state errors may remain in the output common-mode voltage.

[0124] On the other hand, the low-frequency path explained earlier has an integral term 1 / (1-z) in its transfer function (equation (8)). －１ ) is included. The integral term accumulates errors over time and ultimately reduces the steady-state error to zero. Therefore, in the low-frequency path, the output common-mode voltage is V in one cycle. ＣＭ It is not possible to make it a perfect match, but by taking multiple cycles, V ＣＭ It can be converged to this. However, in the low-frequency path, the CMFB node and the first capacitance C are connected during the phase when the second switch Φ2 is ON. ＳＭＡＬＬ and the second capacity C ＢＩＧ Since the switch connecting it is turned off, there is no real-time feedback.

[0125] Thus, low-frequency and high-frequency paths each have their own advantages and disadvantages. However, by combining them, their shortcomings can be compensated for, making it possible to realize a high-speed and high-precision CMFB circuit.

[0126] Here, from equations (8) and (15), V ＣＭＦＢ [n] is removed, and V is expressed only in terms of the voltage during the phase when the second switch Φ2 is ON. ＣＭＦＢ [n+0.5] can be expressed as shown in equation (16).

[0127]

[0128] Next, we derive the loop gain of the high-frequency path. Since we are considering a high-frequency path, we apply V to equation (15). ＣＭＦＢ [n+1] = V ＣＭＦＢ Assuming [n] (steady state), taking the difference over one cycle yields equation (17).

[0129]

[0130] However, V ＣＭＦＢ，Ｈｉｇｈ and V ＣＯＭ The following applies:

[0131] ΔV ＣＭＦＢ，Ｈｉｇｈ ≡V ＣＭＦＢ [n+1.5]-V ＣＭＦＢ [n+0.5]

[0132] ΔV ＣＯＭ ≡(V ＯＰ [n+1.5]+V ＯＮ [n+1.5]) / 2-(V ＯＰ [n+0.5]+V ＯＮ [n+0.5]) / 2

[0133] Therefore, the gain of the high-frequency path in the CMFB circuit is given by the following equation (18).

[0134]

[0135] Here, the common-mode gain of the fully differential amplifier is A. ＣＯＭ Therefore, the loop gain A of the entire high-frequency path is ＣＭＦＢ，Ｈｉｇｈ This is expressed by equation (19).

[0136]

[0137] Comparing equation (10), which shows the loop gain of the low-frequency path, with equation (19), which shows the loop gain of the high-frequency path, we find that the common-mode gain A of a fully differential amplifier is... ＣＯＭ This is included as a common factor. Generally, common mode gain A ＣＯＭ The differential characteristics are large and cannot be freely adjusted. Therefore, the loop gain of the low-frequency path (equation (10)) is affected by other parameters (mainly C). ＢＩＧ , C ＳＭＡＬＬ A ２ Stability is ensured by adjusting the loop gain and poles using (). Typically, low-frequency paths are not intended for high-speed response, so designing the stability of the loop is relatively easy, and the large number of parameters also increases the design flexibility.

[0138] On the other hand, regarding the loop gain of the high-frequency path (Equation 19), in order to reduce the loop gain and ensure stability, capacitance C Ｐ It is necessary to increase the capacity C. Ｐ Increasing capacitance C worsens the settling performance (transient response). The CMFB circuit must be designed so that settling is completed within the period when the second switch Φ2 is ON. Therefore, capacitance C Ｐ If the common-mode gain A is made excessively large, a trade-off occurs where sufficient settling time cannot be secured. Due to this trade-off, ＣＯＭ When the coefficient is large, it can become difficult to design the stability of the high-frequency path.

[0139] [(9) Overall configuration of this embodiment] This technology makes it possible to adjust the loop gain of the high-frequency path without affecting the other path by separating the tail current source, which is the feedback destination for the low-frequency path and the high-frequency path in the CMFB circuit.

[0140] In other words, this technology provides an amplification circuit comprising a fully differential amplifier for amplifying differential signals, and a common-mode feedback (CMFB) circuit for stabilizing the common-mode output voltage of the fully differential amplifier, wherein the CMFB circuit has a low-frequency path for generating a first feedback signal and a high-frequency path for generating a second feedback signal, the fully differential amplifier has a differential input transistor pair and a tail current source connected to a common source of the differential input transistor pair, the tail current source is divided into a first current source and a second current source, the low-frequency path supplies the first feedback signal to the first current source and the second current source, and the high-frequency path supplies the second feedback signal to the second current source.

[0141] This embodiment will be described with reference to Figure 1. Figure 1 is a circuit diagram showing an example of the configuration of an amplifier circuit according to one embodiment of this technology.

[0142] As shown in Figure 1, the fully differential amplifier 1 in this embodiment has a pair of differential input transistors 1b and a tail current source 1a connected to a common source of these differential input transistors 1b.

[0143] Furthermore, a key difference from the comparative example is that this tail current source 1a is divided into a first current source 1a1 and a second current source 1a2.

[0144] Furthermore, the CMFB circuit 2 has a low-frequency path (see Figure 2) that generates a first feedback signal and a high-frequency path (see Figure 3) that generates a second feedback signal.

[0145] As shown in Figure 2, the low-frequency path (shaded area in the CMFB circuit 2) supplies the first feedback signal to both the first current source 1a1 and the second current source 1a2, which are divided tail current sources 1a.

[0146] On the other hand, as shown in Figure 3, the high-frequency path (shaded portion in the CMFB circuit 2) supplies the second feedback signal only to the second current source 1a2 among the divided tail current sources.

[0147] A detailed explanation of Figures 2 and 3 will be provided later.

[0148] According to the amplification circuit of this technology, the tail current source of the fully differential amplifier 1 is divided into a first current source 1a1 and a second current source 1a2. The low-frequency path in the CMFB circuit 2 supplies a feedback signal to both current sources (the first current source 1a1 and the second current source 1a2), while the high-frequency path supplies a feedback signal only to the second current source 1a2.

[0149] This configuration makes it possible to adjust the loop gain of the high-frequency path while maintaining the characteristics of the low-frequency path (e.g., loop gain, phase margin). In other words, because the stability of the high-frequency path can be adjusted independently, the overall design of the amplification circuit becomes easier, and stable operation can be achieved.

[0150] [(10) Fully Differential Amplifier] A fully differential amplifier is an amplifier that has two input terminals, a positive-sequence input terminal IP and a negative-sequence input terminal IN, and two output terminals, a positive-sequence output terminal OP and a negative-sequence output terminal ON. An ideal fully differential amplifier amplifies only the differential input signal (potential difference between IP and IN) and does not amplify the common-mode input signal (average potential between IP and IN). It also generates a differential output signal (potential difference between OP and ON), and the output common-mode voltage (average potential between OP and ON) is kept constant regardless of the input signal (usually the reference voltage VCM).

[0151] A fully differential amplifier achieves a high common-mode rejection ratio (CMRR) because common-mode input signals (such as noise) are not amplified. Furthermore, fully differential amplifiers achieve high linearity because even-order harmonic distortion is suppressed. Additionally, because the output signal of a fully differential amplifier is differential, it can achieve a wider output dynamic range compared to a single-phase output amplifier.

[0152] Because of the advantages mentioned above, fully differential amplifiers can be widely used in analog circuits.

[0153] The fully differential amplifier of this embodiment is configured as a ring amplifier. A ring amplifier has a configuration in which an odd number (for example, three or more) amplification stages are connected in a ring shape. The self-biased ring amplifier shown in Figure 1 is a type of ring amplifier and has a configuration in which three amplification stages are connected in cascade.

[0154] A ring amplifier achieves high open-loop gain by cascading multiple amplification stages. Furthermore, because it does not use negative feedback, it can achieve a relatively wide bandwidth. Additionally, because a ring amplifier can achieve high gain with a relatively small number of stages, it can keep power consumption low.

[0155] In particular, the fully differential amplifier of this embodiment can be configured as a self-biased ring amplifier or a critically damped ring amplifier.

[0156] A self-biased ring amplifier, as shown in Figure 1, is a ring amplifier designed to generate the appropriate bias state internally without requiring fine adjustment of the bias voltage from an external source. This is expected to simplify the circuit, reduce power consumption, and improve resistance to PVT fluctuations.

[0157] A critically damped ring amplifier is a ring amplifier designed to optimize transient response characteristics (such as step response) even when PVT conditions fluctuate (minimizing overshoot and ringing, and achieving fast and stable settling). Critical damping is achieved by adjusting the frequency characteristics by changing the size ratio of the input transistor and the diode-connected load transistor.

[0158] Figure 4 is a circuit diagram showing an example of the configuration of an amplifier circuit according to one embodiment of this technology. This figure is a modified version of the amplifier circuit shown in Figure 1, differing in that the fully differential amplifier 1B is configured as a critically damped ring amplifier.

[0159] The fully differential amplifier 1B of this embodiment also has a tail current source 1a in its first stage, and this tail current source 1a is configured to control the output common-mode voltage. This configuration makes it possible to apply the present technology.

[0160] Furthermore, the fully differential amplifier of this embodiment can also be configured to have a Class AB output stage. The Class AB output stage combines the advantages of both Class A and Class B output stages, achieving both low power consumption and high linearity. This improves the overall performance of the fully differential amplifier.

[0161] Figure 5 is a circuit diagram showing an example of the configuration of an amplifier circuit according to one embodiment of this technology. This figure is a modified version of the amplifier circuit shown in Figure 1, demonstrating that this technology can also be applied to a typical fully differential amplifier in which the output stage has a Class AB configuration.

[0162] The fully differential amplifier 1A shown in Figure 5 is mainly composed of the following elements.

[0163] The input stage consists of a differential pair transistor (NMOS) that receives differential input signals IP and IN, a tail current source (NMOS) that supplies current to them, a Class AB output stage, and a minimum selector circuit. The input stage has a folded cascode configuration, and it is preferable that this load current source (NMOS) is divided into a first current source and a second current source.

[0164] The output stage has a Class AB configuration, and generates the output signals OP and ON using a combination of PMOS and NMOS transistors.

[0165] The CMFB circuit 2 has two paths, a low-frequency path and a high-frequency path, to stabilize the output common-mode voltage.

[0166] A Class AB output stage combines the advantages of both Class A and Class B output stages. A Class A output stage maintains constant current flow, preventing crossover distortion and achieving high linearity. However, it consumes a large amount of power. On the other hand, a Class B output stage only turns on one transistor depending on the input signal level, thus keeping power consumption low. However, it is prone to crossover distortion.

[0167] In a Class AB output stage, when there is no signal or a small signal, a small current (idle current) flows through both transistors (operating in a manner similar to Class A), thereby suppressing crossover distortion. When there is a large signal, the current of one transistor is increased according to the signal level, and the current of the other transistor is decreased (operating in a manner similar to Class B). This allows for both low power consumption and high linearity.

[0168] Thus, the CMFB circuit of this technology can be applied not only to the fully differential amplifier shown in Figure 1, but also to fully differential amplifiers with other circuit topologies, such as the fully differential amplifier with a Class AB output stage shown in Figure 5.

[0169] The various fully differential amplifiers described above (ring amplifier, self-biased type, critically damped type, and Class AB output stage) each have different characteristics, but when used in combination with the CMFB circuit of this technology, they can all realize a high-speed, high-precision, and stable amplification circuit. Depending on the specific application and required specifications, it is possible to select or combine the most suitable fully differential amplifier.

[0170] [(11) Low-frequency path] The feedback path of the low-frequency path in the CMFB circuit 2 according to this embodiment will be described with reference to Figure 2. Figure 2 is a circuit diagram showing an example of the configuration of an amplifier circuit according to one embodiment of this technology.

[0171] As shown in Figure 2, the low-frequency path is the first capacitance C ＳＭＡＬＬ , second capacity C ＢＩＧ It is configured as a switched-capacitor circuit, including a plurality of first switches Φ1 (Φ1a), a second switch Φ2, and an amplification circuit (two-stage ring amplifier) ​​2a.

[0172] Amplifier circuit 2a controls the output common-mode voltage V of the fully differential amplifier 1. ＣＯＭ and reference voltage V ＣＭ The difference is amplified to generate the first voltage.

[0173] First capacity C ＳＭＡＬＬ This is connected to the output of the amplification circuit 2a via the second switch Φ2, and maintains the first voltage.

[0174] Second capacity C ＢＩＧ is the first capacity C ＳＭＡＬＬ It shares charge with and generates the first feedback signal.

[0175] Multiple first switches Φ1 (Φ1a) have a first capacitance C ＳＭＡＬＬ and the second capacity C ＢＩＧ Between and the first capacity C ＳＭＡＬＬ It is connected to the first current source 1a1, respectively. The first switch Φ1 is connected to the first capacitance CSMALL and the second capacitance C ＢＩＧ It connects / disconnects between the two. The first switch Φ1 controls the first capacitance C ＳＭＡＬＬ This connects / disconnects the first current source 1a1 of the fully differential amplifier 1.

[0176] The second switch Φ2 controls the first capacitance C ＳＭＡＬＬ It is connected between the amplifier circuit 2a and the second switch Φ2. ＳＭＡＬＬ This connects / disconnects the output of the amplification circuit 2a.

[0177] The first switch Φ1 and the second switch Φ2 switch on and off in a complementary manner. That is, when the first switch Φ1 is on, the second switch Φ2 is off, and when the first switch Φ1 is off, the second switch Φ2 is on.

[0178] The operation of the low-frequency path will be explained. In the phase when the first switch Φ1 (Φ1a) is ON, the input capacitance C １ This samples (tracks) the input signal.

[0179] Furthermore, the output OP, ON of the fully differential amplifier 1 is the reference voltage V ＣＭ It is connected to and has a capacity of C ＳＥＮＳＥ The output common-mode voltage of the fully differential amplifier 1 is detected via this, and the first stage of the amplification circuit 2a performs auto-zero operation, and the reference voltage V ＣＭ An operating point is set based on this.

[0180] Also, the first capacity C ＳＭＡＬＬ The charge that had been stored in the first switch Φ1 is released through the second capacitor C ＢＩＧ It is shared with the first capacity C. ＳＭＡＬＬ and the second capacity C ＢＩＧA voltage corresponding to the capacitance ratio is generated as a second voltage (first feedback signal) and supplied to the first current source 1a1 and the second current source 1a2.

[0181] Next, in the phase when the second switch Φ2 is ON, the fully differential amplifier 1 amplifies the input signal. When the second switch Φ2 is ON, the amplification circuit 2a combines the output common-mode voltage of the fully differential amplifier 1 with the reference voltage V ＣＭ The difference is amplified to generate the first voltage.

[0182] First capacity C ＳＭＡＬＬ This is connected to the output of the amplification circuit 2a and holds the first voltage.

[0183] The CMFB node enters a high-impedance state, and capacitance C Ｐ The voltage from the previous day is retained.

[0184] With the above configuration and operation, the low-frequency path detects fluctuations in the output common-mode voltage of the fully differential amplifier 1 and uses it as a reference voltage V ＣＭ Feedback control is used to bring it closer to the target.

[0185] In particular, the second capacity C ＢＩＧ However, it is important that the first switch Φ1 is connected not only to the first current source 1a1 of the divided tail current source, but also to the second current source 1a2 when the first switch Φ1 is ON. This configuration allows the loop gain of the entire low-frequency path to be maintained. In other words, even if the tail current source is divided and the high-frequency path is connected only to the second current source 1a2, the characteristics of the low-frequency path do not deteriorate.

[0186] Furthermore, the main pole of the low-frequency path is the first capacitance C ＳＭＡＬＬ and the second capacity C ＢＩＧ This is determined by the capacitance ratio, which is independent of the parameters that determine the differential characteristics of the fully differential amplifier 1. Therefore, the stability of the low-frequency path can be easily ensured without compromising the differential characteristics.

[0187] [(12) High-Frequency Path] The feedback path of the high-frequency path in the CMFB circuit 2 according to this embodiment will be described with reference to Figure 3. Figure 3 is a circuit diagram showing an example of the configuration of an amplifier circuit according to one embodiment of this technology.

[0188] As shown in Figure 3, the high-frequency path is mainly capacitance C. ＦＢ and capacity C Ｐ It is composed of. Capacity C ＦＢ It is connected between the differential output OP and ON of the fully differential amplifier 1. Capacitance C Ｐ This is connected between the CMFB node (the input to the second current source 1a2) and ground.

[0189] The high-frequency path is the capacitance C between the differential outputs of the fully differential amplifier 1. ＦＢ It is connected to the second current source 1a2 via [a certain method].

[0190] The feedback signal from the high-frequency path (the second feedback signal) is transmitted to the second current source 1a2 only when the first switch Φ1 (Φ1a) is off and the second switch Φ2 is on (i.e., during the amplification period of the fully differential amplifier 1).

[0191] The high-frequency path does not retain the feedback amount for the next clock cycle. In other words, it plays a supporting role to the common-mode feedback provided by the low-frequency path. Also, the high-frequency path has a higher loop bandwidth compared to the low-frequency path.

[0192] The operating principle of the high-frequency path will be explained. In the phase when the second switch Φ2 is ON (amplification phase), the differential output OP,ON of the fully differential amplifier 1 will show a common-mode voltage fluctuation component along with the amplified differential signal. This common-mode voltage fluctuation component is due to capacitance C ＦＢ It is transmitted to the CMFB node via [this method].

[0193] Since the CMFB node is connected to the gate of the second current source 1a2 of the divided tail current source, this voltage fluctuation changes the drain current of the second current source 1a2. This current change changes the output common-mode voltage of the fully differential amplifier 1 to the reference voltage V ＣＭ It acts to bring it closer to (negative feedback). The high-frequency path has capacitance C. ＦＢ Because voltage fluctuations between differential outputs are directly fed back via this mechanism, a fast response is possible.

[0194] The low-frequency path is configured, for example, as a switched-capacitor circuit, and over multiple cycles, the output common-mode voltage is referenced to a V2 voltage. ＣＭ It converges to this. On the other hand, the high-frequency path suppresses high-speed common-mode voltage fluctuations that the low-frequency path cannot handle during the phase when the second switch Φ2 is ON.

[0195] In this way, the low-frequency path and the high-frequency path operate on different time scales, leveraging their respective strengths to stabilize the output common-mode voltage over a wide bandwidth.

[0196] The loop gain of a high-frequency path is mainly due to capacitance C. ＦＢ and capacity C Ｐ It is determined by the value of and the common-mode gain of the fully differential amplifier 1. In the comparative example (Figure 12), capacitance C Ｐ The loop gain was adjusted by increasing the capacitance C to ensure stability, but Ｐ There was a trade-off: increasing the value resulted in a longer settling time.

[0197] In this technology, the tail current source is divided and the high-frequency path is connected only to the second current source 1a2, thereby reducing capacitance C Ｐ This allows for a reduction in the loop gain of the high-frequency path without increasing its size. This makes it possible to improve stability without sacrificing settling time.

[0198] The above description of the amplification circuit according to this embodiment can be applied to other embodiments of this technology, unless there are any particular technical inconsistencies.

[0199] [2. Second Embodiment of the Technology (Example 2 of Amplifier Circuit)] In the amplifier circuit of the first embodiment, as shown in Figure 1, the tail current source of the fully differential amplifier 1 is divided into a first current source 1a1 and a second current source 1a2. In the amplifier circuit of the second embodiment, the current ratio of the first current source 1a1 and the second current source 1a2 is set to α:1-α (where 0 < α < 1).

[0200] This division ratio α is a very important parameter in this technology and plays a role in adjusting the loop gain of the high-frequency path.

[0201] As described above (Equation (19)), the loop gain A of the entire high-frequency path ＣＭＦＢ，Ｈｉｇｈ This is expressed by equation (20).

[0202]

[0203] Here, C ＦＢ This is the capacitance of the CMFB high-frequency path, C Ｐ is the capacitance of the CMFB node, the common-mode gain of the fully differential amplifier, and α is the division ratio of the tail current source.

[0204] In the comparative example (Figure 12), the tail current source was not divided, and the loop gain of the CMFB high-frequency path did not have an α term (equivalent to α = 1). Therefore, in order to adjust the loop gain, C ＦＢ Ya C Ｐ The only option was to change the value. However, C Ｐ Increasing this value worsens the settling performance, C ＦＢ There was a problem in that reducing the size reduced the effectiveness of CMFB.

[0205] In this technology, the tail current source is divided in the ratio α:1-α, and the CMFB high-frequency path is connected only to the second current source (α side), thereby C Ｐ Ya C ＦＢ Without changing the design parameter, the loop gain of the high-frequency path can be reduced by a factor of α. α is an adjustable design parameter in the range of 0 < α < 1, and the smaller α is, the lower the loop gain of the high-frequency path can be, thereby improving the stability of the CMFB circuit.

[0206] The value of α is determined based on the overall system requirements (speed, accuracy, power consumption, etc.) to ensure sufficient settling performance while maintaining the stability of the high-frequency path.

[0207] Reducing α lowers the loop gain of the high-frequency path, increases the phase margin, and improves stability. However, excessively reducing α may weaken the suppression effect of the high-frequency path on common-mode voltage fluctuations, potentially increasing the settling time.

[0208] Increasing α strengthens the suppression of common-mode voltage fluctuations by the high-frequency path, shortening the settling time. However, if α is increased excessively, the loop gain of the high-frequency path becomes excessive, reducing the phase margin and increasing the risk of oscillation.

[0209] Generally, simulations are used to optimize the value of α and balance stability and settling performance.

[0210] Importantly, splitting the tail current source does not affect the loop gain of the CMFB low-frequency path. This is because the output of the low-frequency path (C) ＢＩＧ This is because the top plate voltage (and the output of the two-stage ring amplifier) ​​is supplied to both divided current sources (the first current source 1a1 and the second current source 1a2).

[0211] Therefore, this technology allows for independent adjustment of only the loop gain of the high-frequency path while maintaining the characteristics of the low-frequency path. This simplifies the design of the entire CMFB circuit and enables the realization of an amplifier circuit that achieves both stability and high speed.

[0212] Figure 6 is a graph comparing the open-loop frequency characteristics (Bode plot) of the CMFB high-frequency path in the comparative example (Figure 1) and the present technology. Figure 6A shows the gain characteristics, and Figure 6B shows the phase characteristics, with the horizontal axis representing frequency (logarithmic scale).

[0213] In the comparative example, the phase margin at the frequency where the phase is around -180 degrees (the frequency at which the gain is 0 dB, i.e., the unit gain frequency) is very small or negative. This indicates that the CMFB high-frequency path is unstable or highly likely to oscillate. This is mainly due to the following factors.

[0214] First, the common-mode gain A of a fully differential amplifier. ＣＯＭDue to its large size, the DC gain (gain in the low-frequency range) of the CMFB high-frequency path is high. Also, if the main pole of a fully differential amplifier (usually due to the output stage in the case of a ring amplifier) ​​is relatively high, the distance between this main pole and the first non-main pole becomes small, causing a rapid phase drop near the unity gain frequency. When these factors combine, the phase margin becomes insufficient, making the CMFB high-frequency path unstable.

[0215] On the other hand, in this technology, the open-loop characteristics of the CMFB high-frequency path are improved compared to the comparative example as follows.

[0216] First, the DC gain is reduced to α times that of the comparative example (indicated by the arrow "DC gain is α times" in the figure). This is the effect of dividing the tail current source of the first stage of the fully differential amplifier in the ratio α:1-α and connecting the CMFB high-frequency path only to the second current source (α side).

[0217] Furthermore, as the DC gain decreases, the unit gain frequency (the frequency at which the gain becomes 0 dB) shifts to the lower frequency side. As a result, the gain falls below 0 dB before the phase reaches -180 degrees, thus increasing the phase margin (indicated by the "phase margin" arrow in the figure).

[0218] As is clear from this figure, this technology improves the stability of the CMF circuit by reducing the open-loop gain of the high-frequency path by α times, thereby ensuring a phase margin. Importantly, this improvement is achieved without affecting the frequency characteristics of the low-frequency path. The low-frequency path plays a role in converging the output common-mode voltage to the reference voltage, while the high-frequency path plays a role in achieving a fast transient response. Because the characteristics of each path can be adjusted independently in this way, a CMF circuit that achieves both stability and high speed can be easily designed.

[0219] The above description of the amplification circuit according to this embodiment can be applied to other embodiments of this technology, unless there are any particular technical inconsistencies.

[0220] [3. Third Embodiment of the Technology (Example 3 of Amplifier Circuit)] [(1) Integrated Circuit] Due to its excellent characteristics (high speed, high precision, and stability), the amplifier circuit of the technology can be widely applied to various integrated circuits, especially applications requiring analog signal processing.

[0221] Figure 7 is a block diagram showing an example of the configuration of an integrated circuit according to one embodiment of this technology. As shown in Figure 7, the amplification circuit 100 of this technology can be configured as an integrated circuit 300 in combination with an analog-to-digital converter (ADC) 200. The ADC 200 is a circuit that converts analog signals to digital signals and is an essential component in various electronic devices.

[0222] For example, one possible configuration is to connect the output (OP, ON) of the amplification circuit of this technology (see Figure 1) to the input of the ADC200, and have the ADC200 convert the amplified differential signal into a digital signal. By using the amplification circuit of this technology, the signal can be amplified at high speed and with high precision at the input stage of the ADC200, and the common-mode voltage can be stabilized. This makes it possible to improve the overall performance of the ADC200 (conversion speed, resolution, S / N ratio, etc.).

[0223] [(2) Analog Front-End Circuit] Furthermore, the amplification circuit of this technology can be used in an analog front-end circuit. An analog front-end circuit is a circuit that performs processing such as amplification, filtering, and offset removal on minute analog signals output from a signal source such as a sensor so that they can be handled by a subsequent processing circuit (such as an ADC).

[0224] Because the amplification circuit of this technology has features such as low noise, high CMRR (common-mode rejection ratio), and high linearity, it is particularly effective in analog front-end circuits such as the following.

[0225] The amplification circuit of this technology is used in analog front-end circuits that process output signals from various sensors, such as temperature sensors, pressure sensors, acceleration sensors, gyroscopes, light sensors, and biosensors.

[0226] The amplification circuit of this technology is used, for example, in analog front-end circuits in receiving circuits for wireless communication (mobile phones, wireless LANs, etc.) and wired communication (optical fiber communication, etc.).

[0227] The amplification circuit of this technology is used in analog front-end circuits that process audio signals, such as microphone amplifiers and preamplifiers.

[0228] [(3) Pipeline ADC] Figure 8 is a schematic diagram showing an example of the application of an amplification circuit according to one embodiment of the present technology. As shown in Figure 8, the amplification circuit of the present technology can be used as an interstage amplifier of a pipeline ADC.

[0229] A pipelined ADC has a configuration in which multiple conversion stages (Stage 1, Stage 2, Stage 3, etc.) are connected in series. Each stage consists of a sub-ADC, a CDAC (Capacitive Digital-to-Analog Converter), a subtractor, and an amplifier (G1, G2, etc.).

[0230] Let's explain the operation of a pipelined ADC. First, the input analog signal V ｉｎ However, this is entered into the first stage (Stage 1).

[0231] Next, the sub-ADCs in each stage convert the input analog signal into a digital signal (D) with coarse precision. １ , D ２ Convert to (etc.).

[0232] Next, the CDAC converts the digital signal, which is the output of the sub-ADC, into an analog signal.

[0233] Next, input analog signal V ｉｎ The conversion residual (quantization error) is generated by subtracting the output analog signal of the CDAC from this.

[0234] Next, the conversion residual, which is the output of the subtractor, is taken by the amplifier (G １ G ２ The signal is amplified using (etc.). The amplification circuit of this technology is used as this amplifier. The amplified residual becomes the input to the next stage.

[0235] The above process is repeated at each stage, ultimately producing a high-precision digital output signal D. ｏｕｔ Obtain the digital output (D) of each stage. １ , D ２ , D ３ (etc.) are synchronized in timing using a Data Alignment circuit, and the final digital output D ｏｕｔ This is generated.

[0236] As shown in the enlarged view of Figure 8, the amplifiers (G) of each stage １ G ２ The fully differential amplifier 1 of this technology can be applied to applications such as (etc.).

[0237] In each stage of a pipelined ADC, it is necessary to accurately amplify the conversion residual (analog signal) from the preceding stage. By using the amplification circuit of this technology as the amplifier, a high-speed and high-precision pipelined ADC can be realized. In particular, the CMFB circuit of this technology is excellent in terms of speed and stability, and is very effective in improving the conversion speed and accuracy (resolution, S / N ratio, ENOB, etc.) of a pipelined ADC.

[0238] [(4) ΔΣ-type ADC] Figure 9 is a schematic diagram showing an example of the application of an amplification circuit according to one embodiment of the present technology. As shown in Figure 9, the amplification circuit of the present technology can be used as a component of a ΔΣ-type ADC.

[0239] A ΔΣ ADC achieves high-resolution analog-to-digital conversion by combining oversampling, ΔΣ modulation (delta-sigma modulation), and digital filtering.

[0240] A ΔΣ type ADC is mainly composed of the following elements.

[0241] The input stage receives the input analog signals VDBE_P and VDBE_N. A switched-capacitor circuit is used in the input stage to sample the input signal and feed it to the subsequent amplifier.

[0242] The amplifier amplifies the signal from the input stage. A fully differential amplifier, as described in this technology, can be applied as this amplifier.

[0243] A delta-sigma modulator converts an amplified analog signal into a one-bit or multi-bit digital signal. A delta-sigma modulator typically consists of an integrator, a comparator, and a one-bit DAC (digital-to-analog converter).

[0244] The integrator integrates the difference between the input signal and the feedback signal from the 1-bit DAC. The fully differential amplifier technology described here can also be applied as the amplifier for this integrator.

[0245] A comparator (COMP) compares the output of an integrator with a reference voltage and outputs a one-bit (or several-bit) digital signal.

[0246] A 1-bit DAC converts the output of the comparator into an analog signal and feeds it back to the input stage.

[0247] A digital filter (not shown) processes the output of the ΔΣ modulator and outputs a high-resolution digital signal.

[0248] [(5) Effects] By using the amplification circuit of this technology in these amplifiers, the following effects can be expected. First, high signal-to-noise ratio and high linearity can be achieved through common-mode noise rejection by a fully differential configuration, reduction of harmonic distortion, and a wide output dynamic range.

[0249] Furthermore, the wide bandwidth characteristics provided by the fully differential amplifier and the high-speed settling provided by the CMFB circuit allow for a higher oversampling frequency.

[0250] Furthermore, when applied to self-biased ring amplifiers or Class AB output stages, it enables lower power consumption.

[0251] Furthermore, the CMFB circuit of this technology stabilizes the output common-mode voltage, improving the performance (integration accuracy and stability) of the integrator of the ΔΣ type ADC. In particular, by dividing the tail current source and optimizing the connection destination of the CMFB high-frequency path, both high speed and stability can be achieved.

[0252] These application examples demonstrate the usefulness of the amplification circuit of this technology, and are not limited to these examples. The amplification circuit of this technology can also be applied to various other analog circuits and analog-digital circuits.

[0253] The above description of the amplification circuit according to this embodiment can be applied to other embodiments of this technology, unless there are any particular technical inconsistencies.

[0254] [4. Fourth Embodiment of the Technology (Example of a Signal Processing Device)] [(1) Signal Processing Device] Due to its excellent characteristics (high speed, high precision, low noise, high stability, etc.), the amplification circuit of the technology can be applied to various signal processing devices and contribute to improving their performance.

[0255] The amplification circuit of this technology can be incorporated into various signal processing devices. Here, "signal processing device" refers to any device that performs some kind of processing (such as amplification, filtering, modulation / demodulation, encoding / decoding, feature extraction, etc.) on analog signals, digital signals, or both.

[0256] Specifically, the following signal processing devices are possible, but are not limited to these.

[0257] One example of a signal processing device is a system that amplifies and converts signals from sensors and collects them as digital data (a data acquisition system).

[0258] Examples of signal processing devices include transceiver circuits used in wireless and wired communications.

[0259] One example of a signal processing device is a measurement and control system that measures various physical quantities and performs control based on those measurements.

[0260] Examples of signal processing devices include image input / output devices such as cameras, scanners, and displays, as well as image processing circuits.

[0261] Examples of signal processing devices include microphones, speakers, speech recognition and speech synthesis devices, and speech processing circuits.

[0262] In these signal processing devices, the amplification circuit of this technology can be used as part of a functional block for analog signal amplification, filtering (such as switched-capacitor filters), A / D conversion, D / A conversion, or as part of a system combining these functional blocks.

[0263] [(2) Audio equipment] The signal processing device (including the amplification circuit) of this technology can be used in audio equipment that processes audio signals.

[0264] Audio equipment includes, for example, microphone amplifiers, preamplifiers, power amplifiers, equalizers, effects processors, digital audio players, recorders, speakers, and headphones.

[0265] By applying this amplification circuit technology to parts of audio equipment that require characteristics such as low noise, high linearity, and wide dynamic range (for example, microphone amplifiers, preamplifiers, and the input stage of A / D converters), it is possible to improve the overall sound quality of the audio equipment (S / N ratio, distortion rate, frequency response, etc.).

[0266] [(3) IoT devices] The signal processing device (including the amplification circuit) of this technology can be used in IoT (Internet of Things) devices that process sensor signals. IoT devices are systems that detect various physical quantities (temperature, humidity, illuminance, pressure, acceleration, angular velocity, position, gas concentration, etc.) with sensors and collect, analyze, and utilize that information via the internet.

[0267] In IoT devices, the signals from sensors are often weak, requiring low-noise and high-precision amplification circuits. Furthermore, since they are frequently battery-powered, low power consumption is crucial. Additionally, if wireless communication functionality is included, a high CMRR (Common Mode Rejection Ratio) is required to avoid interference with communication circuits.

[0268] The amplification circuit of this technology can meet these requirements and, as an analog front-end circuit for processing signals from various sensors, can contribute to improving the performance, miniaturizing, and reducing the power consumption of IoT devices.

[0269] [(4) LiDAR device] The signal processing device (including the amplification circuit) of this technology can be used in a LiDAR device that processes received signals from LiDAR (Light Detection and Ranging). LiDAR is a technology that measures the distance and shape of an object by irradiating it with laser light and detecting the reflected light. It is used in a wide range of fields, such as autonomous driving, robots, drones, surveying, and environmental measurement.

[0270] LiDAR receiving circuits need to amplify weak signals generated by reflected light at high speed and with high precision. Furthermore, a high CMRR (Common Mitigation Rejection Ratio) is required to suppress the effects of ambient light (such as sunlight).

[0271] The amplification circuit of this technology can meet these requirements and, as an analog front-end circuit for processing LiDAR received signals, can improve the performance of LiDAR devices (distance measurement accuracy, resolution, sensitivity, etc.).

[0272] The amplification circuit of this technology can be applied to various signal processing devices, including the audio equipment, IoT devices, and LiDAR devices mentioned above, and can contribute to improving the performance, functionality, miniaturization, and power consumption of these devices.

[0273] The above description of the signal processing apparatus according to this embodiment can be applied to other embodiments of this technology, unless there are any particular technical inconsistencies.

[0274] [5. Fifth Embodiment of the Technology (Example of Common Mode Feedback Method)] [(1) Overall Flow] The Technology provides a common mode feedback (CMFB) method for stabilizing the output common mode voltage of a fully differential amplifier. This method is particularly effective when applied to fully differential amplifiers such as self-biased ring amplifiers used in switched-capacitor circuits.

[0275] Figure 10 is a flowchart showing an example of the CMFB method of this technology. As shown in Figure 10, the CMFB method of this technology mainly includes the following steps.

[0276] [Step S1: Splitting the tail current source] The tail current source of the first amplification stage of a fully differential amplifier (for example, the self-biased ring amplifier in Figure 1) is split into a first current source and a second current source.

[0277] [Step S2: Generation of the first feedback signal (low-frequency path)] A first feedback signal corresponding to the output common-mode voltage of the fully differential amplifier is generated via a low-frequency path. This first feedback signal is supplied to both the first and second current sources of the divided tail current source.

[0278] [Step S3: Generation of the second feedback signal (high-frequency path)] A second feedback signal corresponding to the output common-mode voltage of the fully differential amplifier is generated via a high-frequency path. This second feedback signal is supplied to the second current source of the divided tail current source.

[0279] The current ratio between the first current source and the second current source can be set to α:1-α (where 0 < α < 1). This division ratio α is an important parameter for adjusting the loop gain of the CMFB high-frequency path. By making α less than 1, the loop gain of the CMFB high-frequency path can be reduced compared to conventional methods, thereby improving stability.

[0280] [(2) Generation of the first feedback signal] Figure 11 is a flowchart showing an example of the CMFB method of this technology. This flowchart divides step S2 (generation of the first feedback signal) of Figure 10 into substeps.

[0281] [Step S2-1: Amplification] Using the amplification circuit (for example, the two-stage ring amplifier in Figure 1) 2a, the output common-mode voltage V of the fully differential amplifier is... ＣＯＭ and reference voltage V ＣＭ The difference is amplified to generate the first voltage.

[0282] [Step S2-2: Voltage holding] First capacitance C ＳＭＡＬＬ This causes the first voltage to be maintained.

[0283] [S2-3: Charge Sharing] Using multiple first switches Φ1 and second switches Φ2, the first capacitance CＳＭＡＬＬ and the second capacity C ＢＩＧ Charge is shared between them. Φ1 and Φ2 switch on and off complementaryly.

[0284] Specifically, the first switch Φ1 controls the first capacitance C ＳＭＡＬＬ and the second capacity C ＢＩＧ Between and the first capacity C ＳＭＡＬＬ They are connected between the first current source 1a1 and the first current source 1a1, respectively.

[0285] The second switch Φ2 controls the first capacitance C ＳＭＡＬＬ It is connected between the amplifier circuit 2a.

[0286] When the first switch Φ1 is ON, the first capacitance C ＳＭＡＬＬ and the second capacity C ＢＩＧ They are connected, and the charge is shared.

[0287] Second capacity C ＢＩＧ When the first switch Φ1 is ON, the first capacitance C ＳＭＡＬＬ The second voltage generated by sharing charge with the first current source is supplied to the first current source as the first feedback signal.

[0288] Second capacity C ＢＩＧ It is always connected to the second current source.

[0289] [S2-4: Supply of feedback signal] The generated first feedback signal (C ＢＩＧ The voltage is supplied in step S4 to both of the divided tail current sources (the first current source 1a1 and the second current source 1a2).

[0290] [(3) Generation of the second feedback signal] Step 3 in Figure 10 (generation of the second feedback signal) involves the capacitance C between the differential outputs of the fully differential amplifier. ＦＢ This includes providing feedback to the second current source 1a2 via [the specified method].

[0291] According to the method described above, the loop gain of the CMF high-frequency path can be reduced by α while maintaining the characteristics of the CMF low-frequency path (loop gain, phase margin, etc.). This ensures the stability of the entire CMF circuit while achieving a fast response. Furthermore, the low-frequency and high-frequency paths operate complementaryly, stabilizing the output common-mode voltage over a wide bandwidth.

[0292] This CMFB method contributes to the stable operation of the amplification circuit. Furthermore, this method is applicable to various types of fully differential amplifiers (e.g., ring amplifiers, self-biased ring amplifiers, critically damped ring amplifiers, and amplifiers with a Class AB output stage).

[0293] The above description of the common-mode feedback method according to this embodiment can be applied to other embodiments of the technology, unless there are any particular technical inconsistencies.

[0294] Furthermore, the embodiments relating to this technology are not limited to the embodiments described above, and various modifications are possible without departing from the gist of this technology. The specific numerical values, shapes, materials (including composition), etc. described in each embodiment are examples only and are not limited thereto.

[0295] Furthermore, this technology can also take the following configurations: [1] An amplification circuit comprising: a fully differential amplifier for amplifying differential signals; and a common-mode feedback (CMFB) circuit for stabilizing the common-mode output voltage of the fully differential amplifier, wherein the CMFB circuit has a low-frequency path for generating a first feedback signal and a high-frequency path for generating a second feedback signal, the fully differential amplifier has a differential input transistor pair and a tail current source connected to a common source of the differential input transistor pair, the tail current source is divided into a first current source and a second current source, the low-frequency path supplies the first feedback signal to the first current source and the second current source, and the high-frequency path supplies the second feedback signal to the second current source. [2] The amplification circuit according to [1], wherein the current ratio of the first current source and the second current source is α:1-α (where 0<α<1). [3] The low-frequency path includes a first capacitor, a second capacitor, a plurality of first switches, a second switch, and an amplification circuit, wherein the amplification circuit amplifies the difference between the output common-mode voltage of the fully differential amplifier and a reference voltage to generate a first voltage, the first capacitor holds the first voltage, the plurality of first switches are connected between the first capacitor and the second capacitor, and between the first capacitor and the first current source, the second switch is connected between the first capacitor and the amplification circuit, the first switch and the second switch are switched on and off complementaryly, and the second capacitor supplies the second voltage, which is generated by sharing charge with the first capacitor when the first switch is on, as a first feedback signal to the first current source and is connected to the second current source, the amplification circuit according to [1] or [2]. [4] The amplification circuit according to any one of [1] to [3], wherein the high-frequency path is connected to the second current source via capacitance between the differential outputs of the fully differential amplifier to generate the second feedback signal. [5] The amplification circuit according to any one of [1] to [4], wherein the fully differential amplifier is a ring amplifier.[6] The amplification circuit according to [5], wherein the fully differential amplifier is a self-biased ring amplifier or a critically damped ring amplifier. [7] The amplification circuit according to any one of [1] to [6], wherein the fully differential amplifier has a Class AB output stage. [8] An integrated circuit comprising the amplification circuit according to any one of [1] to [7] and an analog-to-digital converter that outputs a digital signal based on the output signal of the amplification circuit. [9] The amplification circuit according to any one of [1] to [8], used in an analog front-end circuit.

[10] The amplification circuit according to any one of [1] to [9], used in a pipelined ADC.

[11] The amplification circuit according to any one of [1] to

[10] , used in a ΔΣ ADC.

[12] A signal processing device comprising the amplification circuit according to any one of [1] to

[11] .

[13] The signal processing device according to

[12] , used in an audio device that processes audio signals.

[14] The signal processing device according to

[12] , used in an IoT device that processes sensor signals.

[15] The signal processing device according to

[12] , used in a LiDAR device for processing a received signal of a LiDAR.

[16] A common-mode feedback method for stabilizing the output common-mode voltage of a fully differential amplifier, comprising: generating a first feedback signal corresponding to the output common-mode voltage of the fully differential amplifier via a low-frequency path; generating a second feedback signal corresponding to the output common-mode voltage of the fully differential amplifier via a high-frequency path; dividing the tail current source of the fully differential amplifier into a first current source and a second current source; supplying the first feedback signal to the first current source and the second current source; and supplying the second feedback signal to the second current source.

[17] The common-mode feedback method according to

[16] , wherein the current ratio of the first current source and the second current source is α:1-α (where 0<α<1).

[18] The common-mode feedback method according to

[16] or

[17] , wherein generating the first feedback signal includes: generating a first voltage by amplifying the difference between the output common-mode voltage of the fully differential amplifier and a reference voltage using an amplification circuit; holding the first voltage in a first capacitor; and sharing charge between the first capacitor and the second capacitor using a plurality of first switches and second switches, wherein the plurality of first switches are connected between the first capacitor and the second capacitor and between the first capacitor and the first current source, respectively; the second switch is connected between the first capacitor and the amplification circuit; the first switch and the second switch are switched on and off complementaryly; and the second capacitor supplies the second voltage generated by sharing charge with the first capacitor when the first switch is on to the first current source as the first feedback signal, and is connected to the second current source.

[19] The common-mode feedback method according to any one of

[16] to

[18] , wherein generating the second feedback signal includes feeding it back to the second current source via the capacitance between the differential outputs of the fully differential amplifier.

[0296] 1. Fully Differential Amplifier 1a. Tail Current Source 1a1. First Current Source 1a2. Second Current Source 1b. Differential Input Transistor Pair 2. CMFB Circuit 2a. Amplifier Circuit 100. Amplifier Circuit 200. Analog-to-Digital Converter (ADC) 300. Integrated Circuit C ＳＭＡＬＬ First capacity C ＢＩＧ Second capacity Φ1, Φ1a First switch Φ2 Second switch

Claims

1. An amplification circuit comprising: a fully differential amplifier for amplifying differential signals; and a common-mode feedback (CMFB) circuit for stabilizing the common-mode output voltage of the fully differential amplifier, wherein the CMFB circuit has a low-frequency path for generating a first feedback signal and a high-frequency path for generating a second feedback signal; the fully differential amplifier has a differential input transistor pair and a tail current source connected to a common source of the differential input transistor pair, the tail current source is divided into a first current source and a second current source, the low-frequency path supplies the first feedback signal to the first current source and the second current source, and the high-frequency path supplies the second feedback signal to the second current source.

2. The amplification circuit according to claim 1, wherein the current ratio between the first current source and the second current source is α:1-α (where 0 < α < 1).

3. The low-frequency path includes a first capacitor, a second capacitor, a plurality of first switches, a second switch, and an amplification circuit, wherein the amplification circuit amplifies the difference between the output common-mode voltage of the fully differential amplifier and a reference voltage to generate a first voltage, the first capacitor holds the first voltage, the plurality of first switches are connected between the first capacitor and the second capacitor, and between the first capacitor and the first current source, the second switch is connected between the first capacitor and the amplification circuit, the first switch and the second switch are switched on and off complementaryly, and the second capacitor is connected to the second current source and supplies a second voltage, which is generated when the first switch is on by sharing charge with the first capacitor, as a first feedback signal to the first current source.

4. The amplifier circuit according to claim 1, wherein the high-frequency path is connected to the second current source via capacitance between the differential outputs of the fully differential amplifier to generate the second feedback signal.

5. The amplification circuit according to claim 1, wherein the fully differential amplifier is a ring amplifier.

6. The amplification circuit according to claim 5, wherein the fully differential amplifier is a self-biased ring amplifier or a critically damped ring amplifier.

7. The amplification circuit according to claim 1, wherein the fully differential amplifier has a Class AB output stage.

8. An integrated circuit comprising: an amplification circuit according to claim 1; and an analog-to-digital converter that outputs a digital signal based on the output signal of the amplification circuit.

9. The amplification circuit according to claim 1, used in an analog front-end circuit.

10. The amplification circuit according to claim 1, used in a pipeline type ADC.

11. The amplification circuit according to claim 1, used in a ΔΣ type ADC.

12. A signal processing device comprising the amplification circuit described in claim 1.

13. The signal processing apparatus according to claim 12, used in audio equipment that processes audio signals.

14. The signal processing device according to claim 12, used in IoT devices that process sensor signals.

15. The signal processing device according to claim 12, used in a LiDAR device for processing received signals from a LiDAR.

16. A common-mode feedback method for stabilizing the output common-mode voltage of a fully differential amplifier, comprising: generating a first feedback signal corresponding to the output common-mode voltage of the fully differential amplifier via a low-frequency path; generating a second feedback signal corresponding to the output common-mode voltage of the fully differential amplifier via a high-frequency path; dividing the tail current source of the fully differential amplifier into a first current source and a second current source; supplying the first feedback signal to the first current source and the second current source; and supplying the second feedback signal to the second current source.

17. The common-mode feedback method according to claim 16, wherein the current ratio of the first current source to the second current source is α:1-α (where 0 < α < 1).

18. The common-mode feedback method according to claim 16, wherein generating the first feedback signal includes: generating a first voltage by amplifying the difference between the output common-mode voltage of the fully differential amplifier and a reference voltage using an amplification circuit; holding the first voltage in a first capacitor; and sharing charge between the first capacitor and the second capacitor using a plurality of first switches and second switches, wherein the plurality of first switches are connected between the first capacitor and the second capacitor, and between the first capacitor and the first current source, the second switch is connected between the first capacitor and the amplification circuit, the first switch and the second switch are switched on and off complementaryly, and the second capacitor supplies the second voltage generated by sharing charge with the first capacitor when the first switch is on to the first current source as the first feedback signal, and is connected to the second current source.

19. The common-mode feedback method according to claim 16, wherein generating the second feedback signal includes feeding it back to the second current source via the capacitance between the differential outputs of the fully differential amplifier.

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