Display device and electronic device including demultiplexer circuit

Abstract

A display device includes a display panel including a plurality of data lines and a plurality of pixels connected to the plurality of data lines, a data driver including an output channel that outputs a data voltage, and a demultiplexer circuit that selectively connects the output channel to two or more data lines among the plurality of data lines in response to first and second switching signals. The output channel includes a source output buffer that outputs a data voltage, and a zero control circuit that selectively applies a zero control resistor to an output load of the source output buffer in response to a zero control enable signal and a source output enable signal. Accordingly, the phase margin of the source output buffer may be improved, and the stability of the data driver may be improved.

Description

Display device and electronic device including a demultiplexer circuit

[0001] Embodiments of the present invention relate to a display device including a demultiplexer circuit and an electronic device including said display device.

[0002] A demultiplexing driving technology has been developed to selectively connect each output channel to two or more data lines using a demultiplexer circuit in order to reduce the number of output channels of a data driver. The demultiplexer circuit can sequentially connect each output channel to two or more data lines in a time-division manner within each horizontal time. Accordingly, a display device to which the demultiplexing driving technology is applied can have fewer output channels than the number of data lines.

[0003] The information disclosed in the background section above is intended to aid in understanding the background of the present disclosure and may therefore include information that does not constitute prior art.

[0004] One objective of the present invention is to provide a display device including a data driver having enhanced stability.

[0005] Another objective of the present invention is to provide an electronic device including the above-mentioned display device.

[0006] However, the problem to be solved by the present invention is not limited to the problem mentioned above, and may be expanded in various ways without departing from the spirit and scope of the present invention.

[0007] In a display device with demultiplexing driving technology, when a source output buffer included in an output channel is not connected to a data line, the output load of the source output buffer is reduced, the phase margin is reduced, and the possibility of oscillation of the source output buffer may be increased.

[0008] To achieve one objective of the present invention, a display device according to embodiments of the present invention comprises a display panel including a plurality of data lines and a plurality of pixels connected to the plurality of data lines, a data driver including an output channel that outputs a data voltage, and a demultiplexer circuit that selectively connects the output channel to two or more of the plurality of data lines in response to first and second switching signals. The output channel includes a source output buffer that outputs the data voltage, and a zero control circuit that selectively applies a zero control resistor to the output load of the source output buffer in response to a zero control enable signal and a source output enable signal.

[0009] In one embodiment, the zero-point control circuit may be configured to apply the zero-point control resistor to the output load of the source output buffer in a section where the output channel is not connected to the two or more data lines.

[0010] In one embodiment, the zero point control circuit may be configured to move the zero point of the source output buffer in the low frequency direction during the interval in which the output channel is not connected to the two or more data lines.

[0011] In one embodiment, the zero-point control circuit may include a source output enable transistor connected between the output terminal of the source output buffer and the demultiplexer circuit and turned on in response to the source output enable signal, the zero-point control resistor connected to the demultiplexer circuit, and a zero-point control enable transistor connected in series with the zero-point control resistor between the output terminal of the source output buffer and the demultiplexer circuit and turned on in response to the zero-point control enable signal.

[0012] In one embodiment, the plurality of pixels are arranged in a plurality of pixel rows, and the horizontal time for each of the plurality of pixel rows may include a first section in which both the first switching signal and the second switching signal have an off-level, a second section in which the first switching signal has an on-level and the second switching signal has the off-level, a third section in which both the first switching signal and the second switching signal have the off-level, a fourth section in which the first switching signal has the off-level and the second switching signal has the on-level, and a fifth section in which both the first switching signal and the second switching signal have the off-level.

[0013] In one embodiment, the plurality of data lines includes a first data line and a second data line, and the demultiplexer circuit may include a first switch that connects the output channel to the first data line in response to the first switching signal having the on-level in the second section, and a second switch that connects the output channel to the second data line in response to the second switching signal having the on-level in the fourth section. The demultiplexer circuit may be configured not to connect the output channel to the first and second data lines in the first, third, and fifth sections.

[0014] In one embodiment, the zero-point control enable signal may have an on-level in the first, second, third, fourth, and fifth intervals, and the source output enable signal may have an off-level in the first, third, and fifth intervals and an on-level in the second and fourth intervals.

[0015] In one embodiment, in the second and fourth sections, the zero-point control enable transistor may be configured to be turned on, and the zero-point control resistor may not be applied to the output load of the source output buffer. In the first, third, and fifth sections, the zero-point control enable transistor may be configured to be turned off, and the zero-point control resistor may be applied to the output load of the source output buffer.

[0016] In one embodiment, the source output buffer may include a first amplifier, a second amplifier having an input terminal connected to the output terminal of the first amplifier, and a first capacitor connected between the input terminal of the second amplifier and the output terminal of the second amplifier.

[0017] In one embodiment, the source output buffer may be configured to control the impedance of the source output buffer in response to a capacitance control signal.

[0018] In one embodiment, the source output buffer may be configured to increase the impedance of the source output buffer in the interval where the output channel is not connected to the two or more data lines.

[0019] In one embodiment, the source output buffer may be configured to shift the dominant pole of the source output buffer in the low-frequency direction during the interval in which the output channel is not connected to the two or more data lines.

[0020] In one embodiment, the source output buffer may include a first amplifier, a second amplifier having an input terminal connected to an output terminal of the first amplifier, a first capacitor connected between the input terminal of the second amplifier and the output terminal of the second amplifier, a second capacitor connected to the output terminal of the second amplifier, and a capacitance control transistor connected in series with the second capacitor between the input terminal of the second amplifier and the output terminal of the second amplifier and turned on in response to a capacitance control signal.

[0021] In one embodiment, the plurality of pixels are arranged in a plurality of pixel rows, and the horizontal time for each of the plurality of pixel rows may include a first section in which both the first switching signal and the second switching signal have an off-level, a second section in which the first switching signal has an on-level and the second switching signal has the off-level, a third section in which both the first switching signal and the second switching signal have the off-level, a fourth section in which the first switching signal has the off-level and the second switching signal has the on-level, and a fifth section in which both the first switching signal and the second switching signal have the off-level. The capacitance control signal may have an on-level in the first, third, and fifth sections and an off-level in the second and fourth sections. The above-described capacitance control transistor may be configured to connect the second capacitor to the input terminal of the second amplifier in response to the capacitance control signal having the on-level in the first, third, and fifth intervals.

[0022] To achieve one objective of the present invention, a display device according to embodiments of the present invention comprises a display panel including a plurality of data lines and a plurality of pixels connected to the plurality of data lines, a data driver including an output channel for outputting a data voltage, and a demultiplexer circuit that selectively connects the output channel to two or more of the plurality of data lines in response to switching signals. The output channel includes a source output buffer for outputting the data voltage. The source output buffer is configured to control the impedance of the source output buffer in response to a capacitance control signal.

[0023] In one embodiment, the source output buffer may be configured to increase the impedance of the source output buffer in the interval where the output channel is not connected to the two or more data lines.

[0024] In one embodiment, the source output buffer may be configured to shift the dominant pole of the source output buffer in the low-frequency direction during the interval in which the output channel is not connected to the two or more data lines.

[0025] In one embodiment, the source output buffer may include a first amplifier, a second amplifier having an input terminal connected to an output terminal of the first amplifier, a first capacitor connected between the input terminal of the second amplifier and the output terminal of the second amplifier, a second capacitor connected to the output terminal of the second amplifier, and a capacitance control transistor connected in series with the second capacitor between the input terminal of the second amplifier and the output terminal of the second amplifier and turned on in response to a capacitance control signal.

[0026] In one embodiment, the output channel may further include a zero-point control circuit that selectively applies a zero-point control resistor to the output load of the source output buffer in response to a zero-point control enable signal and a source output enable signal. The zero-point control circuit may include a source output enable transistor connected between the output terminal of the source output buffer and the demultiplexer circuit and turned on in response to the source output enable signal, the zero-point control resistor connected to the demultiplexer circuit, and a zero-point control enable transistor connected in series with the zero-point control resistor between the output terminal of the source output buffer and the demultiplexer circuit and turned on in response to the zero-point control enable signal.

[0027] To achieve another objective of the present invention, an electronic device according to embodiments of the present invention includes a processor that provides input image data, and a display device that receives the input image data from the processor and displays an image based on the input image data. The display device includes a display panel comprising a plurality of data lines and a plurality of pixels connected to the plurality of data lines, a data driver comprising an output channel that outputs a data voltage, and a demultiplexer circuit that selectively connects the output channel to two or more of the plurality of data lines in response to first and second switching signals. The output channel includes a source output buffer that outputs the data voltage, and a zero control circuit that selectively applies a zero control resistor to the output load of the source output buffer in response to a zero control enable signal and a source output enable signal. The source output buffer is configured to control the impedance of the source output buffer in response to a capacitance control signal.

[0028] However, the present disclosure is not limited to the above aspects and features, and the above and additional aspects and features are partially described in the following detailed description with reference to the drawings, some of which become obvious therefrom or can be understood by practicing one or more embodiments of the present disclosure.

[0029] In a display device and electronic device according to embodiments of the present invention, an output channel of a data driver may include a zero-point control circuit that selectively applies a zero-point control resistor to an output load of a source output buffer included in the output channel in response to a zero-point control enable signal and a source output enable signal. Accordingly, the phase margin of the source output buffer and the stability of the data driver can be improved without increasing the settling time of the source output buffer.

[0030] In addition, in a display device and an electronic device according to embodiments of the present invention, a source output buffer included in an output channel of a data driver can control the impedance of the source output buffer in response to a capacitance control signal. Accordingly, the phase margin of the source output buffer can be improved and the stability of the data driver can be improved without increasing the settling time of the source output buffer.

[0031] However, the effects of the present invention are not limited to the effects mentioned above and may be extended in various ways without departing from the spirit and scope of the present invention.

[0032] FIG. 1 is a block diagram showing a display device according to embodiments of the present invention.

[0033] FIG. 2 is a drawing showing an example of a display panel and a demultiplexer circuit according to embodiments of the present invention.

[0034] FIG. 3a is a circuit diagram showing an example of an output load model of a source output buffer in a display device that does not include a zero-point control circuit, and FIG. 3b is a timing diagram to explain an example of an output load of a source output buffer in a display device that does not include a zero-point control circuit.

[0035] FIG. 4 is a circuit diagram showing an example of an output channel of a data driver according to embodiments of the present invention.

[0036] FIG. 5 is a timing diagram for illustrating an example of the output load of a source output buffer in a display device according to embodiments of the present invention.

[0037] FIG. 6 is a drawing for explaining an example of a phase margin of a source output buffer in a display device that does not include a zero-point control circuit, and an example of a phase margin of a source output buffer in a display device according to embodiments of the present invention.

[0038] FIG. 7 is a block diagram showing a display device according to other embodiments of the present invention.

[0039] FIG. 8 is a circuit diagram showing an example of an output channel of a data driver according to other embodiments of the present invention.

[0040] FIG. 9 is a timing diagram illustrating an example of the impedance of a source output buffer in a display device according to other embodiments of the present invention.

[0041] FIG. 10 is a drawing for illustrating an example of a phase margin of a source output buffer in a display device that does not include a zero-point control circuit, and an example of a phase margin of a source output buffer in a display device according to other embodiments of the present invention.

[0042] FIG. 11 is a block diagram showing a display device according to other embodiments of the present invention.

[0043] FIG. 12 is a circuit diagram showing an example of an output channel of a data driver according to other embodiments of the present invention.

[0044] FIG. 13 is a timing diagram illustrating an example of the output load and impedance of a source output buffer in a display device according to other embodiments of the present invention.

[0045] FIG. 14 is a drawing for illustrating an example of a phase margin of a source output buffer in a display device that does not include a zero-point control circuit, and an example of a phase margin of a source output buffer in a display device according to other embodiments of the present invention.

[0046] FIG. 15 is a block diagram of an electronic device according to one embodiment.

[0047] FIG. 16 is a schematic diagram of an electronic device according to various embodiments.

[0048] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions of identical components are omitted.

[0049] FIG. 1 is a block diagram showing a display device according to embodiments of the present invention, FIG. 2 is a diagram showing an example of a display panel and a demultiplexer circuit according to embodiments of the present invention, FIG. 3a is a circuit diagram showing an example of an output load model of a source output buffer in a display device not including a zero-point control circuit, FIG. 3b is a timing diagram for explaining an example of an output load of a source output buffer in a display device not including a zero-point control circuit, FIG. 4 is a circuit diagram showing an example of an output channel of a data driver according to embodiments of the present invention, FIG. 5 is a timing diagram for explaining an example of an output load of a source output buffer in a display device according to embodiments of the present invention, FIG. 6 is a diagram for explaining an example of a phase margin of a source output buffer in a display device not including a zero-point control circuit, and an example of a phase margin of a source output buffer in a display device according to embodiments of the present invention.

[0050] Referring to FIG. 1, a display device (100) according to embodiments of the present invention may include a display panel (110) comprising a plurality of data lines (DL1, DL2) and a plurality of pixels (PX) connected to the plurality of data lines (DL1, DL2), a data driver (120) that provides data voltages (DV) to the plurality of pixels (PX), and a demultiplexer circuit (130) connected between the data driver (120) and the plurality of data lines (DL1, DL2). In one embodiment, as shown in FIG. 1, the display device (100) may further include a scan driver (140) that provides scan signals (SS) to the plurality of pixels (PX), a light-emitting driver (150) that provides light-emitting signals (EM) to the plurality of pixels (PX), and a controller (160) that controls the data driver (120), the demultiplexer circuit (130), the scan driver (140), and the light-emitting driver (150).

[0051] A display panel (110) may include a plurality of data lines (DL1, DL2), a plurality of scan lines, a plurality of light-emitting lines, and a plurality of pixels (PX) connected to the plurality of data lines (DL1, DL2), the plurality of scan lines, and the plurality of light-emitting lines. In one embodiment, each pixel (PX) includes a light-emitting element, and the display panel (110) may be a light-emitting display panel. The light-emitting element may be an Organic Light Emitting Diode (OLED), but is not limited thereto. For example, the light-emitting element may be a Nano Light Emitting Diode (NED), a Quantum Dot (QD) Light Emitting Diode, a Micro Light Emitting Diode, an Inorganic Light Emitting Diode, or any other suitable light-emitting element. However, the display panel (110) is not limited to the light-emitting display panel and may be any suitable display panel.

[0052] The data driver (120) can generate data voltages (DV) based on output image data (ODAT) and a data control signal (DCTRL) received from the controller (160), and provide the data voltages (DV) to a plurality of pixels (PX) through a plurality of source output lines (SL), a demultiplexer circuit (130), and a plurality of data lines (DL1, DL2). In one embodiment, the data control signal (DCTRL) may include an output data enable signal, a horizontal start signal, and a load signal, but is not limited thereto. Additionally, the data driver (120) may include a plurality of output channels (OC) that generate and output data voltages (DV). Each output channel (OC) may include, but is not limited to, a digital-to-analog converter (DAC) that converts output image data (ODAT) for a pixel (PX) into a data voltage (DV), a source output buffer (SOB) that outputs the data voltage (DV), and a zero control circuit (ZCC) that selectively applies (or adds) a zero control resistor to the output load of the source output buffer (SOB). For example, the data driver (120) may further include a shift register that generates sampling signals, and each output channel (OC) may further include, but is not limited to, a sampling latch that samples the output image data (ODAT) in response to one of the corresponding sampling signals, and a holding latch that stores the output image data (ODAT) sampled by the sampling latch. In one embodiment, the data driver (120) and the controller (160) may be implemented as a single integrated circuit, and such integrated circuit may be called a timing controller embedded data driver (TED). In another embodiment, the data driver (120) and the controller (160) may each be implemented as separate integrated circuits.

[0053] The demultiplexer circuit (130) can selectively connect multiple source output lines (SL) connected to multiple output channels (OC) to multiple data lines (DL1, DL2) of the display panel (110) in response to switching signals (SWS). That is, the demultiplexer circuit (130) can perform a demultiplexing operation in which each output channel (OC) is selectively connected to two or more data lines (DL1, DL2) in response to switching signals (SWS). Accordingly, the number of multiple output channels (OC) of the data driver (120) is less than the number of multiple data lines (DL1, DL2) of the display panel (110), and the size of the data driver (120) can be reduced compared to the size of the data driver of a display device that does not include the demultiplexer circuit (130). In one embodiment, the demultiplexer circuit (130) may perform a 1:2 demultiplexing operation in which each output channel (OC) is selectively connected to two data lines (DL1, DL2). In another embodiment, the demultiplexer circuit (130) may perform a 1:N demultiplexing operation in which each output channel (OC) is selectively connected to N data lines (N is an integer greater than or equal to 3). Additionally, in one embodiment, as illustrated in FIG. 1, the demultiplexer circuit (130) may be integrated or formed in the display panel (110). In another embodiment, the demultiplexer circuit (130) may be included in the data driver (120) or implemented within the integrated circuit in which the data driver (120) is formed.

[0054] In one embodiment, to selectively connect each output channel (OC) (or source output line (SL) connected to each output channel (OC)) to two or more data lines (DL1, DL2), as shown in FIG. 2, the demultiplexer circuit (130) may include a plurality of first switches (SW1) that connect a plurality of output channels (OC) (or a plurality of source output lines (SL) connected to a plurality of output channels (OC)) to the first data lines (DL1) among the plurality of data lines (DL1, DL2) in response to a first switching signal (SWS1), and a plurality of second switches (SW2) that connect a plurality of output channels (OC) to the second data lines (DL2) among the plurality of data lines (DL1, DL2) in response to a second switching signal (SWS2). While the first switching signal (SWS1) is at an on-level (e.g., a low level), the first switch (SW1) connects the source output line (SL) of the output channel (OC) to the first data line (DL1), and the output channel (OC) can provide a data voltage (DV) to a pixel (PX) connected to the first data line (DL1). Additionally, while the second switching signal (SWS2) is at the on-level, the second switch (SW2) connects the source output line (SL) of the output channel (OC) to the second data line (DL2), and the output channel (OC) can provide a data voltage (DV) to a pixel (PX) connected to the second data line (DL2). Additionally, while both of the first and second switching signals (SWS1, SWS2) are off-level (e.g., high level), the source output line (SL) of each output channel (OC) may not be connected to both of the first and second data lines (DL1, DL2). In one embodiment, as shown in FIG. 2, a plurality of first switches (SW1) and a plurality of second switches (SW2) may be implemented with PMOS (P-type Metal-Oxide-Semiconductor) transistors, but are not limited thereto.In another embodiment, a plurality of first switches (SW1) and a plurality of second switches (SW2) may be implemented with NMOS (N-type Metal-Oxide-Semiconductor) transistors.

[0055] Referring again to FIG. 1, the scan driver (140) can generate scan signals (SS) based on a scan control signal (SCTRL) received from the controller (160) and provide scan signals (SS) to a plurality of pixels (PX) through the plurality of scan lines. In one embodiment, the scan control signal (SCTRL) may include a scan start signal and a scan clock signal, but is not limited thereto. Also, in one embodiment, the scan driver (140) may be integrated or formed in the display panel (110). In another embodiment, the scan driver (140) may be implemented with one or more integrated circuits.

[0056] The light-emitting driver (150) can generate light-emitting signals (EM) based on a light-emitting control signal (EMCTRL) received from the controller (160) and provide light-emitting signals (EM) to a plurality of pixels (PX) through the plurality of light-emitting lines. In one embodiment, the light-emitting control signal (EMCTRL) may include a light-emitting start signal and a light-emitting clock signal, but is not limited thereto. Also, in one embodiment, the light-emitting driver (150) may be integrated or formed in the display panel (110). In another embodiment, the light-emitting driver (150) may be implemented with one or more integrated circuits.

[0057] A controller (160) (e.g., a timing controller) may receive input image data (IDAT) and a control signal (CTRL) from an external processor (e.g., an Application Processor (AP), a Graphics Processing Unit (GPU), or a Graphics Card). In one embodiment, the control signal (CTRL) may include a horizontal synchronization signal (HSYNC) that defines the horizontal time assigned to each pixel row of the display panel (110). Here, the horizontal time is the time assigned to one row of a plurality of pixels (PX) of the display panel (110), and may correspond to the time obtained by dividing one frame interval by the number of pixel rows of the display panel (110). Additionally, the control signal (CTRL) may include, but is not limited to, a vertical synchronization signal, an input data enable signal, a master clock signal, etc. The controller (150) can generate output image data (ODAT), data control signal (DCTRL), scan control signal (SCTRL), light emission control signal (EMCTRL), and switching signals (SWS) based on input image data (IDAT) and control signal (CTRL). Additionally, the controller (150) can control the data driver (120) by providing the output image data (ODAT) and data control signal (DCTRL) to the data driver (120), control the scan driver (140) by providing the scan control signal (SCTRL) to the scan driver (140), control the light emission driver (150) by providing the light emission control signal (EMCTRL) to the light emission driver (150), and control the demultiplexer circuit (130) by providing the switching signals (SWS) to the demultiplexer circuit (130).

[0058] Meanwhile, in a display device that does not include a zero-point control circuit (ZCC), in the section where the output channel (OC) is not connected to the data lines (DL1, DL2), the output load of the source output buffer (SOB) is reduced, the phase margin of the source output buffer (SOB) is reduced, and the possibility of oscillation of the source output buffer (SOB) may be increased. FIG. 3a shows an example of an output load model (OLM) of the source output buffer (SOB) in a display device that does not include a zero-point control circuit (ZCC), and FIG. 3b shows an example of a horizontal synchronization signal (HSYNC), a first switching signal (SWS1), a second switching signal (SWS2), and an output load (OUTPUT LOAD) of the source output buffer (SOB) in the display device that does not include a zero-point control circuit (ZCC). For example, as illustrated in FIGS. 3a and 3b, a horizontal synchronization signal (HSYNC) defines a horizontal time (HT) assigned to each pixel row of a display panel (110), and a first switching signal (SWS1) and a second switching signal (SWS2) may sequentially have an on-level (e.g., a low level) within the horizontal time (HT). In the interval where the first switching signal (SWS1) or the second switching signal (SWS2) has the above-mentioned on-level, the output terminal of the source output buffer (SOB) may be connected to the source output line resistor (RSL) of the source output line (SL), the source output line capacitor (CSL) of the source output line (SL), the turn-on resistor (RTFT) of the switch (SW) of the demultiplexer circuit (130) (e.g., the first switch (SW1) or the second switch (SW2)), the data line resistor (RDL) of the data line (e.g., the first data line (DL1) or the second data line (DL2)), and the data line capacitor (CDL) of the data line.Meanwhile, in the output load model (OLM), the data line resistor (RDL) may be modeled as three resistors (RDL / 3), and the data line capacitor (CDL) may be modeled as four capacitors (CDL / 6, CDL / 3) connected to the terminals of the three resistors (RDL / 3), but is not limited thereto. Accordingly, in the interval where the first switching signal (SWS1) or the second switching signal (SWS2) has the above-mentioned ON-level, the output load of the source output buffer (SOB) may be “RSLⅩCSL + RTFT + RDLⅩCDL”. However, in the interval where both the first and second switching signals (SWS1, SWS2) have an off-level (e.g., a high level), the switch (SW) of the demultiplexer circuit (130) is turned off, and the output terminal of the source output buffer (SOB) can be connected only to the source output line resistor (RSL) and the source output line capacitor (CSL). Accordingly, in the interval where both the first and second switching signals (SWS1, SWS2) have the off-level, the output load of the source output buffer (SOB) can be reduced to “RSL × CSL”. Additionally, when the output load of the source output buffer (SOB) is reduced, the phase margin of the source output buffer (SOB) is reduced, the possibility of oscillation of the source output buffer (SOB) is increased, and the stability of the data driver (120) may be reduced.

[0059] However, in the display device (100) according to embodiments of the present invention, a zero-point control circuit (ZCC) may be included to apply (or add) a zero-point control resistor to the output load of the output buffer (SOB) in the interval where each output channel (OC) of the data driver (120) is not connected to the data lines (DL1, DL2) in order to increase the phase margin of the source output buffer (SOB) and improve the stability of the data driver (120).

[0060] In one embodiment, as illustrated in FIG. 4, the output channel (OC) may include a digital-to-analog converter (DAC) that converts output image data (ODAT) into a data voltage (DV), a source output buffer (SOB) that outputs the data voltage (DV), and a zero control circuit (ZCC) that selectively applies (or adds) a zero control resistor (ZCR) to the output load of the source output buffer (SOB).

[0061] A source output buffer (SOB) may include a first amplifier (AMP1), a second amplifier (AMP2) including an input terminal connected to the output terminal of the first amplifier (AMP1), and a first capacitor (C1) connected between the input terminal of the second amplifier (AMP2) and the output terminal of the second amplifier (AMP2). The first amplifier (AMP1) may include a non-inverting input terminal that receives a data voltage (DV) from a digital-to-analog converter (DAC), and an inverting input terminal connected to the output terminal of the second amplifier (AMP2). Meanwhile, although an example of a source output buffer (SOB) is shown in FIG. 4, the source output buffer (SOB) is not limited to the example of FIG. 4 and may have any configuration.

[0062] The zero control circuit (ZCC) may selectively apply a zero control resistor (ZCR) to the output load of the source output buffer (SOB) in response to a zero control enable signal (SZCE) and a source output enable signal (SSOE). To perform this operation, the zero control circuit (ZCC) may include a source output enable transistor (SOET), a zero control resistor (ZCR), and a zero control enable transistor (ZCET). The source output enable transistor (SOET) is connected between the output terminal of the source output buffer (SOB) (or the output terminal of the second amplifier (AMP2)) and the demultiplexer circuit (130) (or the source output line (SL) connected to the demultiplexer circuit (130)) and may be turned on in response to the source output enable signal (SSOE). The zero-point control resistor (ZCR) and the zero-point control enable transistor (ZCET) may be connected in series between the output terminal of the source output buffer (SOB) (or the output terminal of the second amplifier (AMP2)) and the demultiplexer circuit (130) (or the source output line (SL) connected to the demultiplexer circuit (130). For example, as shown in FIG. 4, the zero-point control enable transistor (ZCET) may be connected between the output terminal of the source output buffer (SOB) and the zero-point control resistor (ZCR), and the zero-point control resistor (ZCR) may be connected between the zero-point control enable transistor (ZCET) and the source output line (SL). The zero-point control enable transistor (ZCET) may be turned on in response to a zero-point control enable signal (SZCE).

[0063] As illustrated in FIG. 5, the horizontal time (HT) defined by the horizontal synchronization signal (HSYNC) may include a first section (P1) in which both the first and second switching signals (SWS1, SWS2) have an off-level (e.g., high level), a second section (P2) in which the first switching signal (SWS1) has an on-level (e.g., low level) and the second switching signal (SWS2) has the off-level, a third section (P3) in which both the first and second switching signals (SWS1, SWS2) have the off-level, a fourth section (P4) in which the first switching signal (SWS1) has the off-level and the second switching signal (SWS2) has the on-level, and a fifth section (P5) in which both the first and second switching signals (SWS1, SWS2) have the off-level. In the second section (P2), the first switch (SW1) can connect the output channel (OC) to the first data line (DL1) in response to the first switching signal (SWS1) having the on-level. In the fourth section (P4), the second switch (SW2) can connect the output channel (OC) to the second data line (DL2) in response to the second switching signal (SWS2) having the on-level. In the first, third, and fifth sections (P1, P3, P5), the demultiplexer circuit (130) may not connect the output channel (OC) to the plurality of data lines (DL1, DL2).

[0064] The zero-point control enable signal (SZCE) has an ON level (e.g., a high level) in all of the first, second, third, fourth, and fifth intervals (P1, P2, P3, P4, P5), and the zero-point control enable transistor (ZCET) can be turned on in all of the first, second, third, fourth, and fifth intervals (P1, P2, P3, P4, P5). In one embodiment, the zero-point control enable signal (SZCE) and the zero-point control enable transistor (ZCET) can be used to enable or disable the function of the zero-point control circuit (ZCC). For example, when the zero-point control enable signal (SZCE) is at an ON level, the zero-point control enable transistor (ZCET) is turned on, the zero-point control resistor (ZCR) is connected to the output terminal of the source output buffer (SOB), and the zero-point control circuit (ZCC) can be enabled. Conversely, when the zero-point control enable signal (SZCE) is at an OFF level (e.g., a low level), the zero-point control enable transistor (ZCET) is turned off, the zero-point control resistor (ZCR) is not connected to the output terminal of the source output buffer (SOB), and the zero-point control circuit (ZCC) can be disabled.

[0065] The source output enable signal (SSOE) may have an off-level (e.g., low level) in the first, third, and fifth intervals (P1, P3, P5) and an on-level (e.g., high level) in the second and fourth intervals (P2, P4). In the second and fourth intervals (P2, P4), the source output enable transistor (SOET) may be turned on in response to the source output enable signal (SSOE) having an on-level. Accordingly, in the second and fourth intervals (P2, P4), the source output buffer (SOB) can provide a data voltage (DV) to the pixel (PX) through the source output enable transistor (SOET), the source output line (SL), the switch (SW) of the demultiplexer circuit (130) (e.g., the first switch (SW1) or the second switch (SW2)) and the data line (e.g., the first data line (DL1) or the second data line (DL2)). Meanwhile, since the source output enable transistor (SOET), which has almost no resistance, is connected in parallel with the zero-point control resistor (ZCR) between the output terminal of the source output buffer (SOB) and the source output line (SL), the zero-point control resistor (ZCR) is ignored, and the zero-point control resistor (ZCR) may not be applied (or added) to the output load (OUTPUT LOAD) of the source output buffer (SOB). Accordingly, in the second and fourth intervals (P2, P4) where a data voltage (DV) is provided to the pixel (PX), the output load of the source output buffer (SOB) may be “RSLⅩCSL + RTFT + RDLⅩCDL”, substantially the same as the output load shown in FIG. 3b in a display device that does not include a zero point control circuit (ZCC). Accordingly, in the second and fourth intervals (P2, P4) where a data voltage (DV) is provided to the pixel (PX), the settling time of the source output buffer (SOB) may not be increased.

[0066] Additionally, in the first, third, and fifth intervals (P1, P3, P5), the source output enable transistor (SOET) is turned off in response to a source output enable signal (SSOE) having an off-level (OFF), and the first and second switches (SW1, SW2) of the demultiplexer circuit (130) can be turned off in response to the first and second switching signals (SWS1, SWS2). Accordingly, in the first, third, and fifth intervals (P1, P3, P5), the output terminal of the source output buffer (SOB) is connected to the zero-point control resistor (ZCR) and the source output line (SL) through the zero-point control enable transistor (ZCET), and the zero-point control resistor (ZCR) can be applied (or added) to the output load (OUTPUT LOAD) of the source output buffer (SOB). Accordingly, in the first, third, and fifth intervals (P1, P3, P5) where the output channel (OC) is not connected to the data lines (DL1, DL2), the output load of the source output buffer (SOB) may be “(ZCR+RSL)ⅩCSL” increased from the output load shown in FIG. 3b in a display device that does not include a zero-point control circuit (ZCC), i.e., “RSLⅩCSL”. Thus, in the first, third, and fifth intervals (P1, P3, P5) where the output channel (OC) is not connected to the data lines (DL1, DL2), the zero-point control circuit (ZCC) may shift the zero of the source output buffer (SOB) in the low-frequency direction and increase the phase margin of the source output buffer (SOB).

[0067] FIG. 6 shows a graph (210) of the gain of a source output buffer (SOB) according to frequency in a display device that does not include a zero-point control circuit (ZCC) in the first, third, and fifth intervals (P1, P3, P5) where the output channel (OC) is not connected to the data lines (DL1, DL2), a graph (230) of the phase margin of a source output buffer (SOB) according to frequency in a display device (100) according to embodiments of the present invention, a graph (250) of the gain of a source output buffer (SOB) according to frequency in a display device (100) according to embodiments of the present invention, and a graph (270) of the phase margin of a source output buffer (SOB) according to frequency in a display device (100) according to embodiments of the present invention. The source output buffer (SOB) of the display device (100) according to embodiments of the present invention may have a first pole (POLE1) and a second pole (POLE2) substantially identical to the source output buffer (SOB) of the display device that does not include a zero point control circuit (ZCC). However, in the display device (100) according to embodiments of the present invention, in the first, third, and fifth sections (P1, P3, P5) where the output channel (OC) is not connected to the data lines (DL1, DL2), the zero point control resistor (ZCR) is applied (or added) to the output load (OUTPUT LOAD) of the source output buffer (SOB), so the zero point (ZERO') of the source output buffer (SOB) of the display device (100) according to embodiments of the present invention may be shifted in the low frequency direction compared to the zero point (ZERO) of the source output buffer (SOB) of the display device that does not include a zero point control circuit (ZCC). Accordingly, at a frequency where the gain of the source output buffer (SOB) is about 0 dB, i.e., a unit gain frequency (UGF), the phase margin (PM2) of the source output buffer (SOB) of the display device (100) according to embodiments of the present invention can be increased from the phase margin (PM1) of the source output buffer (SOB) of the display device that does not include a zero point control circuit (ZCC).Accordingly, in the display device (100) according to the embodiments of the present invention, since the source output buffer (SOB) has an increased phase margin (PM2), the possibility of oscillation of the source output buffer (SOB) is reduced and the stability of the data driver (120) can be improved.

[0068] As described above, in a display device (100) according to embodiments of the present invention, the output channel (OC) of a data driver (120) may include a zero control circuit (ZCC) that selectively applies a zero control resistor (ZCR) to the output load (OUTPUT LOAD) of a source output buffer (SOB) in response to a zero control enable signal (SZCE) and a source output enable signal (SSOE). Accordingly, the phase margin of the source output buffer (SOB) is improved, the possibility of oscillation of the source output buffer (SOB) is reduced, and the stability of the data driver (120) can be improved without increasing the settling time of the source output buffer (SOB).

[0069] FIG. 7 is a block diagram showing a display device according to another embodiment of the present invention, FIG. 8 is a circuit diagram showing an example of an output channel of a data driver according to another embodiment of the present invention, FIG. 9 is a timing diagram for explaining an example of the impedance of a source output buffer in a display device according to another embodiment of the present invention, FIG. 10 is a diagram for explaining an example of a phase margin of a source output buffer in a display device not including a zero-point control circuit, and an example of a phase margin of a source output buffer in a display device according to another embodiment of the present invention.

[0070] Referring to FIGS. 7 and 8, a display device (300) according to other embodiments of the present invention may include a display panel (110), a data driver (320), a demultiplexer circuit (130), a scan driver (140), a light-emitting driver (150), and a controller (160). Each output channel (OC') of the data driver (320) may include a digital-to-analog converter (DAC) and a source output buffer (SOB'). The source output buffer (SOB') may control the impedance of the source output buffer (SOB') in response to a capacitance control signal (SCC). The display device (300) of FIG. 7 may have substantially the same configuration and substantially the same operation as the display device (100) of FIG. 1, except that each output channel (OC') does not include a zero-point control circuit (ZCC) and the source output buffer (SOB') controls the impedance of the source output buffer (SOB').

[0071] As illustrated in FIG. 8, the output channel (OC') may include a digital-to-analog converter (DAC) that converts output image data (ODAT) into a data voltage (DV), and a source output buffer (SOB') that outputs the data voltage (DV). The source output buffer (SOB') may control the impedance of the source output buffer (SOB') in response to a capacitance control signal (SCC). To perform this operation, the source output buffer (SOB') may include a first amplifier (AMP1), a second amplifier (AMP2) having an input terminal connected to the output terminal of the first amplifier (AMP1), a first capacitor (C1) connected between the input terminal of the second amplifier (AMP2) and the output terminal of the second amplifier (AMP2), a second capacitor (C2) connected to the output terminal of the second amplifier (AMP2), and a capacitance control transistor (CCT) connected in series with the second capacitor (C2) between the input terminal of the second amplifier (AMP2) and the output terminal of the second amplifier (AMP2), and turned on in response to a capacitance control signal (SCC). The first amplifier (AMP1) may include a non-inverting input terminal that receives a data voltage (DV) from a digital-to-analog converter (DAC), and an inverting input terminal connected to the output terminal of the second amplifier (AMP2). Accordingly, the second capacitor (C2) may be optionally connected between the input terminal and the output terminal of the second amplifier (AMP2). In one embodiment, the capacitances of the first and second capacitors (C1, C2) connected between the input terminal and the output terminal of the second amplifier (AMP2) may be increased by the second amplifier (AMP2), and the first and second capacitors (C1, C2) may be called Miller capacitors.

[0072] In a display device (300) according to embodiments of the present invention, a capacitance control signal (SCC) has an on-level (e.g., high level) during a period when the output channel (OC') is not connected to data lines (DL1, DL2), and the source output buffer (SOB') can increase the impedance of the source output buffer (SOB') in response to the capacitance control signal (SCC) having the on-level. In one embodiment, during a period when the output channel (OC') is not connected to data lines (DL1, DL2), a second capacitor (C2) is connected between the input terminal and the output terminal of the second amplifier (AMP2), the dominant pole of the source output buffer (SOB') is shifted in the low-frequency direction, the phase margin of the source output buffer (SOB') is increased, and the possibility of oscillation of the source output buffer (SOB') is reduced.

[0073] For example, as illustrated in FIG. 9, a horizontal time (HT) defined by a horizontal synchronization signal (HSYNC) may include a first section (P1) in which both the first and second switching signals (SWS1, SWS2) have an off-level (e.g., high level), a second section (P2) in which the first switching signal (SWS1) has an on-level (e.g., low level) and the second switching signal (SWS2) has the off-level, a third section (P3) in which both the first and second switching signals (SWS1, SWS2) have the off-level, a fourth section (P4) in which the first switching signal (SWS1) has the off-level and the second switching signal (SWS2) has the on-level, and a fifth section (P5) in which both the first and second switching signals (SWS1, SWS2) have the off-level. The demultiplexer circuit (130) may connect the output channel (OC') to the first data line (DL1) or the second data line (DL2) in response to the first switching signal (SWS1) or the second switching signal (SWS2) having the on-level in the second and fourth intervals (P2, P4), and may not connect the output channel (OC') to the data lines (DL1, DL2) in the first, third, and fifth intervals (P1, P3, P5).

[0074] The capacitance control signal (SCC) may have an ON level (e.g., high level) in the first, third, and fifth intervals (P1, P3, P5) and an OFF level (e.g., low level) in the second and fourth intervals (P2, P4). Accordingly, in the second and fourth intervals (P2, P4), the capacitance control transistor (CCT) is turned off in response to the capacitance control signal (SCC) having an OFF level, and the second capacitor (C2) may not be connected to the input terminal of the second amplifier (AMP2). Accordingly, in the second and fourth intervals (P2, P4) where a data voltage (DV) is provided to the pixel (PX), the impedance of the source output buffer (SOB') is not increased by the second capacitor (C2), and the settling time of the source output buffer (SOB') may not be increased.

[0075] Additionally, in the first, third, and fifth intervals (P1, P3, P5), the capacitance control transistor (CCT) is turned on in response to a capacitance control signal (SCC) having an ON level, and the second capacitor (C2) can be connected to the input terminal of the second amplifier (AMP2). Accordingly, in the first, third, and fifth intervals (P1, P3, P5) where the output channel (OC') is not connected to the data lines (DL1, DL2), the impedance of the source output buffer (SOB') can be increased by the second capacitor (C2). In one embodiment, the first capacitor (C1) and the second capacitor (C2) may have substantially the same capacitance. In this case, in the first, third, and fifth intervals (P1, P3, P5), the capacitance of the capacitor connected between the input terminal and the output terminal of the second amplifier (AMP2) can be doubled. Additionally, if the impedance of the source output buffer (SOB') is increased, the dominant pole of the source output buffer (SOB') shifts toward a low frequency direction, and the phase margin of the source output buffer (SOB') can be increased.

[0076] FIG. 10 shows a graph (210) of the gain of a source output buffer (SOB) according to frequency in a display device in which the source output buffer (SOB) does not include a second capacitor (C2) and a capacitance control transistor (CCT) in the first, third, and fifth intervals (P1, P3, P5) in which the output channel (OC') is not connected to the data lines (DL1, DL2), a graph (230) of the phase margin of a source output buffer (SOB) according to frequency in a display device (300) in which the source output buffer (SOB) does not include a second capacitor (C2) and a capacitance control transistor (CCT), a graph (450) of the gain of a source output buffer (SOB') according to frequency in a display device (300) in accordance with embodiments of the present invention, and a graph (470) of the phase margin of a source output buffer (SOB') according to frequency in a display device (300) in accordance with embodiments of the present invention. In a display device (300) according to embodiments of the present invention, in the first, third, and fifth intervals (P1, P3, P5) where the output channel (OC') is not connected to the data lines (DL1, DL2), the impedance of the source output buffer (SOB') is increased by the second capacitor (C2), so the dominant pole of the source output buffer (SOB') (e.g., the first pole (POLE1')) can be shifted in a low frequency direction compared to the first pole (POLE1) of the source output buffer (SOB) that does not include the second capacitor (C2) and the capacitance control transistor (CCT). In one embodiment, as shown in FIG. 10, the second pole (POLE2') and zero (ZERO') of the source output buffer (SOB') may also be shifted in the low frequency direction compared to the second pole (POLE2) and zero (ZERO) of the source output buffer (SOB) that does not include the second capacitor (C2) and the capacitance control transistor (CCT), but are not limited thereto.When the dominant pole of the source output buffer (SOB'), i.e., the first pole (POLE1'), is shifted in the low-frequency direction, the phase margin (PM3) of the source output buffer (SOB') at the unit gain frequency (UGF') can be increased from the phase margin (PM1) of the source output buffer (SOB) that does not include the second capacitor (C2) and the capacitance control transistor (CCT). Accordingly, in the display device (300) according to the embodiments of the present invention, since the source output buffer (SOB') has an increased phase margin (PM3), the possibility of oscillation of the source output buffer (SOB') is reduced, and the stability of the data driver (320) can be improved.

[0077] As described above, in the display device (300) according to embodiments of the present invention, the source output buffer (SOB') can control the impedance (SOB') of the source output buffer (SOB') in response to a capacitance control signal (SCC). Accordingly, the phase margin of the source output buffer (SOB') is improved, the possibility of oscillation of the source output buffer (SOB') is reduced, and the stability of the data driver (320) can be improved without increasing the settling time of the source output buffer (SOB').

[0078] FIG. 11 is a block diagram showing a display device according to another embodiment of the present invention, FIG. 12 is a circuit diagram showing an example of an output channel of a data driver according to another embodiment of the present invention, FIG. 13 is a timing diagram for explaining an example of an output load and impedance of a source output buffer in a display device according to another embodiment of the present invention, FIG. 14 is a diagram for explaining an example of a phase margin of a source output buffer in a display device not including a zero-point control circuit, and an example of a phase margin of a source output buffer in a display device according to another embodiment of the present invention.

[0079] Referring to FIGS. 11 and 12, a display device (500) according to another embodiment of the present invention may include a display panel (110), a data driver (520), a demultiplexer circuit (130), a scan driver (140), a light-emitting driver (150), and a controller (160). Each output channel (OC'') of the data driver (520) may include a digital-to-analog converter (DAC), a source output buffer (SOB'), and a zero-point control circuit (ZCC). The source output buffer (SOB') may control the impedance of the source output buffer (SOB') in response to a capacitance control signal (SCC). The display device (500) of FIG. 11 may have substantially the same configuration and substantially the same operation as the display device (100) of FIG. 1 or the display device (300) of FIG. 7, except that each output channel (OC') includes a zero-point control circuit (ZCC) that controls the output load of the source output buffer (SOB'), and the source output buffer (SOB') controls the impedance of the source output buffer (SOB').

[0080] As illustrated in FIG. 12, the output channel (OC'') may include a digital-to-analog converter (DAC), a source output buffer (SOB'), and a zero-point control circuit (ZCC). The source output buffer (SOB') may include a first amplifier (AMP1), a second amplifier (AMP2), a first capacitor (C1), a second capacitor (C2), and a capacitance control transistor (CCT). The zero-point control circuit (ZCC) may include a source output enable transistor (SOET), a zero-point control resistor (ZCR), and a zero-point control enable transistor (ZCET). The source output buffer (SOB') may control the impedance of the source output buffer (SOB') by selectively connecting the second capacitor (C2) in response to a capacitance control signal (SCC). In addition, the zero control circuit (ZCC) can enable the function of the zero control circuit (ZCC) by turning on the zero control enable transistor (ZCET) in response to the zero control enable signal (SZCE), and can selectively apply (or add) the zero control resistor (ZCR) to the output load of the source output buffer (SOB') by turning on or off the source output enable transistor (SOET) in response to the source output enable signal (SSOE).

[0081] For example, as illustrated in FIG. 13, in the second and fourth intervals (P2, P4) where a data voltage (DV) is provided to a pixel (PX), the capacitance control signal (SCC) has an off-level (OFF) and the source output enable transistor (SOET) has an on-level (ON), the impedance of the source output buffer (SOB') is not increased by the second capacitor (C2), the zero-point control resistor (ZCR) is not applied (or added) to the output load of the source output buffer (SOB'), and the settling time of the source output buffer (SOB') may not be increased. Additionally, in the first, third, and fifth intervals (P1, P3, P5) where the output channel (OC'') is not connected to the data lines (DL1, DL2), the capacitance control signal (SCC) has an ON level, the source output enable transistor (SOET) has an OFF level, the impedance of the source output buffer (SOB') is increased by the second capacitor (C2), the zero point control resistor (ZCR) is applied (or added) to the output load of the source output buffer (SOB'), the dominant pole and zero point of the source output buffer (SOB') are shifted in the low frequency direction, the phase margin of the source output buffer (SOB') is increased, and the possibility of oscillation of the source output buffer (SOB') can be reduced.

[0082] FIG. 14 shows a graph (210) of the gain of a source output buffer (SOB) according to frequency in a display device in which, in the first, third, and fifth intervals (P1, P3, P5) where the output channel (OC'') is not connected to the data lines (DL1, DL2), the output channel (OC'') does not include a zero-point control circuit (ZCC) and the source output buffer (SOB) does not include a second capacitor (C2) and a capacitance control transistor (CCT); a graph (230) of the phase margin of a source output buffer (SOB) according to frequency in a display device (500) according to embodiments of the present invention, a graph (650) of the gain of a source output buffer (SOB') according to frequency in a display device (500) according to embodiments of the present invention, and a source according to frequency in a display device (500). This shows a graph (670) of the phase margin of the output buffer (SOB'). In a display device (500) according to embodiments of the present invention, in the first, third, and fifth sections (P1, P3, P5) where the output channel (OC) is not connected to the data lines (DL1, DL2), the impedance of the source output buffer (SOB') is increased by the second capacitor (C2), so the dominant pole of the source output buffer (SOB'), i.e., the first pole (POLE1'), is shifted in the low frequency direction compared to the first pole (POLE1) of the source output buffer (SOB) that does not include the second capacitor (C2) and the capacitance control transistor (CCT), and since a zero point control resistor (ZCR) is applied (or added) to the output load (OUTPUT LOAD) of the source output buffer (SOB'), the zero point (ZERO'') of the source output buffer (SOB') can be further shifted in the low frequency direction compared to the conventional zero point (ZERO).Accordingly, the phase margin (PM4) of the source output buffer (SOB') at the unit gain frequency (UGF') can be further increased from the conventional phase margin (PM1). Therefore, in the display device (500) according to the embodiments of the present invention, since the source output buffer (SOB') has an increased phase margin (PM4), the possibility of oscillation of the source output buffer (SOB') is reduced, and the stability of the data driver (520) can be improved.

[0083] As described above, in a display device (500) according to embodiments of the present invention, the output channel (OC'') of the data driver (520) includes a zero control circuit (ZCC) that selectively applies a zero control resistor (ZCR) to the output load (OUTPUT LOAD) of the source output buffer (SOB') in response to a zero control enable signal (SZCE) and a source output enable signal (SSOE), and the source output buffer (SOB') can control the impedance (SOB') of the source output buffer (SOB') in response to a capacitance control signal (SCC). Accordingly, the phase margin of the source output buffer (SOB') is improved, the possibility of oscillation of the source output buffer (SOB') is reduced, and the stability of the data driver (520) can be improved without increasing the settling time of the source output buffer (SOB').

[0084] FIG. 15 is a block diagram of an electronic device according to one embodiment.

[0085] Referring to FIG. 15, an electronic device (10) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0086] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0087] The memory (15) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (15), a video data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) can process the received signal and output video information through a display screen.

[0088] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (10).

[0089] At least one of each component of the electronic device (10) described above may be included in a display device according to the embodiments described above (e.g., the display device (100) of FIG. 1, the display device (300) of FIG. 7, or the display device (500) of FIG. 11). Additionally, some of the individual modules functionally included within a single module may be included within the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device.

[0090] FIG. 16 is a schematic diagram of an electronic device according to various embodiments.

[0091] Referring to FIG. 16, various electronic devices to which a display device according to the embodiments is applied may include not only image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a CID (Center Information Display) and room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0092] The present invention may be applied to any display device and electronic device including the same. For example, the present invention may be applied to mobile phones, smartphones, tablet computers, TVs, digital TVs, 3D TVs, PCs, home electronic devices, laptop computers, PDAs, PMPs, digital cameras, music players, portable game consoles, navigation systems, etc.

[0093] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims.

Claims

1. A display panel comprising a plurality of data lines and a plurality of pixels connected to the plurality of data lines; A data driver including an output channel that outputs a data voltage; and It includes a demultiplexer circuit that selectively connects the output channel to two or more of the plurality of data lines in response to first and second switching signals, and The above output channel is, A source output buffer that outputs the above data voltage; and A display device characterized by including a zero-point control circuit that selectively applies a zero-point control resistor to the output load of the source output buffer in response to a zero-point control enable signal and a source output enable signal.

2. A display device according to claim 1, wherein the zero-point control circuit is configured to apply the zero-point control resistor to the output load of the source output buffer in a section where the output channel is not connected to the two or more data lines.

3. A display device according to claim 1, wherein the zero point control circuit is configured to move the zero point of the source output buffer in the low-frequency direction in the interval where the output channel is not connected to the two or more data lines.

4. In claim 1, the zero-point control circuit is, A source output enable transistor connected between the output terminal of the source output buffer and the demultiplexer circuit, and turned on in response to the source output enable signal; The zero-point control resistor connected to the above demultiplexer circuit; and A display device characterized by including a zero-point control enable transistor connected in series with the zero-point control resistor between the output terminal of the source output buffer and the demultiplexer circuit, and turned on in response to the zero-point control enable signal.

5. In claim 4, the plurality of pixels are arranged in a plurality of pixel rows, and the horizontal time for each of the plurality of pixel rows is A first section in which both the first switching signal and the second switching signal have an off-level; A second section in which the first switching signal has an on-level and the second switching signal has an off-level; A third section in which both the first switching signal and the second switching signal have the off-level; A fourth interval in which the first switching signal has the off-level and the second switching signal has the on-level; and A display device characterized by including a fifth interval in which both the first switching signal and the second switching signal have the off-level.

6. In claim 5, the plurality of data lines includes a first data line and a second data line, and The above demultiplexer circuit is, A first switch that connects the output channel to the first data line in response to the first switching signal having the on-level in the second section; and It includes a second switch that connects the output channel to the second data line in response to the second switching signal having the on-level in the fourth section, A display device characterized in that the above demultiplexer circuit is configured not to connect the output channel to the first and second data lines in the first, third, and fifth sections.

7. In claim 5, the zero-point control enable signal has an on-level in the first, second, third, fourth, and fifth intervals, A display device characterized in that the source output enable signal has an off-level in the first, third, and fifth intervals and an on-level in the second and fourth intervals.

8. In claim 7, in the second and fourth intervals, the zero-point control enable transistor is configured to be turned on, and the zero-point control resistor is configured not to be applied to the output load of the source output buffer, and A display device characterized in that, in the first, third, and fifth sections above, the zero-point control enable transistor is configured to be turned off, and the zero-point control resistor is configured to be applied to the output load of the source output buffer.

9. In claim 1, the source output buffer is, First amplifier; A second amplifier including an input terminal connected to the output terminal of the first amplifier; and A display device characterized by including a first capacitor connected between the input terminal of the second amplifier and the output terminal of the second amplifier.

10. A display device according to claim 1, characterized in that the source output buffer is configured to control the impedance of the source output buffer in response to a capacitance control signal.

11. A display device according to claim 10, wherein the source output buffer is configured to increase the impedance of the source output buffer in a section where the output channel is not connected to the two or more data lines.

12. A display device according to claim 10, wherein the source output buffer is configured to shift the dominant pole of the source output buffer in a low-frequency direction during a section in which the output channel is not connected to the two or more data lines.

13. In claim 10, the source output buffer is, First amplifier; A second amplifier including an input terminal connected to the output terminal of the first amplifier; A first capacitor connected between the input terminal of the second amplifier and the output terminal of the second amplifier; A second capacitor connected to the output terminal of the second amplifier; and A display device characterized by including a capacitance control transistor connected in series with the second capacitor between the input terminal of the second amplifier and the output terminal of the second amplifier, and turned on in response to the capacitance control signal.

14. In claim 13, the plurality of pixels are arranged in a plurality of pixel rows, and the horizontal time for each of the plurality of pixel rows is A first section in which both the first switching signal and the second switching signal have an off-level; A second section in which the first switching signal has an on-level and the second switching signal has an off-level; A third section in which both the first switching signal and the second switching signal have the off-level; A fourth interval in which the first switching signal has the off-level and the second switching signal has the on-level; and It includes a fifth interval in which both the first switching signal and the second switching signal have the off-level, and The above capacitance control signal has an on-level in the first, third, and fifth intervals, and an off-level in the second and fourth intervals, and A display device characterized in that the above-described capacitance control transistor is configured to connect the second capacitor to the input terminal of the second amplifier in response to the capacitance control signal having the on-level in the first, third, and fifth intervals.

15. A display panel comprising a plurality of data lines and a plurality of pixels connected to the plurality of data lines; A data driver including an output channel that outputs a data voltage; and It includes a demultiplexer circuit that selectively connects the output channel to two or more of the plurality of data lines in response to switching signals, and The above output channel includes a source output buffer that outputs the data voltage, and A display device characterized in that the source output buffer is configured to control the impedance of the source output buffer in response to a capacitance control signal.

16. A display device according to claim 15, wherein the source output buffer is configured to increase the impedance of the source output buffer in a section where the output channel is not connected to the two or more data lines.

17. A display device according to claim 15, wherein the source output buffer is configured to shift the dominant pole of the source output buffer in a low-frequency direction during a section in which the output channel is not connected to the two or more data lines.

18. In claim 15, the source output buffer is, First amplifier; A second amplifier including an input terminal connected to the output terminal of the first amplifier; A first capacitor connected between the input terminal of the second amplifier and the output terminal of the second amplifier; A second capacitor connected to the output terminal of the second amplifier; and A display device characterized by including a capacitance control transistor connected in series with the second capacitor between the input terminal of the second amplifier and the output terminal of the second amplifier, and turned on in response to the capacitance control signal.

19. In claim 15, the output channel is, It further includes a zero-point control circuit that selectively applies a zero-point control resistor to the output load of the source output buffer in response to a zero-point control enable signal and a source output enable signal, and The above zero-point control circuit is, A source output enable transistor connected between the output terminal of the source output buffer and the demultiplexer circuit, and turned on in response to the source output enable signal; The zero-point control resistor connected to the above demultiplexer circuit; and A display device characterized by including a zero-point control enable transistor connected in series with the zero-point control resistor between the output terminal of the source output buffer and the demultiplexer circuit, and turned on in response to the zero-point control enable signal.

20. A processor that provides input image data; and It includes a display device that receives input image data from the processor and displays an image based on the input image data. The above display device is, A display panel comprising a plurality of data lines and a plurality of pixels connected to the plurality of data lines; A data driver including an output channel that outputs a data voltage; and It includes a demultiplexer circuit that selectively connects the output channel to two or more of the plurality of data lines in response to first and second switching signals, and The above output channel is, A source output buffer that outputs the above data voltage; and It includes a zero-point control circuit that selectively applies a zero-point control resistor to the output load of the source output buffer in response to a zero-point control enable signal and a source output enable signal, and An electronic device characterized in that the source output buffer is configured to control the impedance of the source output buffer in response to a capacitance control signal.

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