Display device, manufacturing method therefor, and electronic device comprising same

Abstract

An embodiment of the present invention provides a display device comprising: a substrate; a thin film transistor on the substrate; an interlayer insulating layer on the thin film transistor; and signal lines located on the interlayer insulating layer and electrically connected to the thin film transistor, wherein the interlayer insulating layer includes an uneven portion on a surface thereof between the signal lines.

Description

Display device, method of manufacturing the same, and electronic device including the same

[0001] The present disclosure relates to a display device, a method for manufacturing the same, and / or an electronic device comprising the same.

[0002] Display devices, such as organic light-emitting display devices and liquid crystal display devices, may be fabricated on a substrate having a pattern formed thereon, which includes at least one thin film transistor (TFT) and a capacitor, and wiring connecting them for driving. Here, the thin film transistor may include an active layer providing a channel region, a source region, and a drain region, and a gate electrode electrically insulated from the active layer by a gate insulating layer.

[0003] As the resolution of a display device increases, the spacing between the wires connected to the source region, drain region, and gate electrode narrows, leading to a problem where it becomes more susceptible to current leakage.

[0004] The aforementioned background technology is technical information that the inventor possessed for the derivation of the present invention or acquired during the process of deriving the present invention, and it cannot be considered as prior art disclosed to the general public prior to the filing of the present invention.

[0005] Embodiments of the present invention may provide a display device, a method for manufacturing the same, and an electronic device including the same, wherein surface resistance between wires is increased, current leakage is mitigated and prevented, and reliability is improved by arranging irregularities in an insulating layer between wires connected to a source region, a drain region, and a gate electrode, respectively.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other problems and advantages of the present invention not mentioned can be understood from the following description and will be more clearly understood by the embodiments of the present invention. Furthermore, it will be understood that the problems and advantages that the present invention aims to solve can be realized by the means and combinations thereof set forth in the claims.

[0007] One embodiment of the present invention discloses a display device comprising: a substrate; a thin-film transistor on the substrate; an interlayer insulating film on the thin-film transistor; and signal lines located on the interlayer insulating film and electrically connected to the thin-film transistor, wherein the interlayer insulating film includes an uneven surface between the signal lines.

[0008] According to one embodiment of the present invention, by arranging irregularities in an insulating layer between wirings connected to a source region, a drain region, and a gate electrode, respectively, the surface resistance between the wirings is increased, current leakage is mitigated and prevented, and reliability is improved. A display device, a method for manufacturing the same, and an electronic device including the same can be realized.

[0009] However, the effects obtainable through the present invention are not limited to those described above, and other unmentioned technical effects will be clearly understood by those skilled in the art from the description of the invention below.

[0010] The following drawings attached to this specification illustrate preferred embodiments of the present invention and serve to further enhance understanding of the technical concept of the present invention together with the detailed description of the invention provided below; therefore, the present invention should not be interpreted as being limited only to the matters described in such drawings.

[0011] FIG. 1 is a schematic plan view illustrating an example of a display device according to an embodiment of the present invention.

[0012] Figure 2 is a block diagram schematically showing the structure of the display device of Figure 1.

[0013] Figure 3 is an equivalent circuit diagram of one subpixel of the display device of Figure 1.

[0014] FIG. 4 is a schematic cross-sectional view illustrating an example of the II' section of FIG. 1.

[0015] Figure 5 is an enlarged view schematically illustrating an example of A in Figure 4.

[0016] Figure 6 is an enlarged view schematically illustrating an example of B in Figure 5.

[0017] Figure 7 is an enlarged view schematically illustrating another example of B in Figure 5.

[0018] Figure 8 is an enlarged view schematically illustrating another example of B in Figure 5.

[0019] Figure 9 is an enlarged view schematically illustrating another example of B in Figure 5.

[0020] FIGS. 10 to 17 are cross-sectional views schematically illustrating a method for manufacturing a display device according to one embodiment of the present invention.

[0021] FIG. 18 is a block diagram of an electronic device according to embodiments of the present invention.

[0022] FIG. 19 is a schematic diagram of an electronic device according to various embodiments.

[0023] One embodiment of the present invention discloses a display device comprising: a substrate; a thin-film transistor on the substrate; an interlayer insulating film on the thin-film transistor; and signal lines located on the interlayer insulating film and electrically connected to the thin-film transistor, wherein the interlayer insulating film includes an uneven surface between the signal lines.

[0024] In this embodiment, the thin-film transistor may include: a semiconductor layer comprising a channel region and source and drain regions respectively disposed on both sides of the channel region; and a gate electrode positioned overlapping the channel region with a gate insulating film in between.

[0025] In this embodiment, the signal lines include a first signal line that applies a gate signal to the gate electrode, a second signal line that is electrically connected to the source region, and a third signal line that is electrically connected to the drain region, and the interlayer insulating film may include the uneven surface between the first signal line, the second signal line, and the third signal line.

[0026] In this embodiment, the uneven surface may include at least one concave portion.

[0027] In this embodiment, the depth of the concave portion may be 500 Å or more and 1000 Å or less.

[0028] In the present embodiment, the at least one concave portion may include two or more concave portions having different depths, two or more concave portions having different widths, or two or more concave portions having different depths and different widths.

[0029] In this embodiment, the interlayer insulating film may further include an additional insulating film covering the uneven portion.

[0030] In this embodiment, the thickness of the additional insulating film may be 500 Å or more and 1000 Å or less.

[0031] In this embodiment, the dielectric constant of the additional insulating film may be at least 4 or less.

[0032] Another embodiment of the present invention discloses a method for manufacturing a display device comprising the steps of: sequentially forming a semiconductor layer, an interlayer insulating film, and a gate electrode on a substrate to form a thin-film transistor; forming an interlayer insulating film on the thin-film transistor; forming irregularities on the surface of the interlayer insulating film; and forming signal lines electrically connected to the thin-film transistor on the interlayer insulating film.

[0033] In this embodiment, the step of forming the irregular portion on the surface of the interlayer insulating film may include: a step of forming a photoresist layer by coating a photoresist material on the interlayer insulating film; a step of forming a photoresist pattern on the photoresist layer using a half-tone mask; and a step of patterning the interlayer insulating film using the photoresist pattern as a mask.

[0034] In this embodiment, in the step of forming the photoresist pattern, an exposure process and a development process may be performed on the photoresist material.

[0035] In this embodiment, the uneven surface may be located between the signal wires.

[0036] In this embodiment, between the step of forming the thin-film transistor and the step of forming the interlayer insulating film, the step of forming a source region and a drain region by doping impurities into the semiconductor layer using the gate electrode as a mask may be further included.

[0037] In this embodiment, the signal lines include a first signal line that applies a gate signal to the gate electrode, a second signal line that is electrically connected to the source region, and a third signal line that is electrically connected to the drain region, and the uneven surface may be formed on the surface of the interlayer insulating film between the first signal line, the second signal line, and the third signal line.

[0038] In this embodiment, the step of forming an additional insulating film on the interlayer insulating film between the signal wires may be further included.

[0039] In this embodiment, the step of forming the additional insulating film may include: coating a photoresist material on the signal lines; depositing an additional insulating material on the photoresist material and the interlayer insulating film; and removing the photoresist material.

[0040] In this embodiment, the thickness of the additional insulating film may be 500 Å or more and 1000 Å or less.

[0041] In this embodiment, the uneven surface may include at least one concave portion.

[0042] In this embodiment, the depth of the concave portion may be 500 Å or more and 1000 Å or less.

[0043] Another embodiment of the present invention discloses an electronic device comprising: an input module; a memory for storing at least one program; a processor that operates by executing the at least one program; a display device; and a power module that supplies power to the display device; wherein the processor controls the input module to acquire data and controls the display device to visually display the data, and the display device comprises: a substrate; a thin-film transistor on the substrate; an interlayer insulating film on the thin-film transistor; and signal lines located on the interlayer insulating film and electrically connected to the thin-film transistor; and wherein the interlayer insulating film includes an uneven surface between the signal lines.

[0044] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0045] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0046] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0047] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0048] In the following embodiments, when a part such as a unit, area, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another unit, area, or component is interposed in between.

[0049] In the following embodiments, terms such as "connect" or "combine" do not necessarily imply a direct and / or fixed connection or combination of two members unless the context clearly indicates otherwise, nor do they exclude the interposition of another member between the two members.

[0050] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and / or thickness of each component shown in the drawings are arbitrarily depicted for convenience of explanation, and therefore the present invention is not necessarily limited to what is illustrated.

[0051] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0052] FIG. 1 is a plan view schematically illustrating an example of a display device according to an embodiment of the present invention, FIG. 2 is a block diagram schematically showing the structure of the display device of FIG. 1, and FIG. 3 is an equivalent circuit diagram of a subpixel of the display device of FIG. 1.

[0053] First, referring to FIGS. 1 and FIGS. 2, a display device (10) according to one embodiment of the present invention may include a substrate (100) comprising a display area (DA) for displaying an image and a peripheral area (PA) located outside the display area (DA).

[0054] In the display area (DA), a plurality of scan lines (SL1, ..., SLn) extended along a first direction (x), a plurality of data lines (DL1, ..., DLm) extended along a second direction (y) perpendicularly intersecting the first direction (x), and a plurality of subpixels (PX) may be located. In this case, m and n are each natural numbers.

[0055] Wiring capable of applying electrical signals to a plurality of subpixels (PX) may include a plurality of scan lines (SL1, ..., SLn), a plurality of data lines (DL1, ..., DLm), etc. The plurality of scan lines (SL1, ..., SLn) may be arranged in a plurality of rows extending in a first direction (x), for example, to transmit scan signals to the subpixels (PX), and the plurality of data lines (DL1, ..., DLm) may be arranged in a plurality of columns extending in a second direction (y), for example, to transmit data signals to the subpixels (PX), and the plurality of subpixels (PX) may be located at the intersection of the plurality of scan lines (SL1, ..., SLn) and the plurality of data lines (DL1, ..., DLm).

[0056] Each subpixel (PX) may include a light-emitting element and emit red, green, blue, or white light. For example, each subpixel (PX) may include an organic light-emitting diode (OLED) as a light-emitting element, but is not limited thereto.

[0057] In the surrounding area (PA), a data driver (30) that provides data signals to the display area (DA), a scan driver (20) that provides scan signals to the display area (DA), a voltage control unit (50) that controls voltages supplied to the display area (DA), and a control unit (40) that can control the data driver (30), the scan driver (20), and the voltage control unit (50) may be arranged.

[0058] The voltage control unit (50) can generate and control the first voltage (ELVDD), the second voltage (ELVSS), and the initialization voltage (VAINT) provided to the display area (DA).

[0059] A first voltage (ELVDD), a second voltage (ELVSS), and an initialization voltage (VAINT) may be applied to a plurality of subpixels (PX). For example, the first voltage (ELVDD) may be a positive voltage, and the second voltage (ELVSS) may be a negative voltage or a ground voltage. That is, the second voltage (ELVSS) may have a lower level than the first voltage (ELVDD).

[0060] The control unit (40) can receive video signals (RGB) and control signals (CS) from an external source (e.g., a system board). The control unit (40) can generate video data (DATA) by converting the data format of the video signals (RGB) to match the interface specifications with the data driver (30). The control unit (40) can provide the video data (DATA) with the converted data format to the data driver (30).

[0061] The control unit (40) can generate and output a first control signal (CS1) and a second control signal (CS2) in response to a control signal (CS) provided from the outside. The first control signal (CS1) may be defined as a scan control signal, and the second control signal (CS2) may be defined as a data control signal. The first control signal (CS1) may be provided to the scan driving unit (20). The second control signal (CS2) may be provided to the data driving unit (30).

[0062] The scan driving unit (20) can generate a plurality of scan signals in response to a first control signal (CS1). The plurality of scan signals can be applied to a plurality of subpixels (PX) through a plurality of scan lines (SL1, ..., SLn).

[0063] The data driving unit (30) can generate a plurality of data voltages corresponding to image data (DATA) in response to a second control signal (CS2). The plurality of data voltages can be applied to a plurality of subpixels (PX) through data lines (DL1, ..., DLm). The data driving unit (30) can simultaneously provide the data voltages generated on a subpixel row basis to the plurality of subpixels (PX) through the data lines (DL1, ..., DLm).

[0064] Multiple subpixels (PX) can receive multiple data voltages in response to multiple scan signals. Multiple subpixels (PX) can display an image by emitting light of a luminance corresponding to the multiple data voltages. Multiple subpixels (PX) can display the image by emitting light sequentially or simultaneously.

[0065] Referring to FIGS. 1 to 3, a subpixel (PX) may include a pixel circuit (PXC) and a light-emitting element (LD). Additionally, the subpixel (PX) may be connected to a scan line (SL) (or gate line) and a data line (DL). The scan lines (SL) may be one of the plurality of scan lines (SL1, ..., SLn) of FIG. 2, and the data line (DL) may be one of the plurality of data lines (DL1, ..., DLm) of FIG. 2. The scan line (SL) may include a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), a first light-emitting control line (ECL), and a second light-emitting control line (EBL).

[0066] Driving signals may be applied to the scan line (SL) and the data line (DL). A first scan signal (GW) may be applied to the first scan line (SL1), a second scan signal (GR) may be applied to the second scan line (SL2), and a third scan signal (GI) may be applied to the third scan line (SL3). A first light emission control signal (EM) may be applied to the first light emission control line (ECL), a second light emission control signal (EMB) may be applied to the second light emission control line (EBL), and a data signal (Vdata) (or data voltage) may be applied to the data line (DL).

[0067] Additionally, the subpixel (PX) may be further connected to a first voltage line (PL1), a second voltage line (PL2), a third voltage line (PL3), a reference voltage line (RFL), and an initialization voltage line (INL). Voltages may be applied to the first voltage line (PL1), the second voltage line (PL2), the third voltage line (PL3), the reference voltage line (RFL), and the initialization voltage line (INL). A first voltage (ELVDD) may be applied to the first voltage line (PL1), a second voltage (ELVSS) may be applied to the second voltage line (PL2), a first voltage (ELVDD) or a reference voltage (VREF) may be applied to the third voltage line (PL3), a reference voltage (VREF) may be applied to the reference voltage line (RFL), and an initialization voltage (VAINT) may be applied to the initialization voltage line (INL).

[0068] The voltage level of the first voltage (ELVDD) may be higher than the voltage level of the second voltage (ELVSS). The voltage level of the reference voltage (VREF) may be equal to or different from the voltage level of the first voltage (ELVDD). The voltage level of the initialization voltage (VAINT) may be lower than the voltage level of the first voltage (ELVDD) and higher than the voltage level of the second voltage (ELVSS). However, the voltages are not limited to these values, and the voltage levels of the voltages may vary depending on the product specifications.

[0069] Meanwhile, the pixel circuit (PXC) may include a first transistor (T1) (or, driving transistor), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a first capacitor (Cst) (or, storage capacitor), and a second capacitor (Chold) (or, hold capacitor).

[0070] The first transistor (T1) can be electrically connected between the first voltage line (PL1) and the second node (N2). For example, the first electrode of the first transistor (T1) can be connected to the first voltage line (PL1) via the fifth transistor (T5), and the second electrode of the first transistor (T1) can be connected to the second node (N2). As an example, the first electrode may be a source electrode and the second electrode may be a drain electrode. However, it is not limited thereto, and the first electrode may be a drain electrode and the second electrode may be a source electrode.

[0071] The gate electrode of the first transistor (T1) can be connected to the first node (N1). Additionally, the first transistor (T1) may further include a lower electrode (or a second gate electrode) corresponding to the gate electrode. The first transistor (T1) can supply a driving current to the light-emitting element (LD) or control the amount of driving current flowing from the first voltage line (PL1) to the light-emitting element (LD). For example, the first transistor (T1) can supply a driving current to the light-emitting element (LD) corresponding to the voltage of the first node (N1).

[0072] The second transistor (T2) can be electrically connected between the data line (DL) and the first node (N1). The gate electrode of the second transistor (T2) can be connected to the first scan line (SL1). The second transistor (T2) can be turned on in response to the first scan signal (GW) of the first scan line (SL1). When the second transistor (T2) is turned on, the data signal (Vdata) of the data line (DL) can be transmitted to the first node (N1).

[0073] The third transistor (T3) can be electrically connected between the reference voltage line (RFL) and the first node (N1). The gate electrode of the third transistor (T3) can be connected to the second scan line (SL2). The third transistor (T3) can be turned on in response to the second scan signal (GR) of the second scan line (SL2). When the third transistor (T3) is turned on, the reference voltage (VREF) can be delivered to the first node (N1).

[0074] The fourth transistor (T4) can be electrically connected between the anode electrode of the light-emitting element (LD) and the initialization voltage line (INL). The gate electrode of the fourth transistor (T4) can be connected to the third scan line (SL3). The fourth transistor (T4) can be turned on in response to the third scan signal (GI) of the third scan line (SL3). When the fourth transistor (T4) is turned on, the initialization voltage (VAINT) can be delivered to the anode electrode of the light-emitting element (LD).

[0075] The fifth transistor (T5) can be electrically connected between the first voltage line (PL1) and the first transistor (T1). The gate electrode of the fifth transistor (T5) can be connected to the first light emission control line (ECL). The fifth transistor (T5) can be turned on in response to the first light emission control signal (EM) of the first light emission control line (ECL).

[0076] The sixth transistor (T6) can be electrically connected between the second node (N2) and the anode electrode of the light-emitting element (LD). The gate electrode of the sixth transistor (T6) can be connected to the second light-emitting control line (EBL). The sixth transistor (T6) can be turned on in response to the second light-emitting control signal (EMB) of the second light-emitting control line (EBL).

[0077] When the fifth transistor (T5) and the sixth transistor (T6) are turned on, a current path can be formed through which a driving current can flow from the first voltage line (PL1) to the second voltage line (PL2) via the pixel circuit (PXC) and the light-emitting element (LD).

[0078] The first capacitor (Cst) may be formed or electrically connected between the first node (N1) and the second node (N2). A voltage corresponding to the data voltage (Vdata) may be stored in the first capacitor (Cst).

[0079] A second capacitor (Chold) may be formed or electrically connected between the third voltage line (PL3) and the second node (N2). The second capacitor (Chold) may stabilize the voltage of the second node (N2). A first voltage (ELVDD) or a reference voltage (VREF) may be applied to the third voltage line (PL3). For example, when the first voltage (ELVDD) is applied to the third voltage line (PL3), the third voltage line (PL3) may be electrically connected to the first voltage line (PL1) or formed integrally with the first voltage line (PL1). However, the third voltage line (PL3) is not limited thereto.

[0080] The light-emitting element (LD) can be electrically connected between the sixth transistor (T6) and the second voltage line (PL2). For example, the light-emitting element (LD) can be forward-connected between the second node (N2) and the second voltage line (PL2). When a driving current is supplied from the first transistor (T1), the light-emitting element (LD) can emit light with a brightness corresponding to the driving current.

[0081] In one embodiment, the light-emitting element (LD) may include an organic light-emitting diode (OLED). In another embodiment, the light-emitting element (LD) may include at least one inorganic light-emitting diode. The type, size, and / or number of the light-emitting element (LD) may vary depending on the embodiment.

[0082] The thin-film transistors (T) may be N-type transistors, but are not limited thereto. For example, at least one of the thin-film transistors (T) may be changed to a P-type transistor. Additionally, the voltage levels of the driving signals for controlling the operation of the transistors may be set according to the type of each transistor.

[0083] The thin-film transistor (T) may include an oxide semiconductor and / or LTPS (low-temperature polycrystalline silicon). For example, at least one transistor including the first transistor (T1) may be an oxide semiconductor transistor including an oxide semiconductor.

[0084] FIG. 4 is a schematic cross-sectional view illustrating an example of the II' section of FIG. 1.

[0085] The thin-film transistor (T) may include a driving transistor (T1 in FIG. 3) and other switching transistors, etc.

[0086] Meanwhile, a base metal layer (131, 132) that blocks light may be located below the capacitor (Cst) and the thin-film transistor (T). The base metal layer (131, 132) may have a stacked structure of at least a first layer and a second layer made of different materials. The first layer may include Al, and the second layer may include Ti.

[0087] For example, a first base metal layer (131) is disposed in the capacitor (Cst) region, and a second base metal layer (132) is disposed in the driving transistor (T1) region, so that they can perform a light-blocking function to prevent light from entering or exiting through the substrate (100). Additionally, the first base metal layer (131) is electrically connected to the second metal layer (134), and the second base metal layer (132) is electrically connected to the second signal wiring (320) of the thin-film transistor (T) to provide electrical characteristics.

[0088] More specifically, a thin-film transistor (T) and a capacitor (Cst) are provided on the substrate (100), and a light-emitting element (140) electrically connected to the thin-film transistor (T) may be located thereon.

[0089] The substrate (100) may be made of a transparent glass material with SiO2 as the main component. However, it is not necessarily limited to this, and the substrate (100) may be formed of a transparent plastic material. The plastic material may be polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide, polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP), etc.

[0090] A buffer layer (BL) may be formed on the substrate (100). The buffer layer (BL) may contain inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide, or titanium nitride, or organic materials such as polyimide, polyester, or acrylic, and may be formed as a plurality of laminates among the materials exemplified.

[0091] The first base metal layer (131) and the second base metal layer (132) are formed on the substrate (100) and can be covered by a buffer layer (BL). The first base metal layer (131) and the second base metal layer (132) may be composed of a plurality of layers to reduce resistance. For example, the first base metal layer (131) and the second base metal layer (132) may have a first layer containing Al and a second layer containing Ti on the first layer.

[0092] A thin-film transistor (T) includes a semiconductor layer (210), a gate electrode (220), and signal lines (300), and can be located on a buffer layer (BL).

[0093] The semiconductor layer (210) may, for example, include an oxide semiconductor. For instance, the semiconductor layer (210) may include an oxide of a material selected from metal elements of groups 12, 13, and 14 such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), and germanium (Ge), and combinations thereof. For instance, the semiconductor layer (210) may include GIZO[(In2O3)a(Ga2O3)b(ZnO)c] (where a, b, and c are real numbers satisfying the conditions a≥0, b≥0, and c>0, respectively).

[0094] As shown in FIG. 5, the semiconductor layer (210) may include a channel region (211) and a source region (212) and a drain region (213) respectively disposed on both sides of the channel region (211).

[0095] The gate electrode (220) may be located on the semiconductor layer (210) with the gate insulating film (230) in between. Specifically, the gate electrode (220) may be located overlapping with the channel region (211) with the gate insulating film (230) in between.

[0096] The gate electrode (220) can be formed as a single layer or a multilayer of one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0097] Additionally, the gate electrode (220) may have the same structure as the base metal layer (131, 132). That is, the gate electrode (220) may be formed as a stacked structure having at least a first layer containing Al and a second layer containing Ti on the first layer.

[0098] The gate insulating film (230) may be formed as a multilayer or single layer of an inorganic material such as silicon oxide and / or silicon nitride.

[0099] The signal wires (300) are located on the interlayer insulating film (400) and can be electrically connected to the thin-film transistor (T).

[0100] The signal wires (300) may include a first signal wire (310) that applies a gate signal to a gate electrode (220), a second signal wire (320) that is electrically connected to a source region (212), and a third signal wire (330) that is electrically connected to a drain region (213).

[0101] The first signal wiring (310), the second signal wiring (320), and the third signal wiring (330) can be formed on the semiconductor layer (210) with an interlayer insulating film (400) in between. Specifically, the first signal wiring (310) can be formed on the gate electrode (220), and the second signal wiring (320) and the third signal wiring (330) can be electrically connected to both ends of the semiconductor layer (210) doped with N-type or P-type impurities, respectively.

[0102] The first signal wiring (310), the second signal wiring (320), and the third signal wiring (330) may be formed as a single layer or a multilayer of one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0103] The interlayer insulating film (400) can be placed on the thin-film transistor (T). The interlayer insulating film (400) may include irregularities (410) on its surface between the signal lines (300).

[0104] The interlayer insulating film (400) may be formed as a multilayer or single layer of a film made of an inorganic material. For example, the inorganic material may be a metal oxide or a metal nitride, and specifically, the inorganic material may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZrO2), etc.

[0105] A passivation layer (PVX) may be located on the first signal wiring (310), the second signal wiring (320), and the third signal wiring (330). The passivation layer (PVX) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), or HMDSO (hexamethyldisiloxane).

[0106] A light-emitting element (140) may be positioned on the passivation layer (PVX), comprising a pixel electrode (141), a counter electrode (143), and an intermediate layer (142) interposed between the pixel electrode (141) and the counter electrode (143). The light-emitting element (140) may be an organic light-emitting element.

[0107] The pixel electrode (141) can be electrically connected to the second signal wiring (320) of the thin-film transistor (T) via, for example, a contact layer (115). Specifically, the contact layer (115) may be located on a passivation layer (PVX), and a planarization layer (PL) may be formed on the contact layer (115). The passivation layer (PVX) has, for example, an opening that exposes the second signal wiring (320) of the thin-film transistor (T), and the contact layer (115) can make contact with the second signal wiring (320) through this opening.

[0108] The planarization layer (PL) includes organic insulating materials such as acrylic, BCB (Benzocyclobutene), or HMDSO (hexamethyldisiloxane), and can serve to planarize the bending caused by the underlying layers.

[0109] The pixel electrode (141) is located on the flattening layer (PL) and can be electrically connected to the lower contact layer (115) through a via hole.

[0110] The pixel electrode (141) may be a (semi)transparent electrode or a reflective electrode. If the pixel electrode (141) is a (semi)transparent electrode, it may include, for example, ITO, IZO, ZnO, In2O3, IGO, or AZO. If the pixel electrode (141) is a reflective electrode, it may have a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a layer formed of ITO, IZO, ZnO, In2O3, IGO, or AZO. Of course, the present invention is not limited thereto, and the pixel electrode (141) may include various materials, and its structure may also be a single layer or a multilayer, allowing for various modifications.

[0111] A pixel defining film (PDL) may be disposed on top of the planarization layer (PL). The pixel defining film (PDL) serves to define a pixel by having an opening that exposes at least the central part of the pixel electrode (141). Additionally, as shown in FIG. 5, the pixel defining film (PDL) serves to prevent arcs from occurring at the edge of the pixel electrode (141) by increasing the distance between the edge of the pixel electrode (141) and the opposing electrode (143) above the pixel electrode (141). Such a pixel defining film (PDL) may include an organic insulating material such as polyimide or HMDSO (hexamethyldisiloxane).

[0112] The intermediate layer (142) of the light-emitting element (140) includes a light-emitting layer. The light-emitting layer may include a polymer or low-molecular-weight organic material that emits light of a predetermined color. Additionally, the intermediate layer (142) may include at least one functional layer among a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL). Such functional layers may include organic materials. Meanwhile, some of the multiple layers forming the intermediate layer (142), such as the functional layer(s), may be formed integrally across multiple light-emitting elements (140).

[0113] The counter electrode (143) may be positioned to cover the display area (DA). The counter electrode (143) may be formed integrally with a plurality of light-emitting elements (140) and may correspond to a plurality of pixel electrodes (141). This counter electrode (143) may be a (semi)transparent electrode or a reflective electrode.

[0114] When the counter electrode (143) is a (semi)transparent electrode, it may have a layer formed of a metal with a small work function, namely Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof, and a (semi)transparent conductive layer such as ITO, IZO, ZnO, or In2O3. When the counter electrode (143) is a reflective electrode, it may have a layer formed of Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Of course, the composition and material of the counter electrode (143) are not limited to this, and various modifications are possible.

[0115] Although not shown in the drawing, an encapsulation layer (not shown) may be located on the upper part of the counter electrode (143). The encapsulation layer (not shown) serves to protect the light-emitting element (140) from moisture or oxygen from the outside. To this end, the encapsulation layer (not shown) has a shape that extends not only to the display area (DA) where the light-emitting element (140) is located, but also to the surrounding area (PA) outside the display area (DA). Such an encapsulation layer (not shown) may have a multilayer structure. For example, the encapsulation layer (not shown) may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer that are sequentially stacked.

[0116] The first inorganic encapsulation layer may include silicon oxide, silicon nitride and / or silicon oxynitride, etc. Since the first inorganic encapsulation layer is formed along the underlying structure, its upper surface may not be flat.

[0117] The organic encapsulation layer covers the first inorganic encapsulation layer and has sufficient thickness so that the upper surface of the organic encapsulation layer can be substantially flat over the entire display area (DA). This organic encapsulation layer may comprise polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.) or any combination thereof.

[0118] The second inorganic encapsulation layer covers the organic encapsulation layer and may include silicon oxide, silicon nitride and / or silicon oxynitride, etc. The second inorganic encapsulation layer extends outwardly to the organic encapsulation layer and comes into contact with the first inorganic encapsulation layer, thereby preventing the organic encapsulation layer from being exposed.

[0119] Meanwhile, the above-mentioned second base metal layer (132) may be located below the thin-film transistor (T) adjacent to the light-emitting element (140). The second base metal layer (132) performs a light-blocking function that prevents light from entering or exiting through the substrate (100), and at the same time is connected to the second signal wiring (320) to stabilize the saturation characteristics of the second signal wiring (320) and the third signal wiring (330).

[0120] The capacitor (Cst) may include a first capacitor (C1) and a second capacitor (C2).

[0121] The first capacitor (C1) may be composed of a first base metal layer (131) and a first metal layer (133) that overlap each other with a buffer layer (BL) in between. The first metal layer (133) may be formed of the same material on the same layer as the gate electrode (220).

[0122] The second capacitor (C2) may be composed of a first base metal layer (131) consisting of multiple layers, although it is not illustrated.

[0123] In this case, the capacitance of the capacitor (Cst) can be increased by forming two capacitors (C1, C2) in a multilayer structure within the same space on a plane.

[0124] The capacitor (Cst) capacitance can be increased by forming two capacitors (C1, C2) in a multilayer structure without increasing the space occupancy on the plane, and the stability of the display device (10) can be improved.

[0125] The outer circuits placed in the peripheral area (PA) can be electrically connected to each of the pixel circuits driving the subpixels (PX). A gate driving circuit, a terminal section, a driving voltage supply line, and a common voltage supply line may be placed in the peripheral area (PA).

[0126] The outer circuits of the peripheral region (PA) may include a plurality of thin-film transistors (T).

[0127] An outer inspection section including an outer circuit of a peripheral area (PA) may have a thin-film transistor (T) disposed on a substrate (100), such as a display area (DA). Specifically, a buffer layer (BL) may be disposed on the substrate (100), a semiconductor layer (210) on the buffer layer (BL), a gate electrode (220), a thin-film transistor (T) including signal lines (300), and an interlayer insulating film (400) may be disposed on the thin-film transistor (T).

[0128] The semiconductor layer (210) may include a channel region (211) and a source region (212) and a drain region (213) respectively disposed on both sides of the channel region (211). A gate electrode (220) may be located on the semiconductor layer (210) with a gate insulating film (230) in between.

[0129] The signal lines (300) may include a first signal line (310) that applies a gate signal to a gate electrode (220), a second signal line (320) that is electrically connected to a source region (212), and a third signal line (330) that is electrically connected to a drain region (213), all located on an interlayer insulating film (400).

[0130] The first signal wiring (310), the second signal wiring (320), and the third signal wiring (330) can be formed on the semiconductor layer (210) with the interlayer insulating film (400) in between.

[0131] The interlayer insulating film (400) may include an uneven surface (410) between the signal wires (300).

[0132] A passivation layer (PVX) may be formed on the first signal line (310), the second signal line (320), and the third signal line (330), and a flattening layer (PL) may be formed on the passivation layer (PVX).

[0133] In order to increase the resolution of the display device (10), the spacing between the signal wires (300) connected to the source region (212), drain region (213), and gate electrode (220), respectively, may be narrowed. As a result, the display device (10) becomes more susceptible to current leakage problems, and consequently, the reliability of the display device (10) may be reduced.

[0134] To solve the above problem, a method is described for increasing the surface resistance between the wires by placing an uneven portion (410) on the interlayer insulating film (400) between the signal wires (300) connected to the source region (212), drain region (213), and gate electrode (220), respectively.

[0135] FIG. 5 is an enlarged view schematically illustrating an example of enlarged A of FIG. 4, and FIG. 6 is an enlarged view schematically illustrating an example of enlarged B of FIG. 5.

[0136] Referring to FIGS. 5 and 6, the interlayer insulating film (400) may include uneven surfaces (410) between the first signal wiring (310), the second signal wiring (320), and the third signal wiring (330).

[0137] An interlayer insulating film (400) may be disposed on a thin-film transistor (T) on a substrate (100). Signal lines (300) electrically connected to the thin-film transistor (T) may be disposed on the interlayer insulating film (400). The interlayer insulating film (400) may include irregularities (410) on the surface of the interlayer insulating film (400) between the signal lines (300).

[0138] A thin-film transistor (T) may include a semiconductor layer (210), a gate insulating film (230) on a channel region (211) of the semiconductor layer (210), and a gate electrode (220) positioned overlapping the channel region (211) with the gate insulating film (230) in between.

[0139] The semiconductor layer (210) may include a source region (212) and a drain region (213) respectively disposed on both sides of the channel region (211).

[0140] The signal wires (300) may include a first signal wire (310) that applies a signal to the gate electrode (220), a second signal wire (320) that is electrically connected to the source region (212), and a third signal wire (330) that is electrically connected to the drain region (213).

[0141] In the interlayer insulating film (400), between the first signal wiring (310), the second signal wiring (320), and the third signal wiring (330), an uneven surface (410) including at least one concave portion (G) on the surface may be disposed.

[0142] Due to the unevenness (410) of the interlayer insulating film (400) between the signal wires (300), the distance between the signal wires (300), that is, the distance over which current flows from one signal wire to another, can be increased. Specifically, the leakage current between the signal wires (300) flows along the surface of the interlayer insulating film (400), and the current path can be lengthened by the unevenness (410).

[0143] The surface resistance between signal wires (300) can be increased by increasing the current path, which is the distance over which current flows from one signal wire to another. As a result, current leakage between signal wires (300) can be mitigated and prevented.

[0144] The uneven surface (410) may include at least one concave portion (G). Assuming the distance between signal wires (300) is equal, the more concave portions (G) there are and the deeper the depth (h) of the concave portion (G), the longer the path for current to flow from one signal wire to another, and accordingly, the surface resistance between the signal wires (300) may increase. The depth (h) of the concave portion (G) may be, for example, 500 Å or more and 1000 Å or less.

[0145] FIG. 6 illustrates an uneven portion (410) of an interlayer insulating film (400) between a first signal wire (310) and a third signal wire (330). The uneven portion (410) is illustrated to have three concave portions (G), but the number of concave portions (G) is not limited thereto.

[0146] The depth (h) of the concave portion (G) is shown as being the same for each of the multiple concave portions (G), but is not limited thereto, and the depth (h) may differ for each of the multiple concave portions (G).

[0147] The uneven portion (410) between the first signal wire (310) and the second signal wire (320), which is not shown in FIG. 6, may have a shape identical or symmetrical to the uneven portion (410) between the first signal wire (310) and the third signal wire (330) shown in FIG. 6, or it may have a different shape that is not identical or symmetrical. That is, the uneven portion (410) between the first signal wire (310) and the second signal wire (320) and the uneven portion (410) between the first signal wire (310) and the third signal wire (330) are not necessarily identical or symmetrical in shape.

[0148] In FIGS. 5 and 6, the bottom portion of the concave portion (G) of the uneven portion (410) is shown to form an angle of 90° with the depth (h) of the concave portion (G), but is not limited thereto, and the uneven portion (410) may include a concave portion (G) having at least a portion that is curved. Additionally, as an example, the uneven portion (410) may include a concave portion (G) having an embossed shape.

[0149] FIG. 7 is a schematic enlarged view illustrating another example of enlarged B of FIG. 5, FIG. 8 is a schematic enlarged view illustrating yet another example of enlarged B of FIG. 5, and FIG. 9 is a schematic enlarged view illustrating yet another example of enlarged B of FIG. 5.

[0150] Referring to FIG. 7, an example of an interlayer insulating film (400) may include a single concave portion (G). When the uneven portion (410) of the interlayer insulating film (400) has a single concave portion (G) between two adjacent signal wires (300), for example between a first signal wire (310) and a third signal wire (330), the greater the depth (h) of the concave portion (G), the longer the path through which current can flow between the first signal wire (310) and the third signal wire (330), and accordingly, the surface resistance of the interlayer insulating film (400) between the first signal wire (310) and the third signal wire (330) may increase.

[0151] Referring to FIG. 8, the interlayer insulating film (400) may include at least one recess (G). At least two of the at least one recess (G) may have different depths and / or widths. For example, the at least one recess may include two or more recesses (G) having different depths, two or more recesses (G) having different widths, or two or more recesses (G) having different depths and different widths.

[0152] As illustrated in FIG. 8, the uneven surface (410) of an example interlayer insulating film (400) may include three concave portions (G). Each concave portion (G) may have a different depth (h) and may have a different width in a direction parallel to the shortest distance connecting two adjacent signal wires (300).

[0153] The more concave portions (G) there are, the longer the path through which current can flow between two adjacent signal wires (300), for example, between the first signal wire (310) and the third signal wire (330). Specifically, the leakage current between the two signal wires (300) flows along the surface of the interlayer insulating film (400), and the current path can be extended by the uneven portions (410). Accordingly, the surface resistance of the interlayer insulating film (400) between the first signal wire (310) and the third signal wire (330) can be increased.

[0154] Referring to FIG. 9, the interlayer insulating film (400) may further include an additional insulating film (420) covering the uneven portion (410).

[0155] In addition to placing the uneven portion (410) to prevent and mitigate current leakage between the signal wires (300), the interlayer insulating film (400) may also have an additional insulating film (420).

[0156] The additional insulating layer (420) may be composed of a material that does not transmit an electric field relatively well, i.e., a material with a low dielectric constant, so that it is more difficult for current to flow between the signal wires (300). The dielectric constant of the additional insulating layer (420) may be, for example, at least 4 or less.

[0157] Additionally, the parasitic capacitance between the signal wires (300) can be reduced by forming the additional insulating film (420) with a material having a low dielectric constant. In other words, since the additional insulating film (420) with a low dielectric constant is filled between the signal wires (300), the parasitic capacitance between the signal wires (300) can be reduced.

[0158] The additional insulating film (420) has sufficient insulating properties and may have a thickness such that the thickness of the display device (10) does not become thicker. The thickness of the additional insulating film (420) may be, for example, 500 Å or more and 1000 Å or less.

[0159] An additional insulating film (420) can protect the signal wiring (300) or the uneven parts (410) from contaminants. The additional insulating film (420) can be formed from a material that fits well with the grid structure of the layer including the passivation layer (PVX) and the uneven parts (410). This can mitigate and prevent current leakage, and reduce defects or impurities within the interlayer insulating film (400), thereby improving the electrical characteristics, lifespan, and stability of the display device (10).

[0160] In FIGS. 7 to 9, the bottom portion of the concave portion (G) of the uneven portion (410) is shown to form an angle of 90° with the depth (h) of the concave portion (G), but is not limited thereto, and the uneven portion (410) may include a concave portion (G) having at least a portion that is curved. Also, as an example, the uneven portion (410) may include a concave portion (G) having an embossed shape.

[0161] In FIGS. 7 to 9, other components other than the uneven portion (410) and the concave portion (G) can be applied in the same way as described in FIGS. 1 to 6. Additionally, in FIGS. 7 to 9, the depth (h) of the concave portion (G) may be 500 Å or more and 1000 Å or less, as described in FIGS. 5 and 6.

[0162] Additionally, the uneven portion (410) between the first signal wire (310) and the third signal wire (330) is illustrated in FIGS. 7 to 9, and the description in FIGS. 7 to 9 can be applied in the same way to the uneven portion (410) between the first signal wire (310) and the second signal wire (320). However, the uneven portion (410) between the first signal wire (310) and the third signal wire (330) in FIGS. 7 to 9 and the uneven portion (410) between the first signal wire (310) and the second signal wire (320) not described in FIGS. 7 to 9 may have the same or symmetrical shape, or may have a different shape that is not the same or symmetrical.

[0163] FIGS. 10 to 17 are cross-sectional views schematically illustrating a method for manufacturing a display device according to one embodiment of the present invention.

[0164] A display device (10) can be manufactured by sequentially forming a semiconductor layer (210), a gate insulating film (230), and a gate electrode (220) on a substrate (100) to form a thin film transistor (T), forming an interlayer insulating film (400) on the thin film transistor (T), forming an uneven surface (410) on the surface of the interlayer insulating film (400), and forming signal lines (300) electrically connected to the thin film transistor (T) on the interlayer insulating film (400).

[0165] Referring to FIG. 10, first, a thin-film transistor (T) can be formed on a substrate (100). As an example, a buffer layer (BL) can be placed on the substrate (100), and then a thin-film transistor (T) can be formed on the buffer layer (BL).

[0166] Specifically, after forming a semiconductor layer (210) on a buffer layer (BL), a gate insulating film (230) is formed on a region of the semiconductor layer (210), and a gate electrode (220) is formed on the gate insulating film (230) to form a thin-film transistor (T).

[0167] After the step of forming a thin-film transistor (T), a source region (212) and a drain region (213) can be formed by doping impurities into the semiconductor layer (210) using the gate electrode (220) as a mask.

[0168] Referring to FIG. 11, after the step of forming a thin film transistor, the step of forming an interlayer insulating film (400) on the thin film transistor (T) can be performed.

[0169] FIGS. 12 to 16 illustrate the step of forming an interlayer insulating film (400) and then forming an uneven surface (410) on the surface of the interlayer insulating film (400).

[0170] The step of forming an uneven surface (410) on the surface of the interlayer insulating film (400) can first be performed by coating a photoresist material on the interlayer insulating film (400) to form a photoresist layer (PR).

[0171] A photoresist pattern can be formed on the photoresist layer (PR) using a half-tone mask (HM) on the formed photoresist layer (PR).

[0172] The halftone mask (HM) can adjust the transmittance and width for each area to control the width and depth (h) of the concave portion (G) of the uneven portion (410). By using the halftone mask (HM) when forming the photoresist pattern, there is no additional increase in the number of masks, which simplifies the process and reduces manufacturing costs and process time.

[0173] As an example, a halftone mask (HM) can be prepared such that the transmittance of the area where signal wiring (300) is to be formed is high, and the transmittance of the area where the concave portion (G) of the uneven portion (410) is to be formed is low. Specifically, the halftone mask (HM) may have the area where the concave portion (G) of the uneven portion (410) with low transmittance is to be formed positioned between the areas where signal wiring (300) with high transmittance is to be formed.

[0174] A photoresist pattern can be formed by placing a halftone mask (HM) on the photoresist material, that is, on the photoresist layer (PR), and then performing an exposure process and a development process on the photoresist layer (PR).

[0175] After forming a photoresist pattern, the interlayer insulating film (400) can be patterned using the photoresist pattern as a mask, that is, an etching process can be performed on the photoresist pattern.

[0176] After patterning the interlayer insulating film (400), if a stripping step is performed to remove the remaining photoresist pattern, areas where uneven parts (410) and signal lines (300) are to be formed can be formed on the surface of the interlayer insulating film (400).

[0177] The uneven portion (410) can be made into an embossed shape by adjusting the transmittance for each region in the halftone mask (HM), or the width and transmittance for each region in the halftone mask (HM) can be adjusted so that at least one uneven portion (410) includes at least one concave portion (G).

[0178] In addition, the depth (h) of the concave portion (G) of the uneven portion (410) can be controlled by adjusting the transmittance of the halftone mask (HM), the intensity of light in the exposure process, etc. As an example, the depth (h) of the concave portion (G) may be 500 Å or more and 1000 Å or less.

[0179] When an uneven portion (410) is formed on the interlayer insulating film (400), the interlayer insulating film (400) can be patterned so that one portion of the source region (212), drain region (213), and gate electrode (220) is exposed, so that the signal wires (300) are electrically connected to the source region (212), drain region (213), and gate electrode (220).

[0180] Referring to FIG. 17, signal lines (300) electrically connected to a thin-film transistor (T) can be formed on the interlayer insulating film (400) after the formation of the uneven portion (410).

[0181] When an uneven portion (410) is formed on an interlayer insulating film (400), signal lines (300) can be formed on the patterned interlayer insulating film (400) so that a source region (212), a drain region (213), and a region of the gate electrode (220) are exposed by using a suitable halftone mask (HM) with a different transmittance for each region.

[0182] In the halftone mask (HM), low-transmittance regions are formed between high-transmittance regions, so that, as a result, an uneven portion (410) can be disposed between the exposed portions of the source region (212), drain region (213), and gate electrode (220) in the interlayer insulating film (400). The uneven portion (410) can be located between the signal wires (300).

[0183] Specifically, the signal wires (300) may include a first signal wire (310) that applies a gate signal to a gate electrode (220), a second signal wire (320) that is electrically connected to a source region (212), and a third signal wire (330) that is electrically connected to a drain region (213).

[0184] That is, the uneven portion (410) can be formed on the surface of the interlayer insulating film (400) between the first signal wiring (310), the second signal wiring (320) and the third signal wiring (330).

[0185] Although not shown, after the signal wires (300) are formed, an additional insulating film (420) can be further formed on the interlayer insulating film (400) between the signal wires (300).

[0186] The step of forming an additional insulating film (420) may include the step of coating a photoresist material on the signal wires (300), the step of depositing an additional insulating material on the photoresist material and the interlayer insulating film (400), and the step of removing the photoresist material.

[0187] The additional insulating film (420) can protect the uneven portion (410) and the signal wires (300) from contaminants, and as an example, the thickness of the additional insulating film (420) may be 500 Å or more and 1000 Å or less.

[0188] The additional insulating film (420) is made of a material with a low dielectric constant and can mitigate and prevent current leakage between signal wires (300). As an example, the dielectric constant of the additional insulating film (420) may be at least 4 or less.

[0189] The display device (10) described above and the display device (10) manufactured by the manufacturing method described above form an uneven surface (410) on the surface of the interlayer insulating film (400) between the signal wires (300), so that the leakage current between the signal wires (300) flows along the surface of the interlayer insulating film (400), and the current path can be extended by the uneven surface (410). As a result, the resistance between the signal wires (300) increases, and microcurrent leakage can be reduced.

[0190] As a result, it is not necessary to perform an FCA (first article inspection) after the formation of the passivation layer (PVX) or contact layer (115), and an FCA inspection and repair based on the inspection results can be performed early after the formation of the signal wires (300), thereby improving the yield of the display device (10) and reducing costs.

[0191] The uneven surface (410) that increases resistance by increasing the distance through which current flows between signal wires (300) can provide a display device (10) with improved reliability even when the distance between signal wires (300) is shortened to meet the requirement for increased resolution.

[0192] The display device (10) according to the embodiment can be applied to various electronic devices (1000). An electronic device (1000) according to one embodiment includes the display device (10) described above and may further include a module or device having additional functions other than the display device (10).

[0193] FIG. 18 is a block diagram of an electronic device according to an embodiment of the present invention. Referring to FIG. 18, an electronic device (1000) according to an embodiment may include a display module (1100), a processor (1200), a memory (1300), and a power module (1400).

[0194] The processor (1200) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0195] The memory (1300) may store data information necessary for the operation of the processor (1200) or the display module (1100). When the processor (1200) executes an application stored in the memory (1300), a video data signal and / or an input control signal is transmitted to the display module (1100), and the display module (1100) can process the received signal and output video information through a display screen.

[0196] The power module (1400) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (1000).

[0197] At least one of each component of the electronic device (1000) described above may be included within the display device (10) according to the embodiments described above. Additionally, some of the individual modules functionally included within a single module may be included within the display device, while others may be provided separately from the display device. For example, the display device (10) may include a display module (1100), and the processor (1200), memory (1300), and power module (1400) may be provided in the form of other devices within the electronic device (1000) other than the display device (10).

[0198] FIG. 19 is a schematic diagram of an electronic device according to various embodiments.

[0199] Referring to FIG. 19, various electronic devices to which the display device (10) according to the embodiments is applied may include not only image display electronic devices such as a smartphone (1000.1a), a tablet PC (1000.1b), a laptop (1000.1c), a TV (1000.1d), and a desk monitor (1000.1e), but also wearable electronic devices including display modules such as smart glasses (1000.2a), a head-mounted display (1000.2b), and a smart watch (1000.2c), and automotive electronic devices (1000.3) including display modules such as a CID (Center Information Display) and a room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0200] Each of the embodiments described above can be implemented independently, but it goes without saying that the structure of each embodiment can be applied in combination to other embodiments.

[0201] One or more components disclosed above may include, or be implemented by, a processing circuit such as hardware including a logic circuit, a combination of hardware and software including a processor executing software. For example, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0202] As such, the present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

[0203] The specific practices described in the embodiments are examples and do not limit the scope of the embodiments in any way. Furthermore, unless specifically stated as "essential," "importantly," etc., components may not be strictly necessary for the application of the present invention.

[0204] In the specification of the embodiments (particularly in the claims), the use of the term "the above" and similar descriptive terms may be in both singular and plural. Furthermore, where a range is described in the embodiments, it is considered to include the invention with respect to individual values ​​within said range (unless otherwise stated), and is equivalent to describing each individual value constituting said range in the detailed description. Finally, regarding the steps constituting the method according to the embodiments, unless explicitly stated in order or otherwise stated, said steps may be performed in a suitable order. The embodiments are not necessarily limited by the order in which said steps are described. The use of any examples or exemplary terms in the embodiments is merely for the purpose of describing the embodiments in detail, and the scope of the embodiments is not limited by said examples or exemplary terms unless limited by the claims. Furthermore, those skilled in the art will understand that various modifications, combinations, and changes may be made according to design conditions and factors within the scope of the claims or equivalents to which they are added.

Claims

1. Substrate; A thin-film transistor on the above substrate; An interlayer insulating film on the above-mentioned thin-film transistor; and Signal lines located on the interlayer insulating film and electrically connected to the thin-film transistor; comprising A display device in which the above-described interlayer insulating film includes irregularities on its surface between the above-described signal wires.

2. In Paragraph 1, The above thin-film transistor is, A semiconductor layer comprising a channel region and a source region and a drain region respectively disposed on both sides of the channel region; and A display device comprising: a gate electrode positioned overlapping the channel region with a gate insulating film in between.

3. In Paragraph 2, The above signal lines include a first signal line that applies a gate signal to the gate electrode, a second signal line electrically connected to the source region, and a third signal line electrically connected to the drain region. A display device in which the interlayer insulating film includes the uneven surface between the first signal line, the second signal line, and the third signal line.

4. In Paragraph 1, A display device comprising at least one concave portion, wherein the above-mentioned uneven portion includes at least one concave portion.

5. In Paragraph 4, A display device having a depth of 500 Å or more and 1000 Å or less.

6. In Paragraph 4, A display device comprising at least one concave portion having different depths, two or more concave portions having different widths, or two or more concave portions having different depths and different widths.

7. In Paragraph 1, A display device wherein the interlayer insulating film further comprises an additional insulating film covering the uneven portion.

8. In Paragraph 7, A display device having a thickness of the additional insulating film of the above-mentioned amount of 500 Å or more and 1000 Å or less.

9. In Paragraph 7, A display device having a dielectric constant of at least 4 or less of the additional insulating film.

10. A step of forming a thin-film transistor by sequentially forming a semiconductor layer, an interlayer insulating film, and a gate electrode on a substrate; A step of forming an interlayer insulating film on the thin-film transistor; A step of forming irregularities on the surface of the interlayer insulating film; and A method for manufacturing a display device, comprising the step of forming signal lines electrically connected to the thin-film transistor on the interlayer insulating film.

11. In Paragraph 10, The step of forming the irregularities on the surface of the interlayer insulating film is, A step of forming a photoresist layer by coating a photoresist material on the interlayer insulating film above; A step of forming a photoresist pattern on the photoresist layer using a half-tone mask; A method for manufacturing a display device, comprising the step of patterning the interlayer insulating film using the above photoresist pattern as a mask.

12. In Paragraph 11, A method for manufacturing a display device, wherein in the step of forming the above photoresist pattern, an exposure process and a development process are performed on the above photoresist material.

13. In Paragraph 10, A method for manufacturing a display device in which the above-mentioned protrusions are located between the above-mentioned signal wires.

14. In Paragraph 10, Between the step of forming the thin-film transistor and the step of forming the interlayer insulating film, A method for manufacturing a display device, further comprising the step of forming a source region and a drain region by doping impurities into the semiconductor layer using the gate electrode as a mask.

15. In Paragraph 14, The above signal lines include a first signal line that applies a gate signal to the gate electrode, a second signal line electrically connected to the source region, and a third signal line electrically connected to the drain region. A method for manufacturing a display device, wherein the above-mentioned uneven portion is formed on the surface of the interlayer insulating film between the first signal line, the second signal line, and the third signal line.

16. In Paragraph 10, A method for manufacturing a display device, further comprising the step of forming an additional insulating film on the interlayer insulating film between the signal wires.

17. In Paragraph 16, The step of forming the additional insulating film above is, A step of coating a photoresist material on the above signal lines; A step of depositing an additional insulating material on the above photoresist material and the above interlayer insulating film; and A method for manufacturing a display device comprising the step of removing the above photoresist material.

18. In Paragraph 10, A method for manufacturing a display device, wherein the above-mentioned uneven portion includes at least one concave portion.

19. In Paragraph 18, A method for manufacturing a display device, wherein the depth of the above-mentioned concave portion is 500 Å or more and 1000 Å or less.

20. An electronic device including a display device, The above display device is, Substrate; A thin-film transistor on the above substrate; An interlayer insulating film on the above-mentioned thin-film transistor; and Signal wiring located on the interlayer insulating film and electrically connected to the thin-film transistor; including The above-described interlayer insulating film comprises an uneven surface between the signal wires, in an electronic device.

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