Circuit board and semiconductor package

Abstract

This circuit board comprises: a core part including a first core layer and a second core layer disposed on the first core layer; an upper build-up insulation part disposed on the core part and including a plurality of insulation layers stacked along the vertical direction; a first via electrode passing through at least a portion of the first core layer; a second via electrode passing through at least a portion of the second core layer; and a plurality of third via electrodes respectively passing through the plurality of insulation layers of the upper build-up insulation part. The first via electrode includes a first part of which the width in the horizontal direction increases from the second core layer toward the first core layer, and a second part which is disposed on the first part and of which the width in the horizonal direction decreases from the second core layer toward the first core layer. The second via electrode includes a third part of which the width in the horizontal direction increases from the second core layer toward the first core layer, and a fourth part which is disposed on the third part and of which the width in the horizontal direction decreases from the second core layer toward the first core layer. The first part and the second part have the same length in the vertical direction, the third part and the fourth part have different lengths in the vertical direction, and the first via electrode, the second via electrode, and the plurality of third via electrodes overlap along the vertical direction.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, technologies related to electronic products such as AI and servers have been progressing toward multi-functionality and high speed. To respond to this trend, high-layer and large-area circuit board technologies are also developing rapidly to keep pace with the fast-advancing semiconductor chip manufacturing technology.

[0004] In particular, as the density of transistors and wiring within semiconductor chips increases, the number of I / O terminals on the chips is growing. To meet this trend, not only are the wiring densities, lengths, and widths of circuit boards becoming finer, but there is also a trend toward high-layer, large-area designs.

[0005] Furthermore, from the perspective of miniaturizing finished electronic products, the thickness of the applied circuit boards is also decreasing, and technologies related to multilayer circuit boards, which configure more circuit layers within a circuit board of the same thickness, are being actively researched. In addition, as the pitch of semiconductor chips narrows and the size of chips increases, chiplet technology for separating semiconductor chips by function is being researched. Moreover, technologies for connecting separated chiplets on circuit boards are being actively researched. Furthermore, by connecting semiconductor chips with different functions on circuit boards, technologies regarding the connection relationship between circuit boards and semiconductor chips are being actively researched, such as the circuit board connecting semiconductor chips to each other, which was previously considered only from the perspective of conventional semiconductor packaging.

[0006] A circuit board is a device in which circuit line patterns are arranged using a conductive material, such as copper, on an electrically insulating substrate; it is a general term for the package board immediately before mounting electronic components. To densely mount many different types of electronic components on a flat surface, the mounting positions of each component are determined, and circuit patterns connecting the components are printed and fixed onto the surface.

[0007] Recently, as the number of signals that semiconductor chips must process increases, there is a trend toward larger chip sizes. Consequently, the size of the circuit boards on which these chips are mounted is also increasing.

[0008] With the increase in the number of layers and large surface areas of circuit boards, the use of a thick core layer is being considered to improve the warpage characteristics of the circuit board. For example, the circuit board includes a core layer and a plurality of build-up structures symmetrical in the vertical direction with respect to the core layer. Each of the plurality of build-up structures includes a plurality of insulating layers arranged in the vertical direction. The plurality of build-up structures are electrically connected to each other by core via electrodes penetrating the core layer.

[0009] According to the above structure, the manufacturing process is complex and there is a problem of reduced yield due to the bidirectional stacking structure of multiple insulating layers based on the core layer. In addition, there is a problem that there are limitations in improving the density of circuit parts, such as core via electrodes within the core layer, due to the high multilayer structure.

[0010]

[0011] The present invention provides a circuit board and a semiconductor package that can improve the warpage characteristics of the circuit board by sufficiently securing the thickness of the core layer, facilitates the implementation of fine pitch of circuit parts, and improves productivity.

[0012]

[0013] A circuit board according to the present embodiment comprises: a core portion including a first core layer and a second core layer disposed on the first core layer; an upper build-up insulating portion disposed on the core portion and including a plurality of insulating layers stacked along a vertical direction; a first via electrode penetrating at least a portion of the first core layer; and a second via electrode penetrating at least a portion of the second core layer. The upper build-up insulating portion includes a plurality of third via electrodes penetrating each of the plurality of insulating layers, wherein the first via electrode includes a first portion in which the horizontal width widens from the second core layer toward the first core layer, and a second portion disposed on the first portion in which the horizontal width narrows from the second core layer toward the first core layer, and the second via electrode includes a third portion in which the horizontal width widens from the second core layer toward the first core layer, and a fourth portion disposed on the third portion in which the horizontal width narrows from the second core layer toward the first core layer, wherein the vertical length of the first portion is the same as the vertical length of the second portion, and the vertical length of the third portion is different from the vertical length of the fourth portion, and the first via electrode, the second via electrode, and the plurality of third via electrodes overlap along the vertical direction.

[0014] The vertical length of the third part may be shorter than the vertical length of the fourth part.

[0015] It includes a first wiring portion disposed on the first core layer and connected to the first via electrode, and the second via electrode may be vertically connected to the first wiring portion.

[0016] The vertical thickness of the first core layer may be thicker than the vertical thickness of the second core layer.

[0017] The first core layer comprises a plurality of vertically stacked glass fibers, and the second core layer may comprise a single layer of glass fibers.

[0018] Each of the plurality of insulating layers of the upper build-up insulating portion may be a prepreg (PPG).

[0019] The horizontal width of the second via electrode may be greater than the horizontal width of the third via electrode.

[0020] The horizontal width of the first via electrode may be larger than the horizontal width of the second via electrode.

[0021] The first via electrode has a minimum width in the horizontal direction in the area where the first part and the second part meet, and the maximum width of the second via electrode may be greater than the minimum width of the first via electrode.

[0022] A semiconductor package according to the present embodiment comprises: a core portion including a first core layer and a second core layer disposed on the first core layer; an upper build-up insulating portion disposed on the core portion and including a plurality of insulating layers stacked along a vertical direction; a semiconductor chip disposed on the upper build-up insulating portion; a first via electrode penetrating at least a portion of the first core layer; and a second via electrode penetrating at least a portion of the second core layer. The upper build-up insulating portion includes a plurality of third via electrodes penetrating each of the plurality of insulating layers, wherein the first via electrode includes a first portion in which the horizontal width widens from the second core layer toward the first core layer, and a second portion disposed on the first portion in which the horizontal width narrows from the second core layer toward the first core layer, and the second via electrode includes a third portion in which the horizontal width widens from the second core layer toward the first core layer, and a fourth portion disposed on the third portion in which the horizontal width narrows from the second core layer toward the first core layer, wherein the vertical length of the first portion is the same as the vertical length of the second portion, and the vertical length of the third portion is different from the vertical length of the fourth portion, and the first via electrode, the second via electrode, and the plurality of third via electrodes overlap along the vertical direction.

[0023]

[0024] Through this embodiment, by the vertical overlapping structure of via electrodes from the core portion toward each build-up insulating portion, the placement area of ​​the circuit portion within the circuit board can be secured more widely, and there is an advantage of easy implementation of fine pitch.

[0025] In addition, by forming a structure in which the horizontal width of the via electrode gradually decreases as it moves from the core portion toward the build-up insulation portion, there is an advantage of being able to uniformly distribute stress within the circuit board.

[0026] In addition, by implementing the core portion as a structure in which multiple insulating layers are stacked, the via electrode formation process can be made easier compared to a structure in which the core layer is implemented as a single layer, and the manufacturing cost can be lowered and the yield improved.

[0027] In addition, when via electrodes are placed in the core section, the entire inner side of the via hole in the core layer can be filled with a metal layer, which has the advantage of improving mechanical and electrical efficiency, such as heat dissipation, power transmission, and electrical signal transmission.

[0028] In addition, as the core part is implemented with multiple insulating layers, there is an advantage in that the degree of design freedom is improved and production efficiency in processing via holes in the core layer can be improved.

[0029]

[0030] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0031] FIG. 2 is a drawing illustrating the arrangement structure of a first core layer, a second core layer, and via electrodes within an upper build-up insulating portion according to an embodiment of the present invention.

[0032] FIG. 3 is a cross-sectional view of a core portion according to an embodiment of the present invention.

[0033] FIG. 4 is a magnified view of a via hole, which is an area for the placement of a second via electrode within a second core layer according to an embodiment of the present invention.

[0034] Figure 5 is a diagram illustrating stress within a circuit board according to a comparative example.

[0035] FIG. 6 is a diagram illustrating stress within a circuit board according to an embodiment of the present invention.

[0036] FIG. 7 is a perspective view showing the upper surface of a semiconductor package according to an embodiment of the present invention.

[0037]

[0038] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0039] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0040] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0041] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) shall be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, shall be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it shall be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it shall not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0042] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0043] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0044] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0045] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0046] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0047] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0048] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0049] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0050] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0051] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0052] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0053] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is a diagram illustrating the arrangement structure of a first core layer, a second core layer, and a via electrode within an upper build-up insulating portion according to an embodiment of the present invention, FIG. 3 is a diagram showing a cross-section of a core portion according to an embodiment of the present invention, FIG. 4 is a diagram showing an enlarged view of a via hole, which is an arrangement area of ​​a second via electrode within a second core layer according to an embodiment of the present invention, FIG. 5 is a diagram for explaining stress within a circuit board according to a comparative example, and FIG. 6 is a diagram for explaining stress within a circuit board according to an embodiment of the present invention.

[0054] Referring to FIGS. 1 to 6, a circuit board (10) according to an embodiment of the present invention may include a core portion (100), an upper build-up structure (200), a lower build-up structure (300), and a protective layer (410, 420).

[0055] The circuit board (10) may include a core portion (100). The core portion (100) may be a component forming the base of the circuit board (10). Based on the vertical direction, the core portion (100) may be positioned in the center of the circuit board (10). The material of the core portion (100) may include at least one selected from the group consisting of glass, resin, plastic, and metal. For example, the core portion (100) may include resin and glass fibers disposed within the resin. As the rigidity of the core portion (100) is increased through the glass fibers, the bending characteristics of the circuit board (10) may be improved.

[0056] Recently, as the number of signals that semiconductor chips must process increases, there is a trend toward larger chip sizes. Consequently, the size of the circuit boards on which these chips are mounted is also increasing.

[0057] According to the embodiment, in order to improve the bending characteristics of the circuit board (10) as the circuit board (10) becomes more multilayered and larger in area, it is preferable to form the thickness of the core portion (100) thickly.

[0058] The core portion (100) may include a first core layer (110) and a second core layer (150) disposed on one side and the other side of the first core layer (110). The second core layer (150) may be disposed on the upper surface of the first core layer (110) and the lower surface of the first core layer (110), respectively.

[0059] For example, the second core layer (150) may include a plurality of insulating layers stacked in a vertical direction. With respect to the first core layer (110), the second core layer (150) may include a second-1 core layer (151) disposed on the first core layer (110), a second-2 core layer (152) disposed on the second-1 core layer (151), a second-3 core layer (153) disposed on the lower surface of the first core layer (110), and a second-4 core layer (154) disposed on the lower surface of the second-3 core layer (153). However, this is not limited thereto, and with respect to the first core layer (110), the second core layer (150) may be implemented as a single layer on the upper surface and the lower surface of the first core layer (110), respectively. In addition, to control the overall thickness of the core portion (100), the second core layer (150) may have a structure in which a greater number of insulating layers are stacked in the vertical direction. Also, by arranging the number of stacked layers of the second core layer (150) above and below the first core layer (110) differently, the warping that occurs during the process of the circuit board or the warping that occurs after the process can be precisely controlled.

[0060] Based on the vertical direction, the thickness (H1) of the first core layer (110) may be thicker than the thickness (H2) of the second core layer (150). Here, the thickness (H2) of the second core layer (150) may refer to the vertical thickness of each of the plurality of insulating layers constituting the second core layer (150). According to an example, the thickness (H1) of the first core layer (110) may be 100 µm or more and 300 µm or less to improve the warpage characteristics of the circuit board (10) and the processability of the first via electrode (130) to be described later. For example, the first via electrode (130) penetrating the first core layer (110) has a structure in which the entire via hole penetrating the first core layer (110) is filled with metal, which is advantageous for improving mechanical characteristics such as heat dissipation and / or electrical characteristics such as power and signal transmission. However, if the thickness of the first core layer (110) exceeds 300 μm, it is difficult to fill the entire via hole with metal and it is also difficult to process the via hole, so it is preferable that the thickness of the first core layer (110) be provided within the range described above. In addition, the thickness (H2) of the second core layer (150) may be 60 μm or more and 80 μm or less in order to improve the bending characteristics of the circuit board (10) and to advantageously control the total thickness of the core part (100). In this case, the ratio of the thickness of the first core layer (110) and the second core layer (110) may be 5:1 to 5:4.

[0061] If the ratio of the thickness of the second core layer (150) to the first core layer (110) is less than 5:1, the thickness of the core portion (100) may not be sufficiently secured, and a warpage problem of the circuit board (10) may occur due to reduced durability.

[0062] If the ratio of the thickness of the second core layer (150) to the first core layer (110) exceeds 5:4, the manufacturing cost for forming the core part (100) increases relatively, or the yield or productivity decreases, which reduces the utility of implementing the core part (100) through multiple insulating layers, and the process of forming the second via electrode (170) described later within the second core layer (150) also becomes difficult.

[0063] The first core layer (110) may include a resin and glass fibers (112) disposed within the resin. The first core layer (110) may be a prepreg (PPG). For example, the first core layer (110) may include a plurality of glass fibers (112). Each of the plurality of glass fibers (112) extends in a horizontal direction and may be arranged perpendicular to one another. As illustrated in FIG. 3, the plurality of glass fibers (112) may include a first glass fiber (112a) and a second glass fiber (112b) disposed below the first glass fiber (112a).

[0064] The second core layer (150) may include a resin and glass fibers (150a) disposed within the resin. The second core layer (150) may be a prepreg (PPG). Glass fibers (150a) may be disposed horizontally within the resin constituting the second core layer (150). As shown in FIG. 3, a single layer of glass fibers (150a) may be disposed within the second core layer (150).

[0065] According to the embodiment, by implementing the glass fibers (112) in the first core layer (110) as more layers than the glass fibers (150a) in the second core layer (150), the bending characteristics of the circuit board (10) can be improved through the first core layer (110) positioned in the center of the vertical direction.

[0066] In addition, by implementing the core part (100) in a structure in which a second core layer (150) thinner than the thickness of the first core layer (110) is stacked in a vertical direction, it is easy to control the overall thickness of the core part (100) and can improve the degree of freedom in designing circuit parts such as wiring within the core part (100).

[0067] Specifically, the core portion provided by a single layer according to the prior art has a thick thickness, so a mechanical drill must be used to process via holes for the placement of via electrodes. When using a mechanical drill, it is difficult to narrow the spacing between via holes, the processing time for the mechanical drill is prolonged, and high processing costs are incurred. In addition, when placing via electrodes through a plating process within the via holes of the core portion provided by a single layer, it is difficult to completely fill the inside of the via holes, so a metal layer having a predetermined thickness is placed only on the inner walls of the via holes in the horizontal direction. Therefore, there are limitations in improving mechanical and / or electrical characteristics such as heat dissipation, power transmission, electrical signal transmission, insertion loss, and resistance.

[0068] According to the embodiment, by implementing the core portion (100) through a plurality of insulating layers stacked in a vertical direction, compared to a structure in which the core portion is implemented with a single layer, via holes can be processed using a laser in each relatively thin insulating layer as well as mechanical drilling, thereby lowering the manufacturing cost and making it easy to fill the entire inside of the via hole with metal. In addition, by forming the core portion (100) as a structure in which a plurality of insulating layers are stacked vertically, the degree of design freedom regarding the formation of wiring and via electrodes is increased, and accordingly, there is an advantage that production efficiency can be improved.

[0069] The circuit board (10) may include an upper build-up structure (200) and a lower build-up structure (300). Based on the core portion (100), the upper build-up structure (200) may be placed on the core portion (100), and the lower build-up structure (300) may be placed on the lower surface of the core portion (100).

[0070] The upper build-up structure (200) may include an upper build-up insulating portion. The upper build-up insulating portion may include a plurality of insulating layers (210) stacked along a vertical direction. The plurality of insulating layers (210) of the upper build-up insulating portion may be stacked along a vertical direction on the core portion (100). The lowest insulating layer among the plurality of insulating layers (210) constituting the upper build-up insulating portion may be placed on the second core layer (150). The number of the plurality of insulating layers (210) constituting the upper build-up insulating portion may be greater than the number of the second core layer (150).

[0071] The lower build-up structure (300) may include a lower build-up insulating portion. The lower build-up insulating portion may include a plurality of insulating layers (310) stacked along a vertical direction. The plurality of insulating layers (310) of the lower build-up insulating portion may be stacked along a vertical direction on the lower surface of the core portion (100). Among the plurality of insulating layers (310) constituting the lower build-up insulating portion, the uppermost insulating layer may be disposed on the lower surface of the second core layer (150).

[0072] Each of the plurality of insulating layers (210) of the upper build-up insulating section and each of the plurality of insulating layers (310) of the lower build-up insulating section may be any insulating material, such as photocurable and / or thermosetting insulating material. As a thermosetting insulating material, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and a prepreg (PPG) containing glass fibers within a resin may be used. In addition, the resins described above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. At least one of the plurality of insulating layers (210) of the upper build-up insulating section or at least one of the plurality of insulating layers (310) of the lower build-up insulating section may be a photocurable insulating material, and if it is a photocurable insulating material, it may be a PID (Photo Imageable Dielectric).

[0073] In particular, as the core part (100) is implemented with multiple insulating layers, when each of the multiple insulating layers (210) of the upper build-up insulating part and the multiple insulating layers (310) of the lower build-up insulating part is implemented as prepreg (PPG), the durability against bending of the circuit board (10) can be further improved.

[0074] Meanwhile, when the plurality of insulating layers (210) of the upper build-up insulating part and the plurality of insulating layers (310) of the lower build-up insulating part are prepregs (PPG), a single layer of glass fiber may be disposed within the resin constituting the plurality of insulating layers (210) of the upper build-up insulating part and the plurality of insulating layers (310) of the lower build-up insulating part.

[0075] Each of the plurality of insulating layers (210) of the upper build-up insulating part and the plurality of insulating layers (310) of the lower build-up insulating part may have a thickness smaller than the thickness of the first core layer (110) and / or the second core layer (150). Accordingly, the plurality of insulating layers (210) of the upper build-up insulating part and the plurality of insulating layers (310) of the lower build-up insulating part may each be provided with a via electrode (230) smaller than the via electrode (130, 170) disposed within the core part (100). Therefore, the plurality of insulating layers (210) of the upper build-up insulating part and the plurality of insulating layers (310) of the lower build-up insulating part may have wiring that is finer than the via electrode (130, 170) or wiring pattern disposed within the core part (100).

[0076] Specifically, with respect to the vertical direction, the thickness (H7, see FIG. 2) of each of the plurality of insulating layers (210) of the upper build-up insulating part and the plurality of insulating layers (310) of the lower build-up insulating part may be thinner than the thickness (H2) of the second core layer (150). The thickness (H7) of each of the plurality of insulating layers (210) of the upper build-up insulating part and the plurality of insulating layers (310) of the lower build-up insulating part may be 30 µm or more and 45 µm or less in order to secure insulation in the vertical direction and to arrange fine wiring and via electrodes. Accordingly, the ratio of the thickness (H2) of the second core layer (150) to the thickness (H7) of each of the plurality of insulating layers (210) of the upper build-up insulating part and the plurality of insulating layers (310) of the lower build-up insulating part may be 10:3 to 5:4.

[0077] If the ratio of the thickness of each of the plurality of insulating layers (210) of the upper build-up insulating part and the plurality of insulating layers (310) of the lower build-up insulating part relative to the second core layer (150) is less than 10:3, delamination may occur due to stress applied to the insulating layers forming the upper build-up structure (200) and the lower build-up structure (300).

[0078] When the ratio of the thickness of each of the multiple insulating layers (210) of the upper build-up insulating part and the multiple insulating layers (310) of the lower build-up insulating part relative to the second core layer (150) exceeds 5:4, a pattern having a spacing and width similar to the spacing and width of the via electrodes (130, 170) and / or wiring placed within the core part (100) may be placed. That is, there may be difficulties in placing fine patterns, which not only reduces the degree of freedom in wiring design but also becomes a factor requiring a significant increase in the overall size and thickness of the circuit board (10), which may cause peeling and / or warping problems. In addition, when electrically connecting with a semiconductor device, the difference between the impedance matching or the wiring for transmitting signals or power and the terminals of the semiconductor device may become large, making it difficult to make a close connection between the circuit board (10) and the semiconductor device.

[0079] A circuit portion for electrical signal transmission may be disposed in the core portion (100). The circuit portion may include a plurality of wiring portions and a plurality of via electrodes disposed in the core portion (100), the upper build-up structure (200), and the lower build-up structure (300).

[0080] A plurality of wiring sections may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of wiring sections is embedded within a plurality of insulating layers or protective layers (410, 420) constituting a core section (100), an upper build-up structure (200), and a lower build-up structure (300), and is exposed to the outside from the surface. A wiring section may also be named a metal section. Additionally, the surface of the plurality of insulating layers includes a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of a wiring section being disposed on the surface is that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be formed in which a wiring section is disposed on the first surface and the second surface of some of the insulating layers, and a wiring section is disposed on only the first surface or the second surface of other parts of the plurality of insulating layers.

[0081] A plurality of wiring sections may include a first wiring section (121) disposed on the upper surface of the first core layer (110), a second wiring section (123) disposed on the lower surface of the first core layer (110), a third wiring section (160) disposed on the second core layer (150), a fourth wiring section (220) disposed on the upper build-up insulation section, and a fifth wiring section (320) disposed on the lower build-up insulation section. The first to fifth wiring sections (121, 122, 160, 220, 320) may be disposed so as to overlap each other in a vertical direction.

[0082] The third wiring section (160) may be disposed on the surface of each insulating layer constituting the second core layer (150). For example, the third wiring section (160) may be disposed on the upper surface of the second-1 core layer (151), the upper surface of the second-2 core layer (152), the lower surface of the second-3 core layer (153), and the lower surface of the second-4 core layer (154), respectively.

[0083] The fourth wiring section (220) and the fifth wiring section (320) can each be placed on the surface of a plurality of insulating layers (210) of the upper build-up insulating section and a plurality of insulating layers (310) of the lower build-up insulating section.

[0084] A via electrode may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via electrode may be disposed within the via hole.

[0085] The circuit board (10) may include a first via electrode (130). The first via electrode (130) may be positioned to penetrate at least a portion of the first core layer (110). The first via electrode (130) may electrically connect the first wiring portion (121) and the second wiring portion (123).

[0086] The first via electrode (130) may include a first part (134) which gradually narrows in width as it approaches the upper surface of the first core layer (110) from the lower surface of the first core layer (110), and a second part (132) which is disposed on the first part (134) and gradually narrows in width as it approaches the lower surface of the first core layer (110) from the upper surface of the first core layer (110). As shown in FIG. 2, with respect to the second core layer (150) disposed on the first core layer (110), the first part (134) may have a shape in which the horizontal width widens from the second core layer (150) toward the first core layer (110), and the second part (132) may have a shape in which the horizontal width narrows from the second core layer (150) toward the first core layer (110).

[0087] The first part (134) and the second part (132) may be arranged adjacent to each other in a vertical direction. The first part (134) and the second part (132) may be formed integrally. The lower end of the first part (134) may be connected to the second wiring part (123). The upper end of the second part (132) may be connected to the first wiring part (121). The vertical cross-section of the first via electrode (150) may have an hourglass shape due to the first part (134) and the second part (132).

[0088] When a via hole is formed in the first core layer (110) using a laser to place the first via electrode (150), the laser can be irradiated onto the upper and lower surfaces of the first core layer (110), respectively. At this time, depending on conditions such as positional precision and laser intensity, the vertical length (H4) of the first part (134) of the first via electrode (150) and the vertical length (H3) of the second part (132) may be equal to each other. The area where the first part (134) and the second part (132) meet may be an area that divides the vertical length (H1) of the first via electrode (150) into 1 / 2. The ratio of the vertical length (H4) of the first part (134) and the vertical length (H3) of the second part (132) may be 1:1. However, it is not necessarily limited to this, and depending on the conditions of the process described above, the vertical length (H4) of the first part (134) and the vertical length (H3) of the second part (132) may differ from each other.

[0089] The second via electrode (170) may be positioned to penetrate at least a portion of the second core layer (150). The second via electrode (170) may electrically connect the first wiring section (121) and the third wiring section (160), the second wiring section (123) and the third wiring section (160), and a plurality of third wiring sections (160).

[0090] Based on the second core layer (150) disposed on the first core layer (110), the second via electrode (170) may include a fourth part (172) whose width gradually narrows as it approaches the lower surface of the second core layer (150) from the upper surface of the second core layer (150), and a third part (174) disposed below the fourth part (172) whose width gradually widens as it approaches the lower surface of the second core layer (150). The third part (174) may have a shape in which the width in the horizontal direction widens from the second core layer (150) toward the first core layer (110). The fourth part (172) may have a shape in which the width in the horizontal direction narrows from the second core layer (150) toward the first core layer (110). The fourth part (172) may be disposed on the third part (174). The fourth part (172) and the third part (174) may be arranged adjacent to each other in a vertical direction. The fourth part (172) and the third part (174) may be formed as a single unit.

[0091] By the third part (174) and the fourth part (172), the second via electrode (170) may have an hourglass shape in which the cross-section is asymmetric in the vertical direction. As shown in FIG. 2, the vertical length (H5) of the fourth part (172) and the vertical length (H6) of the third part (174) may be different from each other. For example, the vertical length (H5) of the fourth part (172) may be longer than the vertical length (H6) of the third part (174). The ratio of the vertical length (H5) of the fourth part (172) and the vertical length (H6) of the third part (174) in the second via electrode (170) may be different from the ratio of the vertical length (H3) of the first region (151) and the vertical length (H4) of the second region (152) in the first via electrode (150). For example, the ratio of the vertical length (H5) of the fourth part (172) and the vertical length (H6) of the third part (174) in the second via electrode (170) may be 3:2 to 3:1.

[0092] Based on the second core layer (150) disposed on the upper part of the first core layer (110), the via hole in which the second via electrode (170) is disposed can be formed by irradiating a laser from the upper surface of the second core layer (150) toward the lower surface of the second core layer (150). Specifically, as shown in FIG. 4, the via hole (180) in which the second via electrode (170) is disposed may include a first region (184) in which the third part (174) is disposed, and a second region (182) disposed on the first region (184) in which the fourth part (172) is disposed. The first region (184) may have a shape in which the horizontal width widens as it approaches the first core layer (110). The second region (182) may have a shape in which the horizontal width narrows as it approaches the first core layer (110).

[0093] Based on FIG. 2, depending on the process conditions, a laser irradiated on the second core layer (150) may scatter on the upper surface of the first wiring section (121), and a third section (174) with a gradually widening width may be formed. By the third section (174), the bonding area between the second via electrode (170) and the first wiring section (121) is widened, thereby improving the bonding strength of the second via electrode (170).

[0094] In addition, if scattering occurs on the upper surface of the first wiring portion (121) of the laser, it is difficult to form the shape of the via hole of the second core layer (150) for the second via electrode (170) uniformly across the entire circuit board, and the yield may be lowered.

[0095] Accordingly, when the second via electrode (170) completely fills the via hole of the second core layer (150), it is preferable to have a ratio of the vertical length (H5) of the fourth part (172) of the second via electrode (170) and the vertical length (H6) of the third part (174) of the second via electrode (170) of 3:2 to 3:1. Additionally, with reference to FIG. 3, the third part (174) may be located below the glass fiber (150a) disposed within the second core layer (150). Thus, by preventing excessive exposure of the glass fiber (150a), problems such as leakage current or signal loss can be prevented.

[0096] According to the embodiment, the ratio of the vertical lengths of the first part (134) and the second part (132) within the first via electrode (130) is different from the ratio of the vertical lengths of the third part (174) and the fourth part (172) within the second via electrode (170). Additionally, the third via electrode (230) of the upper build-up insulating part and the lower build-up insulating part, which will be described later, may include only a region where the width narrows as it moves from the upper surface toward the lower surface, but is not limited thereto.

[0097] When the third via electrode (230) includes a sixth section in which the horizontal width of the second core layer (150) narrows, and a fifth section disposed below the sixth section in which the horizontal width narrows toward the second core layer (150), the first ratio of the vertical length of the first section (134) of the first via electrode (150) to the vertical length of the second section (132), the second ratio of the vertical length of the third section (174) of the second via electrode (170) to the vertical length of the fourth section (172), and the third ratio of the vertical length of the fifth section of the third via electrode (230) to the vertical length of the sixth section may differ from each other. Here, each ratio is based on the second section (132), the fourth section (172), and the sixth section, in which the width gradually narrows from the upper surface toward the lower surface. The first ratio may be greater than the second ratio, and the second ratio may be greater than the third ratio. For example, the above-described ratio may vary depending on the thickness of the core portion (100), the plurality of insulating layers (210) constituting the upper build-up insulating portion, and the plurality of insulating layers (310) constituting the lower build-up insulating portion. Accordingly, the difference between the first and third ratios described above may relieve stress applied to the upper and / or lower portions of the circuit board (10), have the effect of suppressing bending of the circuit board (10), and have the effect of improving the degree of integration of wiring and the degree of freedom of design for connecting to electronic components such as semiconductor devices.

[0098] In particular, by making the first ratio and the second ratio different, bending occurring during the formation process of the core part (100) can be prevented, and wiring can be arranged in the second core layer (150) to have a wiring density between the wiring density of the insulating layer (210, 310) constituting the upper and lower build-up insulating part and the wiring density of the first core layer (110), thereby making it easy to control impedance matching, insertion loss, etc. In addition, there is an effect of lowering the process unit cost of forming via electrodes arranged in each core part (100) and the insulating layer (210, 310) constituting the upper and lower build-up insulating part, and increasing the yield. Here, density or integration refers to the size of the width and spacing of the wiring or via electrodes, and high density is equivalent to high integration, which should be understood as the width and / or spacing of the wiring and the width and / or spacing of the via electrodes being small.

[0099] Meanwhile, the shape and structure of the second via electrode (170) described above are explained by exemplifying the second via electrode (170) disposed within the second core layer (150) disposed on the first core layer (110). The second via electrode (170) disposed in the second core layer (150) disposed below the first core layer (110) may have a shape in which the third part (174) and the fourth part (172) are inverted in the vertical direction from the structure described above. According to this, the second via electrode (170) in the second core layer (150) disposed at the bottom of the first core layer (110) may include a fourth part (172) whose width gradually narrows as it approaches the upper surface of the second core layer (150) from the lower surface of the second core layer (150), and a third part (174) whose width gradually widens, and the vertical length of the fourth part (172) may be longer than the vertical length of the third part (174).

[0100] In summary, the second via electrode (170) disposed in a plurality of second core layers (150) that are arranged symmetrically in the vertical direction with respect to the first core layer (110) can be symmetrically arranged in the vertical direction with respect to the first core layer (110).

[0101] As illustrated in FIGS. 1 to 3, the second via electrode (170) can be arranged to overlap the first via electrode (130) perpendicularly. Accordingly, the signal transmission length within the core portion (100) can be minimized.

[0102] The width of the second via electrode (170) may be smaller than the width of the first via electrode (130). This is in consideration of the fact that the first core layer (110) has a relatively larger thickness than the second core layer (150), and by forming the width of the first via electrode (130) within the first core layer (110), which has a relatively larger thickness, resistance due to signal transmission can be minimized.

[0103] Meanwhile, at least a portion of the first via electrode (130) may have a width smaller than that of the second via electrode (170). Specifically, the first via electrode (130) may have a minimum width in the horizontal direction in the area where the first part (134) and the second part (132) meet. In this case, the maximum width in the horizontal direction of the area placed at the top or bottom of the second via electrode (170) may be greater than the minimum width of the first via electrode (130). Accordingly, the amount of plating required to form the first via electrode (130) placed within the first core layer (110) can be reduced.

[0104] However, this is not limited to the minimum width in the horizontal direction in the area where the first part (134) and the second part (132) of the first via electrode (130) meet may be greater than the maximum width in the horizontal direction of the second via electrode (170).

[0105] The third via electrode (230) may be positioned to penetrate each of the plurality of insulating layers (210) of the upper build-up insulating portion. The fourth via electrode (330) may be positioned to penetrate each of the plurality of insulating layers (310) of the lower build-up insulating portion. The third via electrode (230) and the fourth via electrode (330) may have a structure that is inverted in a vertical direction with respect to the core portion (100). Accordingly, below, via electrodes positioned in the upper and lower build-up structures will be described based on the third via electrode (230) positioned in each of the plurality of insulating layers (210) constituting the upper build-up insulating portion.

[0106] The third via electrode (230) can electrically connect a plurality of fourth wiring sections (220) arranged in a vertical direction, the fourth wiring sections (220), and the third wiring sections (160). The third via electrode (230) can electrically connect the fourth wiring sections (220) and the pad sections arranged on the upper build-up insulation section.

[0107] The third via electrode (230) may have a shape in which the width gradually narrows as it approaches the lower surface of the insulating layer (210) constituting the upper build-up insulating portion from the upper surface of the insulating layer (210). The fourth via electrode (330) may have a shape in which the horizontal width gradually narrows as it approaches the upper surface of the insulating layer (310) constituting the lower build-up insulating portion from the lower surface of the insulating layer (310).

[0108] The width of the second via electrode (170) may be greater than the width of the third via electrode (230). This takes into account that the second core layer (150) has a relatively larger thickness than the insulating layer (210) constituting the upper build-up insulating portion, and accordingly, the signal transmission resistance in the second via electrode (170) disposed within the core portion (100) can be minimized.

[0109] Although not shown, based on a single fourth wiring section (220), there may be multiple third via electrodes (230) connected to the fourth wiring section (220). Accordingly, signal transmission efficiency can be improved.

[0110] As illustrated in FIGS. 1 and 6, the circuit board (10) according to the embodiment may have a structure in which a first wiring section (121), a second wiring section (123), a third wiring section (160), a fourth wiring section (220), a fifth wiring section (320), a first via electrode (130), a second via electrode (170), a third via electrode (230), and a fourth via electrode (330) are superimposed in a vertical direction. Accordingly, the vertical signal path within the circuit board (10) is reduced, and the signal transmission efficiency can be improved.

[0111] Recently, for semiconductor packages applied in the fields of AI, Cloud, and autonomous driving, package sizes are increasing as high integration is required to achieve high performance. Accordingly, there is an increasing need for stacked vias, a structure in which as many via electrodes as possible between insulating layers are overlapped and connected in a vertical direction, for the purpose of reducing the number of stacked insulating layers constituting the circuit board or shortening the signal path.

[0112] However, according to the conventional circuit board, as the thickness of the core portion increases to suppress warping of the circuit board, the processing method of the via hole is restricted to a mechanical drilling method, which makes it difficult to reduce the size of the via electrode within the core portion. In addition, as the increase in the thickness of the core portion and the increase in the width of the via electrode increase, the stress applied to the via electrode placed in the upper and lower build-up structures also increases, so there is a problem that the number of insulating layers constituting the upper and lower build-up structures must also be increased.

[0113] According to the embodiment, by implementing the core portion (100) as a plurality of insulating layers through the first core layer (110) and the second core layer (150), the process of forming via electrodes (130, 170) provided in each core layer can be performed more easily compared to a conventional single core layer. In addition, as the horizontal width of the via electrodes (130, 170, 230, 330) placed in each insulating layer gradually decreases from the first core layer (110) positioned at the center in the vertical direction toward the surface of the circuit board (10), the stress generated in the vertical overlapping structure of the plurality of via electrodes can be uniformly distributed. That is, the horizontal width of the second via electrode (170) disposed within the second core layer (150) is smaller than the horizontal width of the first via electrode (130) and larger than the horizontal width of the third via electrode (230), so that the arrangement of multiple via electrodes in the vertical direction can be more easily implemented.

[0114] Referring to FIG. 5, the circuit board according to the comparative example includes a single-layer core portion (610) and upper and lower build-up structures (630, 640). A first via electrode (622) is disposed in the core portion (610), and a wiring portion (632, 642) and a second via electrode (634, 644) that vertically connects a plurality of wiring portions (632, 642) are disposed in each build-up structure (630, 640). In this case, the first via electrode (622) and the second via electrode (634, 644), and the first via electrode (622) and the wiring portion (632, 642) are difficult to overlap in the vertical direction due to factors such as differences in horizontal width between different via electrodes or wiring portions, so the via electrodes and wiring portions between multiple insulating layers have a structure in which they are misaligned in the vertical direction.

[0115] Referring to FIG. 5(a), the stress generated in the wiring portion (632, 642) or the second via electrode (634, 644) within the upper and lower build-up structures (630, 640) was measured to be 638.98 MPa. Additionally, referring to FIG. 5(b), when mounting the semiconductor chip (700) on the circuit board according to the comparative example, the stress generated in the bonding area with the semiconductor chip was measured to be 338.16 MPa.

[0116] According to the embodiment, by the vertical overlapping structure of a plurality of via electrodes (130, 170, 230, 330) in which the horizontal width gradually decreases as it goes from the core part (100) to the upper and lower build-up structures (200, 300), the stress generated in the upper and lower build-up structures (200, 300) is measured as 360.07 MPa as in FIG. 6 (a), and it can be confirmed that the stress within the circuit board (10) is uniformly distributed and has low stress when compared to the comparative example.

[0117] In addition, as shown in FIG. 6(b), when mounting the semiconductor chip (1000), the stress generated in the bonding region with the semiconductor chip (1000) was also measured to be 170.64 MPa, which is less than half of that of the comparative example. Therefore, according to the embodiment, as stress is relieved within the circuit board (10), the durability of the circuit board (10) is improved, and bending characteristics and reliability can be improved. In addition, by the vertical overlapping structure of via electrodes and wiring sections between multiple insulating layers arranged in a vertical direction, a fine pitch of via electrodes and wiring sections within each insulating layer can be realized.

[0118] The circuit board (10) may include a protective layer (410, 420). The protective layer (410, 420) may include a first protective layer (410) disposed on the surface of an upper build-up structure (200) and a second protective layer (420) disposed on the surface of a lower build-up structure (300). When a semiconductor device is disposed on the surface of the circuit board (10) using a material such as solder, the first protective layer (410) and the second protective layer (420) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent the problem of external contaminants penetrating into the build-up structure and reducing reliability. The first protective layer (410) and the second protective layer (420) may each utilize a photocurable insulating material. Accordingly, the first protective layer (410) and the second protective layer (420) are provided with a solder resist other than the aforementioned ABF, PPG, BT resin, and PID. However, they are not limited thereto and may be provided with various materials capable of performing low wettability with solder and thus preventing short circuits between solders as described above.

[0119] The first protective layer (410) may include a hole for exposing a pad portion disposed on the surface of the upper build-up structure (200) upward. A connecting member (415), such as a solder ball, may be disposed in the hole. The second protective layer (420) may include a hole for exposing a pad portion disposed on the surface of the lower build-up structure (300) downward to the circuit board (10).

[0120] Accordingly, the circuit board (10) can implement a semiconductor package together with a semiconductor chip that is coupled through a connecting member (415).

[0121] FIG. 7 is a drawing illustrating a semiconductor package according to an embodiment of the present invention.

[0122] Referring to FIG. 7, a semiconductor package according to an embodiment of the present invention may include a semiconductor chip (1000) disposed on a circuit board (10). For example, the semiconductor chip (1000) may be disposed on an upper build-up structure (200). The semiconductor chip (1000) may be electrically and physically coupled through a pad portion and a connecting member (415) disposed on the upper build-up structure (200).

[0123] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0124] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0125] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0126] When a circuit board having the features of the invention described above is used in a transport device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transport device, or safely protect a semiconductor chip controlling the transport device from the outside, and further improve the stability of the transport device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transport device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. A core portion including a first core layer and a second core layer disposed on the first core layer; An upper build-up insulating portion comprising a plurality of insulating layers stacked along a vertical direction and disposed on the above-mentioned core portion; A first via electrode penetrating at least a portion of the first core layer; A second via electrode penetrating at least a portion of the second core layer; and It includes a plurality of third via electrodes penetrating each of the plurality of insulating layers of the upper build-up insulating portion, and The first via electrode comprises a first portion that widens in the horizontal direction from the second core layer toward the first core layer, and a second portion disposed on the first portion that narrows in the horizontal direction from the second core layer toward the first core layer. The second via electrode comprises a third portion that widens in the horizontal direction from the second core layer toward the first core layer, and a fourth portion disposed on the third portion that narrows in the horizontal direction from the second core layer toward the first core layer. The vertical length of the first part and the vertical length of the second part are the same, The vertical length of the third part and the vertical length of the fourth part are different, The first via electrode, the second via electrode, and the plurality of third via electrodes are circuit boards that are superimposed along a vertical direction.

2. In Paragraph 1, A circuit board in which the vertical length of the third part is shorter than the vertical length of the fourth part.

3. In Paragraph 1, It includes a first wiring portion disposed on the first core layer and connected to the first via electrode, The second via electrode is a circuit board vertically connected to the first wiring section.

4. In Paragraph 1, A circuit board in which the vertical thickness of the first core layer is thicker than the vertical thickness of the second core layer.

5. In Paragraph 1, The first core layer comprises a plurality of vertically stacked glass fibers, and The above second core layer is a circuit board comprising one layer of glass fiber.

6. In Paragraph 5, A plurality of insulating layers of the upper build-up insulating portion are each an insulating layer of a circuit board in which the insulating layer is prepreg (PPG).

7. In Paragraph 1, A circuit board in which the horizontal width of the second via electrode is greater than the horizontal width of the third via electrode.

8. In Paragraph 7, A circuit board in which the horizontal width of the first via electrode is larger than the horizontal width of the second via electrode.

9. In Paragraph 1, The first via electrode has a minimum width in the horizontal direction in the area where the first part and the second part meet, A circuit board in which the maximum width of the second via electrode is greater than the minimum width of the first via electrode.

10. A core portion including a first core layer and a second core layer disposed on the first core layer; An upper build-up insulating portion comprising a plurality of insulating layers stacked along a vertical direction and disposed on the above-mentioned core portion; A semiconductor chip disposed on the upper build-up insulating portion above; A first via electrode penetrating at least a portion of the first core layer; A second via electrode penetrating at least a portion of the second core layer; and It includes a plurality of third via electrodes penetrating each of the plurality of insulating layers of the upper build-up insulating portion, and The first via electrode comprises a first portion that widens in the horizontal direction from the second core layer toward the first core layer, and a second portion disposed on the first portion that narrows in the horizontal direction from the second core layer toward the first core layer. The second via electrode comprises a third portion that widens in the horizontal direction from the second core layer toward the first core layer, and a fourth portion disposed on the third portion that narrows in the horizontal direction from the second core layer toward the first core layer. The vertical length of the first part and the vertical length of the second part are the same, The vertical length of the third part and the vertical length of the fourth part are different, The first via electrode, the second via electrode, and the plurality of third via electrodes are a semiconductor package that is superimposed along a vertical direction.

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